Integrated device and forming method thereof

Abstract

Some embodiments relate to an integrated device comprising: a substrate having at least one active component; an interconnect structure disposed on the substrate; a bonding layer disposed above the interconnect structure; a carrier substrate disposed above the bonding structure; a heat dissipation module disposed above the carrier substrate; and a first thermal control layer disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, wherein the first thermal control layer comprises a phase change material (PCM).

Description

Prior Art

[0001] Circuit components within an integrated device generate heat during operation. The generated heat can damage the components, resulting in a loss of efficiency or potentially causing failure of the integrated device. Various methods have been developed to disperse or transfer heat away from the circuit components, including using materials with higher thermal conductivity than silicon dioxide and forming vias that extend through the integrated device and conduct heat toward the external sidewalls of the semiconductor package. Simple diagram description

[0002] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. 1 illustrates a cross-sectional view of some embodiments of an integrated device having one or more thermal control layers disposed between an interconnect structure and an upper surface of a semiconductor package. FIG. 2 shows an exemplary graph of temperature change of a thermal control layer during a phase transition. 3 illustrates a cross-sectional view of some embodiments of an integrated device having one or more thermal control layers disposed between an interconnect structure and an external sidewall of a semiconductor package and further including a heat sink within the interconnect structure. 4 illustrates a cross-sectional view of some embodiments of an integrated device having one or more thermal control layers, wherein the thermal control layers are patterned. 5 illustrates a cross-sectional view of some embodiments of an integrated device having one or more thermal control layers coupled to one or more high thermal conductivity layers to increase heat transfer through the integrated device. 6A-6B illustrate cross-sectional views of some embodiments of integrated devices having one or more thermal control layers patterned and coupled to one or more high thermal conductivity layers to increase heat transfer through the integrated device. 7-8 , 9A, 9B, and 10-13 illustrate a series of cross-sectional views of some embodiments of methods of forming an integrated device having one or more thermal control layers disposed between an interconnect structure and an external sidewall of a semiconductor package. 14-18 illustrate a series of cross-sectional views of some embodiments of methods of forming one or more patterned thermal control layers disposed between an interconnect structure and an exterior sidewall of a semiconductor package. 19 illustrates a flow chart of some embodiments of a method of forming one or more patterned thermal control layers disposed between an interconnect structure and an external sidewall of a semiconductor package. Implementation

[0003] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0005] An integrated device may include a semiconductor substrate, a plurality of semiconductor devices, and interconnect structures overlying the semiconductor devices. The semiconductor devices perform many operations that are critical to the function of the integrated device, such as computation and data retention. During operation, the resistance within the plurality of semiconductor devices and other components causes thermal energy to build up in the form of heat within the integrated device. The heat buildup increases the resistance of many materials and may reduce the efficiency of device operation, resulting in performance loss and potentially leading to failure of the integrated device.

[0006] In some embodiments, multiple technology developments are combined to simultaneously reduce the effects of heat on the function of semiconductor devices and to disperse the heat to the surrounding environment outside the integrated device, thereby reducing the damage caused. Some of these developments include using materials with high thermal conductivity to transfer heat at a higher rate, which reduces the amount of heat that can accumulate at the semiconductor device. In addition, the use of thermal interface materials (TIMs) and heat dissipation modules also transfer heat away from the semiconductor device. In some embodiments, the semiconductor device is modified to distribute the heat throughout the device or to be more resilient to potentially damaging temperatures. Current dynamic solutions to transfer heat away from semiconductor devices include the use of microchannels and liquid cooling. However, these solutions are complex and expensive.

[0007] The aforementioned developments can be used to improve thermal management within an integrated circuit, but in some embodiments, the integrated circuit is in a dormant state for longer periods of time separated by periods of activity, resulting in fast transient temperature spikes. The fast transient temperature spikes can overwhelm the heat transfer capabilities of the aforementioned developments, thereby rapidly introducing an amount of thermal energy that can damage the semiconductor device even though the TIM, high thermal conductivity materials, and heat sinks improve the heat transfer rate. Therefore, a method is needed to reduce the effects of fast transient increases in temperature on an integrated device.

[0008] The present disclosure provides an integrated device with a thermal control layer. The thermal control layer is a phase-change material (PCM) and has a larger thermal capacity than other thermally conductive materials, and additionally absorbs thermal energy as latent heat (e.g., energy that causes a transition between phases rather than a temperature change) near the phase transition temperature of the material. The increase in thermal capacity and energy absorption results in the thermal control layer absorbing thermal energy and reducing the overall temperature increase caused by fast transient spikes. The absorbed thermal energy is then released during a longer dormant period and at a slower rate than the absorbed thermal energy. The slower release of thermal energy at a slower rate is dispersed by the TIM and heat dissipation module. Therefore, the introduction of the thermal control layer effectively reduces the increase in temperature within the integrated device during fast transient spikes, resulting in a longer life of the semiconductor device and a reduced risk of failure during operation. The thermal characteristics of the thermal control layer can be modified by tuning the composition and doping of the film layer, thereby obtaining multiple phase transition temperatures and hysteresis curves by introducing a passive component.

[0009] FIG. 1 illustrates a cross-sectional view 100 of some embodiments of an integrated device having one or more thermal control layers disposed between an interconnect structure and an upper surface of a semiconductor package.

[0010] As shown in the cross-sectional view 100 of FIG. 1 , a plurality of semiconductor devices 104 are disposed above a substrate 102. In some embodiments, the plurality of semiconductor devices 104 may include transistor devices (e.g., planar FETs, FinFETs, gate-all-around (GAA) devices, etc.). The plurality of semiconductor devices 104 are coupled to an interconnect structure 106 via a plurality of contacts 108. The interconnect structure 106 couples the plurality of semiconductor devices 104 to each other and / or to a plurality of back-end-of-line (BEOL) devices (not shown). The interconnect structure 106 and the plurality of semiconductor devices 104 are surrounded by an interlayer dielectric 107.

[0011] The carrier substrate 110 is coupled to the interconnect structure 106 via a bonding layer 112. The carrier substrate 110 is further coupled to a heat dissipating module 114 via a thermal interface material (TIM) 116. The heat dissipating module 114 is, for example, a heat conductive housing surrounding the integrated device, or a heat sink coupled to the heat conductive housing. In some embodiments, the heat dissipating module 114 may include a heat sink including a plurality of fins protruding outward from a horizontally extending surface away from the carrier substrate 110.

[0012] One or more thermal control layers 118 are disposed above the interconnect structure 106. In some embodiments, the one or more thermal control layers 118 may line the surface of the carrier substrate 110 or the bonding layer 112. In some embodiments, the thermal control layer 118 is or includes a shape memory alloy (SMA) material, a solid-solid phase change material (SS-PCM), or the like. In various embodiments, the one or more thermal control layers 118 may include one or more of the following: a first thermal control layer 118a disposed between the bonding layer 112 and the interconnect structure 106, a second thermal control layer 118b disposed between the carrier substrate 110 and the bonding layer 112, and a third thermal control layer 118c disposed between the carrier substrate 110 and the heat dissipation module 114.

[0013] The positioning of one or more thermal control layers 118 within the semiconductor package results in a reduction in peak temperature during fast transient temperature spikes. The material of the thermal control layer 118 is selected to have a phase transition region within the temperature band in which the integrated circuit can safely operate. When the temperature of the thermal control layer 118 is within the phase transition region, the thermal control layer 118 absorbs thermal energy as latent heat. Because latent heat is energy that causes a transition between different phases, the absorption of thermal energy does not increase the temperature and thus reduces the rate of temperature increase and the peak temperature reached within the integrated device. By reducing the peak temperature, the internal resistance at the peak temperature reached is lower. Lower internal resistance increases the efficiency of the integrated circuit and reduces the eventual degradation (e.g., performance degradation) of the plurality of semiconductor devices 104, thereby increasing the life of the integrated device.

[0014] FIG. 2 shows an illustrative graph 200 of temperature changes of a thermal control layer during a phase transition.

[0015] Graph 200 illustrates the change in temperature of a thermal control layer (see thermal control layer 118 of FIG. 1 ) over time during both a heating phase 202 (e.g., a fast transient temperature spike) and a cooling phase 204 (e.g., a longer rest period). During a first portion 208 of the heating phase 202, the material of the thermal control layer (see thermal control layer 118 of FIG. 1 ) is primarily in the first phase, and the change in temperature of the thermal control layer is substantially the same as the change in temperature of the material 206 without a phase change. During a second portion 210 of the heating phase 202, the temperature is within a first phase change region 209, and the material begins to transform from the first phase to the second phase. The transformation from the first phase to the second phase absorbs the heat added during the entire fast transient temperature spike, reducing the overall increase in temperature compared to the change in temperature of the material 206 without a phase change.

[0016] During the cooling phase, the material of the thermal control layer (see thermal control layer 118 of FIG. 1 ) is primarily in the second phase. In some embodiments, the second phase change region 213 is the same temperature or temperature range as the first phase change region 209. In other embodiments, the second phase change region 213 is at a lower temperature than the first phase change region 209 or is centered at a lower temperature than the first phase change region 209. During the first portion 212 of the cooling phase 204, the temperature decreases at a rate comparable to the temperature change of the material 206 without phase change and materials of similar specific heat capacity. During the second portion 214 of the cooling phase 204, the temperature is within the second phase change region 213 and the material begins to transform from the second phase to the first phase. The transformation from the second phase to the first phase releases the heat absorbed during the rapid transient temperature spike and reduces the rate of temperature drop compared to the temperature change of the material 206 without phase change. That is, the transformation from the second phase to the first phase and the resulting heat release is a gradual process that takes a longer time period than a similar temperature change of the material 206 without phase change. Thermal release occurs at a temperature at which the semiconductor device can operate without damage, reducing the performance degradation that may occur during fast transient temperature spikes by lowering the maximum temperature reached.

[0017] The difference in the rate of temperature gain at different temperatures is due to the latent heat used by the material to transition between phases. The latent heat absorbed by the thermal control layer 118 as it transitions between the first phase and the second phase does not increase the temperature of the thermal control layer 118, thereby resulting in a reduction in the overall temperature increase that may occur during a fast transient temperature spike.

[0018] 3 illustrates a cross-sectional view 300 of some embodiments of an integrated device having one or more thermal control layers disposed between an interconnect structure and an external sidewall of a semiconductor package and further including a heat sink within the interconnect structure.

[0019] In some embodiments, the integrated device includes a plurality of stacked chips. The substrate 102 may be coupled to a multilayer board 320 via a second substrate 301. The second substrate 301 is coupled to the multilayer board 320 using a ball grid array 316. A controlled collapsed chip connection 302 overlies the second substrate 301. The controlled collapsed chip connection 302 couples a second interconnect structure 303 of the second substrate 301 to a bond pad layer 304. A plurality of solder balls 308 are used to couple the second interconnect structure 303 to the bond pad layer 304. The solder balls are separated by gap fillers and form a controlled collapsed chip connection (C4) layer 310.

[0020] A heat spreader 306 overlies the bonding pad layer 304. The heat spreader 306 includes a high thermal conductivity material, such as diamond or the like. A back metal layer 305 separates the heat spreader 306 from the substrate 102. The bonding pad layer 304 and the back metal layer 305 each include a second plurality of conductive lines electrically coupled via a second plurality of vias 314 extending through the heat spreader 306.

[0021] The substrate 102 and the interconnect structure 106 include a plurality of logic layers 307 in the integrated device. The uppermost layer of the interconnect structure 106 is a top metal layer 317. The top metal layer 317 has a wire layer 318 having a greater thickness than the wire layer of the rest of the interconnect structure 106.

[0022] FIG. 4 illustrates a cross-sectional view 400 of some embodiments of an integrated device having one or more thermal control layers, wherein the thermal control layers are patterned.

[0023] In some embodiments, the one or more thermal control layers 118 include a plurality of grooves and protrusions. The plurality of grooves and protrusions increase the surface area of ​​the thermal control layer 118, thereby increasing the heat transfer rate between layers coupled to the thermal control layer 118. The plurality of grooves are formed by the sidewalls and horizontally extending surfaces of the one or more thermal control layers 118. In some embodiments, the sidewalls of the one or more thermal control layers 118 contact the sidewalls of the carrier substrate 110. In some embodiments (not shown), individual ones of the one or more thermal control layers 118 may include grooves and protrusions along opposite sides of the thermal control layer (e.g., along the top and bottom of the thermal control layer).

[0024] The plurality of grooves are formed by one of the following two methods: etching a plurality of grooves into an underlying layer (e.g., interlayer dielectric 107, bonding layer 112, or carrier substrate 110) and forming thermal control layer 118 in the grooves, or etching a plurality of grooves into thermal control layer 118 and forming an overlying layer in the grooves. Either or both of these processes may be used to pattern thermal control layer 118. For example, in FIG. 4 , before bonding carrier substrate 110 to bonding layer 112, first thermal control layer 118a, second thermal control layer 118b, and third thermal control layer 118c are patterned by etching underlying layers (e.g., interlayer dielectric 107 under first thermal control layer 118a and carrier substrate 110 under second thermal control layer 118b and third thermal control layer 118c), and first thermal control layer 118a, second thermal control layer 118b, and third thermal control layer 118c are formed over the patterned underlying layers. In some embodiments, the first surface of the carrier substrate 110 is etched, and the second thermal control layer 118b is formed in the resulting plurality of openings. Subsequently, the second surface of the carrier substrate is etched, and the third thermal control layer 118c is formed in the resulting plurality of openings. In other embodiments, both the first surface and the second surface are etched before forming the second thermal control layer 118b and the third thermal control layer 118c.

[0025] 5 illustrates a cross-sectional view 500 of some embodiments of an integrated device having one or more thermal control layers coupled to one or more high thermal conductivity layers to increase heat transfer through the device.

[0026] In some embodiments, the thermal control layer 118 is coupled to a high thermal conductivity layer 502 to increase heat transfer through the integrated device. The high thermal conductivity layer 502 includes a high thermal conductivity material, such as diamond or the like. The presence of the high thermal conductivity layer 502 enhances the heat transfer coefficient near the thermal control layer 118 of the integrated device, resulting in greater reactivity and increased ability of the thermal control layer 118 to absorb or release heat from surrounding layers. The high thermal conductivity layer 502 further improves the thermal distribution of the entire device, thereby reducing the amount of heat that stays in areas with high heat concentrations generated (e.g., near higher power devices, etc.). That is, the high thermal conductivity layer 502 redistributes the generated heat, thereby alleviating heat accumulation at hot spots in the integrated device. The high thermal conductivity layer 502 is disposed between the coupled thermal control layer 118 and the semiconductor device 104, resulting in the heat generated by the active component being distributed on the surface of the thermal control layer 118. In some embodiments, the high thermal conductivity layer 502 has a thickness between approximately 200 nanometers and 5 micrometers, approximately 300 nanometers and 4 micrometers, approximately 100 nanometers and 4.5 micrometers, or the like. In some embodiments, the ratio of the thickness of the thermal control layer 118 to the thickness of the high thermal conductivity layer 502 is between approximately 1:1 and approximately 1:10.

[0027] 6A-6B illustrate cross-sectional views 600a, 600b of some embodiments of integrated devices having one or more thermal control layers patterned and coupled to one or more high thermal conductivity layers to increase heat transfer through the device.

[0028] In some embodiments, high thermal conductivity layers 502 are used with patterned thermal control layers 118 to further enhance the thermal conductivity of the device and improve the effectiveness of thermal control layers 118. When thermal control layers 118 have a patterned surface that contacts high thermal conductivity layers 502, the increased surface area at the interface further increases the amount of heat that can be absorbed by thermal control layers 118. In some embodiments, as depicted in FIG. 6B, one or more of the high thermal conductivity layers 502 are omitted. That is, in some embodiments, an integrated device may have a greater number of thermal control layers 118 than the number of high thermal conductivity layers 502.

[0029] 7-8, 9A, 9B, and 10-13 illustrate a series of cross-sectional views 700 to 1300 of some embodiments of a method of forming an integrated device having one or more thermal control layers disposed between an interconnect structure and an external sidewall of a semiconductor package. Although FIGS. 7-13 are described as a series of actions, it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted in whole or in part.

[0030] As shown in the cross-sectional view 700 of FIG. 7 , a substrate 102 is provided, and a plurality of semiconductor devices 104 are formed on the provided substrate 102. The substrate 102 may be any suitable type of substrate, and / or may be, for example, a semiconductor wafer, one or more dies on a wafer, or any other suitable type of semiconductor body and / or epitaxial layer. In some embodiments, the substrate 102 is or includes silicon, sapphire, the like, or any combination of the foregoing. In some embodiments, the plurality of semiconductor devices 104 is or includes one or more layers, the one or more layers including a first gate, a first dielectric, and a plurality of source / drain regions. The first gate is or includes a conductive material, such as copper (Cu), titanium (Ti), aluminum (Al), doped polysilicon, the like, or a combination of the foregoing. In some embodiments, the first dielectric is or includes an insulator, such as silicon dioxide (SiO 2), a high-k dielectric, or the like. The source / drain region is or includes a region having a high concentration (eg, greater than 10 15 atoms / cm 3 ) of dopants, thereby generating a high concentration of carriers in the source / drain region.

[0031] As shown in the cross-sectional view 800 of FIG. 8 , the interconnect structure 106 is formed over the substrate 102. In some embodiments, the interconnect structure 106 is or includes a conductive material, such as copper (Cu), titanium (Ti), aluminum (Al), the like, or a combination thereof. The interconnect structure includes a plurality of wire levels 106a and a plurality of via levels 106b. The interconnect structure 106 is formed by depositing a layer of an interlayer dielectric 107, etching a plurality of openings in the interlayer dielectric 107, and filling the openings with a conductive material. The process outlined above is repeated until the interconnect structure is completed. In some embodiments, a single damascene process is used to form the plurality of contacts 108, the plurality of wire levels 106a, and the plurality of via levels 106b. In other embodiments, multiple dual damascene processes may be used to form pairs of wire levels 106a and via levels 106b in parallel. Prior to forming the conductive line level 106a and the via level 106b, a plurality of contacts 108 are formed in the first layer of the interlayer dielectric 107. The plurality of contacts 108 couple the plurality of semiconductor devices 104 to the interconnect structure 106.

[0032] As shown in the cross-sectional view 900a of FIG. 9A , the first thermal control layer 118a is formed on the interlayer dielectric 107 above the interconnect structure 106. In some embodiments, the first thermal control layer is omitted. In some embodiments, the first thermal control layer 118a is or includes a shape memory alloy, such as nickel titanium alloy (NiTi), nickel titanium hafnium alloy (NiTiHf), nickel copper titanium alloy (NiCuTi), nickel copper titanium hafnium alloy (NiCuTiHf), nickel titanium vanadium alloy (NiTiV), or the like. In other embodiments, the first thermal control layer 118a includes a solid-solid phase change material that is not a shape memory alloy, such as vanadium oxide (VO 2) or the like. In further embodiments, the first thermal control layer 118a may include a solid-liquid phase change material, such as paraffin or the like. Embodiments using solid-liquid phase change materials further include microchannels, or another method having a phase change material in a liquid state. In some embodiments, the first thermal control layer 118a may include a latent heat between approximately 10 Joule / gram (J / g) and approximately 150 Joule / gram, between approximately 5 Joule / gram and approximately 145 Joule / gram, or other similar values. In some embodiments, the first thermal control layer 118a is formed using one of ALD, CVD, PVD, or the like. In some embodiments, the first thermal control layer 118a has a first thickness between approximately 0.1 micrometers and 5 micrometers, between approximately 0.5 micrometers and 4 micrometers, between approximately 0.2 micrometers and 4.5 micrometers, or the like.

[0033] In some embodiments, as shown in the cross-sectional view 900b of FIG. 9B , before forming the first thermal control layer (see the first thermal control layer 118a of FIG. 9A ), the first high thermal conductivity layer 502a in the high thermal conductivity layer 502 is formed on the interlayer dielectric 107. The high thermal conductivity layer 502 includes a high thermal conductivity material such as diamond, cubic boron nitride (cubic BN), or the like. In some embodiments, the first high thermal conductivity layer 502a is formed at less than 400 degrees Celsius using a microwave plasma-enhanced chemical vapor deposition (MPCVD) process. In further embodiments, the first high thermal conductivity layer 502a includes a seed layer formed before the MPCVD process. The seed layer may be or include diamond nanoparticles, cubic boron nitride (cubic BN) films or nanoparticles, cubic boron phosphide films or nanoparticles, or the like. The final portion of the first thermal control layer 118a is formed by applying an MPCVD process to the seed layer. In some embodiments, the first high thermal conductivity layer 502a has a second thickness between approximately 200 nanometers and 5 micrometers, approximately 300 nanometers and 4 micrometers, approximately 100 nanometers and 4.5 micrometers, or the like. In some embodiments, the ratio of the second thickness of the first high thermal conductivity layer 502a to the first thickness of the first thermal control layer (see the first thermal control layer 118a of FIG. 9A ) is between approximately 1:1 and approximately 1:10.

[0034] As shown in the cross-sectional view 1000 of FIG. 10 , the bonding layer 112 is formed over the first thermal control layer 118a, and the second thermal control layer 118b and the third thermal control layer 118c are formed on the carrier substrate 110. In some embodiments, the bonding layer 112 is formed using a spin coating process, a spray coating process, or the like. In some embodiments, the bonding layer 112 includes an adhesive bonding material, such as benzocyclobutene (BCB) or the like. The bonding layer 112 has a first hardness that is lower than the second hardness of the thermal control layer 118. The first thermal control layer 118a can expand and contract when undergoing a phase change. The placement of the bonding layer 112 in contact with the first thermal control layer 118a results in a lower amount of stress from the contraction or expansion of the first thermal control layer 118a within the integrated device.

[0035] In some embodiments, the second thermal control layer 118b and / or the third thermal control layer 118c are omitted. The second thermal control layer 118b and the third thermal control layer 118c are formed on opposite sides of the carrier substrate 110. In some embodiments, the second thermal control layer 118b and the third thermal control layer 118c are formed using one of ALD, CVD, PVD, or the like. In some embodiments, the second thermal control layer 118b and the third thermal control layer 118c are or include the same material as the first thermal control layer 118a. In other embodiments, the second thermal control layer 118b and the third thermal control layer 118c are or include a different phase change material than the first thermal control layer 118a. In some embodiments, the second thermal control layer 118b and the third thermal control layer 118c have a second thickness of between approximately 0.1 microns and 5 microns, between approximately 0.5 microns and 4 microns, between approximately 0.2 microns and 4.5 microns, or the like.

[0036] In some embodiments, the second high thermal conductivity layer and / or the third high thermal conductivity layer in the high thermal conductivity layer (see the high thermal conductivity layer 502 of FIG. 5 ) are formed after or before forming the second thermal control layer 118 b and the third thermal control layer 118 c. That is, the second high thermal conductivity layer may be formed after the second thermal control layer 118 b, and the third high thermal conductivity layer may be formed before the third thermal control layer 118 c. Once the carrier substrate is bonded to the substrate (see the substrate 102 of FIG. 1 ) in the following step (see FIG. 11 ), the above method results in the second high thermal conductivity layer being located between the interconnect structure 106 and the second thermal control layer 118 b. In addition, the third high thermal conductivity layer will be located between the interconnect structure 106 and the third thermal control layer 118 c. The high thermal conductivity layer (see the high thermal conductivity layer 502 of FIG. 5 ) distributes the heat generated in the active component over the thermal control layer 118 , thereby resulting in an increased heat transfer rate into the thermal control layer 118 .

[0037] As shown in the cross-sectional view 1100 of FIG. 11 , the carrier substrate 110 is bonded to the substrate 102 using the bonding layer 112. That is, the second thermal control layer 118b (or the carrier substrate 110 if the second thermal control layer 118b is omitted) is placed against the bonding layer 112. The bonding layer 112 is then hardened. In some embodiments, the bonding layer 112 can be hardened at room temperature. In other embodiments, the bonding layer 112 can be hardened using one or more of ultraviolet light, applied pressure, or one or more heating cycles. The second thermal control layer 118b can expand and contract when undergoing a phase change. The placement of the bonding layer 112 in contact with the second thermal control layer 118b results in a lower amount of stress from deformation or expansion of the second thermal control layer 118b within the integrated device due to the relatively low hardness of the bonding layer 112.

[0038] As shown in the cross-sectional view 1200 of FIG. 12 , the thermal interface material 116 is formed over the carrier substrate 110. In embodiments where the third thermal control layer 118c is not omitted, the thermal interface material 116 is formed on the third thermal control layer 118c. The thermal interface material 116 is or includes a thermal interface material that conducts heat between the third thermal control layer 118c and a heat dissipation module to be formed below (see the heat dissipation module 114 of FIG. 1 ). In some embodiments, the thermal interface material 116 is or includes a thermal interface material such as a thermal glue, a thermal adhesive, or the like. The thermal interface material 116 has a lower hardness than the hardness of the thermal control layer 118. The third thermal control layer 118c can expand and contract when undergoing a phase change. The placement of the thermal interface material 116 in contact with the third thermal control layer 118c results in a lower amount of stress from deformation or expansion of the third thermal control layer 118c within the integrated device.

[0039] As shown in the cross-sectional view 1300 of FIG. 13 , the heat dissipation module 114 is thermally coupled to the carrier substrate 110 via the thermal interface material 116. The heat dissipation module 114 is or includes a thermally conductive material, such as a metal or the like. In some embodiments, the heat dissipation module 114 is coupled to one of the substrate 102, the second substrate (see the second substrate 301 of FIG. 3 ), or the multilayer board (see the multilayer board 320 of FIG. 3 ) using an adhesive, a welding process, or the like.

[0040] FIGS. 14-18 illustrate a series of cross-sectional views 1400 to 1800 of some embodiments of methods of forming one or more patterned thermal control layers disposed between an interconnect structure and an external sidewall of a semiconductor package. FIGS. 14-15 illustrate a first method of forming a patterned thermal control layer and in some embodiments replace FIG. 9A. FIGS. 16-19 illustrate a second method of forming a patterned thermal control layer and in some embodiments replace FIG. 9A. The methods illustrated in FIGS. 14-15 and 16-18 may also be used when forming a second thermal control layer (see second thermal control layer 118b of FIG. 10) and / or a third thermal control layer (see third thermal control layer 118c of FIG. 10), and different methods may be used to pattern different thermal control layers 118.

[0041] As shown in the cross-sectional view 1400 of FIG. 14 , after forming the interconnect structure 106, an etching process is performed on the uppermost layer of the interlayer dielectric 107 (also the underlying layer relative to the first thermal control layer (see the first thermal control layer 118a of FIG. 1 )). The etching process is performed by first forming and patterning a first masking layer 1404 on the upper surface of the interlayer dielectric. In some embodiments, the first masking layer 1404 is a photoresist and is patterned using lithography. After patterning the photoresist, the interlayer dielectric 107 is patterned using a dry etching process 1402 according to the plurality of openings in the first masking layer 1404. The dry etching process 1402 forms a plurality of openings 1406 in the interlayer dielectric 107. After the dry etching process 1402, the first masking layer 1404 is removed.

[0042] As shown in the cross-sectional view 1500 of FIG. 15 , the first thermal control layer 118a is formed within a plurality of openings (see openings 1406 of FIG. 14 ) in the underlying layer. The deposition process used to form the first thermal control layer 118a causes the first thermal control layer 118a to conform to and fill the plurality of openings (see openings 1406 of FIG. 14 ). Filling the plurality of openings results in the first thermal control layer 118a having a plurality of protrusions extending into the underlying layer. Thus, the first thermal control layer 118a can have an increased surface area obtained from patterning without directly etching the first thermal control layer 118a. A second thermal control layer (see second thermal control layer 118b of FIG. 4 ) and a third thermal control layer (see third thermal control layer 118c of FIG. 4 ) can also be formed using this technique by patterning opposite sides of a carrier substrate (see carrier substrate 110 of FIG. 4 ). The patterned carrier substrate (see carrier substrate 110 of FIG. 1 ) enables the second thermal control layer (see second thermal control layer 118 b of FIG. 4 ) and the third thermal control layer (see third thermal control layer 118 c of FIG. 4 ) to have a larger surface area on one side when formed (see FIG. 10 ), thereby increasing the heat transfer rate between the thermal control layer 118 and the carrier substrate (see carrier substrate 110 of FIG. 1 ).

[0043] As shown in the cross-sectional view 1600 of FIG. 16 , the first thermal control layer 118 a is formed on the interlayer dielectric 107 , as described with respect to the steps in FIG. 9A .

[0044] As shown in the cross-sectional view 1700 of FIG. 17 , an etching process is performed on the first thermal control layer 118 a. The etching process is performed by first forming and patterning a second masking layer 1704 on the upper surface of the interlayer dielectric. In some embodiments, the second masking layer 1704 is a photoresist and is patterned using lithography. After patterning the photoresist, a dry etching process 1702 is used to pattern the first thermal control layer 118 a according to the plurality of openings in the second masking layer 1704. The dry etching process 1702 forms a plurality of openings 1706 in the first thermal control layer 118 a and leaves a plurality of protrusions extending from the first thermal control layer 118 a. After the dry etching process 1702, the second masking layer 1704 is removed.

[0045] As shown in the cross-sectional view 1800 of FIG. 18 , the bonding layer 112 is formed within a plurality of openings (see openings 1706 of FIG. 17 ) in the first thermal control layer 118a. The process used to form the bonding layer 112 causes the bonding layer 112 to conform to and fill the plurality of openings (see openings 1706 of FIG. 17 ). Thus, the first thermal control layer 118a may have an increased surface area contacting the bonding layer 112, which may increase the bonding strength and increase the heat transfer rate between the first thermal control layer 118a and the bonding layer 112. The second thermal control layer (see second thermal control layer 118b of FIG. 1 ) and the third thermal control layer (see third thermal control layer 118c of FIG. 1 ) may also be formed using this technique by patterning the thermal control layer 118 after it is formed on a carrier substrate (see carrier substrate 110 of FIG. 1 ). The patterned carrier substrate (see carrier substrate 110 of FIG. 1 ) causes the second thermal control layer (see second thermal control layer 118 b of FIG. 1 ) and the third thermal control layer (see third thermal control layer 118 c of FIG. 1 ) to have a larger surface area on one side when formed (see FIG. 10 ), thereby increasing the heat transfer rate between the thermal control layer 118 and the carrier substrate (see carrier substrate 110 of FIG. 1 ).

[0046] FIG. 19 illustrates a flow chart of some embodiments of a method of forming one or more patterned thermal control layers disposed between an interconnect structure and an external sidewall of a semiconductor package. Although this method and other methods shown and / or described herein are shown as a series of actions or events, it will be appreciated that the present disclosure is not limited to the order or actions shown. Thus, in some embodiments, the actions may be performed in an order different from that shown and / or may be performed simultaneously. Additionally, in some embodiments, the actions or events shown may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included. [ , , ]

[0047] At 1902, one or more active components are formed on a substrate. See, for example, FIG. 7 .

[0048] At 1904, an interconnect structure is formed over the active component. See, for example, FIG. 8 .

[0049] At 1906, a first thermal control layer is formed over the interconnect structure. See, for example, FIG. 9A.

[0050] At 1908, a bonding layer is formed over the first thermal control layer. See, for example, FIG. 10 .

[0051] At 1910, a second thermal control layer and a third thermal control layer are formed on a carrier substrate. See, for example, FIG. 10 .

[0052] At 1912, a carrier substrate or a second thermal control layer is bonded to the bonding layer. See, for example, FIG. 11 .

[0053] At 1914, a thermal interface material (TIM) is disposed on a carrier substrate or a third thermal control layer. See, for example, FIG. 12 .

[0054] At 1916, the heat sink module is thermally coupled to the TIM. See, for example, FIG. 13 .

[0055] Some embodiments relate to an integrated device, comprising: a substrate having at least one active component; an interconnect structure disposed on the substrate; a bonding layer disposed above the interconnect structure; a carrier substrate disposed above the bonding structure; a heat dissipation module disposed above the carrier substrate; and a first thermal control layer disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, wherein the first thermal control layer comprises a phase change material (PCM). In some embodiments, the integrated device further comprises a high thermal conductivity layer located on a first side of the first thermal control layer. In some embodiments, the integrated device further comprises a second thermal control layer disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, which is different from the first thermal control layer. In some embodiments, the integrated device further comprises a third thermal control layer disposed between the carrier substrate and the heat dissipation module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, which is different from the first thermal control layer and the second thermal control layer. In some embodiments, the first thermal control layer comprises a solid-solid phase change material (SS-PCM). In some embodiments, the SS-PCM is a shape memory alloy.

[0056] Other embodiments are related to an integrated device, comprising: a substrate; an active component located on the substrate; an interconnect structure coupled to the active component; a heat dissipation module disposed above the interconnect structure; and a first thermal control layer disposed between the interconnect structure and the heat dissipation module, wherein the first thermal control layer comprises a solid-solid phase change material (SS-PCM). In some embodiments, the integrated device further comprises a thermal interface material disposed on a first side of the first thermal control layer, wherein the thermal interface material has a first hardness lower than a second hardness of the first thermal control layer. In some embodiments, the first thermal control layer has a first side and a first plurality of protrusions extending from the first side. In some embodiments, the first thermal control layer also has a second side opposite to the first side, and wherein the integrated device further comprises a high thermal conductivity layer covering the second side of the first thermal control layer. In some embodiments, the integrated device further comprises: a carrier substrate disposed between the first thermal control layer and the heat dissipation module; and a second thermal control layer disposed between the carrier substrate and the heat dissipation module. In some embodiments, the second thermal control layer comprises a second side and a second plurality of protrusions extending from the second side, wherein the first plurality of protrusions and the second plurality of protrusions extend into the carrier substrate. In some embodiments, the integrated device further includes: a bonding layer located between the internal connection structure and the first thermal control layer; and a third thermal control layer located between the bonding layer and the internal connection structure, wherein the third thermal control layer includes a third side and a third plurality of protrusions extending from the third side, and wherein the third plurality of protrusions extend toward the internal connection structure.

[0057] Still other embodiments are directed to a method of forming an integrated device, comprising: providing a substrate; forming an active component on the substrate; forming an interconnect structure on the substrate; bonding a carrier substrate to the interconnect structure; forming a thermal interface material on the carrier substrate; positioning a heat dissipation module on the carrier substrate, wherein the thermal interface material thermally couples the carrier substrate to the heat dissipation module; and forming a first thermal control layer on the interconnect structure or the carrier substrate after forming the interconnect structure and before positioning the heat dissipation module. In some embodiments, forming the first thermal control layer further comprises: forming the first thermal control layer on the carrier substrate before the carrier substrate is disposed on the interconnect structure; and forming a bonding layer on the interconnect structure, wherein after the carrier substrate is disposed on the interconnect structure, the carrier substrate and the first thermal control layer are mechanically coupled to the substrate by the bonding layer. In some embodiments, forming the first thermal control layer further includes: before the carrier substrate is disposed on the interconnect structure, forming a second thermal control layer on the carrier substrate, wherein the second thermal control layer is separated from the first thermal control layer by the carrier substrate; and bonding one of the first thermal control layer or the second thermal control layer to the bonding layer. In some embodiments, forming the first thermal control layer further includes: etching a plurality of grooves into one or more of the carrier substrate or the interconnect structure; and depositing the material of the first thermal control layer in a plurality of trenches, so that the first thermal control layer has a first plurality of protrusions extending into one of the carrier substrate or the interconnect structure. In some embodiments, the method further includes forming a bonding layer on the interconnect structure; and when the first thermal control layer is to be located between the carrier substrate and the bonding layer, forming a first high thermal conductivity layer after forming the first thermal control layer, so that the first high thermal conductivity layer is located between the first thermal control layer and the bonding layer. In some embodiments, forming the first thermal control layer further comprises: depositing the material of the first thermal control layer onto a carrier substrate or an interconnect structure; and etching a plurality of trenches into the first thermal control layer to expose a first plurality of protrusions of the first thermal control layer, so that the first thermal control layer has a first plurality of protrusions extending away from one of the carrier substrate or the interconnect structure. In some embodiments, when the first thermal control layer is to be formed on the interconnect structure, a first high thermal conductivity layer is formed before forming the first thermal control layer, so that the first high thermal conductivity layer is located between the first thermal control layer and the interconnect structure.

[0058] It should be understood that in this written description and in the following claims, the terms "first", "second", "third", etc. are merely general identifiers used to distinguish different elements of a figure or series of figures for ease of description. By themselves, these terms do not imply any temporal order or structural proximity of these elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or unillustrated embodiments. For example, a "first dielectric layer" described in conjunction with a first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an unillustrated embodiment.

[0059] The foregoing summarizes the features of several embodiments so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those with ordinary knowledge in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those with ordinary knowledge in the art can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0060] 100, 300, 400, 500, 600a, 600b, 700, 800, 900a, 900b, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800: Cross-sectional views 102: Base 104: Semiconductor device 106:Internal connection structure 106a: Wire level 106b: Through hole level 107: Interlayer dielectric 108: Contact 110: carrier substrate 112: Bonding layer 114: Heat dissipation module 116: Thermal interface material 118: Thermal control layer 118a: first thermal control layer 118b: Second thermal control layer 118c: Third thermal control layer 200: Graph 202: Heating stage 204: Cooling phase 206: Materials without phase change 208, 212: Part I 209: First phase transition zone 210, 214: Part 2 213: Second phase transition zone 301: Second base 302: Controlled Collapse Wafer Connection 303: Second internal connection structure 304: Bonding pad layer 305: back metal layer 306: Heat sink 307:Logical layer 308:Solder ball 310: Controlled collapse wafer connection layer 314: Second plurality of through holes 316:Ball Grid Array Package 317: Top metal layer 318: Wire layer 320:Multilayer board 502: High thermal conductivity layer 502a: first high thermal conductivity layer 1402, 1702: Dry etching process 1404: First mask layer 1406, 1706: Opening 1704: Second mask layer 1902, 1904, 1906, 1908, 1910, 1912, 1914, 1916: Action

Claims

1. An integrated device, comprising: a substrate including at least one active component; An internal connection structure is disposed on the substrate; A bonding layer, disposed above the inner connection structure; A carrier substrate is disposed above the inner connection structure; A heat dissipation module is disposed above the carrier substrate; and a first heat control layer, which is disposed between the carrier substrate and the heat dissipation module, the bonding layer and the inner connection structure, or the carrier substrate and the bonding layer, wherein the first heat control layer comprises a phase change material.

2. The integrated device of claim 1, further comprising a high thermal conductivity layer located on the first side of the first thermal control layer.

3. The integrated circuit device as described in claim 1 further includes a second thermal control layer, which is arranged between the carrier substrate and the heat dissipation module, the bonding layer and the internal connection structure, or the carrier substrate and the bonding layer, which is different from the first thermal control layer.

4. The integrated circuit device as described in claim 3 further includes a third thermal control layer, which is arranged between the carrier substrate and the heat dissipation module, the bonding layer and the internal connection structure, or the carrier substrate and the bonding layer, which is different from the first thermal control layer and the second thermal control layer.

5. The integrated device of claim 1, wherein the first thermal control layer comprises a solid-solid phase change material.

6. An integrated device as described in claim 5, wherein the solid-solid phase change material comprises a shape memory alloy.

7. An integrated device comprising: substrate; an active component, located on the substrate; an internal connection structure coupled to the active component; A heat dissipation module is arranged above the inner connection structure; and a first heat control layer disposed between the inner connection structure and the heat dissipation module, wherein the first heat control layer comprises a phase change material.

8. The integrated device of claim 7, wherein the first thermal control layer comprises a solid-solid phase change material.

9. The integrated device of claim 7, wherein the first thermal control layer comprises a first side and a first plurality of protrusions extending from the first side.

10. The integrated device of claim 9, wherein the first thermal control layer further comprises a second side opposite to the first side, and wherein the integrated device further comprises a high thermal conductivity layer covering the second side of the first thermal control layer.

11. The integrated device of claim 9, further comprising: A carrier substrate, disposed between the first heat control layer and the heat dissipation module; and a second heat control layer, which is arranged between the carrier substrate and the heat dissipation module.

12. The integrated device of claim 11, wherein the second thermal control layer comprises a second side and a second plurality of protrusions extending from the second side, wherein the first plurality of protrusions and the second plurality of protrusions extend into the carrier substrate.

13. The integrated device of claim 12, further comprising: a bonding layer, located between the inner connection structure and the first thermal control layer; and a third thermal control layer located between the bonding layer and the interconnect structure, wherein the third thermal control layer comprises a third side and a third plurality of protrusions extending from the third side, and wherein the third plurality of protrusions extend toward the interconnect structure.

14. A method of forming an integrated device, comprising: providing a substrate; forming an active component on the substrate; forming an internal connection structure on the substrate; bonding a carrier substrate onto the interconnect structure; forming a thermal interface material over the carrier substrate; positioning a heat sink module over the carrier substrate, wherein the thermal interface material thermally couples the carrier substrate to the heat sink module; And after forming the inner connection structure and before positioning the heat dissipation module, forming a first heat control layer on the inner connection structure or the carrier substrate.

15. The method for forming an integrated device according to claim 14, wherein forming the first thermal control layer further comprises: Before the carrier substrate is disposed on the interconnect structure, forming the first thermal control layer on the carrier substrate; and forming a bonding layer on the interconnect structure, wherein after the carrier substrate is disposed above the interconnect structure, the bonding layer is used to mechanically couple the carrier substrate and the first thermal control layer to the substrate.

16. The method for forming an integrated device according to claim 15, wherein forming the first thermal control layer further comprises: Before the carrier substrate is disposed on the interconnect structure, a second thermal control layer is formed on the carrier substrate, wherein the second thermal control layer is separated from the first thermal control layer by the carrier substrate; and one of the first thermal control layer or the second thermal control layer is bonded to the bonding layer.

17. The method for forming an integrated device according to claim 14, wherein forming the first thermal control layer further comprises: etching a plurality of grooves into one or more of the carrier substrate or the interconnect structure; and depositing material of the first thermal control layer within the plurality of grooves so that the first thermal control layer has a first plurality of protrusions extending into one of the carrier substrate or the interconnect structure.

18. The method for forming an integrated device as described in claim 14 further includes forming a bonding layer on the internal connection structure; and when the first thermal control layer is to be located between the carrier substrate and the bonding layer, forming a first high thermal conductivity layer after forming the first thermal control layer, so that the first high thermal conductivity layer is located between the first thermal control layer and the bonding layer.

19. The method for forming an integrated device according to claim 14, wherein forming the first thermal control layer further comprises: Depositing the material of the first thermal control layer onto the carrier substrate or the interconnect structure; and etching a plurality of trenches into the first thermal control layer to expose a plurality of first protrusions of the first thermal control layer, so that the first thermal control layer has the first plurality of protrusions extending away from one of the carrier substrate or the interconnect structure.

20. A method for forming an integrated device as described in claim 14, wherein when the first thermal control layer is to be formed on the internal connection structure, a first high thermal conductivity layer is formed before forming the first thermal control layer, so that the first high thermal conductivity layer is located between the first thermal control layer and the internal connection structure.