Backside contact structures, fabrication for metal on both sides of devices and computing device

Abstract

A device including a circuit structure comprising a device layer including a plurality of devices including a first side and an opposing second side; and a metal interconnect coupled from the second side of the device layer to at least one of the plurality of devices. A method comprising forming a transistor device including a channel region between a source region and a drain region and a gate electrode on a channel defining a first side of the device; and forming an interconnect from the second side of the device to one of the source region and the drain region.

Description

Technical Field

[0001] A semiconductor device includes the device having an electrical connection from the back side of the device. Prior Art In the past few decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features enables an increase in the density of functional units on a limited area of a semiconductor wafer. For example, shrinking transistor sizes allows for a larger number of memory devices to be incorporated on a wafer, thereby enabling the manufacture of products with increased capacity. However, driving ever-increasing capacity is not without problems. The need to optimize the performance of each device becomes increasingly important. Future circuit devices, such as central processing unit devices, will be expected to integrate high-performance devices and low-capacitance, low-power devices on a single die or wafer. Brief Description of the Drawings 100, 400: Structure 110, 410: Substrate 120, 420: Buffer layer 125, 425: Gate 127, 427: Gate dielectric layer 130, 430: Fin 140A, 440A: Source 140B, 440B: Drain 150, 450: Spacer 155, 155A, 155B, 155C, 181, 455A, 455B, 481: Dielectric material 160A, 160B, 170, 460A, 460B, 470, 520, 530: Interconnect 165A, 165B, 175, 186A, 186B, 190A, 196A, 465, 465A, 465B, 475: Contact 180, 480: Carrier 182A, 182B, 482A, 482B: Opening 185A, 185B: Epitaxially grown material 284, 384: Modified portion 285, 285A, 485A, 485B: Epitaxial material 286A, 286B, 386A, 386B, 486A, 486B: Contact metal 385: Implant material 453: Sacrificial material 500: Component 510: Die 515: Device layer 540: Carrier substrate 550: Contact point 590: Package 600: Process 610, 620, 625, 630, 635, 640, 645, 650, 655, 660, 670, 680: Square 700: Inserter 702: First substrate 704: Second substrate 706: Ball grid array 708: Metal contact 710: Through hole 712: Through-silicon via 714: Embedded device 800: Computing device 802: Integrated circuit die 804: CPU 806: Memory on die 808: Communication chip 810: Volatile memory 812: Non-volatile memory 814: Graphics processing unit 816: Digital signal processor 820: Chipset 822: Antenna 824: Touch screen display 826: Touch screen controller 828: Battery 832: Motion co-processor or sensor 834: Speaker 836: Camera 838: User input device 840: Mass storage device 842: Encryption processor 844: Global Positioning System (GPS) device FIG. 1 shows an upper side perspective view of a three-dimensional transistor device on a fin formed on a portion of a silicon-on-insulator (SOI) substrate. FIGS. 2A-2C show cross-sectional side views through FIG. 1. FIG. 3 shows the structure of FIG. 1 after formation of contacts and interconnects to the three-dimensional transistor device. FIGS. 4A-4C show cross-sectional side views through FIG. 2. FIGS. 5A-5C show the structure of FIG. 3 after inversion or flipping of the structure and connection of the structure to the carrier. FIGS. 6A-6C show the structure of FIGS. 5A-5C after removal or thinning of the transistor device to expose the second side or back side of the fins of the transistor device. FIGS. 7A-7C show recesses in the fins. FIGS. 8A-8C show the structure of FIGS. 7A-7C after deposition of dielectric material and patterning of source and drain regions on the back side of the fins of the transistor device with openings. FIGS. 9A-9C show the structure of FIGS. 8A-8C after epitaxial growth of material for back side junction formation in the back side openings to the source and drain regions. FIGS. 10A-10C show the structure of FIGS. 9A-9C after filling the via openings in the dielectric material 180 with conductive contact material. FIGS. 11A-11C show the structure of FIGS. 10A-10C and show interconnects connected to the source contact of the transistor device as part of a first back side interconnect or metal layer. FIGS. 12A-12C show the structure of FIGS. 8A-8C after deposition of doped epitaxial material in the openings to the source and drain regions according to another embodiment of a device for forming contacts from the back side of such a device. FIGS. 13A-13C show the structure of FIGS. 12A-12C after driving dopants from the epitaxial material into the fins in the source and drain regions of the device. FIGS. 14A-14C show the structure of FIGS. 13A-13C after selective removal of the epitaxial material after the dopant drive-in process. FIGS. 15A-15C show the structure of FIGS. 14A-14C after introduction of contact metal in regions aligned with the source and drain. FIGS. 16A-16C show the structure of FIGS. 8A-8C after introduction of implants into regions of the fins of the device aligned with the source and drain regions according to another embodiment of a device for forming contacts from the back side of the device structure. FIGS. 17A-17C show the structure of FIGS. 16A-16C after introduction of contact metal in regions aligned with the source and drain of the device. FIG. 18 shows a top perspective view of a three-dimensional transistor device on a fin formed on a portion of a semiconductor-on-insulator (SOI) substrate according to another embodiment in which a sacrificial material is introduced at the base of the fins in the source and drain regions. Figures 19A - 19C show cross - sectional side views through the structure of FIG. 18. Figures 20A - 20C show the introduction of dielectric material on the first - level interconnects; the inversion or flipping of the structure and connection to the carrier; substrate thinning and fin recess; and the structure of FIGS. 19A - 19C after defining the regions of the fins for source and drain connections to the device on the backside. Figures 21A - 21C show the structure of FIGS. 20A - 20C after removing sacrificial material near the opposite sidewalls of the fins in the source and drain regions. Figures 22A - 22C show the structure following epitaxial growth of materials for back - side contact formation and formation of contacts on the backside of the device. Figure 23 shows a cross - sectional schematic side view of one embodiment of an assembly including an integrated circuit die or chip connected to a package substrate. Figure 24 is a process flow diagram for forming contacts to the source and drain of a three - dimensional transistor device from the backside and backside metallization. Figure 25 is an inserter implementing one or more embodiments. Figure 26 illustrates an embodiment of a computing device. SUMMARY OF THE INVENTION SUMMARY OF THE INVENTION AND EMBODIMENTS Embodiments described herein relate to semiconductor devices including interconnects or wiring on the backside or beneath the device. Such embodiments are achieved by using back - side exposure and back - side processing. The described embodiments include an apparatus including a circuit structure that includes a device layer or a layer including a plurality of devices having a first side and an opposite second side, and metal interconnects connected to at least one of the plurality of devices from the second side of the layer. Embodiments for forming such devices are also described, including examples of back - side epitaxial deposition, back - side implantation, and back - side epitaxial deposition and drive - in. Back - side exposure processing allows flexibility in the types of connections that can be fabricated. Figures 1 - 10C describe a method or process for forming a non - planar multi - gate semiconductor device including electrical connections on the non - device side or the backside of the structure. In one embodiment, the device is a three - dimensional metal - oxide - semiconductor field - effect transistor (MOSFET) and is an isolated device or one device among a plurality of nested devices. As will be appreciated, for a typical integrated circuit, both N - type channel transistors and P - type channel transistors can be fabricated on a single substrate to form a complementary metal - oxide - semiconductor (CMOS) integrated circuit. Additionally, additional interconnects can be fabricated to integrate such devices into an integrated circuit. In the fabrication of non-planar transistors such as multi-gate transistors and FinFETs, non-planar semiconductor bodies can be used to form transistors that can typically be fully depleted with a relatively small gate length (e.g., less than about 30 nm). These semiconductor bodies are typically fin-shaped and are thus often referred to as transistor "fins". For example, in a triple-gate transistor, the transistor fin has a top surface and two opposing sidewalls formed on a bulk semiconductor substrate or a silicon substrate on an insulating layer. A gate dielectric can be formed on the top or upper surface and sidewalls of the semiconductor body, and a gate electrode can be formed on the top or upper surface of the semiconductor body and adjacent to the gate dielectric on the sidewalls of the semiconductor body. Since the gate dielectric and the gate electrode are adjacent to three surfaces of the semiconductor body, three separate channels and gates are formed. Since three separate channels are formed, the semiconductor body can be fully depleted when the transistor is turned on. Regarding finFET transistors, the gate material and the electrode contact the sidewalls of the semiconductor body, such that two separate channels are formed. FIG. 1 shows a top side perspective view of a portion of a semiconductor-on-insulator (SOI) substrate, i.e., a portion of an integrated circuit die or wafer on a wafer, for example. Specifically, FIG. 1 shows a structure 100 including a substrate 110 of silicon or SOI. Overlying substrate 110 is a selective buffer layer 120. In one embodiment, the buffer layer is a silicon-germanium buffer layer introduced on substrate 110 by a growth technique in one embodiment. Representatively, buffer layer 120 has a representative thickness of about a few hundred nanometers (nm). In the embodiment shown in FIG. 1 (the observed upper surface), disposed on the surfaces of substrate 110 and selective buffer layer 120 is a portion of a transistor device such as an N-type transistor device or a P-type transistor device. In this embodiment, the common feature of the N-type or P-type transistor device is a body or fin 130 disposed on the surface of buffer layer 120. In one embodiment, fin 130 is formed of a semiconductor material such as silicon, silicon-germanium, or a III-V or IV-V semiconductor material. In one embodiment, the material of fin 130 is formed according to conventional processing techniques for forming three-dimensional integrated circuit devices. Representatively, the semiconductor material is epitaxially grown on the substrate and then formed into fin 130 (e.g., by a masking and etching process). In one embodiment, the fin 130 has a length dimension (L) greater than the height dimension (H). Representative length ranges are on the order of 10 nanometers (nm) to 1 millimeter (mm), and representative height ranges are on the order of 5 nm to 200 nm. The fin 130 also has a width (W) that is typically about 4 - 10 nm. As shown, the fin 130 is a three-dimensional body extending from the surface of the substrate 110 (or optionally from or on the buffer layer 120). The three-dimensional body shown in FIG. 1 is a rectangular body having opposite sides (a first side and a second side) protruding from the surface of the observed buffer layer 120. It should be understood that when processing such a body, a truly rectangular shape may not be achievable with available tools and other shapes may result. Representative shapes include, but are not limited to, trapezoidal shapes (e.g., the base wider than the top) and arched shapes. In an embodiment of the structure of FIG. 1, a gate stack is disposed on the fin 130. In one embodiment, the gate stack includes a gate dielectric layer such as silicon dioxide or a dielectric material having a dielectric constant greater than that of silicon dioxide (a high-k dielectric material). In one embodiment, a gate 125, such as a metal, is disposed on the gate dielectric layer. The gate stack may include dielectric material spacers 150 on its opposite sides. Representative materials for the spacers 150 are low-k materials such as silicon nitride (SiN) or silicon carbonitride (SiCN). FIG. 1 shows the sidewalls of the gate stack adjacent to and the spacers 150 on the fin 130. Formed on or in the fin 130 on opposite sides of the gate stack are junction regions (source 140A and drain 140B). In one embodiment, to form a three-dimensional transistor structure, a gate dielectric material is formed on the fin 130, for example, by blanket deposition, followed by blanket deposition of a sacrificial or dummy gate material. A masking material is introduced onto the structure and patterned to protect the gate stack material (the gate stack with the sacrificial or dummy gate material) over a designated channel region. Then an etching process is used to remove the gate stack material in the undesired regions and pattern the gate stack over the designated channel region. The spacers 150 are then formed. One technique for forming the spacers 150 is to deposit a thin film on the structure, protect the thin film in the desired regions, and then etch to pattern the thin film into the desired spacer dimensions. After forming a gate stack including sacrificial or dummy gate material on the fin 130 and the spacer 150, a junction region (source and drain) is formed on or in the fin 130. The source and drain are formed in the fin 130 on opposite sides of the gate stack (sacrificial gate electrode on the gate dielectric). In the embodiment shown in FIG. 1, the source 140A and the drain 140B are formed by epitaxially growing source and drain materials as a blanket layer on a portion of the fin 130. Representative materials for the source 140A and the drain 140B include but are not limited to silicon, silicon germanium, or group III-V or IV-V compound semiconductor materials. The source 140A and the drain 140B can alternatively be formed by removing a portion of the fin material and epitaxially growing source and drain materials in the designated junction regions where the fin material is removed. In one embodiment, after forming the source 140A and the drain 140B, the sacrificial or dummy gate is removed and replaced with a gate electrode material. In one embodiment, before removing the sacrificial or dummy gate stack, a dielectric material is deposited on the structure. In an embodiment, the dielectric material is deposited as a blanket of silicon dioxide or a low-k material and then polished to expose the sacrificial or dummy gate 125. The sacrificial or dummy gate and the gate dielectric are then removed by, for example, an etching process. After removing the sacrificial or dummy gate and the gate dielectric, a gate stack is formed within the gate electrode region. The gate stack is introduced (e.g., deposited) on a structure including a gate dielectric and a gate electrode. In an embodiment, the gate electrode 125 of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a material having a dielectric constant greater than that of silicon dioxide (a high-k material). For example, in one embodiment, the gate dielectric layer 127 (see FIGS. 2A-2C) is composed of materials such as but not limited to hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. In one embodiment, the gate electrode 125 is composed of a metal layer, such as but not limited to metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. After the formation of the gate stack, a dielectric material of additional silicon dioxide or low-k dielectric material is deposited on the three-dimensional transistor device (e.g., ILD0) to encapsulate or embed the device structure in the dielectric material. FIG. 1 shows the dielectric material 155A that encapsulates the three-dimensional transistor device (e.g., as ILD0). Figures 2A-2C show cross-sectional side views through the cross-section of FIG. 1. More specifically, FIG. 2A shows a cross-sectional side view through line A-A' of FIG. 1, which is a cross-section through fin 130; FIG. 2B shows a cross-section through line B-B', which is a cross-section through source 140A; and FIG. 2C shows a cross-section through line C-C', which is a cross-section through gate electrode 125. The same cross-sectional orientation (A-C) will be presented throughout the specification. FIG. 3 shows the structure of FIG. 1 after the formation of interconnects to a three-dimensional transistor device structure. In this embodiment, electrical connections are made to a first interconnect layer or metal layer to source 140A, drain 140B, and gate electrode 125. Representatively, to form separate electrical contacts to source 140A, drain 140B, and gate electrode 175, openings are initially formed to the source and gate electrodes by a mask process having openings, for example, to each of source 140A, drain 140B, and gate electrode 125. The dielectric material is etched to expose the source and gate electrodes and then the mask material is removed. Next, a contact material such as tungsten is introduced into the opening, and the opening is filled to form contact 165A to source 140A, contact 165B to drain 140B, and contact 175 to gate electrode 125. The surface of dielectric material 155 (the observed top surface) can then be seeded with a conductive seed material and then patterned with a mask material to define openings for interconnect paths for corresponding openings having exposed contacts 165A, contact 165B, and contact 175. A conductive material such as copper is then formed by an electroplating process to form interconnect 160A connecting to contact 165A to source 140A, interconnect 160B connecting to contact 165B, and interconnect 170 connecting to contact 175 to gate electrode 125. The mask material and unwanted seed material can then be removed. After the formation of the interconnects as the initial metal layer, a dielectric material 155B such as silicon dioxide or a low-k dielectric material can be deposited as an ILD1 layer on and surrounding the interconnects. According to conventional processes, additional interconnect layers can then be formed. Figures 4A-4C show cross-sectional side views through the cross-section of FIG. 2. More specifically, FIG. 4A shows a cross-section through fin 130 through line A-A'; FIG. 4B shows a cross-section through source 140A through line B-B'; and FIG. 4C shows a cross-sectional side view through gate electrode 125 through line C-C'. As shown in FIGS. 3 and 4A-4C, the first-level interconnects are formed and connected to the transistor device on substrate 110. It should be understood that additional interconnect or metallization layers can be formed at this first level by techniques known in the art. Thus, subsequent operations consider a structure (structure 100) having one or more levels of interconnects or metallization on the device side of the structure (the device side of the device layer). Figures 5A-5C show the structure of Figure 3 after inversion or flipping and structural connection to a carrier. Figures 5A-5C respectively represent cross-sections through fins 130, drain 140B, and gate electrode 125 as described with respect to Figures 2A-2C and Figures 4A-4C. Referring to Figures 5A-5C, in this embodiment, structure 100 is inverted and connected to carrier 180. Carrier 180 is, for example, a semiconductor wafer. Structure 100 can be connected to carrier 180 by an adhesive or other bonding technique. Figures 6A-6C show the structure of Figures 5A-5C after removal or thinning of substrate 110 to expose the second or back side of fins 130. In one embodiment, substrate 110 can be removed by a thinning process, such as a mechanical grinding or etching process. Figures 6A-6C show fins 130 exposed from the second or back side of the structure. Following the exposure of fins 130, the fins can be selectively recessed. Figures 7A-7C show the structure of Figures 6A-6C after fins 130 are recessed. In one embodiment, for recessing fins 130, an etching process can utilize an etchant that selectively removes fin material relative to dielectric material 155A. Alternatively, a masking material can be patterned on the surface of dielectric material 155 (exposing the back side surface) having an opening that exposes fins 130. The material of fins 130 can be selectively removed, such as by an etching process, to recess fins 130, and then the masking material is removed. Figures 8A-8C show the structure of Figures 7A-7C after deposition and patterning of dielectric material on the back side of fins 130. Figures 8A-8C show dielectric material 181, such as silicon dioxide or a low-k dielectric material, deposited, for example, by a blanket deposition process. Once deposited, dielectric material 181 can be patterned by, for example, forming a masking material on the surface of dielectric material 180 having openings or vias opposite the source and drain regions on opposite sides of fins 130. Figure 8A shows opening 182A through dielectric material 181 oriented on the back side of fins 130 corresponding to the source region of the fin (source 140A) and opening 182B through dielectric material 181 of the fin (drain 140B). Figure 8B shows that the opening (e.g., opening 182A) has a diameter greater than the width dimension of fins 130. In this way, the back side of fins 130 as well as the sidewalls of fins 130 are exposed. Figure 8B also shows etching through the structure to expose the back side of source 140A. In one embodiment, dielectric material is patterned to form opening 182A and opening 182B such that each opening has a size that exposes the back sides of source 140A and drain 140B, respectively, while allowing material to contact the source and drain and, typically, allowing epitaxial growth thereon, as described in the following operations. Figures 9A-9C illustrate the epitaxial growth of materials for backside contact formation subsequent to the structures of Figures 8A-8C. Figure 9A shows the epitaxially grown material 185A in the region of the opening 182A aligned with the backside of the source 140A and the epitaxially grown material 185B of the fin 130 aligned with the backside of the drain 140B in the opening 182B. Figure 9B shows the material 185A growing epitaxially on the sidewalls of the fin 130 and connecting to the source 140A previously formed on the first side or device side of the structure. In one embodiment, the materials for the material 185A and the material 185B are similar to the materials used for the source 140A and the drain 140B (e.g., silicon, silicon germanium, or III-V or IV-V compound semiconductor materials). Figures 10A-10C illustrate the structures of Figures 9A-9C subsequent to filling the via openings in the dielectric material 180 with a conductive contact material such as tungsten. Figure 10A shows the contact 186A to the epitaxial material 185B associated with the source 140A and the contact metal 186B to the epitaxial material 185B associated with the drain 140B. Figure 10B shows the contact metal 186B to the epitaxial material 185B. Figures 10A and 10B show the connections to the source 140A (through the contact material) from opposite sides of the structure (the first side or device side and the backside or second side), respectively. Interconnections can now be formed to the contacts 186A and 186B by techniques described, for example, above with respect to device side interconnections (see Figures 3 and 4A-4C and the accompanying text). Figures 11A-11C illustrate the structures of Figures 10A-10C and show the interconnection 190A to the contact 196A connecting to the source 140A as part of, for example, a first backside interconnection or metal layer. Figures 11A-11C also show the structure subsequent to depositing the dielectric material 155C of silicon dioxide or a low-k dielectric material on the interconnection or metal layer. After the dielectric material 155C is deposited, one or more additional interconnect levels can be introduced on the dielectric material by, for example, electroplating techniques and connected to devices or underlying interconnections known in the art. Figures 12A-12C illustrate an alternative embodiment for forming contacts to a device from the backside of such a device. In this example, instead of epitaxially depositing in the contact regions around the fins, dopants are driven in after the epitaxial deposition of the doped epitaxial material to modify the fin portions in the contact regions. Figures 12A-12C illustrate the structures of Figures 8A-8C relative to the foregoing embodiments. Figures 13A-13C illustrate epitaxial material 285 introduced into opening 182A of dielectric material 181 and opening 182B of dielectric material 181 that respectively align source 140A and drain 140B on the back side of the device. Suitable materials for epitaxial material 285 are silicon-germanium materials for PMOS devices and silicon materials for NMOS devices. Other suitable materials for epitaxial material 285 for PMOS or NMOS devices include silicon, germanium, silicon-germanium, silicon-germanium-carbon, carbon-doped silicon (for NMOS only), germanium-tin, and III-V compound semiconductor materials such as gallium arsenide, indium arsenide, indium gallium arsenide, indium phosphide, and gallium nitride. Figures 13A-13C illustrate the structure of Figures 12A-12C after driving dopants from epitaxial material 285 into fin 130 from the back side in regions aligned with source 140A and drain 140B. One technique for driving dopants is a thermal process. Representatively, for epitaxial materials of phosphorus-doped silicon (for NMOS) and boron-doped silicon (for PMOS), thermal driving typically involves heating the structure to a temperature of 800 to 1100 °C for a sufficient period of time to allow the dopants to migrate from the epitaxial material into fin 130. Figures 13A-13C illustrate regions of fin 130 modified with dopant 284. Figures 14A-14C illustrate the structure of Figures 13A-13C after selectively removing epitaxial material 285A in openings 182A and opening 182B respectively after the dopant driving process. Figures 15A-15C illustrate the structure of Figures 14A-14C after introducing (e.g., depositing) contact metals in regions aligned with regions respectively connected to source 140A and drain 140B. Figure 15A illustrates contact metals 286A and 286B of tungsten, for example, in contact with a portion of fin 130 modified (modified with dopant), where such regions are aligned with source 140A and drain 140B. Figure 15B illustrates contact metal 286A disposed along opposite sidewalls of modified portion 284 and in contact with source 140A. After forming the contacts, interconnects or metal lines can be formed to contact the back side of the device as described above with respect to Figures 11A-11C and the accompanying text. Figures 16A-16C illustrate another embodiment of a device forming contacts from the back side of the device structure. Figures 16A-16C respectively illustrate the structure of Figures 8A-8C, in one embodiment, a structure formed according to the operations described up to and including Figures 8A-8C. In Figures 16A-16C, implants are introduced into fin 130 from the back side in regions respectively aligned with or opposite to (from a back-side perspective) source 140A and drain 140B. Figure 16A illustrates an implantation process introducing implant material 385 such as arsenic / phosphorus for NMOS devices or boron for PMOS devices. Figures 17A-17C illustrate the structures of Figures 16A-16C after introducing (e.g., depositing) contact metals in regions aligned with source 140A and drain 140B. Figure 17A illustrates contact metals 386A and 386B of tungsten, for example, in contact with a portion of fin 130 modified (modified with implants), where such regions are aligned with source 140A and drain 140B and are connected to source 140A and drain 140B, respectively. Figure 17B illustrates contact metal 386A disposed along opposite sidewalls of the modified portion 384 and in contact with source 140A. After forming the contacts, interconnects or metal lines can be formed to contact the backside of the device as described above with respect to Figures 11A-11C and the accompanying text. Figures 16A and 16B illustrate fin 130 modified with implant material 384. Figures 17A-17C illustrate the structures of Figures 16A-16C after introducing (e.g., depositing) contact metals in regions aligned with source 140A and drain 140B and having implant-modified portions of fin 130. Figure 17A illustrates contact metals 386A and 386B of tungsten, for example, in contact with the implant-modified portion of fin 130, where such regions are aligned with source 140A and drain 140B and are connected to source 140A and drain 140B, respectively. Figure 17B illustrates contact metal 386A disposed along the sidewalls of implant-modified portion 384 of fin 130 and in contact with source 140A. After contact formation to the backside of the device, interconnects or metal lines can be formed to the contacts as described in the previous embodiments (refer to Figures 11A-11C and the accompanying text). Figures 18-22C describe another embodiment of a method or process for forming a non-planar multi-gate semiconductor device including electrical connections on the non-device side or the backside of the structure. Figure 18 shows a top perspective view of a portion of a semiconductor-on-insulator (SOI) substrate, i.e., a portion of an integrated circuit die or wafer on a wafer, for example. Specifically, Figure 18 shows a structure 400 including a substrate 410 of silicon or SOI. Overlying substrate 410 is a selective buffer layer 420 such as silicon germanium. In the embodiment shown in Figure 18 (the observed upper surface), disposed on the surfaces of substrate 410 and selective buffer layer 420 is a portion of a transistor device such as an N-type transistor device or a P-type transistor device. In this embodiment, the common feature of the N-type or P-type transistor devices is a body or fin 430 disposed on the surface of substrate 410 or on buffer layer 420 (if present). In one embodiment, fin 430 is formed of a semiconductor material such as silicon, silicon germanium, or a III-V or IV-V semiconductor material. As shown, the fin 430 is a three-dimensional body extending from the surface of the substrate 410 (or optionally from or on the buffer layer 420) and has a height dimension H and a length dimension L greater than the height dimension and the width dimension. After forming the fin 430 from the substrate 410 or the optional buffer layer 420 or on the substrate 410 or the optional buffer layer 420, the sacrificial material 453 is introduced (e.g., deposited) along a portion of the opposite sidewalls of the fin. As shown in FIG. 18, the sacrificial material 453 is disposed on the opposite sidewalls of the fin 430 along the region of the length dimension designated for the junctions (source and drain). The sacrificial material 453 is disposed on or below the fin along the height dimension of the fin 430 in the region where the junctions are formed in the fin. In one embodiment, the three-dimensional transistor device including the fin 430 will be embedded in a dielectric material such as silicon dioxide or a low-k dielectric material. When the fin 430 is formed, the fin is exposed. At that point, the sacrificial material 453 can be introduced at a height h below the portion of the fin 430 where the junctions are to be formed by blanket deposition along the base of the fin 430. The representative height h of the sacrificial material is on the order of 10 nanometers (nm) to 100 nm. In one embodiment, where the fin 430 will later be recessed, a dielectric material layer of silicon dioxide or a low-k dielectric can be introduced on the base of the fin 430 after the introduction of the sacrificial material 453. The sacrificial material 453 can ultimately be removed to connect to the source and drain of the transistor device from the backside of the device. In one embodiment, the material for the sacrificial material 453 is a material that meets the thermal stability requirements of the processing environment and can be selectively etched relative to the dielectric material (e.g., SiO2) of the material that will ultimately be embedded in the device and the fin 430. Representative materials for the sacrificial material 453 are dielectric materials such as silicon nitride (SiN) or titanium nitride (TiN). Once the sacrificial material 453 is introduced, the material is patterned to a thickness t such that when the sacrificial material 453 is later removed, the sidewalls of the fin 430 are exposed from the backside of the structure, allowing the respective source and drain to make contact and / or epitaxially grow from the source and drain. After forming the sacrificial material 453 on the fin 430, the transistor device can be formed as described above with reference to FIG. 1 and the accompanying text. In this embodiment, the transistor device includes a gate dielectric layer such as silicon dioxide or a dielectric material having a dielectric constant greater than that of silicon dioxide (high-k dielectric material) and a gate 425 such as a metal disposed on the fin 430. The gate stack may include dielectric material spacers 450 on its opposite sides. Representative materials for the spacers 450 are low-k materials such as silicon nitride (SiN) or silicon carbonitride (SiCN). Formed on or in the fin 430 on opposite sides of the gate stack are junction regions (source 440A and drain 440B). In this embodiment, the source 440A and the drain 440B are formed to blanket the top and sidewalls of the fin 430. In one embodiment, the source 440A and the source 440B have a height dimension along the sidewalls that extends to the depth of the sacrificial material 453. FIG. 18 shows the structure 400 after embedding the transistor device in a dielectric material 455A (e.g., ILD0) and forming the interconnects to the three-dimensional transistor device structure. In this embodiment, electrical connections are made to a first interconnect layer or metal layer to the source 440A, the drain 440B, and the gate electrode 425. FIG. 18 shows that a contact material such as tungsten is introduced into the openings or vias of the dielectric material 455 to form a contact 465A to the source 440A, a contact 465B to the drain 440B, and a contact 475 to the gate electrode 425. FIG. 18 also shows a first metal or interconnect line or layer on the surface of the dielectric material 455 including an interconnect 460A connected to the contact 465A to the source 440A, an interconnect 460B connected to the contact 465B, and an interconnect 470 connected to the contact 475 to the gate electrode 425. After forming the interconnects as an initial metal layer, a dielectric material such as silicon dioxide or a low-k dielectric material can be deposited as an ILD1 layer on and surrounding the interconnects. According to a conventional process, additional interconnect layers can then be formed. FIGS. 19A-19C show cross-sectional side views through FIG. 18. More specifically, FIG. 19A shows a cross-section through the fin 430 along line A-A'; FIG. 19B shows a cross-section through the drain 440B along line B-B'; and FIG. 19C shows a cross-sectional side view through the gate electrode 425 along line C-C' and shows the gate dielectric 427 between the gate electrode 425 and the fin 430. Figures 20A - 20C show the introduction of dielectric material on the first - level interconnects; the inversion or flipping of the structure and the connection structure to the carrier; substrate thinning and fin recess; and the structure of Figures 19A - 19C after defining the regions of the fins for the source and drain connected to the device on the back - side. Figures 20A - 20C respectively show cross - sections through fin 430, drain 440B, and gate electrode 425. Referring to Figures 20A - 20C, in this embodiment, the first - level interconnects are passivated by a dielectric material 455B such as silicon dioxide or a low - k dielectric material. Then the structure 400 is inverted or flipped and connected to a carrier 480, such as a semiconductor wafer device - side down. The structure 400 can be connected to the carrier 480 through an adhesive or other bonding technique between the dielectric material 455B and the carrier 180. Figures 20A - 20C also show the structure of Figures 19A - 19C after removing or thinning the substrate 410, for example, by a mechanical grinding or etching process to expose the second or back - side of the fin 430. In one embodiment, the fin 430 is then selectively recessed. Figures 20A - 20C further show the structure after the deposition and patterning of dielectric material on the back - side of the fin 430. Figures 20A - 20C show a dielectric material 481 such as silicon dioxide or a low - K dielectric material deposited, for example, by a blanket deposition process. Once deposited, the dielectric material 481 is patterned by forming, for example, a mask material on the surface of the dielectric material 481 having openings or vias opposite the source and drain regions on opposite sides of the fin 430. Figure 20A shows an opening 482A through the dielectric material 481 oriented on the back - side of the fin 430 corresponding to the source region of the fin (source 440A) and an opening 482B through the dielectric material 481 oriented on the drain region of the fin (drain 440B). Figure 20B shows that the opening (e.g., opening 482A) has a diameter larger than the width dimension of the fin 430. In this way, the back - side of the fin 430 and the sacrificial material 453 are exposed. Figures 21A - 21C show the structure of Figures 20A - 20C after removing the sacrificial material 453 near the opposite sidewalls of the fin 430. In one embodiment, the sacrificial material 453 can be removed by an etching process using an etchant selective to the sacrificial material 453 relative to the dielectric materials 455A and 481 and relative to the fin 430. Figure 21B shows that after the removal of the sacrificial material 453, the back - side of the fin 430 is exposed as the sidewall of the fin 430 and the source 440A. Figures 22A-22C illustrate structures following epitaxial growth of materials for backside junction formation and contacts formed on the backside of the device. Figure 22A shows epitaxially grown material 485A in the region of opening 482A aligned with the backside of source 440A and epitaxially grown material 485B of fin 430 aligned with the backside of drain 440B in opening 482B. Figure 22B shows material 485A epitaxially grown on the sidewalls of fin 430 and connected to source 440A previously formed on the first side or device side of the structure. Although epitaxial growth options are presented, it is understood that other methods described above (doped epitaxial drive-in (Figures 12A-15C), implantation (Figures 16A-17C)) may be selectively used. Figures 22A-22C illustrate structures after filling via openings in dielectric material 481 with a conductive contact material such as tungsten. Figure 22A shows contact 486A to epitaxial material 485B associated with source 440A and contact metal 486B to epitaxial material 485B associated with drain 440B. Figure 22B shows contact metal 486B to epitaxial material 485B. Figures 22A and 22B show connections to source 440A (through the contact material) from opposite sides of the structure (the first side or device side and the backside or second side), respectively. Interconnections can now be formed to contacts 486A and 486B by techniques such as those described above for device side interconnections (see Figures 3 and 4A-4C and the accompanying text). FIG. 23 shows a schematic cross-sectional side view of one embodiment of an assembly including an integrated circuit die or chip connected to a package substrate. Assembly 500 includes die 510, which may be formed as described above with reference to FIGS. 1-22C. Die 510 includes a device layer or a layer 515 including several devices (e.g., transistor devices). Device layer 515 includes a first side 5150A representing the first side of the layer and a second side or back side 5150B opposite the first side 5150A. The transistor devices include, for example, one or more power transistors and logic circuits. Interconnects 520 connected to device layer 515 of die 510 on the first side include, in one embodiment, but are not limited to, several conductive metal lines connecting from first side 5150A to devices of device layer 515. Referring to interconnects 160A, 160B, and 170 of FIG. 3, interconnects 220 of the first level above device layer 515 are represented. Above interconnects 520 (as seen) is carrier substrate 540, which is similar to carrier substrate 180 described above with reference to FIGS. 5A-17. In one embodiment, the devices connected to die 510 through the second side 5100B of the die are interconnects 530, which may be, for example, power interconnects (VDD, VDD gated, and VSS), logic interconnects, or both. Interconnects 530 on the second side or back side 5100B include one or more metallization levels or rows. Referring to FIGS. 10A-11, interconnect 190A represents the first level of interconnects 530 below device layer 515. FIG. 23 also shows a connection in such a metallization layer of this level to a contact (e.g., C4 bump) 550 operable to connect die 510 to package 590. FIG. 23 further shows VDD and VSS connections through package substrate 590 connected to die 510. FIG. 24 is a process flow diagram for forming contacts from the backside and backside metallization to the source and drain of a three-dimensional transistor device. Referring to FIG. 24, process 600 begins with a three-dimensional transistor device formed on a substrate, the device including fins extending from the substrate and source and drain formed in or on the fins (block 610). Sacrificial material may be optionally formed on the base of the fins as described above with reference to FIG. 18. From a first side or device side of the structure, a contact is established to the device and device side metallization (block 620). After the metallization is established, the device is inverted and bonded device side down to a carrier (block 625). The substrate is then removed to expose the fins (block 630) and the fins are selectively recessed (block 635). Then a dielectric material is introduced and patterned on the backside of the device, having vias or openings to the source and drain around the fins of the device (block 640). If sacrificial material was previously formed on the base of the fins, the sacrificial material is removed. In one embodiment, then epitaxial material is introduced on and around the fins to the source and drain (block 645). In a second embodiment, doped epitaxial material is introduced onto the fins and dopants in the epitaxial material are driven into the fins (block 650). According to the second embodiment, after the dopant drive-in, the epitaxial material is optionally removed (block 655). In a third embodiment, implants are introduced into the fins in the source and drain regions (block 660). After one of the above embodiments, the backside vias or openings are filled with contact material to form backside contacts to the source and drain respectively (block 670). Then backside metallization is optionally constructed (block 675). The above embodiments describe the formation of transistor devices with backside contacts. Although three-dimensional transistor devices are presented, such presentation is not meant to be limiting. The implementation of backside transistor contacts and techniques regarding their formation are applicable to other devices, including nanowire devices and planar devices. FIG. 25 illustrates an inserter 700 including one or more embodiments. The inserter 700 is an insertion substrate for bridging a first substrate 702 to a second substrate 704. The first substrate 702 may be, for example, an integrated circuit die. The second substrate 704 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the use of the inserter 700 is to extend connections to a wider pitch or reroute connections to different connections. For example, the inserter 700 may couple an integrated circuit die to a ball grid array (BGA) 706 which may subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702 / 704 are attached to opposite sides of the inserter 700. In other embodiments, the first and second substrates 702 / 704 are attached to the same side of the inserter 700. In further embodiments, three or more substrates are interconnected by the inserter 700. The inserter 700 can be formed of epoxy resin, glass fiber-reinforced epoxy resin, ceramic material, or a polymer material such as polyimide. In a further implementation, the inserter can be formed of an alternative rigid or flexible material, which can include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. The inserter can include metal interconnects 708 and vias 710, which include but are not limited to through-silicon vias (TSVs) 712. The inserter 700 can further include embedded devices 714, including passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices can also be formed on the inserter 700. According to an embodiment, the devices or processes disclosed herein can be used in the manufacture of the inserter 700. FIG. 26 illustrates a computing device 800 according to an embodiment of the present invention. The computing device 800 can include several components. In one embodiment, these components are attached to one or more motherboards. In an alternative embodiment, these components are manufactured on a single system-on-chip (SoC) die rather than on a motherboard. The components in the computing device 800 include but are not limited to an integrated circuit die 802 and at least one communication chip 808. In some implementations, the communication chip 808 is manufactured as part of the integrated circuit die 802. The integrated circuit die 802 can include a CPU 804 and on-die memory 806, which is typically used as cache memory and can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM). The computing device 800 may include other components, which may or may not be physically and electrically coupled to the motherboard or fabricated within the SoC die. These other components include but are not limited to volatile memory 810 (e.g., DRAM), non-volatile memory 812 (e.g., ROM or flash memory), graphics processing unit 814 (GPU), digital signal processor 816, encryption processor 842 (a dedicated processor that performs cryptographic algorithms in hardware), chipset 820, antenna 822, display or touch screen display 824, touch screen controller 826, battery 828 or other power source, power amplifier (not shown), global positioning system (GPS) device 844, compass 830, motion co-processor or sensor 832 (which may include accelerometer, gyroscope, and compass), speaker 834, camera 836, user input device 838 (such as keyboard, mouse, stylus, and touch pad), and mass storage device 840 (such as hard disk, compact disc (CD), digital versatile disc (DVD), etc.). The communication chip 808 enables wireless communication for transferring data to and from the computing device 800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data by using modulated electromagnetic radiation via a non-solid medium. This term does not imply that the related devices do not contain any circuitry, although in some embodiments they may not contain any circuitry. The communication chip 808 can implement any number of wireless standards or protocols to achieve wireless communication, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and beyond. The computing device 800 may include multiple communication chips 808. For example, the first communication chip 808 may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 808 may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor 804 of the computing device 800 includes one or more devices (such as transistors or metal interconnects) that are formed according to embodiments including backside contacts to the devices and selective backside metallization. The term "processor" can refer to any device or portion of a device that processes electronic data from registers and / or memory and transforms the electronic data into other electronic data that can be stored in registers and / or memory. The communication chip 808 may also include one or more devices (such as transistors or metal interconnects) formed according to embodiments including backside contact to the devices and selective backside metallization. In a further embodiment, other components housed in the computing device 800 may contain one or more devices (such as transistors or metal interconnects) formed according to embodiments including backside contact to the devices and selective backside metallization. In various embodiments, the computing device 800 can be a laptop computer, a thin and light laptop, a notebook computer, an ultra-thin and light notebook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-thin mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In a further implementation, the computing device 800 can be any other electronic device that processes data. Examples Example 1 is a device, including A circuit structure includes a device layer, the device layer includes a plurality of devices, the devices include a first side and an opposite second side; and metal interconnects coupled to at least one of the plurality of devices from the second side of the device layer. In Example 2, the metal interconnect of the device of Example 1 is a first metal interconnect, and the device further includes a second metal interconnect, the second metal interconnect being coupled to the device from the first side of the device layer. In Example 3, at least one of the plurality of devices of the device of any of Example 1 or 2 includes a transistor device and the metal interconnect is coupled to the source or drain of the transistor device. In Example 4, the metal interconnect of the device of Example 3 is a first metal interconnect, and the device further includes a second metal interconnect, the second metal interconnect being coupled to the other of the source or the drain of the transistor device from the second side of the device layer. In Example 5, the metal interconnect of the device of Example 3 is a first metal interconnect, and the device further includes a second metal interconnect, the second metal interconnect being coupled to the gate of the transistor device from the first side of the device layer. In Example 6, one of the source and the drain at the point coupled to the metal interconnect of the device of Example 3 includes one of the following: a material epitaxially grown on one of the source and the drain; a material of one of the source and the drain modified by one of implanted material and material doping. Example 7 is a method, which includes forming a transistor device, the transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device. In Example 8, before forming the interconnect to one of the source region and the drain region, the method of Example 7 includes exposing one of the source region and the drain region from the second side and one of the following: forming a material on the one of the source region and the drain region that is exposed; modifying a portion of the one of the source region and the drain region. In Example 9, the method of Example 8 includes forming a material on the one of the source region and the drain region that is exposed, and such forming includes epitaxially growing the material. In Example 10, the method of Example 8 includes modifying a portion of the one of the source region and the drain region, and the modifying includes doping and implanting a material into the source region and the drain region. In Example 11, forming the transistor device of the method of any of Examples 7-10 includes forming fins on a substrate, and forming the source region and the drain region in the fins separated by the channel region, and forming the gate electrode on the channel region of the fins. In Example 12, before forming the interconnect, the method of Example 11 includes exposing a region of the fins from the second side in one of the source region and the drain region; and introducing a material on the exposed fin region or into the fins in the exposed fin region. In Example 13, introducing the material on the exposed fin region in the method of Example 12 includes epitaxially growing the material on the fins. In Example 14, introducing the material into the fins in the exposed fin region in the method of Example 12 includes doping the fins. In Example 15, the transistor device of the method of any of Examples 12-14 is formed on a substrate, and exposing the region of the fins from the second side includes bonding the substrate to the carrier with the transistor device facing the carrier; and removing the substrate. In Example 16, before bonding the substrate to the carrier, the method of any of Examples 12-15 includes forming spacer material on opposite sidewalls of the one of the source region and the drain region and exposing the region around the fins includes removing the spacer material. Example 17 is a method that includes forming a non-planar transistor device, the non-planar transistor device including fins on a substrate and source and drain regions in the fins separated by a channel region, and a gate electrode on the channel region of the fins that defines a first side of the device; bonding the substrate to the carrier with the transistor device facing the carrier; removing the substrate to expose a second side of the device opposite the first side; exposing a region around the fins from the second side of the device in one of the source region and the drain region; and forming an interconnect from the second side of the device to one of the source region and the drain region. In Example 17, prior to forming the interconnect, the method of Example 17 includes one of the following: forming a material over the exposed regions of the source and drain regions and modifying a portion of one of the source and drain regions in the exposed regions. In Example 19, the method of Example 18 includes forming a material over the regions exposed in the source and drain regions, and such forming includes epitaxially growing the material. In Example 20, the method of Example 18 includes modifying a portion of one of the source and drain regions, and the modifying includes doping and implanting a material into the source and drain regions. In Example 21, the method of Example 18 includes forming a material over one of the exposed source and drain regions, and such forming includes depositing the material and processing the transistor device to drive dopants from the material into one of the source and drain regions. In Example 22, prior to bonding the substrate to the carrier, the method of any of Examples 18 - 21 includes forming spacer material on opposite sidewalls of one of the source and drain regions and exposing the region around the fin including removing the spacer material. The foregoing description of the illustrated embodiments, including what is set forth in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments and examples of the invention have been described herein for purposes of illustration, various equivalent modifications within the scope of the invention will be apparent to those of ordinary skill in the art. These modifications may be made in accordance with the foregoing detailed description. The terms used in the claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope of the invention is entirely determined by the claims, which are to be construed in accordance with the principles established for interpreting claims.

Claims

1. An integrated circuit structure, comprising: a semiconductor body having a top, a bottom, a first side, and a second side, the first side and the second side being between the top and the bottom, and the first side being opposite to the second side; a gate structure at least above the top and extending along the first side and the second side of the semiconductor body; a first source or drain structure at a first side of the gate structure; a second source or drain structure at a second side of the gate structure, the second side being opposite to the first side; and a conductive contact directly below the first source or drain structure and in contact with the first source or drain structure.

2. The integrated circuit structure of claim 1, wherein the conductive contact further extends along a first side of the first source or drain structure.

3. The integrated circuit structure of claim 2, wherein the conductive contact further extends along a second side of the first source or drain structure.

4. The integrated circuit structure of claim 1, wherein the gate structure extends along a portion of the first side and the second side of the semiconductor body.

5. The integrated circuit structure of claim 1, further comprising: a second conductive contact directly above the second source or drain structure and in contact with the second source or drain structure.

6. The integrated circuit structure of claim 5, further comprising: an epitaxial semiconductor structure vertically between the second conductive contact and the second source or drain structure.

7. The integrated circuit structure of claim 1, further comprising: a second conductive contact directly above the first source or drain structure and in contact with the first source or drain structure.

8. The integrated circuit structure of claim 1, further comprising: a second conductive contact directly below the second source or drain structure and in contact with the second source or drain structure.

9. The integrated circuit structure of claim 1, further comprising: a second conductive contact directly above the first source or drain structure and in contact with the first source or drain structure; and a third conductive contact directly below the second source or drain structure and in contact with the second source or drain structure.

10. A computing device, comprising: a memory; and an integrated circuit die coupled to the memory, the integrated circuit die comprising an integrated circuit structure, the integrated circuit structure comprising: a semiconductor body having a top, a bottom, a first side, and a second side, the first side and the second side being between the top and the bottom, and the first side being opposite to the second side; a gate structure at least above the top and extending along the first side and the second side of the semiconductor body; a first source or drain structure at a first side of the gate structure; a second source or drain structure at a second side of the gate structure, the second side being opposite to the first side; and a conductive contact directly below the first source or drain structure and in contact with the first source or drain structure.

11. The system of claim 10, further comprising: a graphics processing unit coupled to the integrated circuit die.

12. The system of claim 10 further comprises: an antenna coupled to the integrated circuit die.

13. The system of claim 10 further comprises: a display coupled to the integrated circuit die.

14. The system of claim 10 further comprises: a battery coupled to the integrated circuit die.

15. The system of claim 10 further comprises: a global positioning system coupled to the integrated circuit die.

16. The system of claim 10 further comprises: a compass coupled to the integrated circuit die.

17. The system of claim 10, wherein the conductive contact is further along a first side of the first source or drain structure.

18. The system of claim 17, wherein the conductive contact is further along a second side of the first source or drain structure.

19. The system of claim 10, wherein the gate structure extends along a first side and a portion of the second side of the semiconductor body.

20. The system of claim 10, wherein the integrated circuit structure further comprises: a second conductive contact directly above and in contact with the second source or drain structure.