Magnetic memory device

Abstract

The magnetic memory device of an embodiment of the present invention includes a substrate, a first wiring, a first insulator, a second insulator, a second wiring, and a first magnetoresistive element. The first wiring and the first insulator extend along a first direction along the substrate. The second insulator extends in a second direction and penetrates the first wiring and the first insulator. The second wiring is disposed around the second insulator, extends along the second direction, and penetrates the first wiring and the first insulator. The first magnetoresistive element is disposed in a ring around the second wiring between the first wiring and the second wiring. The first magnetoresistive element has a first ferromagnetic body between the second wiring and the first wiring, a first non-magnetic body between the first ferromagnetic body and the first wiring, and a second ferromagnetic body between the first non-magnetic body and the first wiring.

Description

Technical Field

[0001] The present invention relates to a magnetic memory device. Prior Technology

[0002] A magnetic memory device using a magnetoresistive element as a memory element is known. Various methods have been proposed for writing data to the magnetoresistive element. For example, a writing method using spin-orbit torque is known. Summary of the Invention

[0003] The present invention aims to provide a magnetically stable magnetic memory device.

[0004] A magnetic memory device in one embodiment includes a substrate, a first wiring, a first insulator, a second insulator, a second wiring, and a first magnetoresistive element. The first wiring and the first insulator extend along a first direction along the substrate and are arranged in a second direction intersecting the first direction. The second insulator extends in the second direction and penetrates the first wiring and the first insulator. The second wiring is disposed around the second insulator, extends along the second direction, and penetrates the first wiring and the first insulator. The first magnetoresistive element is arranged in a ring around the second wiring between the first wiring and the second wiring. The first magnetoresistive element has a first ferromagnetic body between the second wiring and the first wiring, a first non-magnetic body between the first ferromagnetic body and the first wiring, and a second ferromagnetic body between the first non-magnetic body and the first wiring. Simple Explanation of the Diagram

[0005] Figure 1 shows a block diagram of an example of the configuration of the magnetic memory device 1 in the first embodiment. Figure 2 shows a circuit diagram of an example of the circuit configuration of the memory cell array 10 in the first embodiment. Figure 3 shows an example of the planar layout of the memory cell array 10 in the magnetic memory device 1 of the first embodiment. Figure 4 shows an example of the cross-sectional structure of the magnetic memory device 1 in the first embodiment, and is a cross-sectional view along line IV-IV in Figure 3. Figure 5 shows an example of the cross-sectional structure of the magnetic memory device 1 in the first embodiment, and is a cross-sectional view along line VV in Figure 3. Figure 6 shows an example of the cross-sectional structure of the memory column MP in the magnetic memory device 1 of the first embodiment, and is an enlarged view of region VI in Figure 4. Figure 7 shows an example of the voltage and current characteristics of the memory cell in the magnetic memory device 1 of the first embodiment. Figures 8(A) and (B) show an example of the cross-sectional structure of the memory column MP in the magnetic memory device 1 of the first embodiment, and are cross-sectional views along line VIII-VIII of Figure 3. Figure 9 shows an example of the voltage applied to the memory cell array in the first example of the write operation in the magnetic memory device 1 of the first embodiment. Figure 10 shows an example of the current and magnetization direction applied to the memory cell array in the first example of the write operation in the magnetic memory device 1 of the first embodiment. Figure 11 shows an example of the current and magnetization direction applied to the memory cell array in a second example of the write operation in the magnetic memory device 1 of the first embodiment. Figures 12 and 13 show an example of the voltage applied to the memory cell array during the readout operation of the magnetic memory device 1 in the first embodiment. Figure 14 shows a flowchart of an example of a manufacturing method for the magnetic memory device 1 of the first embodiment. Figures 15 to 27 show an example of a cross-sectional structure during the manufacturing process of the magnetic memory device 1 of the first embodiment. Figure 28 shows an example of the cross-sectional structure of the memory column MPb in the magnetic memory device 1b of the first embodiment. Figures 29(A) and (B) show an example of the cross-sectional structure of the memory column MPb in the magnetic memory device 1b of the first embodiment, and are cross-sectional views along line XXVIIII-XXVIIII in Figure 28. Figure 30 shows an example of the cross-sectional structure of the memory column MPC in the magnetic memory device 1c of the second embodiment. Figure 31 shows a flowchart of an example of a manufacturing method for the magnetic memory device 1c of the second embodiment. Figures 32 and 33 show an example of a cross-sectional structure during the manufacturing process of the magnetic memory device 1c of the second embodiment. Implementation

[0006] The embodiments will now be described with reference to the diagrams. Furthermore, in the following description, constituent elements having the same function and structure will be marked with common reference symbols. Also, when distinguishing multiple constituent elements with common reference symbols, the markings on these common reference symbols will be differentiated. Furthermore, when it is not necessary to specifically distinguish multiple constituent elements, only the common reference symbols will be marked on the multiple constituent elements, without any additional markings. These markings are not limited to subscript or superscript text; for example, they may include lowercase English letters, symbols, and indexes indicating arrangement added to the end of the reference symbols.

[0007] The diagram is a schematic diagram, and the relationship between thickness and planar dimensions, as well as the ratio of thicknesses of each layer, may differ from the actual drawing. Furthermore, the diagram may also include parts where the dimensional relationships or ratios of each other differ.

[0008] The following descriptions use the XYZ orthogonal coordinate system. In some cases, the positive direction of the vertical axis is called the upper side and the negative direction the lower side. Similarly, the positive direction of the horizontal axis is called the right side and the negative direction the left side. That is, in a top view showing the XY plane (XY plane view (hereinafter the same)), the upper side refers to the +Y direction, the lower side to the -Y direction, the right side to the +X direction, and the left side to the -X direction.

[0009] In the top view, shaded lines are appropriately added for easier viewing. The shaded lines added to the top view are not necessarily related to the raw materials or characteristics of the components to which the shaded lines are attached. In the sectional view, components such as insulating layers, substrates, wiring, and terminals are appropriately omitted for easier viewing.

[0010] Furthermore, unless otherwise stated, any step in the process of implementing the method is not limited to the illustrated order and may be performed in a different order and / or in parallel with other steps.

[0011] In this specification and technical solution, "connection" means electrical connection, which does not exclude the presence of other components in between. "Electrical connection" can be separated from the electrically connected object as long as it can operate in the same way.

[0012] In this specification, the magnetic memory device is, for example, MRAM (Magnetoresistive Random Access Memory). The magnetic memory device includes a magnetoresistive element as a memory element. The magnetoresistive element is a resistance-changing element that exhibits the magnetoresistance effect through a magnetic tunnel junction (MTJ). This magnetoresistive element is also referred to as an MTJ element.

[0013] 1. First Implementation Form The semiconductor device of the first embodiment will be described. First, the structure of the magnetic memory device of the first embodiment will be described.

[0014] Figure 1 is a block diagram showing an example of the configuration of a magnetic memory device according to a first embodiment. The magnetic memory device 1 includes a memory cell array 10, a column decoder 11, a row decoder 12, a read circuit 13, a write circuit 14, a sense amplifier 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0015] The memory cell array 10 is the data storage unit in the magnetic memory device 1. The memory cell array 10 has a plurality of memory cells MC. Each of the plurality of memory cells MC is associated with a row and a column. Memory cells MC located in the same column are associated with the same read word line RWL. Memory cells MC located in the same row are associated with the same read bit line RBL and write bit line WBL.

[0016] The column decoder 11 is a circuit that selects columns of the memory cell array 10. The column decoder 11 is connected to the memory cell array 10 via read word lines RWL. An address ADD from the input / output circuit 17 is supplied to the column decoder 11. The column decoder 11 decodes the address ADD and selects the read word line RWL corresponding to the column based on the decoding result. Hereinafter, the selected read word line RWL is referred to as the selected word line RWL. Furthermore, read word lines RWL other than the selected word line RWL are referred to as non-selected word lines RWL.

[0017] The row decoder 12 is a circuit that selects rows of the memory cell array 10. The row decoder 12 is connected to the memory cell array 10 via the read bit line RBL and the write bit line WBL. The row decoder 12 is supplied with an address ADD from the input / output circuit 17. The row decoder 12 decodes the address ADD and selects the write bit line WBL and the read bit line RBL corresponding to the row based on the decoding result. Hereinafter, the selected read bit line RBL is referred to as the selected read bit line RBL. Hereinafter, the selected write bit line WBL is referred to as the selected write bit line WBL. Furthermore, the read bit lines RBL other than the selected write bit line WBL are referred to as the non-selected write bit lines WBL. Furthermore, the read bit lines RBL other than the selected read bit line RBL are referred to as the non-selected read bit lines RBL.

[0018] The readout circuit 13 reads data from the memory cell MC. The readout circuit 13 includes, for example, a sense amplifier 15. The sense amplifier 15 is a circuit that outputs a voltage based on the data stored in the memory cell MC of the data readout object, and determines that the data is stored in the memory cell MC of the data readout object.

[0019] The write circuit 14 includes, for example, a write driver (not shown). The write circuit 14 performs the writing of data to the memory cell MC.

[0020] The voltage generation circuit 16 uses a power supply voltage (not shown) provided from an external source (external source) of the magnetic memory device 1 to generate voltages for various operations of the memory cell array 10. For example, the voltage generation circuit 16 generates various voltages required for a write operation and outputs them to the write circuit 14. Also, for example, the voltage generation circuit 16 generates various voltages required for a read operation and outputs them to the read circuit 13.

[0021] Input / output circuit 17 is responsible for communication with the external environment of magnetic memory device 1. Input / output circuit 17 transmits the address ADD from the external environment of magnetic memory device 1 to column decoder 11 and row decoder 12. Input / output circuit 17 transmits the instruction CMD from the external environment of magnetic memory device 1 to control circuit 18. Input / output circuit 17 sends and receives various control signals CNT between the external environment of magnetic memory device 1 and control circuit 18. Input / output circuit 17 transmits data DAT from the external environment of magnetic memory device 1 to write circuit 14, and outputs data DAT transmitted by self-read circuit 13 to the external environment of magnetic memory device 1.

[0022] The control circuit 18 includes, for example, a processor such as a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory). Based on the control signal CNT and the instruction CMD, the control circuit 18 controls the operation of the column decoder 11, row decoder 12, read circuit 13, write circuit 14, voltage generation circuit 16, and input / output circuit 17 within the magnetic memory device 1.

[0023] Next, the configuration of the memory cell array of the magnetic memory device in the first embodiment will be explained.

[0024] Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array in the first embodiment. In Figure 2, various components are displayed by way of labels containing indices ("<>").

[0025] The memory cell array 10 includes a plurality of read word lines RWL, write word lines WWL, a plurality of read bit lines RBL, a plurality of write bit lines WBL, a plurality of memory strings MS, and a plurality of switching elements TR1.

[0026] The complex number of read character lines RWL contains (M+1) read character lines WL <0> ... WL <m>...and WL <m>M is an integer greater than or equal to 1 (0... <m<M)。

[0027] The complex number of read bit lines RBL includes (N+1) read bit lines RBL <0> ... RBL <n>...and RBL <n>N is an integer greater than or equal to 1 (0 ≤ N ≤ 1). <n<N)。

[0028] The complex number of write bit lines WBL includes (N+1) write bit lines WBL <0> ... WBL <n>...and WBL <n>.

[0029] The plurality of switching elements TR1 includes (N+1) switching elements TR1 <0> TR1 <n>...and TR1 <n>.

[0030] The complex number of memory strings MS contains (N+1) memory strings MS <0> MS <n>... and MS <n>Memory string MS <0> ~MS <n>Each has the same structure. The following uses memory strings MS... <n>Let's take an example to illustrate.

[0031] Memory String MS <n>Includes SOTL wiring <n>and (M+1) memory cells MC<0,n>, ...,MC<m,n> ...and MC<M,n> .

[0032] SOTL wiring <n>With read bit line RBL <n>The first terminal of the connection is connected to the switching element TR1. <n>The first end connects to the second end, and the central part between the two ends. (M+1) memory cells MC<0,n>, ...,MC<m,n> ...and MC<M,n> Connected separately to the SOTL wiring <n>The central section. A portion of the SOTL wiring also serves as the memory cell MC.<M,n> One part of it performs the function. The following will describe the SOTL wiring. <n>In the central part of the memory cell MC<0,n>~MC<M,n> The portion connected to any of the first terminals is also called a "cell". The wiring SOTL <n>The portion between two adjacent cell portions in the central part is also called the "wiring portion".

[0033] Memory cells MC<0,n>~MC<M,n> The second end is connected to the read character line RWL respectively. <0> ~RWL <m>Connection. Memory cells MC<0,n>~MC<M,n> Each has the same composition. The following uses the memory cell MC...<m,n> Let's take an example to illustrate.

[0034] Memory Cell MC<m,n> Includes SOTL wiring <n>MC and memory cells<m,n> Connecting cell section, switching element SEL2<m,n> and magnetoresistive element MTJ<m,n> .

[0035] Switching element SEL2<m,n> For example, a two-terminal switching element. Switching element SEL2<m,n> With magnetoresistive effect element MTJ<m,n> The first end of the connection, and the read character line RWL <m>The second terminal of the connection. For example, when the voltage applied between the two terminals does not reach the threshold, the switching element SEL2 is in a "high resistance" state, such as a non-conducting state (off state). When the voltage applied between the two terminals is above the threshold, the switching element SEL2 is in a "low resistance" state, such as a conducting state (on state). The switching element SEL2 can have this function regardless of the voltage polarity. That is, the switching element SEL2 can have the above function regardless of whether a positive voltage or a negative voltage is applied. By turning the switching element SEL2 on or off, the supply of current to the magnetoresistive element MTJ connected to the switching element SEL2 can be controlled, that is, the selection or non-selection of the magnetoresistive element MTJ.

[0036] MTJ magnetoresistive element<m,n> Connected in series with switching element SEL2<m,n> , and wiring SOTL <n>The middle is connected to the memory cell MC<m,n> Between the cell units. Magnetoresistive element MTJ<m,n> A resistive element. A magnetoresistive element (MTJ).<m,n> It functions as a memory element that stores data based on changes in the resistance state rather than in a volatile manner.

[0037] As described above, each memory string MS contains (M+1) memory cells MC connected to one wiring SOTL. Therefore, the memory cell array 10, having (N+1) memory strings MS, becomes an array containing (M+1)×(N+1) memory cells MC<0,0>, ..., MC<0,n>, ..., MC<0,N>, ..., MC<0,N>.<m,0> ... MC<m,n> ... MC<m、N> ... MC<M,0> ... MC<M,n> ...and MC<M、N> Its composition.

[0038] Switching element TR1 <0> ~TR1 <n>Each of these is, for example, a 3-terminal switching element like a MOSFET. Switching element TR1 <0> ~Switching element TR1 <n>Each has the same structure. Hereinafter, we will take the switching element TR1 as an example. <n>Let's take an example to illustrate.

[0039] Switching element TR1 <n>With SOTL wiring <n>The first connection point is connected to the write bit line WBL. <n>The second terminal of the connection, and the control terminal connected to the write character line WWL. Herein, the switching element TR1... <n>Controllable whether to apply to the write bit line WBL <n>The voltage is transmitted to the SOTL wiring. <n>.

[0040] Figure 3 shows an example of the planar layout of the memory cell array 10 in the magnetic memory device 1 of the first embodiment. Figure 3 shows the area that functions as a block BLK (or serial unit SU). The memory cell array 10 includes a plurality of components SLT, a plurality of memory cylinders MP, a plurality of contacts CC, a plurality of read word lines RWL, and a plurality of read bit lines RBL. Furthermore, as shown in Figure 3, the memory cell array 10 includes, for example, a memory region MA and a lead-out region (wiring lead-out region) HA. The memory region MA and the lead-out region HA are arranged along the X direction. For example, the lead-out region HA is provided at the end of the memory region MA on the -X direction side. The lead-out region HA may also be provided at the ends of the memory region MA on the +X direction side and the -X direction side, respectively.

[0041] The memory region MA is the area that actually stores data. Multiple memory cylinders MP are set in the memory region MA.

[0042] The HA area is a region for setting up various wirings that connect to memory cylinders MP located in the memory region MA, as well as wirings and contact plugs that connect to, for example, column decoders 11.

[0043] Read the character line RWL from the lead-out region HA. <0> ~RWL <m>Each has a portion (stepped portion) at its end that does not overlap with the upper wiring layer (conductor layer). The portion that does not overlap with the upper wiring layer has a stepped shape.

[0044] Specifically, at the read character line RWL <0> With read character line RWL <1> Between, read out character lines RWL <1> With read character line RWL <2> Between, ..., read out character lines RWL <m-1>With read character line RWL <m>Step differences are set between them.

[0045] A plurality of SLT components extend along the X direction and are arranged along the Y direction. The SLT components have an internally embedded insulating component. The SLT components are disposed on the same wiring layer and separate adjacent conductive layers via the SLT components.

[0046] Each of the plurality of memory columns MP functions as, for example, a memory string MS. The plurality of memory columns MP are arranged, for example, along the X direction in the region between adjacent components SLT. Not limited thereto, the number and arrangement of memory columns MP between adjacent slits can be changed as appropriate.

[0047] Furthermore, each memory cylinder MP has one read bit line RBL overlapping it. For example, multiple read bit lines RBL extend along the Y direction and are arranged along the X direction. The read bit lines RBL overlapping the memory cylinder MP are electrically connected to the memory cylinder MP.

[0048] Multiple contacts CC are configured within the lead-out area HA and respectively on the read character line RWL. <0> ~RWL <m>The stepped portion of each component. As the contact plug CC, a metallic material such as phosphorus-doped silicon or tungsten is used. Readout character line RWL <0> ~RWL <m>It is electrically connected to the column decoder 11 via the contact CC. That is, the column decoder 11 and the stacked wiring (e.g., read word line RWL) connected to the memory string MS are connected via the contact CC.

[0049] In the planar layout of the memory cell array 10 of the magnetic memory device 1 described above, the area divided by the component SLT functions as a block BLK. In the memory cell array 10, for example, the layout corresponding to the block BLK shown in FIG3 is repeatedly arranged in the Y direction. Then, according to each space divided by the component SLT, a memory column MP is electrically connected to a read bit line RBL.

[0050] Figure 4 is a cross-sectional view along line IV-IV of Figure 3, showing an example of the cross-sectional structure of the magnetic memory device 1 in the first embodiment. From Figure 4 onwards, examples are shown where the number of read word lines RWL is 10 (M=9). As shown in Figure 4, the magnetic memory device 1 includes a semiconductor substrate 20, conductive layers 24-27, a plurality of multilayer wiring layers LL that function as read word lines RWL0-RWL9, insulating layers 30-34, a plurality of components SLT, memory pillars MP, contacts CV and CS, and a switching element TR1.

[0051] An insulating layer 30 is disposed on a semiconductor substrate 20. The insulating layer 30 contains, for example, silicon oxide (SiO2). Although a portion of the illustration is omitted, a circuit region is disposed within a portion of the semiconductor substrate 20 and the insulating layer 30, and a memory cell array 10 is disposed above the insulating layer 30. In the circuit region, circuits for, for example, a column decoder 11 or a sense amplifier 15 are formed. The circuit region includes a switching element TR1, conductive layers 25-27, and a contact CS.

[0052] The switching element TR1 includes a gate electrode GC, a source / drain region NN, and an insulating layer OX. The gate electrode GC is disposed on the upper surface of the semiconductor substrate 20 through a gate insulator. The source / drain region NN sandwiches the region below the gate electrode GC in the surface region of the semiconductor substrate 20. The insulating layer OX covers the side of the gate electrode GC.

[0053] One of the source / drain regions NN is connected to the conductive layer 25 via a columnar contact CS. The other source / drain region NN is connected to the conductive layer 27 via contact CS. The gate electrode GC is connected to the conductive layer 26 via contact CS.

[0054] An insulating layer 31 is disposed on top of the insulating layer 30. The insulating layer 31 contains, for example, silicon oxide (SiO2).

[0055] Layered wiring layers LL and insulating layers 32 are alternately deposited on top of insulating layer 31. The layered wiring layers LL are, for example, formed as a plate extending along the XY plane. The plurality of deposited layered wiring layers LL are sequentially used as readout word lines RWL0 to RWL9, starting from the semiconductor substrate 20 side. Details of the layered wiring layers LL will be described later with reference to FIG6. Insulating layer 32 contains, for example, silicon oxide.

[0056] An insulating layer 33 is disposed above the topmost multilayer wiring layer LL. The insulating layer 33 may contain, for example, silicon oxide. A conductive layer 24 is disposed above the insulating layer 33. The conductive layer 24 may be formed as a line extending along the Y direction. The conductive layer 24 is used as a readout bit line RBL. In areas not shown, a plurality of conductive layers 24 are arranged along the X direction. The conductive layer 24 may contain, for example, copper (Cu).

[0057] An insulating layer 34 is disposed on the conductive layer 24. The insulating layer 34 may contain, for example, silicon oxide. The insulating layer 34 may include wiring for connecting the memory cell array 10, the column decoder 11, and the sense amplifier 15.

[0058] Each of the plurality of memory pillars MP extends along the Z-direction, penetrating the insulating layers 31-32 and the multilayer wiring layer LL. The upper end of each memory pillar MP is contained within the insulating layer 33. The lower end of each memory pillar MP contacts the conductive layer 25.

[0059] The portion of the memory column MP that intersects with the stacked wiring layer LL functions as a cell CP (shown in Figure 6). The shape of the memory column MP in the portion where the stacked wiring layer LL intersects with the memory column MP differs from the shape of the memory column MP in other portions. For example, in the portion where the stacked wiring layer LL intersects with the memory column MP, the diameter of the memory column MP is larger than the diameter of other portions of the memory column MP. This detail will be described later with reference to Figure 5.

[0060] Each memory cylinder MP includes, for example, a core component 40, an SOT layer 41, and a magnetoresistive element MTJ. The core component 40 extends along the Z direction and is disposed in the center of the memory cylinder MP. For example, the upper end of the core component 40 is disposed on a layer above the layer on which the uppermost stacked wiring layer LL is disposed. The lower end of the core component 40 is in contact with the conductive layer 25. The core component 40 includes, for example, an insulator such as silicon oxide.

[0061] SOT layer 41, for example, covers the area around core component 40. For example, the bottom surface of SOT layer 41 is in contact with conductive layer 25. Details of SOT layer 41 will be described later with reference to FIG6.

[0062] The magnetic memory device 1 in the first embodiment may also lack the core component 40, but have a structure in which the SOT layer 41 is embedded up to the center. This structure will be described later in the variation section.

[0063] The magnetoresistive element MTJ has a cylindrical shape that covers the area around the SOT layer 41 at the intersection of the memory pillar MP and the multilayer wiring layer LL. Details of the magnetoresistive element MTJ will be described later with reference to FIG5.

[0064] In the structure of the memory column MP described above, the part where the memory column MP intersects with a multilayer wiring layer LL functions as a memory cell MC.

[0065] A columnar contact CV is provided on the upper surface of the SOT layer 41. The contact CV is electrically connected to the non-magnetic layer 412 (described later) in the SOT layer 41.

[0066] One conductive layer 24, i.e., one read bit line RBL, is in contact with the upper surface of the contact CV. In each space divided by the component SLT, one contact CV is connected to one conductive layer 24. That is, the memory pillars MP disposed between adjacent component SLTs are electrically connected to each of the conductive layers 24.

[0067] The component SLT, for example, has a plate-shaped portion arranged along the XZ plane, which divides the multilayer wiring layer LL and the insulating layers 31-32 along the Y direction.

[0068] The circuit configuration and cross-sectional structure of the magnetic memory device 1 in the first embodiment are not limited to the above-described configuration. For example, Figure 2 and the following description show an example where the switching element TR1 is disposed on the semiconductor substrate 20 located below (-Z side) the multilayer wiring structure, but this is not a limitation. The switching element TR1 may also be disposed above the multilayer wiring structure, for example.

[0069] Furthermore, the switching element TR1 can also be composed of a two-terminal switching element.

[0070] Figure 5 is a cross-sectional view along line VV of Figure 3, showing an example of the cross-sectional structure of the magnetic memory device 1 in the first embodiment. As shown in Figure 5, the magnetic memory device 1 further includes conductive layers 22 and 37.

[0071] In the lead-out region HA, the ends of the plurality of stacked wiring layers LL are configured in a stepped shape. Furthermore, in the lead-out region HA, the memory cell array 10 further includes a plurality of conductive layers 37.

[0072] On the stepped portion of each of the plurality of multilayer wiring layers LL, a contact CC is provided. A conductive layer 37 is provided on each contact CC, and the contact CC and the conductive layer 37 are electrically connected.

[0073] A conductive layer 22 is disposed between the semiconductor substrate 20 and the lowest conductive layer 23 of the memory region MA. The conductive layer 22 is formed, for example, as a line extending in the Y direction, and is used as at least a portion of the source line SL. For example, the conductive layer 27 shown in FIG4 functions as at least a portion of the write bit line WBL and is connected to the conductive layer 22.

[0074] Furthermore, the configuration of the memory cell array 10 in the lead-out region HA is not limited to those described above. For example, the ends of the stacked wiring layers LL can also be stepped in the Y direction. The ends of the stacked wiring layers LL in the lead-out region HA can be stepped in any number of rows.

[0075] Figure 6 is an enlarged view of region VI in Figure 4, showing an example of the cross-sectional structure of the memory column MP in the magnetic memory device 1 of the first embodiment. Figure 6 shows a portion of the memory column MP, and the structure of the multilayer wiring layer LL and the region within the memory column MP that intersects with the multilayer wiring layer LL. The memory column MP extends along the Z direction and has a portion protruding along the XY direction. The portion protruding in the XY direction is a magnetoresistive element MTJ.

[0076] The SOT layer 41 includes, for example, a non-magnetic layer 411 and a non-magnetic layer 412. As described above, the core member 40 extends along the Z direction and is disposed at the center of the memory pillar MP. The non-magnetic layer 411 is disposed, for example, on the side of the core member 40 and has, for example, a cylindrical shape. The non-magnetic layer 411 has a non-magnetic, high-resistivity conductive film, an insulating film, or a semiconductor. When the non-magnetic layer 412 is formed, the non-magnetic layer 411 functions as a protective layer (barrier metal layer) to protect the non-magnetic layer 412 from oxidation. Furthermore, the non-magnetic layer 411 functions as a capping layer for the non-magnetic layer 412. From the viewpoint of improving the adhesion of the film, the non-magnetic layer 411 contains, for example, tantalum (TaN), tungsten (W), titanium (Ti), or silicon (Si), or nitride films of these, namely tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), or silicon nitride (SiN). Alternatively, there may be no non-magnetic layer 411.

[0077] A non-magnetic layer 412 is disposed on the side of the non-magnetic layer 411 and has, for example, a cylindrical shape. The non-magnetic layer 412 functions as a wiring SOTL. The portion of the non-magnetic layer 412 that intersects with the magnetoresistive element MTJ is used as at least a part of the cell portion CP. The portion of the non-magnetic layer 412 that does not intersect with the magnetoresistive element MTJ is used as a wiring portion.

[0078] The non-magnetic layer 412 contains a heavy metal that is non-magnetic and conductive. For example, the non-magnetic layer 412 contains at least one element selected from β-Ta, α-tungsten (α-W), β-tungsten (β-W), hafnium (Hf), bismuth (Bi), antimony (Sb), iridium (Ir), platinum (Pt), gold (Au), ruthenium (Te), and selenium (Se). The non-magnetic layer 412 may contain, for example, BiSb, Bi alloys, Sb alloys, or alloys of Sb, ruthenium (Te), and selenium (Se) with added arsenic (As). The non-magnetic layer 412 may be composed of a single layer containing the above materials, or it may be composed of multiple laminated layers containing the above materials.

[0079] The non-magnetic layer 412 is the layer that primarily generates spin-orbit torque (SOT) induced by the spin Hall effect through the current flowing through it. The spin-orbit torque plays a role at the interface (hereinafter referred to as the ferromagnetic layer 421) in the magnetoresistive element MTJ where it contacts the non-magnetic layer 412. To obtain a larger spin-orbit torque, it is necessary to increase the current flowing through the non-magnetic layer 412, i.e., increase the current density, thereby increasing the spin polarization at the interface. The current density required to ensure magnetization reversal of the ferromagnetic layer 421 is controlled, for example, by controlling the thickness of the non-magnetic layer 412 in the radial direction. The radial direction is the direction that penetrates the cylindrical layer within the memory cylinder MP. In other words, the radial direction is perpendicular to the circumference of the cylindrical layer within the memory cylinder MP.

[0080] The SOT layer 41 may also have a non-magnetic layer 413 (not shown) at the interface between the non-magnetic layer 412 and the magnetoresistive element MTJ. The non-magnetic layer 413 may contain, for example, oxides or nitrides. Examples of non-magnetic layer 413 include oxides with a NaCl structure such as magnesium oxide (MgO) or nickel oxide (NiO), iron oxide (FeO), cobalt oxide (CoOx), iron oxide (FeOx), MnO, titanium oxide (TiOx), tungsten oxide (WOx), or spinel structure oxides such as magnesium aluminum oxide (MgAlO).

[0081] The magnetoresistive element MTJ includes, for example, a ferromagnetic layer 421, a non-magnetic layer 422, a ferromagnetic layer 423, and a non-magnetic layer 424.

[0082] A ferromagnetic layer 421, having a cylindrical shape, is disposed on the side of the non-magnetic layer 412 within a layer including the multilayer wiring layer LL. The ferromagnetic layer 421 is electrically connected to the non-magnetic layer 412. When a non-magnetic layer 413 is disposed, the non-magnetic layer 413 has a thickness sufficient to electrically connect the non-magnetic layer 412 to the ferromagnetic layer 421. The ferromagnetic layer 421 is a ferromagnetic conductive film. The ferromagnetic layer 421 is used as a storage layer. The spin-orbit torque generated in the non-magnetic layer 412 acts on the ferromagnetic layer 421.

[0083] The ferromagnetic layer 421 may be, for example, a ferromagnetic layer containing iron (Fe), cobalt (Co), and nickel (Ni), represented by cobalt-iron alloy (CoFe), cobalt-iron-nickel (CoFeNi), nickel-iron (NiFe), and cobalt-iron-boron alloy (CoFeB). More specifically, for example, the ferromagnetic layer 421 may contain a ferromagnetic material containing Co, cobalt-iron-nickel (CoFeNi), nickel-iron (NiFe), CoFe, or CoFeB, formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition). Furthermore, the ferromagnetic layer 421 may contain nickel-iron (NiFe), nickel (Ni), or cobalt-iron (CoFe), formed by a plating method.

[0084] A non-magnetic layer 422 covers the surface of the ferromagnetic layer 421, except for the portion where the ferromagnetic layer 421 contacts the non-magnetic layer 412. The non-magnetic layer 422 is a non-magnetic insulating film. The non-magnetic layer 422 serves as a tunnel barrier layer. The non-magnetic layer 422 is disposed between the ferromagnetic layers 421 and 423, forming a magnetic tunnel junction together with these two ferromagnetic layers 421 and 423. That is, a magnetoresistance effect is generated at the magnetic tunnel junction portion.

[0085] The non-magnetic layer 422 may contain, for example, boron nitride (BN) or aluminum nitride (AlN). More specifically, the non-magnetic layer 422 may contain BN or AlN formed by ALD or CVD. Furthermore, for the non-magnetic layer 422, there are cases where oxides such as magnesium oxide (MgO) or aluminum oxide Al2O3 with a NaCl structure, or magnesium aluminum oxide (MgAl2O4) with a spinel structure, are used. The non-magnetic layer 422 may be formed by CVD or ALD.

[0086] A ferromagnetic layer 423 is disposed on the side of the non-magnetic layer 422 and has, for example, a cylindrical shape. The ferromagnetic layer 423 is a conductive film with ferromagnetic properties. The ferromagnetic layer 423 is used as a reference layer.

[0087] Ferromagnetic layer 423 may be, for example, a ferromagnetic layer containing iron (Fe), cobalt (Co), and nickel (Ni), or alternatively, a cobalt-iron alloy (CoFe) and a cobalt-iron-boron alloy (CoFeB). More specifically, for example, ferromagnetic layer 421 may contain a ferromagnetic material containing Co, cobalt-iron-nickel (CoFeNi), nickel-iron (NiFe), CoFe, or CoFeB, formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition). Furthermore, ferromagnetic layer 423 may contain, for example, nickel-iron (NiFe), nickel (Ni), or cobalt-iron (CoFe), formed by plating.

[0088] The non-magnetic layer 424 covers the surface of the ferromagnetic layer 423, except for the portion where the ferromagnetic layer 423 contacts the non-magnetic layer 422. The non-magnetic layer 424 is a non-magnetic conductive film. The non-magnetic layer 424 functions as a substrate layer for the ferromagnetic layer 423. The non-magnetic layer 424 prevents the ferromagnetic layer 423 from directly contacting the multilayer wiring layer LL.

[0089] The non-magnetic layer 424 contains at least one element selected from the group consisting of tantalum (Ta), tungsten (W), and titanium (Ti). More specifically, for example, the non-magnetic layer 424 contains tantalum (Ta), tungsten (W), titanium (Ti), or nitrides thereof formed by ALD or CVD.

[0090] Alternatively, a silicon (Si) layer can be disposed between the non-magnetic layer 424 and the multilayer wiring layer LL.

[0091] Thus, the magnetoresistive element MTJ has, for example, a structure in which the ferromagnetic layer 421 and the non-magnetic layer 422 are connected to the SOT layer 41, while the ferromagnetic layer 423 and the non-magnetic layer 424 are not connected to it. In other words, for example, the ferromagnetic layer 421 is connected to the non-magnetic layer 412. The non-magnetic layer 422 is disposed between the insulating layer 32 and the ferromagnetic layer 421, and has a portion connected to the non-magnetic layer 412. The ferromagnetic layer 423 is not connected to the non-magnetic layer 412. Other structures will be described later in the second embodiment.

[0092] The multilayer wiring layer LL includes a conductor layer 23 and a switching layer 43. The conductor layer 23 is, for example, configured as a plate extending along the XY plane. The conductor layer 23 contains, for example, tungsten (W) or molybdenum (Mo). The conductor layer 23 primarily functions as the read word line RWL.

[0093] The switching layer 43 covers the surface of the conductive layer 23, except for the portion where the conductive layer 23 contacts the component SLT (not shown). The switching layer 43 has portions disposed between the conductive layer 23 and the non-magnetic layer 424, and between the conductive layer 23 and the insulating layer 32. The switching layer 43 includes a layer that functions as a selector in the memory cell MC. That is, the switching layer 43 functions as a switching element SEL2 in the memory cell MC. The switching layer 43 has a substrate layer 431, a variable resistance material layer 432, and a capping layer 433.

[0094] The capping layer 433 covers the surface of the conductive layer 23, except for the portion of the conductive layer 23 that contacts the component SLT (not shown). The capping layer 433 may contain, for example, Ta, W, Ti, TaN, WN, TiN, or amorphous carbon (aC). The capping layer 433 may be composed of a single layer containing the above materials, or it may be composed of multiple laminated layers containing the above materials. The capping layer 433 may, for example, improve the adhesion between the conductive layer 23 and the switching layer 43. The capping layer 433 may, for example, function as a barrier metal layer for the conductive layer 23. The capping layer 433 may, for example, prevent W contained in the conductive layer 23 from diffusing to the adjacent insulating layer 32.

[0095] The variable resistance material layer 432 covers the area around the cover layer 433, except for the portion of the cover layer 433 that contacts the component SLT (not shown).

[0096] The variable resistance material layer 432 may contain, for example, at least one chalcogenide element selected from the group consisting of tellurium (Te), selenium (Se), and sulfur (S). Alternatively, the variable resistance material layer 432 may contain compounds containing the aforementioned chalcogenide elements, i.e., sulfides. Similarly, the variable resistance material layer 432 may also contain at least one element selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb).

[0097] Furthermore, the variable resistance material layer 432 can also use a pn bonding material, which uses silicon (Si) and germanium (Ge).

[0098] The substrate layer 431 covers the area surrounding the variable resistance material layer 432, except for the portion where the variable resistance material layer 432 contacts the component SLT (not shown). The substrate layer 431 is, for example, disposed between the variable resistance material layer 432 and the non-magnetic layer 424, and between the variable resistance material layer 432 and the insulating layer 32. The substrate layer 431 contains, for example, Ta, W, Ti, TaN, WN, TiN, or α-C. The substrate layer 431 can be composed of a single layer containing the above materials, or it can be composed of multiple laminated layers containing the above materials. The substrate layer 431, for example, improves the contact between the magnetoresistive element MTJ and the switching layer 43. The substrate layer 431 can also function as a barrier metal layer for the conductive layer 23. The substrate layer 431 can, for example, prevent W contained in the conductive layer 23 from diffusing to the adjacent insulating layer 32.

[0099] The switching layer 43 is, for example, a two-terminal switching element. The first terminal of the two terminals corresponds to the surface of the cover layer 433 that is in contact with the conductive layer 23, and the second terminal of the two terminals corresponds to the surface of the base layer 431 that is in contact with the insulating layer 32 and the non-magnetic layer 424. When the voltage applied between the two terminals does not reach a threshold, the switching element is in a "high resistance" state, for example, a non-conductive state (open state). When the voltage applied between the two terminals is above the threshold, the switching element becomes a "low resistance" state, for example, a conductive state (closed state).

[0100] The above-described structure of switch layer 43 is one example. Switch layer 43 can also have other structures as long as it functions as a switching element between two terminals. Switch layer 43 can use, for example, a quick-return switch type selector, a nonlinear type IV selector, a unipolar diode based on a pn junction, or a bipolar diode. In other words, switch layer 43 can use a selector with nonlinear current-voltage characteristics, a selector with quick-return characteristics, or a diode. Later, referring to FIG7, an example of the voltage and current characteristics of the memory cell MC when a selector with quick-return characteristics is used in switch layer 43 will be described.

[0101] The above-described structure of the magnetoresistive element MTJ is one example; the magnetoresistive element MTJ can also have other structures. For example, the non-magnetic layer 422 can also have a portion disposed on the side of the non-magnetic layer 412 in the layer containing the insulating layer 32 (hereinafter referred to as non-magnetic layer 422a). In other words, the non-magnetic layer 422 can also have a portion sandwiched between the insulating layer 32 and the non-magnetic layer 412, namely, the non-magnetic layer 422a. The non-magnetic layer 422a can be disposed on the entire side of the non-magnetic layer 412 in the layer containing the insulating layer 32, or it can be disposed on a portion thereof. That is, the non-magnetic layer 422 can be continuously disposed in the layer containing the insulating layer 32 and the layer containing the multilayer wiring layer LL, or it can be discontinuously disposed. The magnetoresistive element MTJ can include additional layers.

[0102] Figure 7 shows an example of the voltage and current characteristics of the memory cell in the magnetic memory device 1 of the first embodiment. The switching element SEL2 (switching layer 43) can have the quick-return characteristics shown in Figure 7. The horizontal axis of the graph shows the magnitude of the terminal voltage (i.e., the potential difference between the two ends) of the memory cell MC. The vertical axis of the graph shows the magnitude of the current flowing through the memory cell MC on a logarithmic scale. In Figure 7, the hypothetical characteristics not actually shown are shown by dashed lines. Figure 7 shows the memory cell MC in a low resistance state and in a high resistance state.

[0103] As the voltage increases from 0, the current continues to increase until it reaches the threshold voltage Vth. The switching element SEL2 of the memory cell MC is turned off, i.e., non-conducting, until the voltage reaches the threshold voltage Vth.

[0104] As the voltage increases further and reaches the threshold voltage Vth, i.e., at point A, the relationship between voltage and current exhibits discontinuous changes, displaying the characteristics shown at points B1 and B2. The current at points B1 and B2 is significantly greater than the current at point A. This rapid change in current is due to the switching element SEL2 of the memory cell MC being turned on. The magnitude of the current at points B1 and B2 depends on the resistance state of the MTJ element MTJ in the memory cell MC.

[0105] From the state where the switching element SEL2 is turned on, for example, when the voltage and current display shows the relationship between point B1 or point B2 and a point with a higher voltage, the current continues to decrease as the voltage decreases.

[0106] When the voltage decreases further and reaches a certain level, the voltage-current relationship exhibits discontinuous changes. The voltage at which this discontinuity begins depends on the terminal voltage of the MTJ element in the memory cell MC, i.e., whether the MTJ element is in a high-resistance or low-resistance state. When the MTJ element is in a low-resistance state, the voltage-current relationship exhibits discontinuities starting from point C1. When the MTJ element is in a high-resistance state, the voltage-current relationship exhibits discontinuities starting from point C2. When points C1 and C2 are reached, the voltage-current relationship exhibits the characteristics shown at points D1 and D2, respectively. The current magnitudes at points D1 and D2 are significantly smaller than the current magnitudes at points C1 and C2, respectively. This rapid change in current is due to the opening of the switching element SEL2 in the memory cell MC.

[0107] The terminal voltage at point D1 of the memory cell MC of an MTJ element in a low-resistance state is called the low holding voltage VhdL. The terminal voltage at point D2 of the memory cell MC of an MTJ element in a high-resistance state is called the high holding voltage VhdH.

[0108] Figure 8 is a cross-sectional view along line VIII-VIII of Figure 6, showing an example of the cross-sectional structure of the memory pillar MP in the magnetic memory device 1 of the first embodiment. Specifically, Figure 8 shows the cross-sectional structure of the memory pillar MP in a layer parallel to the surface of the semiconductor substrate 20 and including the conductive layer 23. The upper part (A) of Figure 8 shows an example when the magnetoresistive element MTJ is in a low-resistance state. The lower part (B) of Figure 8 shows an example when the magnetoresistive element MTJ is in a high-resistance state.

[0109] In a cross-section including the conductive layer 23, the memory module MP has a core component 40 at its center. An SOT layer 41 surrounds the sides of the core component 40. A ferromagnetic layer 421 surrounds the sides of the SOT layer 41. A non-magnetic layer 422 surrounds the sides of the ferromagnetic layer 421. A ferromagnetic layer 423 surrounds the sides of the non-magnetic layer 422. A non-magnetic layer 424 surrounds the sides of the ferromagnetic layer 423. A switching layer 43 surrounds the sides of the non-magnetic layer 424. The conductive layer 23 surrounds the sides of the switching layer 43.

[0110] When viewed from the +Z side in the XY plane (top view), the ferromagnetic layer 423 has an easy magnetization axis extending along its shape (or circumference). The magnetization direction of the ferromagnetic layer 423 is fixed. "Fixed magnetization direction" means that the magnetization direction will not change due to a torque of magnitude that could reverse the magnetization direction of the ferromagnetic layer 423. In the example of Figure 8, the magnetization direction of the ferromagnetic layer 423, when viewed from above, is clockwise along the easy magnetization axis.

[0111] When viewed from the +Z side in the XY plane (top view), the ferromagnetic layer 421 has an easy magnetization axis extending along its shape (or circumference). The spin-orbit torque generated in the non-magnetic layer 412 acts on the ferromagnetic layer 421. When a specified voltage Vw0 or Vw1 (described later in Figure 9) is applied and a specified spin-orbit torque is applied, the magnetization direction of the ferromagnetic layer 421 is reversed.

[0112] Depending on whether the magnetoresistive element MTJ has parallel or antiparallel magnetization directions between the memory layer (ferromagnetic layer 421) and the reference layer (ferromagnetic layer 423), it can be either in a low-resistance state or a high-resistance state.

[0113] The upper part (A) of Figure 8 shows an example of the magnetoresistive element MTJ in a low-resistance state. In this state, the ferromagnetic layer 421 is magnetized clockwise when viewed from the +Z side in the XY plane (viewed from above). That is, the relative magnetization directions of the memory layer (ferromagnetic layer 421) and the reference layer (ferromagnetic layer 423) are parallel. In this parallel state, the resistance of the magnetoresistive element MTJ is at its lowest, and the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "P (Parallel) state," for example, defined as the state of data "0".

[0114] Figure 8, bottom part (B), shows an example of the magnetoresistive element MTJ in a high-resistance state. In this state, the ferromagnetic layer 421 is magnetized in a counter-clockwise direction when viewed from the +Z side in the XY plane (viewed from above). That is, the relative magnetization directions of the memory layer (ferromagnetic layer 421) and the reference layer (ferromagnetic layer 423) are antiparallel. In this antiparallel state, the resistance of the magnetoresistive element MTJ is highest, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (Anti-Parallel) state," for example, defined as the state of data "1".

[0115] Furthermore, the way data "1" and data "0" are defined is not limited to the above example. For example, the P state can also be defined as data "1" and the AP state as data "0".

[0116] Next, the operation of the magnetic memory device in the first embodiment will be explained.

[0117] First, the first example of a write operation will be explained. In the magnetic memory device 1, the magnetization direction of the memory layer relative to the reference layer is controlled by utilizing the voltage control of magnetic anisotropy (VCMA) effect and spin-orbit torque. Specifically, a write method is adopted that utilizes the VCMA effect generated by applying a voltage to the read word line RWL and the spin-orbit torque generated by allowing current to flow to the wiring SOTL.

[0118] Figure 9 shows an example of the voltage applied to the memory cell array in the first example of the write operation of the magnetic memory device in the first embodiment. Figure 9 shows the case where the write current Ic0 flows to the wiring SOTL to write data "0", representing the first example of the write operation. In Figure 9, the memory cell MC selected as the write target (i.e., the selected state) is memory cell MC.<m,n> .

[0119] Figure 9 shows a portion of the memory cell array 10. Specifically, first, the selected memory cells MC are displayed.<m,n> SOTL connection wiring <n>Select readout bit line RBL <n>Select Write Bit Line WBL <n>and select readout character line RWL <m>Furthermore, in Figure 9, MC is considered as an unselected memory cell.<m,n> The connection wiring SOTL, non-select read bit line RBL, non-select write bit line WBL, and non-select word line RWL are represented, showing the SOTL wiring. <n-1>and SOTL<n+1> Non-selective readout bit line RBL <n-1>and non-selective RBL<n+1> Non-selective write bit line WBL <n-1>and WBL<n+1> Non-selective read character line RWL <m-1>and RWL<m+1> Areas not shown are not associated with the selected memory cell MC.<m,n> The states of the connection wiring SOTL, non-select read bit line RBL, non-select write bit line WBL, and non-select read word line RWL are the same as those of wiring SOTL in the following description. <n-1>and SOTL<n+1> Readout bit line RBL <n-1>and RBL<n+1> Write bit line WBL <n-1>and WBL<n+1> Read out character lines RWL <m-1>and RWL<m+1> Their states are the same.

[0120] Additionally, in Figure 9, the switching elements SEL2 and TR1 in the ON state are marked with "○", and the switching elements SEL2 and TR1 in the OFF state are marked with "×".

[0121] Furthermore, regarding the selection of memory cells MC<m,n> In the first case of performing a write operation, the read bit line RBL is... <n>and write bit line WBL <n>Apply voltages Vc0 and VSS respectively. Voltage VSS is, for example, 0V. Voltage Vc0 is used to induce the write current Ic0. <n>(Not shown) The voltage flowing to the SOTL wiring has the effect of causing the write current Ic0. <n>The size of the flow to the SOTL wiring. Applied to the read bit line RBL. <n>and write bit line WBL <n>The voltage is controlled by the line decoder 12. Next, the read bit lines RBL are respectively... <n-1>and write bit line WBL <n-1>Apply voltage VSS. Then apply voltage to the readout bit line RBL.<n+1> and write bit line WBL<n+1> A voltage VSS is applied. Therefore, the write current Ic0 will not flow to the wiring SOTL. <n>All other wiring SOTL.

[0122] Furthermore, for the selected character line RWL <m>Apply voltage Vw0. Voltage Vw0 is, for example, greater than the threshold voltage of switching element TR1 and less than the breakdown voltage of switching element TR1. Details of voltage Vw0 will be described later in Figure 10. Apply to the select word line RWL. <m>The voltage is controlled by column decoder 11.

[0123] RWL for non-selected character lines <m-1>and RWL<m+1> Apply voltage VSS.

[0124] By applying the voltage as described above, the switching element SEL2<m,n> When TR1 is in the ON state, all other switching elements SEL2 are in the OFF state. <n>It becomes the ON state. Meanwhile, all other switching elements TR1 become the OFF state.

[0125] When selecting the readout character line RWL <m>When a voltage Vw0 is applied, for example, a current Iw0 <m>(Not shown) Via the selected memory cell MC<m,n> Flow to select write bit line WBL <n>As mentioned above, due to the switching element SEL2<m,n> With the circuit in the ON state, all other switching elements SEL2 are in the OFF state, so the current Iw0 will not flow to the other write bit lines WBL.

[0126] Figure 10 is a diagram showing an example of the current and magnetization direction applied to the memory cell array in the first example of the write operation of the magnetic memory device in the first embodiment. Figure 10 shows a configuration including the selected memory cell MC.<m,n> MS memory string <n>.

[0127] As described above, for the selected readout bit line RBL <n>and select write bit line WBL <n>Voltages Vc0 and VSS are applied respectively. This is used to control the SOTL wiring. <n>In the non-magnetic layer 412 that performs the function, the write current Ic0 <n>Flow is directed in the -Z direction. This is achieved by increasing the write current Ic0. <n>As it flows through the non-magnetic layer 412, it generates a spin-orbit torque that aims to make the magnetization direction of the ferromagnetic layer 421 parallel to that of the ferromagnetic layer 423. The spin-orbit torque acts on all the ferromagnetic layers 421 that are in contact with the non-magnetic layer 412.

[0128] Furthermore, as mentioned above, for the selection character line RWL <m>A voltage Vw0 is applied to the conductive layer 23, which performs the function. This causes a current Iw0 to flow in the non-magnetic layer 412. <m>Flowing in the -Z direction. Current Iw0 <m>via magnetoresistive element MTJ<m,n> and switching element SEL2<m,n> , self-selected read character line RWL <m>The conductive layer 23, which performs the function, flows into the non-magnetic layer 412. Current Iw0 <m>The current value is less than the write current Ic0 <n>The current value.

[0129] Here, the voltage Vw0 is used to select the memory cell MC via the VCMA effect.<m,n> MTJ magnetoresistive element<m,n> The voltage at which the energy barrier height is reduced below energy Ew0 during magnetization reversal of the ferromagnetic layer 421 contained therein is a voltage that reduces the energy barrier height below energy Ew0. The following describes the magnetoresistive element MTJ.<m,n> The height of the energy barrier when the magnetization of the ferromagnetic layer 421 is reversed is called the energy barrier height ΔE.<m,n> The situation.

[0130] By applying a voltage Vw0 to the conductive layer 23, the energy barrier height ΔE<m,n> The energy becomes below Ew0. The VCMA effect only acts on the ferromagnetic layer 421 on the read word line RWL where the applied voltage Vw0 is applied. That is, the VCMA effect does not act on the magnetoresistive element MTJ.<m-1,n> and magnetoresistive element MTJ<m+1,n> The ferromagnetic layer 421. Therefore, the energy barrier height ΔE<m-1,n> and ΔE<m+1,n> It is a value greater than the energy Ew0.

[0131] At the energy barrier height ΔE<m,n> When the energy Ew0 is below, the write current Ic0 flows to the wiring SOTL. <n>Subsequently, the magnetization direction of ferromagnetic layer 421 becomes parallel to ferromagnetic layer 423 due to the generated spin-orbit torque (the state in the upper part (A) of Figure 8). That is, the selected memory cell MC<m,n> The magnetization direction of ferromagnetic layer 421 is reversed to a direction parallel to the magnetization direction of ferromagnetic layer 423. The VCMA effect caused by voltage Vw0, for example, accelerates the selective memory cell MC arising from spin-orbit torque.<m,n> The reversal speed of the magnetization direction of the ferromagnetic layer 421.

[0132] Also, as shown in Figure 10, E<m-1,n> and ΔE<m+1,n> As shown, when the energy barrier height ΔE is greater than the energy Ew0, even if the write current Ic0 flows to the wiring SOTL <n>Even with the spin-orbit torque in effect, the magnetization direction of the ferromagnetic layer 421 will not be reversed.

[0133] By performing the above actions, the data "0" is written to the selected memory cell MC.<m,n> middle.

[0134] Next, a second example of the write operation will be described. Figure 11 shows an example of the current and magnetization direction applied to the memory cell array in the second example of the write operation of the magnetic memory device in the first embodiment. Figure 11 corresponds to Figure 10 in the first example of the write operation. In Figure 11, the write current Ic1 flows to the wiring SOTL to write the data "1", which is the second example of the write operation.

[0135] For the selection of memory cells MC<m,n> In the second example of performing a write operation, the on or off state of the switching element SEL2 is the same as in Figure 9 of the first example of the write operation. Furthermore, regarding the memory string MS... <n>The second example of the write operation for the memory string MS is the same as the first example of the write operation, so the explanation is omitted.

[0136] Selected readout bit line RBL <n>and select write bit line WBL <n>Voltages VSS and Vc1 are applied respectively. This is used to control the SOTL wiring. <n>In the non-magnetic layer 412 that performs the function, the write current Ic1 <n>Flow is directed towards the +Z direction. This is achieved through the write current Ic1. <n>As it flows through the non-magnetic layer 412, it generates a spin-orbit torque that aims to make the magnetization direction of the ferromagnetic layer 421 antiparallel to that of the ferromagnetic layer 423. The spin-orbit torque acts on all the ferromagnetic layers 421 that are in contact with the non-magnetic layer 412.

[0137] Furthermore, regarding the RWL as a selection character line... <m>A voltage Vw1 is applied to the conductive layer 23 that performs the function. The voltage Vw1 is, for example, greater than the threshold voltage of the switching element TR1 and less than the breakdown voltage of the switching element TR1. Therefore, a current Iw1 flows in the non-magnetic layer 412. <m>Flowing in the +Z direction. Current Iw1 <m>via magnetoresistive element MTJ<m,n> and switching element SEL2<m,n> , self-selected read character line RWL <m>The conductive layer 23, which performs the function, flows into the non-magnetic layer 412. Current Iw1 <m>The current value is less than the write current Ic1 <n>The current value.

[0138] Here, the voltage Vw1 is used to increase the energy barrier height ΔE through the VCMA effect.<m,n> Lowering the voltage to below energy Ew1 has the effect of reducing the energy barrier height ΔE<m,n> Reduced to a size below energy Ew1.

[0139] By applying a voltage Vw1 to the conductive layer 23, the energy barrier height ΔE<m,n> The energy becomes below Ew1. The VCMA effect only acts on the ferromagnetic layer 421 on the read word line RWL where the applied voltage Vw1 is applied. That is, the VCMA effect does not act on the magnetoresistive element MTJ.<m-1,n> and magnetoresistive element MTJ<m+1,n> The ferromagnetic layer 421. Therefore, the energy barrier height ΔE<m-1,n> and ΔE<m+1,n> It is a value greater than the energy Ew1.

[0140] At the energy barrier height ΔE<m,n> When the energy is below Ew1, the write current Ic1 flows to the wiring SOTL. <n>Subsequently, the magnetization direction of ferromagnetic layer 421 becomes antiparallel to ferromagnetic layer 423 due to the generated spin-orbit torque (the state in the lower part (B) of Figure 8). That is, the selected memory cell MC<m,n> The magnetization direction of ferromagnetic layer 421 is reversed to an antiparallel direction relative to the magnetization direction of ferromagnetic layer 423. The VCMA effect caused by voltage Vw1, for example, accelerates the selective memory cell MC arising from spin-orbit torque.<m,n> The reversal speed in the magnetization direction of the ferromagnetic layer 421.

[0141] Also, as shown in Figure 11, E<m-1,n> and ΔE<m+1,n> As shown, when the energy barrier height ΔE is greater than the energy Ew1, even if the write current Ic1 flows to the wiring SOTL <n>Even with the spin-orbit torque in effect, the magnetization direction of the ferromagnetic layer 421 will not be reversed.

[0142] By performing the above actions, data "1" is written into the selected memory cell MC.<m,n> middle.

[0143] Next, the readout operation will be explained. Figure 12 shows an example of the voltage applied to the memory cell array during the readout operation of the magnetic memory device in the first embodiment. In the example of Figure 12, the voltage applied from the memory cell MC...<m,n> Example of reading data. Displaying and selecting memory cells (MCs).<m,n> SOTL connection wiring <n>Select readout bit line RBL <n>Select Write Bit Line WBL <n>and select readout character line RWL <m>Similarly, as shown in Figure 9, the SOTL wiring is illustrated as an example. <n-1>and SOTL<n+1> Non-selective readout bit line RBL <n-1>and RBL<n+1> Non-selective write bit line WBL <n-1>and WBL<n+1> Non-selective read character line RWL <m-1>and RWL<m+1> Similar to Figure 9, this shows an example of the voltage applied to each wiring. Also, similar to Figure 9, the switching elements SEL2 and TR1 in the ON state are marked with "○", and the switching elements SEL2 and TR1 in the OFF state are marked with "×".

[0144] For the selection of memory cells MC<m,n> When performing a read operation, select the read bit line RBL. <n>and select write bit line WBL <n>By having the line decoder 12 enter the selection state, the selected readout bit line RBL is selected. <n>Apply voltage VSS. Apply a voltage to the write word line WWL that turns off all switching elements TR1. Since switching elements TR1 are off, a voltage is applied to the select write bit line WBL. <n>The voltage is arbitrary. Furthermore, the non-selectable readout bit line RBL... <n-1>and non-select write bit line WBL <n-1>The line decoder 12 becomes non-selected and electrically floating. Similarly, the non-selected readout bit line RBL...<n+1> and non-select write bit line WBL<n+1> The line decoder 12 is in a non-selected state and becomes an electrically floating state.

[0145] Furthermore, for the selected character line RWL <m>Apply voltage Vr. Voltage Vr is, for example, greater than the threshold voltage of switching element TR1, and less than voltages Vw0 and Vw1. For the select word line RWL... <m>Non-select character lines RWL on both sides <m-1>and RBL<m+1> Apply voltage VSS.

[0146] By applying the voltage described above, the switching element SEL2<m,n> When the switch is in the ON state, all other switching elements SEL2 become OFF state. All switching elements TR1 become OFF state.

[0147] When selecting the readout character line RWL <m>When a voltage Vr is applied, for example, the current Ir is read out. <m>(Not shown) Via the selected memory cell MC<m,n> Flow to select read bit line RBL <n>Read the current Ir <m>The current value is less than the write current Ic0 <n>and Ic1 <n>The current value. As mentioned above, due to the switching element SEL2<m,n> When the circuit is on, all other switching elements SEL2 are off, so the read current Ir does not flow to the other select read bit lines RBL.

[0148] Figure 13 shows an example of the current applied to the memory cell array during the readout operation of the magnetic memory device in the first embodiment. Figure 13 shows the memory cell MC containing the readout object (i.e., the selected state).<m,n> MS memory string <n>.

[0149] As mentioned above, for the selection character line RWL <m>A voltage Vr is applied to the conductive layer 23, which performs the function. This allows the current Ir to be read out in the non-magnetic layer 412. <m>Flowing in the +Z direction. Read the current Ir. <m>via magnetoresistive element MTJ<m,n> and switching element SEL2<m,n> , self-selected read character line RWL <m>The conductive layer 23, which performs the function, flows into the non-magnetic layer 412.

[0150] By allowing the read current Ir to flow through the magnetoresistive element MTJ, the read circuit 13 can determine whether the magnetoresistive element MTJ is in a high-resistance state or a low-resistance state based on the read current Ir. Furthermore, the read current Ir is controlled to be less than the write currents Ic0 and Ic1.

[0151] Next, the manufacturing method of the magnetic memory device of the first embodiment will be described. Figure 14 is a flowchart showing an example of the manufacturing method of the magnetic memory device of the first embodiment. Figures 15 to 27 are examples of cross-sectional structures during the manufacturing process of the magnetic memory device 1 of the first embodiment. Figures 15 to 27 show a region including a portion of the area shown in Figure 4. Hereinafter, referring appropriately to Figure 14, an example of the manufacturing process related to the formation of the multilayer wiring structure within the memory cell array 10 in the magnetic memory device 1 of the first embodiment will be described. As shown in Figure 14, the manufacturing method of the magnetic memory device 1 of the first embodiment, for example, sequentially performs steps S101 to S113.

[0152] In step S101, as shown in FIG15, sacrificial members and insulating layers are alternately deposited. First, insulating layer 30 and insulating layer 31 are sequentially formed on semiconductor substrate 20. Switching element TR1, conductive layers 25-27 and contact CS are formed in a portion of semiconductor substrate 20 and within insulating layer 30. Sacrificial member 51 and insulating layer 32 are alternately deposited on insulating layer 31. Insulating layer 33a is formed on the uppermost sacrificial member 51. Insulating layers 30-33a and sacrificial member 51 are formed, for example, by ALD or CVD.

[0153] The sacrificial member 51 is formed in a predetermined region of the multilayer wiring layer LL that functions as the read word line RWL. For example, the number of layers forming the sacrificial member 51 is equal to the number of read word lines RWL. The insulating layers 30 to 33a each contain, for example, silicon oxide. The sacrificial member 51 contains, for example, silicon nitride.

[0154] In step S102, as shown in FIG16, a hole MH is formed. FIG16 shows a region including a portion of the area shown in FIG15. From FIG16 onwards, illustrations of the semiconductor substrate 20, switching element TR1, conductive layers 25-27, and contact CS are omitted. For example, the hole MH is formed by RIE (Reactive Ion Etching). The hole MH penetrates both the insulating layers 31-33a and the sacrificial member 51. The bottom of the hole MH reaches the conductive layer 25 within the insulating layer 30.

[0155] In step S103, as shown in FIG17, a portion of the sacrificial member 51 is recessed. FIG17 shows a cross-section of the same area as FIG16. Specifically, wet etching is performed via the via MH to remove a portion of each of the plurality of sacrificial members 51 exposed on the side of the via MH. The etching solution contains, for example, phosphoric acid (H3PO4). Thereby, the side of the via MH is shaped to remove a portion of the sacrificial member 51. The space created by removing a portion of the sacrificial member 51 in this process is referred to as space RP1. Space RP1 is, for example, a predetermined area for forming a magnetoresistive element MTJ.

[0156] In step S104, as shown in FIG18, a ferromagnetic layer 623 is formed. FIG18 shows a region including a portion of the region shown in FIG17. FIG18 shows a portion of the hole MH and the structure of the sacrificial member 51 and the region within the hole MH that intersects with the sacrificial member 51. First, a non-magnetic layer 424 is formed on the surface and bottom surface of the hole MH and the surface exposed in the space RP1. Next, a ferromagnetic layer 623 is formed on the surface of the non-magnetic layer 424. The ferromagnetic layer 623 is embedded in the space RP1, for example. The non-magnetic layer 424 and the ferromagnetic layer 623 are formed, for example, by ALD or CVD. By performing the process described later, a ferromagnetic layer 423 is formed from a portion of the ferromagnetic layer 623.

[0157] In step S105, as shown in FIG19, a ferromagnetic layer 423 is formed. FIG19-FIG.22 show cross-sections of the same area as FIG18. Wet etching is performed through the via MH. The wet etching solution etches the ferromagnetic layer 623 and the non-magnetic layer 424 formed in the via MH. That is, the ferromagnetic layer 623 and the non-magnetic layer 424 formed on the side of the insulating layer 32 are removed.

[0158] A portion of each of the ferromagnetic layer 623 and the non-magnetic layer 424 formed on the layer containing the sacrificial member 51 is removed. In this process, the space created by removing a portion of the ferromagnetic layer 623 and the non-magnetic layer 424 formed on the layer containing the sacrificial member 51 is referred to as space RP2. Space RP2 is the space that exposes a portion of space RP1 again. Therefore, the side of the hole MH is machined into a shape to remove a portion of the ferromagnetic layer 623 and the non-magnetic layer 424 formed in step S104. The ferromagnetic layer 623 after etching is ferromagnetic layer 423. That is, ferromagnetic layer 423 is formed by etching ferromagnetic layer 623.

[0159] In step S106, as shown in FIG20, a non-magnetic layer 422 and a ferromagnetic layer 621 are formed. Specifically, firstly, by the process in step S105, an oxide film or the like that accidentally formed on the surface of the ferromagnetic layer 423 is removed. Next, a non-magnetic layer 422 is formed on the surface of the ferromagnetic layer 423. Next, a ferromagnetic layer 621 is formed on the surface of the non-magnetic layer 422. The non-magnetic layer 422 and the ferromagnetic layer 621 are embedded, for example, in a space RP2. The non-magnetic layer 422 and the ferromagnetic layer 621 are continuously formed in a vacuum environment of ALD or CVD. By performing the process described later, a ferromagnetic layer 421 is formed from a portion of the ferromagnetic layer 621.

[0160] In step S107, as shown in FIG21, a magnetoresistive element MTJ is formed. Specifically, wet etching is performed via via MH. The wet etching solution etches the ferromagnetic layer 621 and the non-magnetic layer 422 formed in the via MH. That is, the ferromagnetic layer 621 and the non-magnetic layer 422 formed on the side of the insulating layer 32 are removed. The ferromagnetic layer 621 after the etching process is called the ferromagnetic layer 421. That is, the ferromagnetic layer 421 is formed by etching the ferromagnetic layer 621.

[0161] Ideally, the size of the outer perimeter of the aperture MH is substantially the same in both the layer containing the insulating layer 32 and the layer containing the sacrificial member 51. That is, ideally, the position of the exposed side of the ferromagnetic layer 421 in the aperture MH is substantially the same in the Z-direction (when viewed from above in XY). However, for example, the size of the outer perimeter of the aperture MH may deviate due to the difference in etching rates between the insulating layer 32 and the ferromagnetic layer 421. For example, the size of the outer perimeter of the aperture MH may be larger in the layer containing the sacrificial member 51 than in the layer containing the insulating layer 32.

[0162] Furthermore, Figure 21 describes the removal of the non-magnetic layer 422 formed on the side of the insulating layer 32, but it is also possible to retain part or all of the non-magnetic layer 422. Only the ferromagnetic layer 621 needs to be removed from the side of the insulating layer 32.

[0163] In step S108, as shown in FIG22, an SOT layer 41 and a core member 40 are formed. Specifically, firstly, a non-magnetic layer 412 is formed on the surface exposed in the via MH. The lower end of the non-magnetic layer 412 contacts a conductive layer 25 (not shown) within the insulating layer 30. Next, a non-magnetic layer 411 is formed on the surface of the non-magnetic layer 412. Then, the core member 40 is embedded in the via MH. The non-magnetic layer 412, the non-magnetic layer 411, and the core member 40 are formed, for example, by ALD or CVD. This forms the memory pillar MP.

[0164] In step S109, as shown in FIG23, a slit SH is formed. FIG23 shows a cross-section of the same region as FIG16. First, an insulating layer 33b is formed on the upper surface of the insulating layer 33a and the memory pillar MP. Hereinafter, the layer including the insulating layer 33a and the insulating layer 33b is referred to as insulating layer 33. A slit SH is formed in a predetermined region of the forming member SLT. Specifically, a mask corresponding to the opening of the region of the slit SH is formed by photolithography, etc., and the slit SH is formed by anisotropic etching using the mask. The slit SH, for example, separates the insulating layers 31-33 and the sacrificial member 51 and reaches the insulating layer 30.

[0165] In step S110, as shown in FIG24, the sacrificial member 51 is removed. FIG24 shows a cross-section of the same area as FIG16. For example, the sacrificial member 51 is selectively removed via a slit SH by wet etching. The etching solution contains, for example, phosphoric acid (H3PO4). This creates a space in a predetermined area where the multilayer wiring layer LL is formed. At this time, the magnetoresistive element MTJ, by having a non-magnetic layer 424, prevents the etching solution from eroding the ferromagnetic layer 423. The three-dimensional structure of the structure after the sacrificial member 51 is removed is maintained by a plurality of memory pillars MP.

[0166] In step S111, as shown in FIG25, a switching layer 43 is formed. FIG25 shows a cross-section of the same region as FIG18. First, a base layer 431 is formed via a slit SH on the surface exposed in the space after the sacrificial member 51 is removed. Next, a variable resistance material layer 432 is formed on the surface of the base layer 431 via the slit SH. Next, a capping layer 433 is formed on the surface of the variable resistance material layer 432 via the slit SH. The base layer 431, the variable resistance material layer 432, and the capping layer 433 are formed, for example, by ALD or CVD. Thus, the switching layer 43 is formed in a portion of the space after the sacrificial member 51 is removed.

[0167] In step S112, as shown in FIG26, a conductive layer 23 is formed. FIG26 shows a cross-section of the same region as FIG18. The conductive layer 23 is formed on the surface of the capping layer 433 through the slit SH, and the space after the removal of the sacrificial member 51 is embedded by the conductive layer 23. The conductive layer 23 is formed, for example, by ALD or CVD. Then, the base layer 431, the variable resistance material layer 432, the capping layer 433 and the conductive layer 23 formed inside the slit SH are removed by an etching process. Thereby, a plurality of stacked wiring layers LL that function as readout character lines RWL0 to RWL9 are formed respectively.

[0168] In step S113, as shown in Figure 27, the component SLT is formed. Figure 27 shows a cross-section of the same area as in Figure 16. First, the component SLT is embedded in the slit SH. Next, the contact CV is set on the memory pillar MP. Then, a conductive layer 25, which functions as the read bit line RBL, is formed on the contact CV (see Figure 5).

[0169] The manufacturing process of the magnetic memory device 1 in the first embodiment described above forms a multilayer wiring structure within the memory cell array 10. Furthermore, the manufacturing process described above is merely one example and is not limited to it. For example, other processes can be inserted between the manufacturing processes, and some processes can be omitted or combined. Also, the order of the manufacturing processes can be changed within the scope of not causing problems.

[0170] For example, when forming the layers of a magnetoresistive element MTJ via a hole MH, to improve embeddability, the layers of the magnetoresistive element MTJ can be formed in a microcrystalline state, such as amorphous. In this case, the layers of the magnetoresistive element MTJ can be formed by ALD.

[0171] Furthermore, for example, when forming the layers of the magnetoresistive effect element MTJ through the aperture MH, if it is desired to selectively form the layers contained in the magnetoresistive effect element MTJ in the space RP1 or RP2 to be thicker than the side surface of the insulating layer 32, for example, ALD can also be used.

[0172] For example, when forming each layer of the switching layer 43 via the slit SH, to improve embeddability, each layer of the switching layer 43 can be formed in a microcrystalline state, such as amorphous. In this case, each layer of the switching layer 43 can be formed by ALD.

[0173] Furthermore, for example, the above-described manufacturing method shows an example of removing the sacrificial member 51 after forming the magnetoresistive element MTJ, but it is not limited to this. The magnetoresistive element MTJ or a portion thereof may also be formed after removing the sacrificial member 51. That is, the magnetoresistive element MTJ or a portion thereof may also be formed via the slit SH. For example, when the ferromagnetic layer 423 is formed via the slit SH, since it is not necessary to protect the ferromagnetic layer 423 from the etching solution in step S110, the formation of the non-magnetic layer 424 can be omitted.

[0174] The effects of the magnetic memory device 1 in the first embodiment will be explained below.

[0175] According to the magnetic memory device 1 of the first embodiment, the magnetoresistive element MTJ has a circulating magnetization structure (closed magnetic circuit, closed magnetic path). That is, the ferromagnetic layers 421 and 423 are formed in a cylindrical shape, and the magnetization circulates along the circumference. Therefore, in a static environment, no magnetic charge is generated at the ends of the ferromagnetic layers 421 and 423. Since no magnetic charge is generated at the ends of the ferromagnetic layers 421 and 423, the magnetoresistive element MTJ can have a structure that is stable to both heat and external magnetic fields.

[0176] Furthermore, according to the magnetic memory device 1 of the first embodiment, since there are no magnetic charges at the ends of the ferromagnetic layers 421 and 423, no leakage magnetic field is generated to the outside. Therefore, the magnetoresistive element MTJ will not cause magnetic field disturbance to adjacent bits. That is, according to the structure of the magnetoresistive element MTJ of the magnetic memory device 1, interference from the ferromagnetic layers 421 and 423 to adjacent bits can be suppressed.

[0177] Furthermore, according to the magnetic memory device 1 of the first embodiment, the magnetoresistive element MTJ does not have a SAF (Synthetic Anti-Ferromagnetic) structure. That is, the magnetoresistive element MTJ does not have a shift canceling layer and a spacer layer on the outer periphery of the reference layer. In other words, the magnetoresistive element MTJ does not have a structure between the ferromagnetic layer 423 and the multilayer wiring layer LL that is antiferromagnetically coupled to the ferromagnetic layer 423. The reason for this is that, as described above, since the ferromagnetic layers 421 and 423 do not generate leakage magnetic fields to the outside, there is no need for a SAF structure to specifically suppress the leakage magnetic field from the ferromagnetic layer 423 to the ferromagnetic layer 421. Thus, since the magnetoresistive element MTJ does not have a SAF structure, the structure can be simplified, the design can be made easier, and the manufacturing cost can be reduced.

[0178] Furthermore, in the magnetic memory device 1 according to the first embodiment, the non-magnetic layer 422 can be made thicker than the plate-like tunnel barrier layer in a magnetoresistive element (such as a magnetoresistive element MTJr) that is provided in a cuboid shape. To avoid obstructing read current, the tunnel barrier layer, which has insulating properties, requires a design to reduce resistance. For example, the tunnel barrier layer of the magnetoresistive element MTJr has a lower resistance design by making it thinner.

[0179] In contrast, since the non-magnetic layer 422 has a cylindrical shape, its conductive area can be designed to be larger compared to a plate-shaped tunnel barrier layer. That is, due to the larger conductive area, the non-magnetic layer 422 becomes a structure that allows current to flow easily to the magnetoresistive element MTJ even without thin-film fabrication. Compared to a plate-shaped tunnel barrier layer, the non-magnetic layer 422 can be made thicker to overcome the limitations of thin-film fabrication. In other words, according to the magnetic memory device 1 of the first embodiment, the design related to the resistance of the magnetoresistive element MTJ becomes easier.

[0180] Furthermore, in the magnetic memory device 1 according to the first embodiment, in the magnetoresistive effect element MTJ having a cylindrical shape, the reference layer, i.e., the ferromagnetic layer 423, is disposed on the outer periphery of the memory layer, i.e., the ferromagnetic layer 421. In this structure, it is easy to form the volume of the ferromagnetic layer 423 to be larger than the volume of the ferromagnetic layer 421. For example, when the thickness of the ferromagnetic layer 423 and the ferromagnetic layer 421 is the same, the volume of the ferromagnetic layer 423 will necessarily be larger than the volume of the ferromagnetic layer 421. At this time, the retention energy of the reference layer is greater than the retention energy of the memory layer. That is, by creating a difference between the volume of the reference layer and the volume of the memory layer, the magnetoresistive effect element MTJ can easily create a difference between the retention energy of the reference layer and the retention energy of the memory layer.

[0181] For example, in magnetoresistive devices, the energy retention of the reference layer needs to be designed to be greater than that of the memory layer. In the case of a structure like the magnetoresistive element MTJr, it is difficult to create a difference in the energy retention between the reference and memory layers based solely on the volume difference between the reference and memory layers. In such cases, the difference in energy retention between the reference and memory layers is controlled by the difference in magnetic anisotropy of the materials. That is, there are situations where different materials are used for the reference and memory layers.

[0182] In contrast, magnetoresistive (MTJ) devices can use the same material for both the reference and memory layers. By using the same material, it becomes easier to control the retained energy of the magnet compared to controlling magnetic anisotropy through materials. As a result, the design of magnetoresistive (MTJ) devices becomes easier.

[0183] Furthermore, according to the magnetic memory device 1 of the first embodiment, the magnetic memory device 1 has a switching layer in the multilayer wiring layer LL. Therefore, the magnetic memory device 1 can, for example, suppress the read current Ir from winding back to the memory cell MC on the same read word line RWL, thereby improving the selectivity of the memory cell MC. Also, it can suppress interference to adjacent bits caused by the applied voltage Vw0 or voltage Vw1.

[0184] Furthermore, according to the magnetic memory device 1 of the first embodiment, a write current Ic0 or Ic1 needs to flow during data writing. Therefore, it is possible to prevent erroneous writing during read operations (when the read current Ir is flowing).

[0185] Furthermore, according to the magnetic memory device 1 of the first embodiment, for example, compared with the STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory) magnetic memory device, the magnitude of the current (write current Ic0 or Ic1) flowing through the magnetoresistive element MTJ during writing can be reduced.

[0186] Furthermore, according to the magnetic memory device 1 of the first embodiment, film formation can be performed without sputtering in all manufacturing processes. For example, the magnetic memory device 1 can use ALD or CVD for film formation throughout all manufacturing processes. Also, the magnetic memory device 1 can be etched without using IBE (Ion Beam Etching) throughout all manufacturing processes. For example, the magnetic memory device 1 can use chemical etching (wet etching or RIE) for etching throughout all manufacturing processes. Thus, the magnetic memory device 1 can be manufactured using equipment that reduces manufacturing costs throughout all manufacturing processes.

[0187] In the magnetic memory device 1 of the first embodiment described above, a core member 40 is shown in the central part of the memory column MP. However, the memory column MP of the magnetic memory device 1 may also not have the core member 40. Hereinafter, the magnetic memory device 1, memory column MP and non-magnetic layer 412 in the variation of the first embodiment will be referred to as magnetic memory device 1b, memory column MPb and non-magnetic layer 412b respectively, to distinguish them from the magnetic memory device 1, memory column MP and non-magnetic layer 412 of the first embodiment.

[0188] Figure 28 shows an example of the cross-sectional structure of the memory column MPb in the magnetic memory device 1b of the first embodiment. Figure 28 shows a portion of the memory column MPb, showing the structure of the multilayer wiring layer LL and the region within the memory column MPb that intersects with the multilayer wiring layer LL. Figure 28 shows a cross-section of the same region in the magnetic memory device 1 as in Figure 6.

[0189] As shown in Figure 28, the memory cylinder MPb does not have a core component 40 and a non-magnetic layer 411. In the region of the memory cylinder MP where the core component 40 and the non-magnetic layer 411 are located, a non-magnetic layer 412b is embedded in the memory cylinder MPb. In other words, the non-magnetic layer 412b extends along the Z-direction and is located in the center of the memory cylinder MP.

[0190] Since the structure of the magnetoresistive element MTJ and the multilayer wiring layer LL is the same as in the first embodiment, the description is omitted.

[0191] Figure 29 is a cross-sectional view along line XXVIIII-XXVIIII of Figure 28, showing an example of the cross-sectional structure of the memory pillar MPb in the magnetic memory device 1b of the first embodiment. Specifically, Figure 29 shows the cross-sectional structure of the memory pillar MP in a layer parallel to the surface of the semiconductor substrate 20 and including the conductive layer 23. Figure 29 shows a cross-section of the same region in the magnetic memory device 1 as in Figure 8. The upper part (A) of Figure 29 shows an example when the magnetoresistive element MTJ is in a low resistance state. The lower part (B) of Figure 29 shows an example when the magnetoresistive element MTJ is in a high resistance state.

[0192] In the cross-section including the conductive layer 23, the non-magnetic layer 412b is disposed in the center of the memory pillar MPb. Other structures are the same as in the first embodiment, so description is omitted.

[0193] In the first embodiment of the magnetic memory device 1b, the thickness of the non-magnetic layer 412b in the radial direction can be adjusted by adjusting the presence or absence of the core member 40 or the thickness of the core member 40 in the radial direction. That is, the current density in the non-magnetic layer 412b (wired SOTL) can be adjusted, thereby adjusting the generated spin-orbit torque.

[0194] 2. Second Implementation Form The magnetic memory device 1 of the second embodiment will now be described. The magnetic memory device 1 of the second embodiment is different from the magnetic memory device 1 of the first embodiment. Hereinafter, in order to distinguish it from the magnetic memory device 1 of the first embodiment, the magnetic memory device 1 of the second embodiment may be referred to as magnetic memory device 1c.

[0195] Furthermore, in order to distinguish them from the memory column MP, magnetoresistive element MTJ, ferromagnetic layer 421, non-magnetic layer 422, ferromagnetic layer 423, and non-magnetic layer 424 in the first embodiment, the memory column MP, magnetoresistive element MTJ, ferromagnetic layer 421, non-magnetic layer 422, ferromagnetic layer 423, and non-magnetic layer 424 in the second embodiment may be referred to as memory column MPc, magnetoresistive element MTJc, ferromagnetic layer 421c, non-magnetic layer 422c, ferromagnetic layer 423c, and non-magnetic layer 424c, respectively.

[0196] The magnetic memory device 1c differs from the magnetic memory device 1 of the first embodiment mainly in the structure and manufacturing method of the magnetoresistive element MTJc. Regarding other structures and manufacturing methods, the second embodiment is largely the same as the first embodiment. The following mainly describes the differences between the magnetic memory device 1c of the second embodiment and the first embodiment.

[0197] Figure 30 illustrates the details of the construction of the magnetoresistive element MTJc in the magnetic memory device 1c. Figure 30 shows an example of the cross-sectional structure of the memory column MPc in the magnetic memory device 1c of the second embodiment. Figure 30 shows a portion of the memory column MPc, showing the structure of the multilayer wiring layer LL and the region within the memory column MPc that intersects with the multilayer wiring layer LL. Figure 30 shows a cross-section of the same region as in Figure 6 of the first embodiment.

[0198] Similar to the first embodiment, the memory column MPC has a portion extending along the Z direction and protruding in the XY direction. The portion protruding in the XY direction is a magnetoresistive element MTJc.

[0199] The construction of the core component 40 and the SOT layer 41 is the same as in the first embodiment, so the description is omitted.

[0200] A magnetoresistive element MTJc includes, for example, a ferromagnetic layer 421c, a non-magnetic layer 422c, a ferromagnetic layer 423c, and a non-magnetic layer 424c. The magnetoresistive element MTJc has a structure in which, for example, the ferromagnetic layer 421c, the non-magnetic layer 422c, the ferromagnetic layer 423c, and the non-magnetic layer 424c are connected to the SOT layer 41. That is, the main difference between the magnetoresistive element MTJc and the magnetoresistive element MTJ is that, not only are the ferromagnetic layer 421c and the non-magnetic layer 422c connected to the SOT layer 41, but the ferromagnetic layer 423c and the non-magnetic layer 424c are also connected to the SOT layer 41.

[0201] Specifically, ferromagnetic layer 421c is disposed on the side of non-magnetic layer 412 within the layer including multilayer wiring layer LL. Non-magnetic layer 422c covers the surface of ferromagnetic layer 421c, except for the portion where ferromagnetic layer 421c contacts non-magnetic layer 412c. Ferromagnetic layer 423c covers the surface of ferromagnetic layer 422c, except for the portion where non-magnetic layer 422c contacts ferromagnetic layer 421c. Non-magnetic layer 424c covers the surface of ferromagnetic layer 423c, except for the portion where ferromagnetic layer 423c contacts non-magnetic layer 422c.

[0202] In other words, for example, the ferromagnetic layer 421c is in contact with the non-magnetic layer 412. The non-magnetic layer 422c is disposed between the insulating layer 32 and the ferromagnetic layer 421c, and has a first portion in contact with the non-magnetic layer 412. The ferromagnetic layer 423c is disposed between the insulating layer 32 and the first portion, and has a second portion in contact with the non-magnetic layer 412.

[0203] The materials and functions of ferromagnetic layer 421c, non-magnetic layer 422c, ferromagnetic layer 423c and non-magnetic layer 424c are the same as those of ferromagnetic layer 421, non-magnetic layer 422, ferromagnetic layer 423 and non-magnetic layer 424, respectively, so the description is omitted.

[0204] The construction of the multilayer wiring layer LL is the same as in the first embodiment, so the description is omitted.

[0205] Next, the manufacturing method of the magnetic memory device 1c in the second embodiment will be described. The main difference between the manufacturing method of the magnetic memory device 1c in the second embodiment and the manufacturing method of the magnetic memory device 1 in the first embodiment lies in the formation of the magnetoresistive element MTJc.

[0206] Figure 31 is a flowchart showing an example of a manufacturing method for the magnetic memory device 1c of the second embodiment. Figures 32 and 33 are examples of cross-sectional structures during the manufacturing process of the magnetic memory device 1c of the second embodiment. Figures 32 and 33 show cross-sections of the same area as in Figure 20. Hereinafter, referring appropriately to Figure 31, an example of a series of manufacturing processes related to the formation of the multilayer wiring structure within the memory cell array 10 in the magnetic memory device 1c of the second embodiment will be described. As shown in Figure 31, in the manufacturing method of the magnetic memory device 1c of the second embodiment, for example, steps S101-S103, S201, S202, and S108-S113 are performed sequentially.

[0207] First, similar to the first embodiment, steps S101 to S103 are executed sequentially.

[0208] In step S201, as shown in FIG32, a non-magnetic layer 424c, a ferromagnetic layer 623c, a non-magnetic layer 422c, and a ferromagnetic layer 621c are formed. Specifically, firstly, the non-magnetic layer 424c is formed on the surface and bottom surface of the hole MH, and on the surface exposed in the space RP1. Next, the ferromagnetic layer 623c is formed on the surface of the non-magnetic layer 424c. Next, the non-magnetic layer 422c is formed on the surface of the ferromagnetic layer 623c. Next, the ferromagnetic layer 621c is formed on the surface of the non-magnetic layer 422c. The non-magnetic layers 424c, ferromagnetic layer 623c, non-magnetic layer 422c, and ferromagnetic layer 621c are embedded, for example, in the space RP1.

[0209] Non-magnetic layer 424c, ferromagnetic layer 623c, non-magnetic layer 422c, and ferromagnetic layer 621c are continuously formed in a vacuum environment of ALD or CVD. Ferromagnetic layer 423c is formed from a portion of ferromagnetic layer 623c by performing the process described later. Ferromagnetic layer 421c is formed from a portion of ferromagnetic layer 621c by performing the process described later.

[0210] In step S202, as shown in FIG33, a magnetoresistive element MTJc is formed. Specifically, wet etching is performed via via MH. The wet etching solution etches the non-magnetic layer 424c, ferromagnetic layer 623c, non-magnetic layer 422c, and ferromagnetic layer 621c formed within the via MH. That is, the non-magnetic layer 424c, ferromagnetic layer 623c, non-magnetic layer 422c, and ferromagnetic layer 621c formed on the side of the insulating layer 32 are removed. The ferromagnetic layer 623c and ferromagnetic layer 621c after the etching process are referred to as ferromagnetic layer 423c and ferromagnetic layer 421c, respectively. That is, ferromagnetic layer 423c and ferromagnetic layer 421c are formed by etching ferromagnetic layer 623c and ferromagnetic layer 621c, respectively.

[0211] Then, similar to the first embodiment, steps S108 to S113 are executed sequentially. This forms the multilayer wiring structure within the memory cell array in the second embodiment. Furthermore, the manufacturing process described above is only one example; other processes can be inserted between each manufacturing step.

[0212] The effects of the magnetic memory device 1c in the second embodiment will be explained below.

[0213] According to the magnetic memory device 1c of the second embodiment, the ferromagnetic layer 421c, the non-magnetic layer 422c, the ferromagnetic layer 423c, and the non-magnetic layer 424c in the magnetoresistive element MTJc are continuously formed in a vacuum environment. This prevents the magnetoresistive element MTJc from exposing the film to air during film formation. Therefore, the magnetoresistive element MTJc can suppress the presence of impurities such as oxide films. By suppressing the presence of impurities, the magnetoresistive element MTJc can suppress the degradation of its properties.

[0214] 3. Other variations, etc. Additionally, some or all of the above-mentioned embodiments may also be described as follows, but not limited to the following.

[0215] (Postscript 1) A method for manufacturing a magnetic memory device, comprising: Forming a laminate in which sacrificial components and a first insulator are alternately laminated along a second direction; Memory pores are formed that extend along the second direction described above and penetrate the aforementioned laminated body; One portion of the sacrificial member is removed via the aforementioned memory hole; A second ferromagnetic body is formed in the first space after the aforementioned sacrificial member is removed; Remove a portion of the second ferromagnetic material via the aforementioned memory hole; A first non-magnetic body and a first ferromagnetic body are sequentially formed in one portion of the first space and one portion of the memory hole; A portion of either the first non-magnetic material or the first ferromagnetic material is removed via the aforementioned memory hole; A second wiring extending along the second direction is formed in a portion of the aforementioned memory hole; Forming a narrow slit that divides the aforementioned laminated body; The sacrificial member is selectively removed via the aforementioned slit; A variable resistance material is formed in a portion of the space after the aforementioned sacrificial member is removed; The first wiring is formed in the space after the aforementioned sacrificial member is removed; and A fourth insulator is formed in the aforementioned slit; and The first ferromagnetic material and the second ferromagnetic material are formed in a ring shape between the first wiring and the second wiring. The first ferromagnetic body and the second ferromagnetic body mentioned above have an easily magnetized axis along the circumferential direction.

[0216] (Postscript 2) The manufacturing method of the magnetic memory device, as described in Appendix 1, further includes: After the second wiring is formed in one part of the memory hole, the second insulator is formed in the memory hole.

[0217] (Note 3) As in Appendix 1, the manufacturing method of the magnetic memory device, in which... The aforementioned second ferromagnetic body, the aforementioned first non-magnetic body, the aforementioned first ferromagnetic body, the aforementioned second wiring, the aforementioned first wiring, and the aforementioned variable resistor material are formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition).

[0218] (Note 4) A method for manufacturing a magnetic memory device, comprising: Forming a laminate in which sacrificial components and a first insulator are alternately laminated along a second direction; Memory pores are formed that extend along the second direction described above and penetrate the aforementioned laminated body; One portion of the sacrificial member is removed via the aforementioned memory hole; In the first space after the sacrificial member is removed and in one portion of the memory hole, a second ferromagnetic body, a first non-magnetic body, and a first ferromagnetic body are sequentially formed; The second ferromagnetic material, the first non-magnetic material, and a portion of the first ferromagnetic material are removed through the aforementioned memory hole; A second wiring extending along the second direction is formed in a portion of the aforementioned memory hole; Forming a narrow slit that divides the aforementioned laminated body; The sacrificial member is selectively removed via the aforementioned slit; A variable resistance material is formed in a portion of the space after the aforementioned sacrificial member is removed; The first wiring is formed in the space after the aforementioned sacrificial member is removed; and A fourth insulator is formed in the aforementioned slit; and The first ferromagnetic material and the second ferromagnetic material are formed in a ring shape between the first wiring and the second wiring. The first ferromagnetic body and the second ferromagnetic body mentioned above have an easily magnetized axis along the circumferential direction.

[0219] (Note 5) The manufacturing method of the magnetic memory device, as described in Appendix 5, further includes: After the second wiring is formed in one part of the memory hole, the second insulator is formed in the memory hole.

[0220] In the first and second embodiments, the magnetic memory devices 1 to 1c may also have other structures. The magnetic memory devices 1, 1b and 1c may also have other structures.

[0221] The embodiments of this invention are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments or variations thereof are included in the scope or spirit of the invention, and are also included in the scope of the invention described in the patent application and its equivalents.

[0222] 1, 1b, 1c: Magnetic memory devices 10: Memory Cell Array 11: Column Decoder 12: Line Decoder 13: Readout Circuit 14: Writing Circuit 15: Sensing Amplifier 16: Voltage generation circuit 17: Input / output circuit 18: Control Circuit 20: Semiconductor substrate 22-27: Conductor layer 30-34, 33a, 33b, 37: Insulating layer 40: Core Components 41: SOT layer 43: Switching Layer 51: Sacrificial Component 411, 412, 413, 412b, 422, 422c, 424, 424c: Non-magnetic layers 421, 421c, 423, 423c, 621, 623: Ferromagnetic layers 431: Basal layer 432: Variable resistance material layer 433: Cap layer A, B1, B2, C1, C2, D1, D2: Points ADD: address BLK: block CC, CS, CV: Contacts CMD command CNT: Control signal CP: Cellular Unit DAT: Data Ew0, Ew1: Energy GC: Gate electrode HA: Termination Region Ic0 <n>, Ic1 <n>Write current Ir <m>Read the current Iw0 <m>, Iw1 <m>Current LL: Multilayer Wiring MA: Memory area MC, MC0~MC9, MC<0,0>~MC<M,N> : Memory cell MH: Kong MP, MPb, MPc: Memory columns MS <0> ~MS <n>: Memory string MTJ, MTJ<0,0>~MTJ<M,N> MTJc: Magnetoresistive element NN: Source / Drain Region OX: Insulator layer RBL, RBL <0> ~RBL <n>Read out bit lines RP1, RP2: Space RWL, RWL0~RWL9, RWL <0> ~RWL <m>Read out the character lines S101~S113, S201, S202: Steps SEL2: Switching element SEL2<0,0>~SEL2<M,N> Switching elements SH: Slit SL: Source Line SLT: Component SOTL <0> ~SOTL <n>:wiring TR1, TR1 <0> ~TR1 <n>Switching elements Vc0, Vc1, VSS, Vw0, Vw1: Voltage VhdH: High holding voltage VhdL: Low holding voltage VI: Area Vr: Voltage Vth: Threshold voltage WBL, WBL <0> ~WBL <n>Write bit line WWL: Write character line X, Y, Z: Direction ΔE<m,n> , ΔE<m+1,n> , ΔE<m-1,n> Energy barrier height< / n> < / n> < / n> < / m> < / n> < / n> < / m> < / m> < / m> < / n> < / n> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / m> < / n> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / n> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m>

Claims

1. A magnetic memory device comprising: a substrate; a first wiring and a first insulator extending in a first direction along the substrate; a second insulator extending in a second direction and penetrating the first wiring and the first insulator; a second wiring disposed around the second insulator, extending in the second direction and penetrating the first wiring and the first insulator; and a first magnetoresistive element disposed in a ring around the second wiring between the first wiring and the second wiring; wherein the first magnetoresistive element comprises: a first ferromagnetic material between the second wiring and the first wiring; a first non-magnetic material between the first ferromagnetic material and the first wiring; and a second ferromagnetic material between the first non-magnetic material and the first wiring.

2. The magnetic memory device of claim 1, wherein the first wiring and the first insulator are arranged in a second direction intersecting the first direction, and the magnetic memory device further comprises: a first switching element disposed between the first wiring and the first magnetoresistive element, and connected in series with the first magnetoresistive element.

3. The magnetic memory device of claim 1, further comprising: a plurality of third wirings and a plurality of third insulators, extending along the first direction and alternately arranged in the second direction, penetrating the second wirings and the second insulators; and a plurality of second magnetoresistive elements, arranged in a ring around the second wirings between the plurality of third wirings and the second wirings; and each of the plurality of second magnetoresistive elements having: a third ferromagnetic body between the second wirings and the third wirings; a second non-magnetic body between the third ferromagnetic body and the third wirings; and a fourth ferromagnetic body between the second non-magnetic body and the third wirings.

4. The magnetic memory device of claim 1, wherein during the write operation of writing data to the first magnetoresistive element, a first voltage is applied to the first wiring, a second voltage lower than the first voltage is applied to the first terminal of the second wiring, and a third voltage higher than the second voltage is applied to the second terminal, wherein the third voltage has a magnitude that causes a first current to flow from the second terminal to the first terminal.

5. The magnetic memory device as claimed in claim 4, wherein the second voltage mentioned above is the ground voltage.

6. The magnetic memory device of claim 1, wherein the first ferromagnetic body is connected to the second wiring; the first non-magnetic body further has a portion disposed between the first insulator and the first ferromagnetic body and connected to the second wiring; the second ferromagnetic body is not connected to the second wiring.

7. The magnetic memory device of claim 1, wherein the first ferromagnetic body is connected to the second wiring; the first non-magnetic body further has a first portion disposed between the first insulator and the first ferromagnetic body and connected to the second wiring; the second ferromagnetic body further has a second portion disposed between the first insulator and the first portion and connected to the second wiring.

8. The magnetic memory device of claim 2, wherein the first magnetoresistive element further comprises a third non-magnetic element between the second ferromagnetic element and the first wiring, and the first switching element comprises: a first conductor on the first wiring; a variable resistive material on the first conductor; and a second conductor on the variable resistive material.

9. The magnetic memory device of claim 1, wherein the first non-magnetic body contains at least one element selected from boron (B), magnesium (Mg) and aluminum (Al); and the first ferromagnetic body and the second ferromagnetic body contain at least one element selected from cobalt (Co), iron (Fe) and nickel (Ni).

10. The magnetic memory device of claim 1, wherein the first non-magnetic element contains hexagonal boron nitride (h-BN) or hexagonal aluminum nitride (h-AlN).

11. The magnetic memory device of claim 8, wherein the third non-magnetic element contains at least one element selected from tantalum (Ta), tungsten (W) and titanium (Ti).

12. The magnetic memory device of claim 8, wherein the variable resistor material contains at least one element selected from sulfur (S), selenium (Se), tellurium (Te), boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb).

13. The magnetic memory device of claim 2, wherein the first switching element is a selector having nonlinear current-voltage characteristics, a selector having quick-return characteristics, or a diode.

14. A magnetic memory device comprising: a substrate; a first wiring and a first insulator extending in a first direction along the substrate; a second wiring extending in a second direction and penetrating the first wiring and the first insulator; a first magnetoresistive element disposed in a ring around the second wiring between the first wiring and the second wiring; and a first switching element disposed between the first wiring and the first magnetoresistive element and connected in series with the first magnetoresistive element; wherein the first magnetoresistive element comprises: a first ferromagnetic body between the second wiring and the first wiring; a first non-magnetic body between the first ferromagnetic body and the first wiring; and a second ferromagnetic body between the first non-magnetic body and the first wiring.

15. The magnetic memory device of claim 14, wherein the first wiring and the first insulator are arranged in a second direction intersecting the first direction, and the magnetic memory device further comprises: a plurality of third wirings and a plurality of third insulators, which extend along the first direction and are alternately arranged in the second direction, penetrating the second wiring; and a plurality of second magnetoresistive elements, which are arranged in a ring around the second wiring between the plurality of third wirings and the second wiring; each of the plurality of second magnetoresistive elements comprises: a third ferromagnetic body between the second wiring and the third wiring; a second non-magnetic body between the third ferromagnetic body and the third wiring; and a fourth ferromagnetic body between the second non-magnetic body and the third wiring.

16. The magnetic memory device of claim 14, wherein during the write operation of writing data to the first magnetoresistive element, a first voltage is applied to the first wiring, a second voltage lower than the first voltage is applied to the first terminal of the second wiring, and a third voltage higher than the second voltage is applied to the second terminal, wherein the third voltage has a magnitude that causes a first current to flow from the second terminal to the first terminal.

17. The magnetic memory device of claim 14, wherein the first non-magnetic body contains at least one element selected from boron (B), magnesium (Mg) and aluminum (Al); and the first ferromagnetic body and the second ferromagnetic body contain at least one element selected from cobalt (Co), iron (Fe) and nickel (Ni).

18. The magnetic memory device of claim 14, wherein the first ferromagnetic body is connected to the second wiring; the first non-magnetic body further has a portion disposed between the first insulator and the first ferromagnetic body and connected to the second wiring.

19. The magnetic memory device of claim 14, wherein the first magnetoresistive element further comprises a third non-magnetic element between the second ferromagnetic element and the first wiring, and the first switching element comprises: a first conductor on the first wiring; a variable resistive material on the first conductor; and a second conductor on the variable resistive material.

20. The magnetic memory device of claim 19, wherein the variable resistor material contains at least one element selected from sulfur (S), selenium (Se), tellurium (Te), boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb).