Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device that can improve yield. One embodiment of the semiconductor memory device includes: a substrate; a laminate disposed above the substrate in a first direction; a first conductive layer disposed between the substrate and the laminate; a memory pillar comprising a semiconductor film extending in the first direction and penetrating the first conductive layer; and a first member disposed spaced from the memory pillar in a second direction intersecting the first direction, extending in the first direction and penetrating the first conductive layer. The laminate has a structure formed by sequentially stacking a first semiconductor layer, a second semiconductor layer, a second conductive layer, and a third conductive layer from the substrate side. The first semiconductor layer covers the first-direction end of the semiconductor film and the first-direction end of the first member.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device. Prior Technology

[0002] NAND (Not-And) type flash memory is known as a semiconductor memory device that can store data in a non-volatile manner. Summary of the Invention

[0003] Provides semiconductor memory devices that can improve yield.

[0004] An embodiment of a semiconductor memory device includes: a substrate; a laminate disposed above the substrate in a first direction; a first conductive layer disposed between the substrate and the laminate; a memory pillar comprising a semiconductor film and extending in the first direction through the first conductive layer; and a first member disposed spaced from the memory pillar in a second direction intersecting the first direction and extending in the first direction through the first conductive layer. The laminate has a structure formed by sequentially stacking a first semiconductor layer, a second semiconductor layer, a second conductive layer, and a third conductive layer from the substrate side. The first semiconductor layer covers the first-direction end of the semiconductor film and the first-direction end of the first member. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram showing an example of the configuration of a memory system including the semiconductor memory device of the first embodiment. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array contained in the semiconductor memory device of the first embodiment. Figure 3 is a perspective view showing the general bonding structure of the semiconductor memory device of the first embodiment. Figure 4 is a top view showing an example of the planar layout of the memory cell array contained in the semiconductor memory device of the first embodiment. Figure 5 is a top view showing an example of the planar layout of the memory cell array in the memory region of the semiconductor memory device of the first embodiment. Figure 6 is a cross-sectional view along line VI-VI of Figure 5, showing an example of the cross-sectional structure of the memory cell array in the memory region of the semiconductor memory device of the first embodiment. Figure 7 is a cross-sectional view along line VII-VII of Figure 6, showing an example of the cross-sectional structure of the memory pillars contained in the semiconductor memory device of the first embodiment. Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the first embodiment. Figure 9 is an enlarged cross-sectional view of a portion of the layered body in Figure 8. Figure 10 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 11 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 12 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 13 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 14 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 15 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 16 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 17 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 18 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the second embodiment. Figure 19 is an enlarged cross-sectional view of a portion of the laminations in Figure 18. Figure 20 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 21 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 22 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the third embodiment. Figure 23 is an enlarged cross-sectional view of a portion of the layered body in Figure 22. Figure 24 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the third embodiment. Figure 25 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the third embodiment. Figure 26 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the third embodiment. Figure 27 is a cross-sectional view showing one example of the cross-sectional structure of a semiconductor memory device according to the first variation of the third embodiment. Figure 28 is an enlarged cross-sectional view of a portion of the laminations in Figure 27. Figure 29 is a cross-sectional view showing one example of the cross-sectional structure of a semiconductor memory device of the second variation of the third embodiment. Figure 30 is an enlarged cross-sectional view of a portion of the laminations in Figure 29. Figure 31 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the fourth embodiment. Figure 32 is an enlarged cross-sectional view of a portion of the layered body in Figure 31. Figure 33 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the fourth embodiment. Figure 34 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the fifth embodiment. Figure 35 is an enlarged cross-sectional view of a portion of the layered body in Figure 34. Figure 36 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device according to the fifth embodiment. Figure 37 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the sixth embodiment. Figure 38 is an enlarged cross-sectional view of a portion of the laminations in Figure 37. Figure 39 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the seventh embodiment. Figure 40 is an enlarged cross-sectional view of a portion of the laminations in Figure 39. Figure 41 is a cross-sectional view showing one example of the cross-sectional structure of the semiconductor memory device of the first variation of the seventh embodiment. Figure 42 is an enlarged cross-sectional view of a portion of the layered body in Figure 41. Figure 43 is a cross-sectional view showing one example of the cross-sectional structure of a semiconductor memory device according to the second variation of the seventh embodiment. Figure 44 is an enlarged cross-sectional view of a portion of the layered body in Figure 43. Figure 45 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the eighth embodiment. Figure 46 is an enlarged cross-sectional view of a portion of the laminations in Figure 45. Implementation

[0006] The following description uses reference to illustrations to illustrate the embodiments. The dimensions and proportions of the illustrations may not be the same as the actual embodiments. Furthermore, in the following description, constituent elements with substantially the same function and structure are marked with the same symbols. When specifically distinguishing between constituent elements with the same structure, there may be instances where the same symbols are followed by different text or numbers.

[0007] 1. First Implementation Form 1.1 Composition 1.1.1 Composition of the memory system Using Figure 1, the configuration of a memory system including the semiconductor memory device of the first embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of a memory system. The memory system 1 is a memory device configured to be connected to an external host machine (not shown). The memory system 1 is, for example, a memory card such as an SDTM card, UFS (universal flash storage), or SSD (solid state drive). As shown in Figure 1, the memory system 1 includes a memory controller 2 and a semiconductor memory device 3.

[0008] The memory controller 2 is, for example, an integrated circuit such as a system-on-a-chip (SoC). Based on requests from the host machine, the memory controller 2 controls the semiconductor memory device 3. For example, the memory controller 2 writes data requested from the host machine to the semiconductor memory device 3. Furthermore, the memory controller 2 reads data requested from the host machine from the semiconductor memory device 3 and sends it back to the host machine.

[0009] Semiconductor memory device 3 is a memory that stores data in a non-volatile manner. Semiconductor memory device 3 is, for example, a NAND flash memory. Hereinafter, NAND flash memory will be used as an example to explain semiconductor memory device 3.

[0010] 1.1.2 Composition of Semiconductor Memory Devices Next, referring to FIG1, the configuration of the semiconductor memory device 3 will be described. As shown in FIG1, the semiconductor memory device 3 includes an array chip 100 and a circuit chip 200.

[0011] The array chip 100 includes, for example, a memory cell array 10.

[0012] The memory cell array 10 comprises a plurality of blocks BLK0 to BLK (n is an integer greater than or equal to 1). A block BLK is a collection of a plurality of memory cell transistors that can non-volatilely store data. A block BLK is used, for example, as a unit for data erasure. Furthermore, the memory cell array 10 includes a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated, for example, with one bit line and one word line. The detailed structure of the memory cell array 10 will be described later.

[0013] The circuit chip 200 includes, for example, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a column decoder module 15, and a sense amplifier module 16. Hereinafter, the instruction register 11, the address register 12, the sequencer 13, the driver module 14, the column decoder module 15, and the sense amplifier module 16 are collectively referred to as "peripheral circuits".

[0014] Instruction register 11 is the circuitry that receives instructions (CMD) from memory controller 2 from memory semiconductor memory device 3. Instructions (CMD) may include commands that cause sequencer 13 to perform read, write, and erase operations.

[0015] Address register 12 is a circuit that receives the address ADD from the memory controller 2 in the memory semiconductor memory device 3. The address ADD includes, for example, block address BAd, page address PAd, and row address CAd. For example, block address BAd, page address PAd, and row address CAd are used to select block BLK, word line, and bit line, respectively.

[0016] The sequencer 13 is a circuit that controls the operation of other circuits according to a preset program. The sequencer 13 controls the operation of the entire semiconductor memory device 3. For example, the sequencer 13 controls the driver module 14, the column decoder module 15, and the sense amplifier module 16 based on the instruction CMD stored in the instruction register 11. For example, the sequencer 13 performs read operations, write operations, and erase operations.

[0017] The driver module 14 is a circuit that generates the voltage used in read, write, and erase operations. For example, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line based on the page address PAd stored in the address register 12.

[0018] The column decoder module 15 selects a block BLK within the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. For example, the column decoder module 15 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0019] The sense amplifier module 16 is a circuit that selects a bit line based on the row address CAd stored in the address register 12. For example, during a write operation, the sense amplifier module 16 applies a voltage based on the write data DAT received from the memory controller 2 to the selected bit line. Furthermore, during a read operation, the sense amplifier module 16 determines the data stored in the memory cell transistor based on the voltage of the selected bit line. The sense amplifier module 16 transmits the determination result as read data DTA to the memory controller 2.

[0020] 1.1.3 Circuit Configuration of Memory Cell Array Figure 2 will be used to explain the circuit configuration of the memory cell array 10. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10. In Figure 2, one block BLK of the plurality of blocks BLK contained in the memory cell array 10 is shown. As shown in Figure 2, the block BLK contains, for example, five string units SU0 to SU4. The string unit SU is a set of NAND strings NS, which will be described later. For example, in a write operation or a read operation, the NAND strings NS in the string unit SU are selected together.

[0021] Each string cell SU contains a plurality of NAND strings NS associated with bit lines BL0~BLm (m being an integer above). Each NAND string NS contains, for example, memory cell transistors MT0~MT7, and select transistors ST1 and ST2. Each memory cell transistor MT contains a control gate and a charge accumulation layer, which non-volatilely stores data. Select transistors ST1 and ST2 are used to select the string cell SU during various operations.

[0022] In each NAND string NS, memory cell transistors MT0~MT7 are connected in series. The drain of selector transistor ST1 is connected to the associated bit line BL. The source of selector transistor ST1 is connected to one end of the series-connected memory cell transistors MT0~MT7. The drain of selector transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0~MT7. The source of selector transistor ST2 is connected to the source line SL.

[0023] Within the same BLK, the control gates of memory cell transistors MT0~MT7 are connected to word lines WL0~WL7 respectively. The gate of select transistor ST1 within serial cells SU0~SU4 is connected to select gate lines SGD0~SGD4 respectively. The gate of select transistor ST2 within serial cells SU0~SU4 is connected to select gate line SGS.

[0024] Each bit line BL0~BLm is assigned a different row address CAd. Each bit line BL is shared by the NAND string NS because multiple blocks of BLK share the same row address CAd. Word lines WL0~WL7 are each set according to each block of BLK. The source line SL is shared, for example, among multiple blocks of BLK.

[0025] A collection of multiple memory cell transistors (MTs) connected to a common word line (WL) within a single serial unit (SU) is called a unit group (CU). For example, the memory capacity of a unit group (CU) containing memory cell transistors (MTs) that each store 1 bit of data is defined as "1 page of data". The number of bits of data stored in a unit group (CU) based on the memory cell transistors (MTs) can have a memory capacity of more than 2 pages of data.

[0026] Furthermore, the circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, the number of string cells SU contained in each BLK can be designed to be arbitrary. The number of memory cell transistors MT, and select transistors ST1 and ST2 contained in each NAND string NS can be designed to be arbitrary.

[0027] 1.1.4 Bonding Structure of Semiconductor Memory Devices Figure 3 is used to illustrate the general structure of the bonding of the semiconductor memory device 3. Figure 3 is a perspective view showing the general structure of the bonding of the semiconductor memory device 3.

[0028] As shown in Figure 3, the semiconductor memory device 3 has a structure in which an array chip 100 is bonded to a circuit chip 200. The array chip 100 and the circuit chip 200 each include a plurality of bonding pads BP disposed on opposing surfaces. In the bonding structure, bonding pads BP of the array chip 100 and bonding pads BP of the circuit chip 200 are bonded together to form one bonding pad BP. In other words, bonding pads BP are formed by bonding the electrodes (conductors) constituting the bonding pads BP disposed on the array chip 100 and the electrodes (conductors) constituting the bonding pads BP disposed on the circuit chip 200.

[0029] Hereinafter, the surface on which the array chip 100 and the circuit chip 200 are bonded (hereinafter referred to as the "bonding surface") is defined as the XY plane. The mutually orthogonal directions in the XY plane are defined as the X direction and the Y direction. Furthermore, the direction that is substantially perpendicular to the XY plane and extends from the array chip 100 toward the circuit chip 200 is defined as the Z1 direction. The direction that is substantially perpendicular to the XY plane and extends from the circuit chip 200 toward the array chip 100 is defined as the Z2 direction. When neither the Z1 nor Z2 direction is specified, it is referred to as the Z direction. Furthermore, in the array chip 100, the surface on the bonding surface side of a certain component is referred to as the "first surface," and the surface on the opposite side of the bonding surface of a certain component is referred to as the "second surface." In the circuit chip 200, the surface on the bonding surface side of a certain component is referred to as the "first surface," and the surface on the opposite side of the bonding surface of a certain component is referred to as the "second surface."

[0030] 1.1.5 Planar Construction of Memory Cell Array Figure 4 illustrates the planar structure of the memory cell array 10. Figure 4 is a top view showing an example of the planar layout of the memory cell array 10. In Figure 4, the regions corresponding to the four blocks BLK0~BLK3 are shown.

[0031] The memory cell array 10 includes a multilayer wiring structure and a plurality of components SLT and SHE. The multilayer wiring structure includes select gate lines SGD and SGS, and a plurality of word lines WL. The multilayer wiring structure is constructed by stacking select gate lines SGD and SGS, and a plurality of word lines WL along the Z-direction. Furthermore, in the following description, select gate lines SGD and SGS, and a plurality of word lines WL are collectively referred to as "multilayer wiring". Also, the memory cell array 10 includes, for example, a memory region MR arranged in the X-direction and a lead-out region HR. The memory region MR is the region that actually stores data. Furthermore, the memory region MR is the region used for connecting bit lines BL to peripheral circuits. The lead-out region HR is the region used for connecting multilayer wiring to peripheral circuits.

[0032] The multilayer wiring configuration is, for example, set up in the X direction, spanning the memory region MR and the lead-out region HR.

[0033] Each component SLT extends in the X direction. Each component SLT spans the memory region MR and the lead-out region HR, traversing the multilayer wiring structure in the X direction. Each component SLT has, for example, a structure with an insulator or a plate-shaped conductor embedded inside. Each component SLT divides adjacent multilayer wirings. The regions divided by a plurality of component SLTs each correspond to one block BLK.

[0034] Each component SHE extends in the X direction. In this embodiment, four component SHEs are respectively arranged between adjacent component SLTs. Each component SHE spans the memory region MR and traverses the multilayer wiring structure in the X direction. Each component SHE has, for example, a structure with embedded insulator. Each component SHE, for example, separates adjacent select gate lines SGDs. The region divided by the plurality of component SLTs and SHEs corresponds to one string cell SU.

[0035] In the memory cell array 10, for example, the planar layout shown in Figure 4 is repeatedly configured in the Y direction.

[0036] Furthermore, the planar layout of the memory cell array 10 is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be arbitrary, depending on the number of string cells SU.

[0037] 1.1.6 Construction of memory cell arrays in memory regions The structure of the memory cell array 10 in the memory region MR is explained.

[0038] 1.1.6.1 Planar Construction of Memory Cell Arrays in Memory Regions First, the planar structure of the memory cell array 10 in the memory region MR will be explained using Figure 5. Figure 5 is a top view showing an example of the planar layout of the memory cell array 10 in the memory region MR.

[0039] As shown in Figure 5, in the memory region MR, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. Furthermore, each component SLT includes a conductor LI and a spacer SP.

[0040] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MP) are arranged in an alternating pattern, for example, in 24 rows, within the area between two adjacent components (SLT). For example, counting from the top of the page, the memory columns (MP) in the 5th, 10th, 15th, and 20th rows are each overlapped by one component (SHE).

[0041] A plurality of bit lines BL extend in the Y direction. Also, a plurality of bit lines BL are arranged in the X direction. Each bit line BL is configured to overlap with at least one memory column MP for each string unit SU. In the example of Figure 5, each bit line BL is configured to overlap with two memory columns MP for each string unit SU. One bit line BL among the plurality of bit lines BL overlapping with the memory column MP is electrically connected to that memory column MP via a contact CV. For example, no contact is provided between the memory column MP overlapping with the component SHE and the bit line BL. That is, the memory column MP overlapping with the component SHE is not electrically connected to the bit line BL.

[0042] Conductor L1 is a conductor extending in the X direction. Spacer SP is an insulator disposed on the side of conductor L1. Conductor L1 is held by spacer SP. Conductor L1 and its adjacent multilayer wiring in the Y direction are electrically separated by spacer SP. Thus, conductor L1 and its adjacent multilayer wiring in the Y direction are electrically insulated from each other.

[0043] 1.1.6.2 Cross-sectional structure of the memory cell array in the memory region Next, using FIG6, the cross-sectional structure of the memory cell array 10 in the memory region MR will be described. FIG6 is a cross-sectional view along line VI-VI of FIG5 showing an example of the cross-sectional structure of the memory cell array 10 in the memory region MR. In FIG6, the upper side of the paper corresponds to the bonding surface side.

[0044] As shown in Figure 6, the memory cell array 10 further includes a conductive layer 30, semiconductor layers 31a and 31b, conductive layers 32a, 32b, 33, and 35, a plurality of conductive layers 34, 36, 37, and 38, insulating layers 40, 41, 43, and 44, and a plurality of insulating layers 42. Figure 6 shows five memory pillars MP among the plurality of memory pillars MP. Also, Figure 6 shows a configuration comprising a plurality of conductive layers 34 and a plurality of insulating layers 42, comprising eight conductive layers 34 and eight insulating layers 42.

[0045] The conductive layer 30 is, for example, configured as a plate extending along the XY plane. The conductive layer 30 is made of a conductive material. This conductive material may include, for example, an N-type semiconductor with added impurities.

[0046] A semiconductor layer 31a is disposed on the second surface of the conductive layer 30. The semiconductor layer 31a may, for example, comprise doped polysilicon with added N-type impurities. As described later, the semiconductor layer 31a is formed on the second surface of each of the conductive layer 30, the plurality of memory pillars MP, and the plurality of component SLTs. Therefore, the second surface of the semiconductor layer 31a may, for example, have irregularities corresponding to the plurality of memory pillars MP. That is, the second surface of the semiconductor layer 31a may also be non-flat.

[0047] A semiconductor layer 31b is disposed on the second surface of the semiconductor layer 31a. The semiconductor layer 31b may, for example, comprise doped polycrystalline silicon with added N-type impurities. As described later, the semiconductor layer 31b is formed on the second surface of the semiconductor layer 31a. Therefore, the second surface of the semiconductor layer 31b may, for example, have irregularities similar to the second surface of the semiconductor layer 31a. That is, the second surface of the semiconductor layer 31b may also be uneven, just like the second surface of the semiconductor layer 31a.

[0048] A conductive layer 32a is disposed on the second surface of the semiconductor layer 31b. The conductive layer 32a may contain, for example, titanium or titanium nitride. The conductive layer 32a functions as a barrier metal for the conductive layer 32b. As described later, the conductive layer 32a is formed on the second surface of the semiconductor layer 31b. Therefore, the second surface of the conductive layer 32a may have irregularities, for example, similar to the second surface of the semiconductor layer 31b. That is, the second surface of the conductive layer 32a may also be uneven, just like the second surface of the semiconductor layer 31b.

[0049] A conductive layer 32b is disposed on the second surface of the conductive layer 32a. The conductive layer 32b may contain, for example, tungsten. As described later, the conductive layer 32b is formed on the second surface of the conductive layer 32a. Therefore, the second surface of the conductive layer 32b may have irregularities, for example, similar to the second surface of the conductive layer 32a. That is, the second surface of the conductive layer 32b may also be uneven, just like the second surface of the conductive layer 32a.

[0050] The conductor layer 30, semiconductor layers 31a and 31b, and conductor layers 32a and 32b, as described above, function as source lines SL. By stacking polysilicon (conductor layer 30, semiconductor layers 31a and 31b) and metal (conductor layers 32a and 32b), the resistance of the source lines SL can be reduced. Hereinafter, the stacked structure disposed on the second surface of the conductor layer 30 will be referred to as "stacked body SB". In this embodiment, the stacked body SB has a structure formed by sequentially stacking semiconductor layers 31a, 31b, conductor layers 32a, and 32b from the conductor layer 30 side.

[0051] An insulating layer 40 is disposed on the first surface of the conductive layer 30. The insulating layer 40 may contain, for example, silicon oxide. A conductive layer 33 is disposed on the first surface of the insulating layer 40. The conductive layer 33 may be disposed in a plate shape extending along the XY plane. The conductive layer 33 functions as a selector gate line (SGS). The conductive layer 33 may contain, for example, tungsten.

[0052] An insulating layer 41 is disposed on the first surface of the conductive layer 33. The insulating layer 41 may contain silicon oxide, for example. On the first surface of the insulating layer 41, eight conductive layers 34 and eight insulating layers 42 are stacked in the Z1 direction in the order of conductive layer 34, insulating layer 42, ..., conductive layer 34, and insulating layer 42. The conductive layer 34 may be disposed in the form of a plate extending along the XY plane. The eight conductive layers 34 function as character lines WL0 to WL7 in sequence along the Z1 direction. The conductive layer 34 may contain tungsten, for example. The insulating layer 42 may contain silicon oxide, for example.

[0053] A conductive layer 35 is disposed on the first surface of the uppermost insulating layer 42 in the Z1 direction among the eight insulating layers 42. The conductive layer 35 is, for example, disposed in a plate shape extending along the XY plane. The conductive layer 35 functions as a selective gate line (SGD). The conductive layer 35 is, for example, composed of a plurality of components (SHE), electrically insulated according to each string unit (SU). The conductive layer 35 contains, for example, tungsten.

[0054] An insulating layer 43 is disposed on the first surface of the conductive layer 35. The insulating layer 43 may contain, for example, silicon oxide. A plurality of conductive layers 36 are disposed on the first surface of the insulating layer 43. Each conductive layer 36 extends along the Y direction. Figure 6 shows one of the plurality of conductive layers 36. Each conductive layer 36 functions as a bit line BL. The plurality of conductive layers 36 are electrically connected to a plurality of memory pillars MP via a plurality of conductive layers 37 and 38. The conductive layers 36 may contain, for example, copper.

[0055] An insulating layer 44 is provided on the first surface of the conductive layer 36. The insulating layer 44 may contain, for example, silicon oxide.

[0056] In the Z1 direction, below the plurality of conductive layers 36, a plurality of memory pillars MP are provided extending in the Z direction. The first surface of each of the plurality of memory pillars MP is located, for example, between conductive layers 35 and conductive layers 36. The plurality of memory pillars MP penetrate conductive layers 30, 33 and 35, as well as the plurality of conductive layers 34.

[0057] Each of the plurality of memory pillars (MPs) includes, for example, a core component 50, a semiconductor film 51, and a multilayer film 52. The core component 50 extends along the Z-direction. The semiconductor film 51 covers the periphery of the core component 50. The Z2-direction end of the semiconductor film 51 is in contact with the semiconductor layer 31a. The multilayer film 52 covers the sides of the semiconductor film 51, except for the portion where the semiconductor film 51 contacts the semiconductor layer 31a. The core component 50 comprises an insulator such as silicon oxide. The semiconductor film 51, for example, comprises silicon. The structure of the multilayer film 52 will be described later.

[0058] A conductive layer 37 is disposed on the first surface of the semiconductor film 51. The conductive layer 37 functions as, for example, a columnar contact. The conductive layer 37 contains, for example, tungsten. A conductive layer 38 is disposed on the first surface of the conductive layer 37. The conductive layer 38 functions as, for example, a contact CV. The conductive layer 38 contains, for example, tungsten. With the configuration described above, the conductive layers 37 and 38 connect the semiconductor film 51 and the conductive layer 36. For each conductive layer 36, one conductive layer 37 and one conductive layer 38 are connected in each space divided by the components SLT and SHE.

[0059] The component SLT, for example, divides conductive layers 30, 33, and 35, and a plurality of conductive layers 34. In other words, the component SLT extends through conductive layers 30, 33, and 35, and a plurality of conductive layers 34. A conductor LI within the component SLT is disposed along the component SLT. A first surface of the conductor LI is located, for example, between conductive layers 35 and 36. A second surface of the conductor LI is in contact with semiconductor layer 31a. The conductor LI, for example, contains tungsten. A spacer SP is disposed between the conductor LI and conductive layers 30, semiconductor layer 31a, conductive layers 33 and 35, and a plurality of conductive layers 34. In other words, the conductor LI has its sides covered by the spacer SP. The conductor LI is separated from conductive layers 33 and 35, and a plurality of conductive layers 34 by the spacer SP, and is electrically insulated. The spacer SP, for example, contains silicon oxide. Additionally, although not shown in Figure 6, the conductor LI may also include a barrier metal. That is, the conductor LI may, for example, have a structure in which the second surface and side surfaces of a conductive member containing a metal such as tungsten are covered by a barrier metal. Furthermore, the conductor LI may be formed from a semiconductor member, or it may have a structure in which the insulator of the spacer SP is embedded in the entire member SLT.

[0060] The portions where each of the plurality of memory pillars MP intersects with the conductor layer 33 function as select transistor ST2. The portions where each of the plurality of memory pillars MP intersects with the plurality of conductor layers 34 function as memory cell transistor MT. The portions where each of the plurality of memory pillars MP intersects with the conductor layer 35 function as select transistor ST1.

[0061] Although the illustration is omitted in Figure 6, in this embodiment, the situation where the insulator 46 covers the space between the memory pillar MP and each of the conductive layers 33, 34 and 35, the first and second surfaces of each of the conductive layers 33, 34 and 35, and the side surface of the spacer SP will be described.

[0062] 1.1.6.3 Cross-sectional structure of memory cylinder Figure 7 illustrates the cross-sectional structure of a memory cylinder (MP). Figure 7 is a cross-sectional view along line VII-VII of Figure 6, showing an example of the cross-sectional structure of a memory cylinder (MP).

[0063] As shown in Figure 7, the laminated film 52 includes, for example, a tunnel insulating film 53, an insulating film 54, and a barrier insulating film 55. The tunnel insulating film 53 covers the sides of the semiconductor film 51, except for the portion where the semiconductor film 51 contacts the semiconductor layer 31a. The insulating film 54 covers the sides of the tunnel insulating film 53. The barrier insulating film 55 covers the sides of the insulating film 54. An insulator 46 covers the sides of the barrier insulating film 55. The insulator 46, together with the barrier insulating film 55, functions as the barrier insulating film of the memory cell transistor (MT). The conductive layer 34 covers the sides of the insulator 46. The tunnel insulating film 53 and the barrier insulating film 55, for example, contain silicon oxide. The insulating film 54, for example, contains silicon nitride. The insulator 46, for example, contains aluminum oxide.

[0064] In the configuration described above, the semiconductor film 51 functions as a channel for each of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. Furthermore, the insulating film 54 functions to accumulate a charge corresponding to the amount of data stored in the memory cell transistors MT. That is, the insulating film 54 functions as a charge accumulation layer for the memory cell transistors MT. The semiconductor memory device 3, by setting each of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2 to the ON state, allows current to flow between the source line SL and the bit line BL, through the memory pillar MP and the conductive layers 37 and 38.

[0065] 1.1.7 Cross-sectional structure of the entire semiconductor memory device Using Figure 8, the cross-sectional structure of the entire semiconductor memory device 3 will be explained. Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3. In Figure 8, a cross-sectional structure of a portion of the semiconductor memory device 3 (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0066] 1.1.7.1 Circuit Chip First, the cross-sectional structure of the circuit chip 200 will be explained.

[0067] As shown in Figure 8, the circuit chip 200 includes, for example, a semiconductor substrate 71, a plurality of conductive layers 201, 202, 203, 204, 205, and 206 constituting part of the peripheral circuit, and insulating layers 45 and 61. The semiconductor substrate 71 is, for example, made of a P-type semiconductor with added impurities. The plurality of conductive layers 201-206 function as, for example, pillar-shaped contacts or wiring. Figure 8 shows one conductive layer 203 of the plurality of conductive layers 203, one conductive layer 204 of the plurality of conductive layers 204, one conductive layer 205 of the plurality of conductive layers 205, and one conductive layer 206 of the plurality of conductive layers 206.

[0068] An insulating layer 45 is disposed on the first surface of the semiconductor substrate 71. The insulating layer 45 may include, for example, silicon oxide. A plurality of conductive layers 201, 202, 203, 204, and 205 are disposed within the insulating layer 45.

[0069] Peripheral circuitry is disposed on the first surface of the semiconductor substrate 71. Figure 8 shows a transistor TR1 as an example of the configuration of the peripheral circuitry. The transistor TR1 is, for example, included in the sense amplifier module 16. The transistor TR1 includes a gate insulating film, a gate electrode, and a source and drain electrode (not shown) disposed on the semiconductor substrate 71.

[0070] A conductive layer 201 is provided on the first surface of the gate electrode, source electrode, and drain electrode of the transistor TR1. A corresponding conductive layer 202 is provided on the first surface of each of the plurality of conductive layers 201.

[0071] A corresponding conductive layer 203 is disposed on the first surface of each of the plurality of conductive layers 202.

[0072] A corresponding conductive layer 204 is provided on the first surface of each of the plurality of conductive layers 203.

[0073] A corresponding conductive layer 205 is disposed on the first surface of each of the plurality of conductive layers 204. The first surface of each of the plurality of conductive layers 205 is configured to be flush with the first surface of the insulating layer 45.

[0074] An insulating layer 61 is provided on the first surface of each of the insulating layer 45 and the plurality of conductive layers 25. The insulating layer 61 may contain, for example, silicon oxide.

[0075] A plurality of conductive layers 206 are disposed on the same layer as the insulating layer 61. Each of the plurality of conductive layers 206 is connected to the first surface of a corresponding conductive layer 205. The first surface of each of the plurality of conductive layers 206 is configured to be flush with the first surface of the insulating layer 61. The conductive layers 206 may contain, for example, copper. The plurality of conductive layers 206 function as a plurality of bonding pads BP for electrically connecting the circuit chip 200 and the array chip 100.

[0076] 1.1.7.2 Array Chip Next, the cross-sectional structure of the array chip 100 will be described.

[0077] As shown in Figure 8, the array chip 100 includes, for example, a plurality of conductive layers 101, 102, 103, and 104, and a memory cell array 10. The plurality of conductive layers 101-104 function as, for example, pillar-shaped contacts or wiring. Figure 8 shows one conductive layer 101 from the plurality of conductive layers 101, one conductive layer 102 from the plurality of conductive layers 102, one conductive layer 103 from the plurality of conductive layers 103, and one conductive layer 104 from the plurality of conductive layers 104. The memory cell array 10 includes a conductive layer 30, a stacked layer SB, conductive layers 33 and 35, a plurality of conductive layers 34, 36, 37, and 38, a plurality of memory pillars MP, and a plurality of components SLT and SHE. The conductive layer 30 is disposed between the conductive layers 33 and 35, the plurality of conductive layers 34 and the laminate SB, and is spaced apart from the conductive layers 33 and 35 and the plurality of conductive layers 34 in the Z2 direction, and is connected to the semiconductor layer 31a.

[0078] In the array chip 100, an insulating layer 62 is disposed on the first surface of the circuit chip 200. The insulating layer 62 may contain, for example, silicon oxide.

[0079] A plurality of conductors 101 are disposed on the same layer as the insulating layer 62. Each of the plurality of conductor layers 101 is connected to the first surface of the corresponding conductor layer 206. The second surface of each of the plurality of conductor layers 101 is configured to be flush with the second surface of the insulating layer 62. The conductor layer 101 includes, for example, copper. The plurality of conductors 101 function as a plurality of bonding pads BP for electrically connecting the circuit chip 200 and the array chip 100. With the configuration described above, the circuit chip 200 and the array chip 100 are electrically connected by the plurality of conductor layers 206 and 101.

[0080] An insulating layer 44 is provided on the second surface of each of the insulating layer 62 and the plurality of conductive layers 101. A plurality of conductive layers 102 to 104 are provided within the insulating layer 44.

[0081] A corresponding conductive layer 102 is disposed on the second surface of each of the plurality of conductive layers 101. A corresponding conductive layer 103 is disposed on the second surface of each of the plurality of conductive layers 102. A corresponding conductive layer 104 is disposed on the second surface of each of the plurality of conductive layers 103. The second surface of each of the plurality of conductive layers 104 is connected to conductive layer 36. With the above-described configuration, conductive layer 36 and transistor TR1 are configured to be interconnected. That is, the bit lines BL of memory cell array 10 are electrically connected to sense amplifier module 16.

[0082] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 9 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 8.

[0083] As shown in Figure 9, insulator 46 is disposed between the barrier insulating film 55 and the conductive layer 33, between the barrier insulating film 55 and the conductive layer 34, and between the barrier insulating film 55 and the conductive layer 35 (not shown). Insulator 46 is disposed on the first and second surfaces of the conductive layer 33, the first and second surfaces of the conductive layer 34, and the first and second surfaces of the conductive layer 35 (not shown). Insulator 46 covers the side surface of the spacer SP, except for the portion of the spacer SP in contact with the conductive layer 33, the portion of the spacer SP in contact with the conductive layer 34, and the portion of the spacer SP in contact with the conductive layer 35 (not shown). Hereinafter, the structure including the spacer SP covering the side surface of the conductor LI in the Y direction and the insulator 46 covering the side surface of the spacer SP in the Y direction will be referred to as "insulator SW". Insulator SW covers the side surface of the conductor LI in the Y direction. Furthermore, the structure comprising the conductor LI and the insulator SW covering the side of the conductor LI in the Y direction is also called "component SLT".

[0084] The Z2-direction ends of the spacer SP and insulator 46 are cut off. More specifically, the corner of the Z2-direction end of the spacer SP that is not in contact with the conductor LI is cut off. That is, the Z2-direction end face of the spacer SP has an inclined portion IPa on the side that is not in contact with the conductor LI. The Z2-direction end of the insulator 46 is cut off up to the first surface of the conductor layer 30. That is, the Z2-direction end face of the insulator 46 has an inclined portion IPb following the inclined portion IPa. The inclined portion IPb reaches the first surface of the conductor layer 30. In other words, the Z2-direction end face EF of the insulator SW has an inclined portion IP on the side that is not in contact with the conductor LI. The inclined portion IP includes the inclined portion IPa and the inclined portion IPb. There is a recess RP between the inclined portion IP and the conductor layer 30. The angle of the inclined portion IP relative to the side surface of the conductor layer 30 is an acute angle. The inclined portion IP is in contact with the semiconductor layer 31a. Furthermore, the inclined portion IP is connected to the conductive layer 30 at a position lower than the upper surface of the conductive layer 30 in the Z2 direction.

[0085] In the Z2 direction, a semiconductor layer 31a is disposed on each of the conductor layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the barrier insulating film 55, the conductor LI, the spacer SP, and the insulator 46. The semiconductor layer 31a covers the Z2 direction end face (and side face) of the semiconductor film 51. The semiconductor layer 31a also covers the Z2 direction end face of the member SLT (the Z2 direction end face of the conductor LI, the Z2 direction end face of the spacer SP, and the Z2 direction end face of the insulator 46). The recess RP is embedded by the semiconductor layer 31a.

[0086] Semiconductor layer 31a contains a plurality of grains. The solid lines in Figure 9 schematically show grain boundaries (GBs) within semiconductor layer 31a. The portion surrounded by two grain boundaries (GBs) corresponds to a grain.

[0087] In the Z2 direction, a semiconductor layer 31b is disposed above the semiconductor layer 31a. The semiconductor layer 31b contains a plurality of grains. The solid lines in Figure 9 schematically show the grain boundaries GB within the semiconductor layer 31b. The portion surrounded by two grain boundaries GB corresponds to a grain.

[0088] As shown in Figure 9, the grain boundary GB of semiconductor layer 31a is not connected to the grain boundary GB of semiconductor layer 31b. That is, the grain boundary GB of semiconductor layer 31a and semiconductor layer 31b are discontinuous. Furthermore, the grain size (dimension) of semiconductor layer 31a is different from that of semiconductor layer 31b. For example, the grain size of semiconductor layer 31a is smaller than that of semiconductor layer 31b. The grain size of semiconductor layers 31a and 31b varies, for example, due to factors such as the film formation method of semiconductor layers 31a and 31b, the amount of impurities implanted into semiconductor layers 31a and 31b, the type of impurities implanted into semiconductor layers 31a and 31b, and the film thickness of semiconductor layers 31a and 31b. For example, the greater the film thickness, the larger the grain size of semiconductor layers 31a and 31b.

[0089] Alternatively, an oxide film may be disposed between semiconductor layer 31a and semiconductor layer 31b.

[0090] A conductive layer 32a is disposed on top of the semiconductor layer 31b in the Z2 direction. A conductive layer 32b is disposed on top of the conductive layer 32a in the Z2 direction.

[0091] 1.2 Manufacturing method of semiconductor memory device The manufacturing method of the semiconductor memory device 3 will be described using Figures 10 to 17. Figures 10 to 17 are cross-sectional views illustrating one example of the manufacturing method of the semiconductor memory device 3. Figures 10 to 13 show cross-sectional views corresponding to the area in Figure 8. Figures 14 to 17 show cross-sectional views corresponding to the area in Figure 9.

[0092] First, as shown in FIG10, on the first surface of the semiconductor substrate 71, a transistor TR1, a plurality of conductive layers 201-206, and insulating layers 45 and 61 comprising the peripheral circuit are formed. That is, a circuit chip 200 is formed.

[0093] Next, as shown in FIG11, on the first surface of the semiconductor substrate 72, which is composed of a P-type semiconductor with added impurities, an insulating layer 47, a semiconductor layer 31, conductive layers 30, 33, and 35, a plurality of conductive layers 34, 36, 37, 38, and 101-104, insulating layers 40, 41, 43, 44, and 62, a plurality of insulating layers 42, a plurality of memory pillars MP, and a plurality of components SLT and SHE are formed. That is, a structure corresponding to the array chip 100 is formed. The semiconductor layer 31, for example, contains doped polysilicon with added N-type impurities. Furthermore, the semiconductor layer 31, and the insulating layers 47 and 62 are all formed on the first surface of the semiconductor substrate 72.

[0094] Next, as shown in FIG12, the circuit chip 200 and the corresponding structure of the array chip 100 are bonded together by a bonding process. More specifically, the plurality of conductive layers 206 in the circuit chip 200 that function as bonding pads BP and the plurality of conductive layers 101 in the array chip 100 that function as bonding pads BP are arranged in an opposing manner. Furthermore, the opposing bonding pads BP are bonded together by heat treatment. Afterwards, the semiconductor substrate 72 is removed, for example, by CMP (Chemical Mechanical Polishing).

[0095] Next, as shown in Figure 13, the insulating layer 47 and semiconductor layer 31 in the portion corresponding to the memory cell array 10 are removed. This exposes the Z2-direction ends of each of the plurality of memory pillars MP and component SLT. Furthermore, in the area outside the portion corresponding to the memory cell array 10, the insulating layer 47 and semiconductor layer 31 remain because a resist mask is formed.

[0096] Next, as shown in Figure 14, the laminated film 52 is removed. For example, the barrier insulating film 55, the insulating film 54, and the tunnel insulating film 53 are removed sequentially from the laminated film 52.

[0097] First, the barrier insulating film 55 is removed. For example, the barrier insulating film 55 is processed by isotropic etching using wet etching with buffered hydrofluoric acid (BHF). This removes the barrier insulating film 55 above the second surface of the conductive layer 30 at the Z2 direction end of the memory pillar MP. At this time, the Z2 direction ends of the spacer SP and the insulator 46 are also slightly removed.

[0098] Next, the insulating film 54 is removed. For example, the insulating film 54 is processed by isotropic etching using wet etching with phosphoric acid. In this way, the insulating film 54 on the upper side of the second surface of the more conductive layer 30 is removed at the end of the memory pillar MP in the Z2 direction.

[0099] Next, the tunnel insulating film 53 is removed. For example, the tunnel insulating film 53 is processed by isotropic etching using CDE (Chemical Dry Etching). In this way, the tunnel insulating film 53 above the second surface of the conductive layer 30 is removed from the Z2 direction end of the memory pillar MP. At this time, the Z2 direction ends of the spacer SP and the insulator 46 are also slightly removed.

[0100] By removing the barrier insulating film 55, the insulating film 54, and the tunnel insulating film 53, the Z2-direction end of the semiconductor film 51 of the memory pillar MP is exposed. That is, the channel is exposed. As a result, the second surface of the memory pillar MP has a step. Also, as described above, the Z2-direction ends of the spacer SP and the insulator 46 are slightly removed. Since the component SLT has a structure in which the side of the conductor LI is covered by the spacer SP and the insulator 46, the corner of the Z2-direction end of the spacer SP that is not in contact with the conductor LI is obliquely cut off, and the Z2-direction end of the insulator 46 is obliquely cut off along the portion of the spacer SP that is cut off.

[0101] After removing the stacked film 52, isotropic etching using diluted hydrofluoric acid (DHF) is performed, for example, to eliminate the interfacial resistance of the conductive layer 30. This removes the native oxide film on the second surface of the conductive layer 30. At this time, as shown in FIG. 15, the Z2-direction ends of the spacer SP and insulator 46 are also removed. Since the component SLT has a structure in which the side of the conductor LI is covered by the spacer SP and insulator 46, an inclined portion IPa is formed on the side of the Z2-direction end face of the spacer SP that is not in contact with the conductor LI. An inclined portion IPb following the inclined portion IPa is formed on the Z2-direction end face of the insulator 46. The inclined portion IPb reaches the first surface of the conductive layer 30. In other words, an inclined portion IP is formed on the side of the Z2-direction end face EF of the insulator SW that is not in contact with the conductor LI. This forms a recess RP between the inclined portion IP and the conductive layer 30. The angle between the inclined portion IP and the side surface of the conductive layer 30 is an acute angle. In other words, the recessed portion RP is recessed at an acute angle.

[0102] Next, as shown in Figure 16, a semiconductor layer 31a is formed. For example, the semiconductor layer 31a is formed by LP-CVD (Low Pressure Chemical Vapor Deposition) or PE-CVD (Plasma Enhanced Chemical Vapor Deposition). For example, amorphous silicon is formed as the semiconductor layer 31a. The semiconductor layer 31a is thus formed on the second surface of the conductor layer 30, the plurality of memory pillars MP, and the plurality of component SLTs. More specifically, in the Z2 direction, the semiconductor layer 31a is formed on the conductor layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the barrier insulating film 55, the conductor LI, the spacer SP, and the insulator 46. By using LP-CVD or PE-CVD, which have relatively high coverage, a recessed portion RP with an acute angle is also embedded by the semiconductor layer 31a.

[0103] Next, as shown in Figure 17, a semiconductor layer 31b is formed. For example, the semiconductor layer 31b is formed by PVD (Physical Vapor Deposition). For example, amorphous silicon can be formed as the semiconductor layer 31b. Thus, the semiconductor layer 31b is formed on the second surface of the semiconductor layer 31a. Alternatively, the semiconductor layer 31b can also be formed by methods other than PVD. For example, the semiconductor layer 31b can also be formed by LP-CVD or PE-CVD.

[0104] Next, for example, impurities are introduced into semiconductor layers 31a and 31b by ion implantation. Impurities include, for example, phosphorus.

[0105] Next, for example, laser annealing is used to perform heat treatment on semiconductor layers 31a and 31b. Using a laser with a relatively long wavelength, the impurities are activated by instantaneous heating. In this way, the impurities diffuse into semiconductor layers 31a and 31b. Furthermore, the grains of the formed semiconductor layers 31a and 31b (amorphous silicon) move and grow due to heat, eventually crystallizing and being modified into polycrystalline silicon.

[0106] When the film formation methods of semiconductor layers 31a and 31b are different, the grain growth methods of amorphous silicon also differ. Furthermore, the grain growth methods of amorphous silicon also differ depending on the amount of impurities implanted into semiconductor layers 31a and 31b, the type of impurities implanted into semiconductor layers 31a and 31b, and the film thickness of semiconductor layers 31a and 31b. Therefore, the grain boundaries of semiconductor layer 31a and semiconductor layer 31b are discontinuous. Moreover, the grain sizes of semiconductor layer 31a and semiconductor layer 31b also become different. For example, the greater the film thickness, the larger the grain size of semiconductor layers 31a and 31b. When the film thickness of semiconductor layer 31b is set to be greater than that of semiconductor layer 31a, the grain size of semiconductor layer 31a is smaller than that of semiconductor layer 31b.

[0107] After heat treatment, for example, to eliminate the interface resistance of semiconductor layer 31b, isotropic etching using DHF wet etching is performed. Herein, the native oxide film on the second surface of semiconductor layer 31b is removed.

[0108] Next, a conductive layer 32a is formed. For example, the conductive layer 32a is formed by PVD. As the conductive layer 32a, titanium or titanium nitride is formed, for example. Thereby, the conductive layer 32a is formed on the second surface of the semiconductor layer 31b.

[0109] Next, a conductive layer 32b is formed. For example, the conductive layer 32b is formed by PVD. For example, tungsten is formed as the conductive layer 32b. Thus, the conductive layer 32b is formed on the second surface of the conductive layer 32a, forming the structure shown in FIG9.

[0110] The semiconductor memory device 3 is formed through the manufacturing steps described above. However, the manufacturing steps described above are merely one example and are not limited to this. For example, other processes can be inserted between the manufacturing steps, or some steps can be omitted or combined. A step of forming an oxide film between semiconductor layers 31a and 31b can also be inserted between the step of forming semiconductor layer 31a and the step of forming semiconductor layer 31b. Furthermore, the manufacturing steps can be replaced to the extent possible.

[0111] 1.3 Effects of this implementation After the array chip 100 and the circuit chip 200 are bonded together, a source line SL with polycrystalline silicon, barrier metal, and metal stack is formed on the uppermost conductive layer. Before the amorphous silicon film is formed, the stacked film 52 of the memory pillars MP and the native oxide film on the conductive layer are removed. At this time, a portion of the insulator SW of the component SLT is removed, and a recessed portion with an acute angle may be formed between the component SLT and the conductive layer. If such a recessed portion is formed, during the amorphous silicon film formation, a portion not embedded by the amorphous silicon may be generated in the recessed portion. If there is an unembedded portion in the recessed portion, during the removal of the native oxide film before the barrier metal and metal film formation, the etchant enters the unembedded amorphous silicon portion of the recessed portion by wet etching, and the insulator SW of the component SLT may melt. If there is a molten portion in the insulator SW, then when forming the metal film, the metal film will be formed on the molten portion of the insulator SW, and a short circuit may occur between the source line SL and the select gate line SGS.

[0112] In this embodiment, two semiconductor layers are formed as the semiconductor layer covering the semiconductor film 51 (channel) and the component SLT. For example, semiconductor layers 31a and 31b are formed. Since two semiconductor layers are formed, the coating performance of the recessed portion RP with an acute angle is improved compared to the case where only one semiconductor layer is formed. Therefore, the recessed portion RP is buried by semiconductor layer 31a (amorphous silicon). As a result, compared to the case where only one semiconductor layer is formed, the dissolution of the insulator SW caused by wet etching can be suppressed in the removal step of the barrier metal and the native oxide film before metal film formation. Therefore, short circuits between the source line SL and the select gate line SGS can be suppressed. Therefore, the yield can be improved. In addition, three or more semiconductor layers can be formed as the semiconductor layer covering the semiconductor film 51, and the same effect can be obtained even when three or more semiconductor layers are formed.

[0113] In this embodiment, for example, LP-CVD or PE-CVD is used to form the semiconductor layer 31a. Since LP-CVD or PE-CVD has relatively high coating strength, the coating strength for the acute-angled recess RP is improved compared to the case where the semiconductor layer 31a is formed using methods other than LP-CVD or PE-CVD. Therefore, the semiconductor layer 31a (amorphous silicon) is embedded in the recess RP. Thus, the yield can be improved.

[0114] Furthermore, when the grain boundary of semiconductor layer 31a is connected to the grain boundary of semiconductor layer 31b, during the removal of the natural oxide film before the barrier metal and metal film are formed, the etching solution is transferred to the insulator SW through wet etching, which may open up the insulator SW and form pinholes.

[0115] In contrast, in this embodiment, the grain boundaries of semiconductor layer 31a and semiconductor layer 31b are discontinuous. For example, semiconductor layer 31a can be deposited using LP-CVD or PE-CVD. Semiconductor layer 31b is deposited using PVD. That is, the deposition methods for semiconductor layers 31a and 31b are different. The grain growth method differs due to the deposition method, thus the grain boundaries of semiconductor layer 31a and semiconductor layer 31b become discontinuous. Furthermore, the grain sizes of semiconductor layer 31a and semiconductor layer 31b are also different. Therefore, compared to the case where the grain boundaries of semiconductor layer 31a and semiconductor layer 31b are connected, pinhole formation in the insulator SW can be suppressed during the removal step of the native oxide film before the barrier metal and metal deposition. Therefore, the yield can be improved. Furthermore, the method of grain growth varies depending on the amount of impurities implanted into semiconductor layers 31a and 31b, the type of impurities implanted into semiconductor layers 31a and 31b, and the film thickness of semiconductor layers 31a and 31b. Therefore, even when the amount of impurities, the type of impurities, and the film thickness of semiconductor layers 31a and 31b are different, the same effect can be obtained.

[0116] 2. Second Implementation Form The semiconductor memory device of the second embodiment will be described. In the semiconductor memory device 3A of this embodiment, the structure of the multilayer SB is different from that of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0117] 2.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 18, the cross-sectional structure of the entire semiconductor memory device 3A will be explained. Figure 18 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3A. In Figure 18, a cross-sectional structure of a portion of the semiconductor memory device 3A (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0118] As shown in FIG. 18, the memory cell array 10, in addition to the configuration shown in FIG. 8 of the first embodiment, further includes an insulating layer 48. More specifically, the stacked body SB has a configuration in which the insulating layer 48 is disposed between the semiconductor layer 31a and the semiconductor layer 31b. The cross-sectional configuration other than the stacked body SB is the same as that shown in FIG. 8 of the first embodiment.

[0119] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 19 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 18.

[0120] As shown in Figure 19, an insulating layer 48 is disposed on top of the semiconductor layer 31a in the Z2 direction. The insulating layer 48 may contain, for example, silicon oxide or silicon nitride. That is, the insulating layer 48 may be, for example, an oxide film or a nitride film. A semiconductor layer 31b is disposed on top of the insulating layer 48 in the Z2 direction.

[0121] As shown in Figure 19, the grain boundary GB of semiconductor layer 31a and the grain boundary GB of semiconductor layer 31b are separated by insulating layer 48. Therefore, the grain boundary GB of semiconductor layer 31a and the grain boundary GB of semiconductor layer 31b are not connected. That is, the grain boundary GB of semiconductor layer 31a and the grain boundary GB of semiconductor layer 31b are discontinuous. Furthermore, the grain size of semiconductor layer 31a is different from that of semiconductor layer 31b. For example, the grain size of semiconductor layer 31a is smaller than that of semiconductor layer 31b.

[0122] 2.2 Manufacturing method of semiconductor memory device The manufacturing method of the semiconductor memory device 3A will be described using Figures 20 and 21. Figures 20 and 21 are cross-sectional views illustrating one example of the manufacturing method of the semiconductor memory device 3A. Figures 20 and 21 show cross-sectional views corresponding to the area in Figure 19.

[0123] First, the process is carried out in the same manner as in the first embodiment until the removal of the natural oxide film on the second surface of the conductive layer 30 after the removal of the stacked film 52 is completed.

[0124] Next, a semiconductor layer 31a is formed. For example, the semiconductor layer 31a is formed by PVD. For example, amorphous silicon is formed as the semiconductor layer 31a. Thus, in the Z2 direction, the semiconductor layer 31a is formed on each of the conductive layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the barrier insulating film 55, the conductor LI, the spacer SP, and the insulator 46. Alternatively, the semiconductor layer 31a can also be formed by a film-forming method other than PVD. For example, the semiconductor layer 31a can also be formed by LP-CVD or PE-CVD.

[0125] Next, for example, by laser annealing, heat treatment is performed on the semiconductor layer 31a. Herein, the grains of the semiconductor layer 31a (amorphous silicon) move and are embedded in the recess RP from the semiconductor layer 31a.

[0126] Next, as shown in Figure 20, an insulating layer 48 is formed on the semiconductor layer 31a in the Z2 direction. For example, the structure with the semiconductor layer 31a is exposed to the atmosphere in a cleanroom, thereby forming the insulating layer 48. The thickness of the insulating layer 48 is, for example, about 1 nm.

[0127] Furthermore, as an insulating layer 48, an oxide film can be formed by oxidation by free radicals in the plasma, rather than by a naturally occurring oxide film. Also, as an insulating layer 48, a nitrided film can be formed by nitriding by free radicals in the plasma.

[0128] Next, as shown in FIG21, a semiconductor layer 31b is formed, for example, by PVD. The semiconductor layer 31b is, for example, formed of amorphous silicon. Thus, the semiconductor layer 31b is formed on the insulating layer 48 in the Z2 direction. Alternatively, the semiconductor layer 31b can also be formed by a film-forming method other than PVD. For example, the semiconductor layer 31b can also be formed by LP-CVD or PE-CVD.

[0129] Subsequently, the steps of impurity introduction, heat treatment, removal of the natural oxide film on the second surface of semiconductor layer 31b, formation of conductive layer 32a, and formation of conductive layer 32b are performed in the same manner as in the first embodiment. In the heat treatment step, for example, laser annealing is used to heat-treat the semiconductor layers 31a and 31b (amorphous silicon), causing the grains to move and grow due to heat. Since an insulating layer 48 exists between semiconductor layers 31a and 31b, the growth of amorphous silicon grains stops at the insulating layer 48. Therefore, the grain size of semiconductor layer 31a and the grain size of semiconductor layer 31b become different.

[0130] 2.3 Effects of this implementation In this embodiment, for example, after amorphous silicon is deposited as a semiconductor layer 31a using PVD, a laser annealing heat treatment is performed. The grains of the amorphous silicon move and grow due to heat. Therefore, by the movement of the grains of the semiconductor layer 31a (amorphous silicon), the amorphous silicon is embedded in the recess RP. Thus, similar to the first embodiment, the dissolution of the insulator SW caused by wet etching can be suppressed in the step of removing the native oxide film before the barrier metal and metal film formation. Therefore, the yield can be improved.

[0131] Furthermore, in this embodiment, an insulating layer 48 is provided between semiconductor layer 31a and semiconductor layer 31b, for example. This separates semiconductor layer 31a and semiconductor layer 31b by the insulating layer 48. That is, the grain boundaries of semiconductor layer 31a and semiconductor layer 31b become discontinuous. Also, the growth of the grains in semiconductor layers 31a and 31b (amorphous silicon) stops at the insulating layer 48. Therefore, the grain size of semiconductor layer 31a and the grain size of semiconductor layer 31b become different. Thus, similar to the first embodiment, pinholes can be suppressed in the insulator SW during the removal step of the native oxide film before the barrier metal and metal film formation. Therefore, the yield can be improved.

[0132] 3. Third Implementation Form The semiconductor memory device of the third embodiment will be described. In the semiconductor memory device 3B of this embodiment, the structure of the multilayer SB differs from that of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0133] 3.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 22, the cross-sectional structure of the entire semiconductor memory device 3B will be explained. Figure 22 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3B. In Figure 22, a cross-sectional structure of a portion of the semiconductor memory device 3B (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0134] As shown in Figure 22, the memory cell array 10 differs from the configuration shown in Figure 8 of the first embodiment by removing the semiconductor layer 31b. More specifically, the stacked body SB has a structure formed by sequentially stacking the semiconductor layer 31a, the conductor layer 32a, and the conductor layer 32b from the semiconductor substrate 71 side. The cross-sectional structure other than the stacked body SB is the same as that shown in Figure 8 of the first embodiment.

[0135] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 23 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB shown in Figure 22.

[0136] As shown in Figure 23, the Z2-direction ends of the spacer SP and insulator 46 are cut off. More specifically, the spacer SP and insulator 46 are cut down to a position lower than the upper surface of the conductor LI in the Z2 direction and the upper surface of the conductor layer 30 in the Z2 direction. That is, the Z2-direction end faces of the spacer SP and insulator 46 are located lower than the upper surface of the conductor LI in the Z2 direction and the upper surface of the conductor layer 30 in the Z2 direction. The Z2-direction end face of the insulator 46 reaches the first surface of the conductor layer 30. In other words, the Z2-direction end face EF of the insulator SW is located lower than the upper surface of the conductor LI in the Z2 direction and the upper surface of the conductor layer 30 in the Z2 direction. A recess RP exists between the Z2-direction end face EF of the insulator SW and the conductor layer 30. The angle between the Z2-direction end face EF of the insulator SW and the side surface of the conductor layer 30 is a relatively large angle (close to 90 degrees). The side surface of the conductor LI in the Z2 direction and the end face EF of the insulator SW in the Z2 direction are connected to the semiconductor layer 31a.

[0137] In the Z2 direction, a semiconductor layer 31a is disposed on each of the conductive layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the barrier insulating film 55, the conductor LI, the spacer SP, and the insulator 46. The semiconductor layer 31a may contain, for example, doped polycrystalline silicon with added N-type impurities. The semiconductor layer 31a covers the Z2 direction end (end face and side face) of the semiconductor film 51. The semiconductor layer 31a also covers the Z2 direction end (end face and side face) of the conductor LI. The recess RP is embedded by the semiconductor layer 31a.

[0138] In the Z2 direction, a conductive layer 32a is disposed above the semiconductor layer 31a. The conductive layer 32a may contain, for example, titanium or titanium nitride. In the Z2 direction, a conductive layer 32b is disposed above the conductive layer 32a. The conductive layer 32b may contain, for example, tungsten.

[0139] 3.2 Manufacturing method of semiconductor memory device The manufacturing method of the semiconductor memory device 3B will be described using Figures 24-26. Figures 24-26 are cross-sectional views illustrating one example of the manufacturing method of the semiconductor memory device 3B. Figures 24-26 show cross-sectional views corresponding to the area in Figure 23.

[0140] First, the process is carried out in the same manner as in the first embodiment until the removal of the natural oxide film on the second surface of the conductive layer 30 after the removal of the stacked film 52 is completed.

[0141] Next, as shown in FIG24, an insulating layer 49 is formed. For example, the insulating layer 49 is formed into a film by PVD. For example, the insulating layer 49 is formed into a film with a thickness of more than half the height of the recess RP. Silicon oxide is formed into the insulating layer 49, for example. In this way, the insulating layer 49 is formed on each of the conductor layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the barrier insulating film 55, the conductor LI, the spacer SP, and the insulator 46 in the Z2 direction.

[0142] Next, as shown in Figure 25, isotropic etching using wet etching with DHF is performed, for example. The etching rate is relatively high. Herein, the insulating layer 49 is removed, and the Z2-direction ends of the spacer SP and the insulator 46 are cut away. Due to the relatively high etching rate, the entire Z2-direction end of the spacer SP and the insulator 46 is cut away. For example, the Z2-direction ends of the spacer SP and the insulator 46 are cut away to a position lower than the upper surface of the conductor LI in the Z2-direction and the upper surface of the conductor layer 30 in the Z2-direction. The Z2-direction end face of the insulator 46 reaches the first surface of the conductor layer 30. In other words, the position of the Z2-direction end face EF of the insulator SW becomes lower than the upper surface of the conductor LI in the Z2-direction and the upper surface of the conductor layer 30 in the Z2-direction. A recess RP is formed between the Z2-direction end face EF of the insulator SW and the conductor layer 30. The angle between the end face EF of the insulator SW in the Z2 direction and the side surface of the conductor layer 30 is relatively large. In other words, the recess RP is recessed at a relatively large angle.

[0143] Next, as shown in FIG26, a semiconductor layer 31a is formed. For example, the semiconductor layer 31a is formed by PVD. As the semiconductor layer 31a, for example, an amorphous silicon film is formed. Thereby, the semiconductor layer 31a is formed on the second surface of each of the conductor layer 30, the plurality of memory pillars MP, and the plurality of components SLT. More specifically, in the Z2 direction, the semiconductor layer 31a is formed on each of the conductor layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the barrier insulating film 55, the conductor LI, the spacer SP, and the insulator 46. The recess RP, which is recessed at a relatively large angle, is embedded in the semiconductor layer 31a. Alternatively, the semiconductor layer 31a can also be formed by film formation methods other than PVD. For example, the semiconductor layer 31a can also be formed by LP-CVD or PE-CVD.

[0144] Subsequently, the steps of introducing impurities, heat treatment, removing the natural oxide film on the second surface of the semiconductor layer 31a, forming the conductive layer 32a, and forming the conductive layer 32b are performed in the same manner as in the first embodiment.

[0145] 3.3 Effects of this implementation In this embodiment, after removing the stacked film 52 of the memory pillar MP on the conductive layer 30 and the native oxide film, the insulating layer 49 is formed. Here, a recess RP with an acute angle is embedded in the insulating layer 49. Next, etching is performed at a relatively high etching rate. Here, the entire insulator SW is removed, forming a recess RP with a relatively large angle between the insulator SW and the conductive layer 30. Therefore, compared to the case where the semiconductor layer 31a (amorphous silicon) is formed on the recess RP with an acute angle, the coating properties of the recess RP are improved. Therefore, the recess RP is embedded by amorphous silicon. Here, similar to the first embodiment, in the step of removing the native oxide film before the barrier metal and metal film formation, the dissolution of the insulator SW caused by wet etching can be suppressed. Therefore, the yield can be improved.

[0146] 3.4 Example of the first variation The semiconductor memory device of the first variation of the third embodiment will be described. In this variation of the semiconductor memory device 3Ba, the structure of the multilayer SB differs from that of the third embodiment. Hereinafter, the description will focus on the differences from the third embodiment.

[0147] 3.4.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 27, the cross-sectional structure of the entire semiconductor memory device 3Ba will be explained. Figure 27 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3Ba. In Figure 27, a cross-sectional structure of a portion of the semiconductor memory device 3Ba (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0148] As shown in FIG. 27, the memory cell array 10, in addition to the configuration shown in FIG. 22 in the third embodiment, further includes a semiconductor layer 31b. More specifically, the stacked body SB has a structure in which the semiconductor layer 31b is disposed between the semiconductor layer 31a and the conductor layer 32a. The cross-sectional structure other than the stacked body SB is the same as that shown in FIG. 22 in the third embodiment.

[0149] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 28 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 27.

[0150] As shown in Figure 28, a semiconductor layer 31b is disposed above the semiconductor layer 31a in the Z2 direction. The semiconductor layer 31b may contain, for example, doped polysilicon with added N-type impurities. A conductive layer 32a is disposed above the semiconductor layer 31b in the Z2 direction.

[0151] 3.4.2 Manufacturing method of semiconductor memory device In the manufacturing method of the semiconductor memory device 3Ba, for example, between the semiconductor layer 31a formation step and the conductor layer 32a formation step shown in the third embodiment, the semiconductor layer 31b formation step shown in the first embodiment is inserted.

[0152] 3.4.3 Effects of this variation According to this variation, it achieves the same effect as the third embodiment. Furthermore, it achieves the same effect as the first embodiment.

[0153] 3.5 Second variation example The semiconductor memory device of the second variation of the third embodiment will be described. In this variation of the semiconductor memory device 3Bb, the structure of the multilayer SB differs from that of the first variation of the third embodiment. Hereinafter, the description will focus on the differences from the first variation of the third embodiment.

[0154] 3.5.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 29, the cross-sectional structure of the entire semiconductor memory device 3Bb will be explained. Figure 29 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3Bb. In Figure 29, a cross-sectional structure of a portion of the semiconductor memory device 3Bb (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0155] As shown in Figure 29, the memory cell array 10, in addition to the configuration shown in Figure 27 of the first variation of the third embodiment, further includes an insulating layer 48. More specifically, the laminate SB has a structure in which the insulating layer 48 is disposed between the semiconductor layer 31a and the semiconductor layer 31b. The cross-sectional structure other than the laminate SB is the same as that shown in Figure 27 of the first variation of the third embodiment.

[0156] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 30 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 29.

[0157] As shown in Figure 30, an insulating layer 48 is disposed above the semiconductor layer 31b in the Z2 direction. The insulating layer 48 may contain, for example, silicon oxide or silicon nitride. A conductive layer 32a is disposed above the insulating layer 48 in the Z2 direction.

[0158] 3.5.2 Manufacturing method of semiconductor memory device In the manufacturing method of the semiconductor memory device 3Bb, for example, between the semiconductor layer 31a formation step and the semiconductor layer 31b formation step shown in the first variation of the third embodiment, the insulating layer 48 formation step shown in the second embodiment is inserted.

[0159] 3.5.3 Effects of this variation According to this variation, it achieves the same effect as the third embodiment. Furthermore, it achieves the same effect as the second embodiment.

[0160] 4. Fourth Implementation Form The semiconductor memory device of the fourth embodiment will be described. In the semiconductor memory device 3C of this embodiment, the structure of the multilayer SB is different from that of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0161] 4.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 31, the cross-sectional structure of the entire semiconductor memory device 3C will be explained. Figure 31 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3C. In Figure 31, a cross-sectional structure of a portion of the semiconductor memory device 3C (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0162] As shown in Figure 31, the memory cell array 10 differs from the configuration shown in Figure 8 of the first embodiment by removing semiconductor layers 31a and 31b. The stacked body SB has a structure formed by sequentially stacking conductive layers 32a and 32b from the semiconductor substrate 71 side. The cross-sectional structure other than the stacked body SB is the same as that shown in Figure 8 of the first embodiment.

[0163] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 32 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 31.

[0164] As shown in Figure 32, the Z2-direction ends of the spacer SP and insulator 46 are cut off. More specifically, the corner of the Z2-direction end of the spacer SP that is not in contact with the conductor LI is cut off. That is, the Z2-direction end face of the spacer SP has an inclined portion IPa on the side that is not in contact with the conductor LI. The Z2-direction end of the insulator 46 is cut off up to the first surface of the conductor layer 30. That is, the Z2-direction end face of the insulator 46 has an inclined portion IPb following the inclined portion IPa. The inclined portion IPb reaches the first surface of the conductor layer 30. In other words, the Z2-direction end face EF of the insulator SW has an inclined portion IP on the side that is not in contact with the conductor LI. The inclined portion IP includes the inclined portion IPa and the inclined portion IPb. There is a recess RP between the inclined portion IP and the conductor layer 30. The angle of the inclined portion IP relative to the side surface of the conductor layer 30 is an acute angle. The inclined portion IP is in contact with the conductor layer 32a. Furthermore, the inclined portion IP is located at a position lower than the upper surface of the conductive layer 30 in the Z2 direction, and is in contact with the conductive layer 30.

[0165] In the Z2 direction, a conductive layer 32a is provided on each of the conductive layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the barrier insulating film 55, the conductor LI, the spacer SP, and the insulator 46. The conductive layer 32a may contain, for example, titanium or titanium nitride. The conductive layer 32a covers the Z2 direction end (end face and side face) of the semiconductor film 51. The conductive layer 32a covers the Z2 direction end of the member SLT (the Z2 direction end face of the conductor LI, the Z2 direction end face of the spacer SP, and the Z2 direction end face of the insulator 46). The recess RP is embedded by the conductive layer 32a. In the Z2 direction, a conductive layer 32b is provided on top of the conductive layer 32a. The conductive layer 32b may contain, for example, tungsten.

[0166] 4.2 Manufacturing method of semiconductor memory device Figure 33 illustrates a method for manufacturing a semiconductor memory device 3C. Figure 33 is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor memory device 3C. Figure 33 shows a cross-sectional view corresponding to the area in Figure 32.

[0167] First, the process is carried out in the same manner as in the first embodiment until the removal of the natural oxide film on the second surface of the conductive layer 30 after the removal of the stacked film 52 is completed.

[0168] Next, as shown in Figure 33, a conductive layer 32a is formed. For example, the conductive layer 32a is formed by PVD. For example, titanium or titanium nitride can be formed as the conductive layer 32a. Thus, in the Z2 direction, the conductive layer 32a is formed on each of the conductive layer 30, the semiconductor film 51, the tunnel insulating film 53, the insulating film 54, the barrier insulating film 55, the conductor LI, the spacer SP, and the insulator 46. As the conductive layer 32a, a material with relatively high coverage is formed, thereby embedding the acute-angled recess RP within the conductive layer 32a. Alternatively, the conductive layer 32a can also be formed by methods other than PVD. For example, the conductive layer 32a can also be formed by LP-CVD or PE-CVD.

[0169] Next, a conductive layer 32b is formed. For example, the conductive layer 32b is formed by PVD. For example, tungsten is formed as the conductive layer 32b. Thus, the conductive layer 32b is formed on top of the conductive layer 32a in the Z2 direction, forming the structure shown in FIG32. Alternatively, the conductive layer 32b can also be formed by a film-forming method other than PVD. For example, the conductive layer 32b can also be formed by LP-CVD or PE-CVD.

[0170] 4.3 Effects of this implementation In this embodiment, two conductive layers are formed as the stack SB covering the semiconductor film 51 and the component SLT. For example, conductive layers 32a and 32b are formed. As conductive layer 32a, titanium or titanium nitride is formed, for example. Since these materials have relatively high coverage, the coverage of the recessed portion RP with an acute angle is improved compared to the case where a film is formed with a material with relatively low coverage. Therefore, the recessed portion RP is embedded by the conductive layer 32a. Herein, similar to the first embodiment, the dissolution of the insulator SW caused by wet etching can be suppressed in the step of removing the native oxide film before the barrier metal and the metal are formed. Therefore, the yield can be improved.

[0171] Furthermore, in this embodiment, since the stacked body SB does not contain a semiconductor layer, the movement of the semiconductor layer (amorphous silicon) grains caused by heat treatment can be disregarded.

[0172] 5. Fifth Implementation Form The semiconductor memory device of the fifth embodiment will be described. In the 3D semiconductor memory device of this embodiment, the structure of the multilayer SB and the insulator SW is different from that of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0173] 5.1 Cross-sectional structure of the semiconductor memory device Figure 34 illustrates the cross-sectional structure of the overall 3D semiconductor memory device. Figure 34 is a cross-sectional view showing an example of the cross-sectional structure of the 3D semiconductor memory device. Figure 34 shows the cross-sectional structure of a portion of the 3D semiconductor memory device (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200).

[0174] As shown in Figure 34, in the laminate SB, the end face of the conductor LI in the Z2 direction is covered by the spacer SP. That is, in the Z2 direction, the end face of the conductor LI is not in contact with the semiconductor layer 31a. In the Z2 direction, the end face of the spacer SP is in contact with the semiconductor layer 31a. The cross-sectional structure of the laminate SB, except for the insulator SW described later, is the same as that shown in Figure 8 of the first embodiment.

[0175] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 35 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 34.

[0176] As shown in Figure 35, the cross-sectional structure of the laminate SB and the insulator SW is the same as that shown in Figure 9 of the first embodiment, except for the point where the end face of the conductor LI in the Z2 direction is covered by the spacer SP. That is, the cross-sectional structure of the semiconductor layer 31a, semiconductor layer 31b, conductor layer 32a, conductor layer 32b, and insulator 46 is the same as that shown in Figure 9 of the first embodiment.

[0177] 5.2 Manufacturing method of semiconductor memory device Figure 36 illustrates a method for manufacturing a 3D semiconductor memory device. Figure 36 is a cross-sectional view illustrating one example of a method for manufacturing a 3D semiconductor memory device. Figure 36 shows a cross-sectional view corresponding to the area in Figure 35.

[0178] In the formation of the component SLT, not only the side surface of the conductor LI, but also the bottom surface of the conductor LI is covered by the spacer SP. Otherwise, the process continues in the same manner as in the first embodiment until the removal step of the laminated film 52. In this way, the structure shown in FIG36 is formed.

[0179] Subsequently, the steps of removing the native oxide film on the second surface of the conductive layer 30, forming the semiconductor layer 31a, forming the semiconductor layer 31b, introducing impurities, heat treatment, removing the native oxide film on the second surface of the semiconductor layer 31b, forming the conductive layer 32a, and forming the conductive layer 32b are performed in the same manner as in the first embodiment. This forms the structure shown in FIG35.

[0180] 5.3 Effects of this implementation According to this embodiment, it achieves the same effect as the first embodiment.

[0181] 6. Sixth Implementation Form The semiconductor memory device of the sixth embodiment will be described. In the semiconductor memory device 3E of this embodiment, the structure of the multilayer SB and the insulator SW differs from that of the second embodiment. Hereinafter, the description will focus on the differences from the second embodiment.

[0182] 6.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 37, the cross-sectional structure of the entire semiconductor memory device 3E will be explained. Figure 37 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3E. In Figure 37, a cross-sectional structure of a portion of the semiconductor memory device 3E (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0183] As shown in Figure 37, similar to the fifth embodiment, in the laminate SB, the end face of the conductor LI in the Z2 direction is covered by the spacer SP. The cross-sectional structure of the laminate SB and the insulator SW (described later) is the same as that shown in Figure 18 of the second embodiment.

[0184] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 38 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 37.

[0185] As shown in Figure 38, the cross-sectional structure of the laminate SB and the insulator SW is the same as that shown in Figure 19 of the second embodiment, except for the point where the end face of the conductor LI in the Z2 direction is covered by the spacer SP. That is, the cross-sectional structure of the semiconductor layer 31a, the insulator layer 48, the semiconductor layer 31b, the conductor layer 32a, the conductor layer 32b, and the insulator 46 is the same as that shown in Figure 19 of the second embodiment.

[0186] 6.2 Manufacturing method of semiconductor memory device The manufacturing method of semiconductor memory device 3E is explained.

[0187] First, similar to the fifth embodiment, a component SLT is formed until the natural oxide film on the second surface of the conductive layer 30 after the delaminated film 52 is removed. Thus, the structure shown in FIG36 is formed, similar to the fifth embodiment.

[0188] Subsequently, the following steps are performed in the same manner as in the second embodiment: removal of the native oxide film on the second surface of the conductive layer 30, formation of the semiconductor layer 31a, heat treatment, formation of the insulating layer 48, formation of the semiconductor layer 31b, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31b, formation of the conductive layer 32a, and formation of the conductive layer 32b. This forms the structure shown in FIG38.

[0189] 6.3 Effects of this implementation According to this embodiment, it achieves the same effect as the second embodiment.

[0190] 7. Seventh Implementation Form The semiconductor memory device of the seventh embodiment will be described. In the semiconductor memory device 3F of this embodiment, the structure of the multilayer SB differs from that of the third embodiment. Hereinafter, the description will focus on the differences from the third embodiment.

[0191] 7.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 39, the cross-sectional structure of the entire semiconductor memory device 3F will be explained. Figure 39 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3F. In Figure 39, a cross-sectional structure of a portion of the semiconductor memory device 3F (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0192] As shown in Figure 39, in the laminate SB, when forming the component SLT described later, the end face of the conductor LI in the Z2 direction is covered by the spacer SP. Therefore, the end face of the conductor LI in the Z2 direction is located lower than the end faces of the core component 50 and the semiconductor film 51 in the Z2 direction. The cross-sectional structure outside the laminate SB is the same as that shown in Figure 22 in the third embodiment.

[0193] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 40 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 39.

[0194] As shown in Figure 40, the cross-sectional structure of the laminate SB is the same as that shown in Figure 23 of the third embodiment, except that in the Z2 direction, the end face of the conductor LI is located lower than the end face of the core member 50 and the semiconductor film 51. That is, the cross-sectional structures of the semiconductor layer 31a, the conductor layer 32a, and the conductor layer 32b are the same as those shown in Figure 23 of the third embodiment.

[0195] 7.2 Manufacturing method of semiconductor memory device The manufacturing method of semiconductor memory device 3F is explained.

[0196] First, similar to the fifth embodiment, a component SLT is formed until the natural oxide film on the second surface of the conductive layer 30 after the delaminated film 52 is removed. Thus, the structure shown in FIG36 is formed, similar to the fifth embodiment.

[0197] Subsequently, similar to the third embodiment, the following steps are performed: removal of the native oxide film on the second surface of the conductive layer 30, formation of the insulating layer 49, removal of the insulating layer 49, formation of the semiconductor layer 31a, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31a, formation of the conductive layer 32a, and formation of the conductive layer 32b. This forms the structure shown in FIG40.

[0198] 7.3 Effects of this implementation According to this embodiment, it achieves the same effect as the third embodiment.

[0199] 7.4 Example of the first variation The semiconductor memory device of the first variation of the seventh embodiment will be described. In this variation of the semiconductor memory device 3Fa, the structure of the multilayer SB differs from that of the first variation of the third embodiment. Hereinafter, the description will focus on the differences from the first variation of the third embodiment.

[0200] 7.4.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 41, the cross-sectional structure of the entire semiconductor memory device 3Fa will be explained. Figure 41 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3Fa. In Figure 41, a cross-sectional structure of a portion of the semiconductor memory device 3Fa (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0201] As shown in Figure 41, in the laminate SB, the Z2 direction end face of the conductor LI is located lower than the Z2 direction end faces of the core member 50 and the semiconductor film 51. The cross-sectional structure outside the laminate SB is the same as that shown in Figure 27 of the first variation of the third embodiment.

[0202] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 42 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 41.

[0203] As shown in Figure 42, the cross-sectional structure of the laminate SB is the same as that shown in Figure 28 of the first variation of the third embodiment, except that the end face of the conductor LI is located lower than the end face of the core member 50 and the semiconductor film 51 in the Z2 direction. That is, the cross-sectional structures of each of the semiconductor layer 31a, semiconductor layer 31b, conductor layer 32a, and conductor layer 32b are the same as those shown in Figure 28 of the first variation of the third embodiment.

[0204] 7.4.2 Manufacturing method of semiconductor memory device The manufacturing method of the semiconductor memory device 3Fa is explained.

[0205] First, similar to the fifth embodiment, a component SLT is formed until the natural oxide film on the second surface of the conductive layer 30 after the delaminated film 52 is removed. Thus, similar to the fifth embodiment, the structure shown in FIG36 is formed.

[0206] Subsequently, similar to the first variation of the third embodiment, the following steps are performed: removal of the native oxide film on the second surface of the conductive layer 30, formation of the insulating layer 49, removal of the insulating layer 49, formation of the semiconductor layer 31a, formation of the semiconductor layer 31b, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31a, formation of the conductive layer 32a, and formation of the conductive layer 32b. This forms the structure shown in FIG42.

[0207] 7.4.3 Effects of this variation According to this variation, it achieves the same effect as the first variation of the third implementation.

[0208] 7.5 Example of the second variation The semiconductor memory device of the second variation of the seventh embodiment will be described. In this variation of the semiconductor memory device 3Fb, the structure of the multilayer SB differs from that of the second variation of the third embodiment. Hereinafter, the description will focus on the differences from the second variation of the third embodiment.

[0209] 7.5.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 43, the cross-sectional structure of the entire semiconductor memory device 3Fb will be explained. Figure 43 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3Fb. In Figure 43, a cross-sectional structure of a portion of the semiconductor memory device 3Fb (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0210] As shown in Figure 43, in the laminate SB, the Z2 direction end face of the conductor LI is located lower than the Z2 direction end faces of the core member 50 and the semiconductor film 51. The cross-sectional structure outside the laminate SB is the same as that shown in Figure 29 of the second variation of the third embodiment.

[0211] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 44 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 43.

[0212] As shown in Figure 44, the cross-sectional structure of the laminate SB is the same as that shown in Figure 30 of the second variation of the third embodiment, except that the end face of the conductor LI is located lower than the end face of the core member 50 and the semiconductor film 51 in the Z2 direction. That is, the cross-sectional structures of each of the semiconductor layer 31a, the insulating layer 48, the semiconductor layer 31b, the conductor layer 32a, and the conductor layer 32b are the same as those shown in Figure 30 of the second variation of the third embodiment.

[0213] 7.5.2 Manufacturing method of semiconductor memory device The manufacturing method of the semiconductor memory device 3Fb is explained.

[0214] First, similar to the fifth embodiment, a component SLT is formed until the natural oxide film on the second surface of the conductive layer 30 after the delaminated film 52 is removed. Thus, similar to the fifth embodiment, the structure shown in FIG36 is formed.

[0215] Subsequently, similar to the second variation of the third embodiment, the following steps are performed: removal of the native oxide film on the second surface of the conductive layer 30, formation of the insulating layer 49, removal of the insulating layer 49, formation of the semiconductor layer 31a, heat treatment, formation of the insulating layer 48, formation of the semiconductor layer 31b, introduction of impurities, heat treatment, removal of the native oxide film on the second surface of the semiconductor layer 31a, formation of the conductive layer 32a, and formation of the conductive layer 32b. This forms the structure shown in FIG44.

[0216] 7.5.3 Effects of this variation According to this variation, it achieves the same effect as the second variation of the third implementation.

[0217] 8. Eighth Implementation Form The semiconductor memory device of embodiment 8 will be described. In the semiconductor memory device 3G of this embodiment, the structure of the multilayer SB and the insulator SW differs from that of embodiment 4. Hereinafter, the description will focus on the differences from embodiment 4.

[0218] 8.1 Cross-sectional structure of the entire semiconductor memory device Using Figure 45, the cross-sectional structure of the entire semiconductor memory device 3G will be explained. Figure 45 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3G. In Figure 45, a cross-sectional structure of a portion of the semiconductor memory device 3G (corresponding to the memory region MR of the array chip 100 and the region of the memory region MR of the circuit chip 200) is shown.

[0219] As shown in Figure 45, in the laminate SB, the end face of the conductor LI in the Z2 direction is covered by the spacer SP. The cross-sectional structure of the laminate SB and the insulator SW (described later) is the same as that shown in Figure 31 in the fourth embodiment.

[0220] Next, details of the cross-sectional structure of the laminated body SB and its vicinity will be described. Figure 46 is an enlarged cross-sectional view of a portion (region R1) of the laminated body SB in Figure 45.

[0221] As shown in Figure 46, the cross-sectional structure of the laminate SB and the insulator SW is the same as that shown in Figure 32 of the fourth embodiment, except for the point where the end face of the conductor LI in the Z2 direction is covered by the spacer SP. That is, the cross-sectional structure of the conductor layer 32a, the conductor layer 32b, and the insulator 46 is the same as that shown in Figure 32 of the fourth embodiment.

[0222] 8.2 Manufacturing method of semiconductor memory device The manufacturing method of semiconductor memory device 3G is explained.

[0223] First, similar to the fifth embodiment, a component SLT is formed until the natural oxide film on the second surface of the conductive layer 30 after the delaminated film 52 is removed. Thus, the structure shown in FIG36 is formed, similar to the fifth embodiment.

[0224] Subsequently, the removal of the natural oxide film on the second surface of the conductive layer 30, the formation of the conductive layer 32a, and the formation of the conductive layer 32b are performed in the same manner as in the fourth embodiment. This results in the structure shown in FIG46.

[0225] 8.3 Effects of this implementation According to this embodiment, it achieves the same effect as the fourth embodiment.

[0226] 9. Examples of variations, etc. As described above, the semiconductor memory device (3) of the embodiment includes: a substrate (71); a stacked body (SB) disposed above the substrate in a first direction (Z2); a first conductive layer (33 / 34 / 35) disposed between the substrate and the stacked body; a memory pillar (MP) comprising a semiconductor film (51) and extending in the first direction through the first conductive layer; and a first member (SLT) disposed spaced from the memory pillar in a second direction (Y) intersecting the first direction and extending in the first direction through the first conductive layer. The stacked body (SB) has a structure formed by sequentially stacking a first semiconductor layer (31a), a second semiconductor layer (31b), a second conductive layer (32a), and a third conductive layer (32b) from the substrate (71) side. The first semiconductor layer (31a) covers the end of the semiconductor film (51) in the first direction (Z2) and the end of the first component (SLT) in the first direction.

[0227] Furthermore, the implementation form is not limited to the form described above, and various variations are possible.

[0228] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and similarly within the scope of the invention described in the patent application and its equivalents.

[0229] 1: Memory System 2: Memory controller 3,3A,3B,3Ba,3Bb,3C,3D,3E,3F,3Fa,3Fb,3G: Semiconductor memory devices 10: Memory Cell Array 11: Instruction Register 12: Address Register 13: Sequencer 14: Driver Module 15: Column Decoder Module 16: Sensing Amplifier Module 30: Conductor layer 31, 31a, 31b: Semiconductor layers 32a, 32b: Conductor layers 33~38: Conductor layer 40~45: Insulating layer 46: Insulator 47, 48: Insulating layer 49: Insulating layer 50: Core Components 51: Semiconductor film 52: Laminated film 53: Tunnel insulation film 54: Insulating film 55: Barrier insulating film 61, 62: Insulating layer 71,72: Semiconductor substrate 100: Array chip 101~104: Conductor layer 200: Circuit chip 201~206: Conductor layer ADD: address BAd: Block Address BL: Bitline BL0~BLm: Bit lines BLK: block BLK0~BLKn: blocks BP: Bonding pad CAd: row address CMD command CU: Unit Group CV: contact DAT: Write Data EF: End face GB: Grain boundary HR: Leading Region IP: Inclined section IPa: Inclined section IPb: Inclined portion LI: Conductor MP: Memory Column MR: Memory Region MT0~MT7: Memory Cell Electron NS: NAND string PAd: Page address R1: Region RP: Depression SB: Stacked body SGD: Select Gate Line SGD0~SGD4: Select gate line SGS: Select Gate Line SHE: Component SL: Source Line SLT: Component SP: Spacer ST1: Select Transistor ST2: Select Transistor SU0~SU4: Serial units SW: Insulator TR1: Transistor WL0~WL7: Character lines X: Direction Y: direction Z1: Direction Z2: Direction

Claims

1. A semiconductor memory device comprising: a substrate; a laminate disposed above the substrate in a first direction; a first conductor layer disposed between the substrate and the laminate; a memory pillar comprising a semiconductor film extending in the first direction and penetrating the first conductor layer; and a first member disposed spaced apart from the memory pillar in a second direction intersecting the first direction, extending in the first direction and penetrating the first conductor layer; wherein the laminate has a structure formed by sequentially stacking a first semiconductor layer, a second semiconductor layer, a second conductor layer, and a third conductor layer from the substrate side; the first semiconductor layer covers the end portion of the semiconductor film in the first direction and the end portion of the first member in the first direction.

2. The semiconductor memory device of claim 1, wherein the grain boundary of the first semiconductor layer and the grain boundary of the second semiconductor layer are discontinuous.

3. The semiconductor memory device of claim 2, wherein the grain size of the first semiconductor layer is different from the grain size of the second semiconductor layer.

4. The semiconductor memory device of claim 3, wherein the grain size of the first semiconductor layer is smaller than the grain size of the second semiconductor layer.

5. The semiconductor memory device of claim 2, wherein the stacked body has a structure in which an insulating layer is disposed between the first semiconductor layer and the second semiconductor layer.

6. The semiconductor memory device of claim 5, wherein the insulating layer is an oxide film or a nitride film.

7. The semiconductor memory device of claim 1, further comprising: a fourth conductor layer disposed between the first conductor layer and the laminate, spaced apart from the first conductor layer in the first direction and connected to the first semiconductor layer; and the first member comprising a conductor and a first insulator covering the side surface of the conductor in the second direction and the end face of the conductor in the first direction; the end face of the first insulator in the first direction having an inclined portion on the side not connected to the conductor; the inclined portion being connected to the first semiconductor layer and being connected to the fourth conductor layer at a position lower than the upper surface of the fourth conductor layer in the first direction.

8. The semiconductor memory device of claim 7, wherein the first insulator comprises a second insulator covering the side surface of the conductor in the second direction and the end face of the conductor in the first direction, and a third insulator covering the side surface of the second insulator in the second direction.

9. The semiconductor memory device of claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise polysilicon.

10. The semiconductor memory device of claim 1 further comprises: a first wafer including the substrate; and a second wafer including the laminate, the first conductor layer, the memory pillar and the first member; and having a structure in which the second wafer is bonded to the first wafer.

11. The semiconductor memory device of claim 1, wherein the semiconductor memory device is a NAND flash memory.

12. A semiconductor memory device comprising: a substrate; a laminate disposed above the substrate in a first direction; a first conductor layer disposed between the substrate and the laminate; a memory pillar comprising a semiconductor film extending in the first direction and penetrating the first conductor layer; and a first member disposed spaced apart from the memory pillar in a second direction intersecting the first direction, extending in the first direction and penetrating the first conductor layer; wherein the laminate has a structure formed by sequentially stacking the first semiconductor layer, the second conductor layer, and the third conductor layer from the substrate side; the first member comprising a conductor and a first insulator covering the side surface of the conductor in the second direction; the first semiconductor layer covering the end portion of the semiconductor film in the first direction and the end portion of the conductor in the first direction.

13. The semiconductor memory device of claim 12, further comprising: a fourth conductor layer disposed between the first conductor layer and the laminate, spaced apart from the first conductor layer in the first direction and connected to the first semiconductor layer; and the end face of the first insulator in the first direction being located lower than the upper surface of the conductor in the first direction and the upper surface of the fourth conductor layer in the first direction; the side surface of the end face of the conductor in the first direction and the end face of the first insulator in the first direction being connected to the first semiconductor layer.

14. The semiconductor memory device of claim 13, wherein the stacked body has a structure in which a second semiconductor layer is disposed between the first semiconductor layer and the second conductor layer.

15. The semiconductor memory device of claim 14, wherein the stacked body has a structure in which an insulating layer is disposed between the first semiconductor layer and the second semiconductor layer.

16. The semiconductor memory device of claim 12, wherein the first semiconductor layer comprises polysilicon.

17. A semiconductor memory device comprising: a substrate; a laminate disposed above the substrate in a first direction; a first conductor layer disposed between the substrate and the laminate; a memory pillar comprising a semiconductor film extending in the first direction and penetrating the first conductor layer; and a first member disposed spaced apart from the memory pillar in a second direction intersecting the first direction, extending in the first direction and penetrating the first conductor layer; wherein the laminate has a structure formed by sequentially stacking a second conductor layer and a third conductor layer from the substrate side; the second conductor layer covers the end portion of the semiconductor film in the first direction and the end portion of the first member in the first direction.

18. The semiconductor memory device of claim 17, further comprising: a fourth conductor layer disposed between the first conductor layer and the laminate, spaced apart from the first conductor layer in the first direction and connected to the second conductor layer; and the first member comprising a conductor and a first insulator covering the side surface of the conductor in the second direction and the end face of the conductor in the first direction; the end face of the first insulator in the first direction having an inclined portion on the side not connected to the conductor; the inclined portion being connected to the second conductor layer and being connected to the fourth conductor layer at a position lower than the upper surface of the fourth conductor layer in the first direction.

19. The semiconductor memory device of claim 18, wherein the first insulator comprises a second insulator covering the side surface of the conductor in the second direction and the end face of the conductor in the first direction, and a third insulator covering the side surface of the second insulator in the second direction.

20. The semiconductor memory device of claim 17, wherein the second conductive layer comprises titanium or titanium nitride; and the third conductive layer comprises tungsten.