Semiconductor memory devices
The semiconductor memory device improves yield and efficiency by employing a laminate structure with optimized conductive and semiconductor layers to enhance bonding and electrical connectivity in memory cell arrays, addressing existing challenges in construction and integration.
TWI933368BActive Publication Date: 2026-07-21KIOXIA CORP
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Patent Information
- Application Number
- TW114107174
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2024-09-04
- Filing Date
- 2025-02-26
- Publication Date
- 2026-07-21
- Estimated Expiration
- 2045-02-25
AI Technical Summary
Technical Problem
Existing semiconductor memory devices face challenges in improving yield and efficiency, particularly in the construction and integration of memory cell arrays.
Method used
The semiconductor memory device incorporates a laminate structure with a specific arrangement of conductive and semiconductor layers, including memory pillars and members, to enhance the bonding and electrical connectivity of memory cell arrays, thereby improving yield and performance.
Benefits of technology
The proposed structure enhances the yield and efficiency of semiconductor memory devices by optimizing the bonding and electrical connectivity of memory cell arrays, leading to improved data storage capabilities.
✦ Generated by Eureka AI based on patent content.
Abstract
This invention provides a semiconductor memory device that can improve yield. One embodiment of the semiconductor memory device includes: a substrate; a laminate disposed above the substrate in a first direction; a first conductive layer disposed between the substrate and the laminate; a memory pillar comprising a semiconductor film extending in the first direction and penetrating the first conductive layer; and a first member disposed spaced from the memory pillar in a second direction intersecting the first direction, extending in the first direction and penetrating the first conductive layer. The laminate has a structure formed by sequentially stacking a first semiconductor layer, a second semiconductor layer, a second conductive layer, and a third conductive layer from the substrate side. The first semiconductor layer covers the first-direction end of the semiconductor film and the first-direction end of the first member.
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