Semiconductor device with dielectric thermal conductor

Abstract

The present invention provides a semiconductor device. The semiconductor device includes a back-side power distribution network (BSPDN), a high thermal conductivity dielectric layer, a heat sink, and a heat transfer pillar. The heat transfer pillar is connected to the high thermal conductivity dielectric layer and extends to the heat sink.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device and the resulting structure. More specifically, this disclosure relates to a method for manufacturing a semiconductor device having a back-side power distribution network and a heat dissipation structure. Prior Technology

[0002] Generally, power delivery networks for semiconductor devices are designed to provide power and reference voltage to active devices on the wafer. Traditionally, a power delivery network may comprise a network of metal lines fabricated through back-end-of-line (BEOL) processing on the front side of the wafer. This space is shared by the power delivery network and interconnects designed to transmit signals. Semiconductor devices may include a front-end-of-line (FEOL) area, a middle-of-line (MOL) area, and a BEOL area. Generally, the FEOL is the first part of the fabrication of an integrated circuit (IC) in which individual components (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor. The FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. The back-end-of-line (BEOL) area is the second part of the fabrication of the IC, where individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer. Generally, MOL refers to a set of wafer processing steps used to create structures that provide local electrical connections between transistors (primarily gate contact formation), and these processing steps occur after FEOL (transistor finite element online) and before BEOL (wired online) processes. BEOL processing typically begins when the first metal layer is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for wafer-to-package connections.

[0003] The layers in the FEOL region include transistors that generate a large amount of heat. In order to maintain the proper operating temperature of these various transistors, it is necessary to effectively transfer the generated heat from these devices to, for example, a cooling module. Summary of the Invention

[0004] The embodiments disclosed herein relate to a semiconductor device. The semiconductor device includes a backside power distribution network (BSPDN), a high thermal conductivity dielectric layer, a heat sink, and a heat transfer pillar. The heat transfer pillar is connected to the high thermal conductivity dielectric layer and extends to the heat sink.

[0005] The embodiments disclosed herein relate to an electronic device. The electronic device includes a semiconductor device. The semiconductor device includes a back-side power distribution network (BSPDN), a high thermal conductivity dielectric layer, a heat sink, and a heat transfer pillar. The heat transfer pillar is connected to the high thermal conductivity dielectric layer and extends to the heat sink.

[0006] The embodiments disclosed herein relate to a semiconductor device. The semiconductor device includes a back-side power distribution network (BSPDN), a front-end process (FEOL) region on the BSPDN, a mid-end process / back-end process (MOL / BEOL) region on the FEOL region, a heat sink on the MOL / BEOL region, a high thermal conductivity dielectric layer, and a heat transfer pillar. The heat transfer pillar is connected to the high thermal conductivity dielectric layer and extends to the heat sink.

[0007] The above overview is not intended to describe each of the illustrated embodiments or implementations of this disclosure. Simple Explanation of the Diagram

[0008] The drawings included in this application are incorporated in and form part of the specification. The drawings illustrate embodiments of the present disclosure and, together with the specification, explain the principles of the disclosure. The drawings illustrate only certain embodiments and do not limit the scope of the disclosure.

[0009] Figure 1A is a cross-sectional view of a semiconductor device at an intermediate stage of the manufacturing process, taken along line X1-X2 of Figure 1B according to an embodiment.

[0010] Figure 1B is a simplified top view of the semiconductor device of Figure 1A according to an embodiment.

[0011] Figure 1C is a cross-sectional view of the semiconductor device of Figure 1A taken along line Y1-Y2 of Figure 1B according to an embodiment.

[0012] Figure 2A is a cross-sectional view of the semiconductor device of Figure 1A taken along line X1-X2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0013] Figure 2B is a cross-sectional view of the semiconductor device of Figure 1C taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0014] Figure 3A is a cross-sectional view of the semiconductor device of Figure 2A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0015] Figure 3B is a cross-sectional view of the semiconductor device of Figure 2B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0016] Figure 4A is a cross-sectional view of the semiconductor device of Figure 3A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0017] Figure 4B is a cross-sectional view of the semiconductor device of Figure 3B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0018] Figure 5A is a cross-sectional view of the semiconductor device of Figure 4A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0019] Figure 5B is a cross-sectional view of the semiconductor device of Figure 4B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0020] Figure 6A is a cross-sectional view of the semiconductor device of Figure 5A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0021] Figure 6B is a cross-sectional view of the semiconductor device of Figure 5B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0022] Figure 7A is a cross-sectional view of the semiconductor device of Figure 6A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0023] Figure 7B is a cross-sectional view of the semiconductor device of Figure 6B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0024] Figure 8A is a cross-sectional view of the semiconductor device of Figure 7A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0025] Figure 8B is a cross-sectional view of the semiconductor device of Figure 7B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0026] Figure 9A is a cross-sectional view of the semiconductor device of Figure 8A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0027] Figure 9B is a cross-sectional view of the semiconductor device of Figure 8B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0028] Figure 10A is a cross-sectional view of the semiconductor device of Figure 9A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0029] Figure 10B is a cross-sectional view of the semiconductor device of Figure 9B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0030] Figure 11A is a cross-sectional view of the semiconductor device of Figure 10A taken along line X1-X2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0031] Figure 11B is a cross-sectional view of the semiconductor device of Figure 10B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0032] Figure 12A is a cross-sectional view of the semiconductor device of Figure 11A taken along line X1-X2 of Figure 1B after additional manufacturing operations, according to an embodiment.

[0033] Figure 12B is a cross-sectional view of the semiconductor device of Figure 11B taken along line Y1-Y2 of Figure 1B after additional manufacturing operations according to an embodiment.

[0034] Figure 13A is a cross-sectional view of a semiconductor device taken along line X1-X2 of Figure 1B according to an embodiment, wherein a high thermal conductivity dielectric layer is formed as a planar layer on the interlayer dielectric layer.

[0035] Figure 13B is a cross-sectional view of the semiconductor device of Figure 13A taken along line Y1-Y2 of Figure 1B according to an embodiment.

[0036] Figure 14A is a cross-sectional view of a semiconductor device taken along line X1-X2 of Figure 1B according to an embodiment, wherein a high thermal conductivity dielectric layer is formed as a planar layer on the bottom interlayer dielectric layer.

[0037] Figure 14B is a cross-sectional view of the semiconductor device of Figure 14A taken along line Y1-Y2 of Figure 1B according to an embodiment.

[0038] Figure 15A is a cross-sectional view of a semiconductor device according to an embodiment, showing a high thermal conductivity dielectric layer in contact with a vertical heat transfer column.

[0039] Figure 15B is a cross-sectional view of a semiconductor device according to an embodiment, showing a high thermal conductivity dielectric layer in contact with a vertical heat transfer column.

[0040] Figure 15C is a cross-sectional view of a semiconductor device according to an embodiment, showing a high thermal conductivity dielectric layer in contact with a vertical heat transfer column.

[0041] Figure 15D is a cross-sectional view of a semiconductor device according to an embodiment, showing a high thermal conductivity dielectric layer in contact with a vertical heat transfer column.

[0042] Figure 15E is a cross-sectional view of a semiconductor device according to an embodiment, showing a high thermal conductivity dielectric layer in contact with a vertical heat transfer column. Implementation

[0043] The flowcharts and cross-sectional views in the figures illustrate methods of manufacturing a semiconductor device according to various embodiments. In some alternative embodiments, the manufacturing steps may occur in a different order than that indicated in the figures, and certain additional manufacturing steps may be performed between the steps mentioned in the figures. Furthermore, any of the layered structures depicted in the figures may contain multiple sublayers.

[0044] Various embodiments of this disclosure are described herein with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of this disclosure. It should be noted that various connections and positional relationships (e.g., above, below, adjacent, etc.) are described in the following description and between the elements in the drawings. Unless otherwise specified, such connections and / or positional relationships may be direct or indirect, and this disclosure is not intended to be restrictive in this regard. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, referring to the present description, a layer "A" is formed above layer "B" including one or more intermediate layers (e.g., layer "C") located between layer "A" and layer "B," provided that the relevant characteristics and functions of layers "A" and "B" are not substantially altered by the intermediate layers.

[0045] The following definitions and abbreviations are used to interpret the scope of the patent application and this specification. As used herein, the terms "comprises / comprising," "includes / including," "has / having," "contains or containing," or any other variations thereof are intended to cover non-exclusive inclusions. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to the composition, mixture, process, method, article, or apparatus.

[0046] For the purposes of the description below, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall be oriented as shown in the accompanying drawings and relating to the described structure and method. The terms "overlapping," "on top of," "on the top of," "located on," or "located on top of" mean that a first element, such as a first structure, exists on a second element, such as a second structure, wherein an intervening element, such as an interface structure, may exist between the first and second elements. The term "direct contact" means that the first element, such as a first structure, and the second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer. It should be noted that the term "selective towards," such as "the first element is selective towards the second element," means that the first element can be etched, and the second element can act as an etching terminator.

[0047] For the sake of brevity, known techniques related to semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and procedural steps described herein may be incorporated into more comprehensive procedures or processes with additional steps or functionalities not described in detail herein. Specifically, the various steps involved in manufacturing semiconductor devices and semiconductor-based ICs are well-known, and therefore, for the sake of brevity, many known steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0048] Generally, the various processes used to form microchips to be packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from the wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP) and similar processes. Semiconductor doping modifies electrical properties by doping, for example, transistor sources and drains, generally by diffusion and / or by ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopant. Films of both conductors (e.g., polycrystalline silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by applying voltage. By creating the structures of these various components, millions of transistors can be built and wired together to form the complex circuit systems of modern microelectronic devices. Semiconductor lithography forms a three-dimensional raised image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called photoresist. To construct the complex structure of the transistors and the numerous wires of the millions of transistors that connect the circuits, the lithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built in to form the final device.

[0049] Turning to a more specific overview of the techniques related to the present disclosure, metal-oxide-semiconductor field-effect transistors (MOSFETs) are used to amplify or switch electronic signals. A MOSFET has a source electrode, a drain electrode, and a metal-oxide-semiconductor gate electrode. The metal gate portion of the metal-oxide-semiconductor gate electrode is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material (such as silicon dioxide or glass), which results in a relatively high input resistance for the MOSFET. The gate voltage controls whether the current path from the source to the drain is open ("disconnected") or resistive ("connected"). n-type field-effect transistors (nFETs) and p-type field-effect transistors (pFETs) are two types of complementary MOSFETs. An nFET includes an n-doped source and drain junction and uses electrons as current carriers. A pFET includes a p-doped source and drain junction and uses holes as current carriers. Complementary metal-oxide-semiconductor (CMOS) is a technique that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. As mentioned above, the hole mobility on a pFET can affect the overall device performance.

[0050] The wafer footprint of a FET is related to the conductivity of the channel material. If the channel material has relatively high conductivity, the FET can be fabricated with a correspondingly smaller wafer footprint. A known method to increase channel conductivity and reduce FET size is to form nanostructured channels. For example, the so-called gate-all-around (GAA) nanosheet FET is a known architecture used to provide a relatively small FET footprint by forming the channel region as a series of nanosheets. In a known GAA configuration, the nanosheet-based FET includes a source region, a drain region, and a stacked nanosheet channel between the source and drain regions. Semiconductor nanosheet FET devices typically include one or more suspended nanosheets acting as channels. The gate surrounds the stacked nanosheet channel and modulates the electron flow through the nanosheet channel between the source and drain regions. GAA nanosheet FETs are fabricated by forming alternating layers of channel nanosheets and sacrificial nanosheets. The sacrificial nanosheets are released from the channel nanosheets before the FET device is completed. For n-type FETs, the channel nanosheet is typically silicon (Si) and the sacrificial nanosheet is typically silicon germanium (SiGe). For p-type FETs, the channel nanosheet can be SiGe and the sacrificial nanosheet can be Si. In some implementations, the channel nanosheet of a p-type FET can be either SiGe or Si, and the sacrificial nanosheet can be either Si or SiGe. Alternating layers of channel nanosheets formed from first-type semiconductor materials (e.g., Si for n-type FETs and SiGe for p-type FETs) and sacrificial nanosheets formed from second-type semiconductor materials (e.g., SiGe for n-type FETs and Si for p-type FETs) form GAA nanosheets, providing excellent channel electrostatic control that can help continuously reduce gate lengths to seven (7) nanometer CMOS technology and below.

[0051] In some semiconductor devices, a front-side power distribution network (FSPDN) can be used, and the FSPDN is formed on the front side of the semiconductor wafer. In other instances, a back-side power distribution network (BSPDN) can be used. Generally, BSPDN allows for the decoupling of the power delivery network from the signal network by moving the entire power distribution network to the back side of the silicon wafer rather than the front side (i.e., as in an FSPDN). However, BSPDN can have increased thermal resistance (e.g., about 15%) compared to FSPDN, which can make it more difficult to transfer heat out of the device. Therefore, it may be necessary to improve the effectiveness and efficiency of heat transfer in semiconductor devices utilizing BSPDN.

[0052] Referring now to the figures, where the same numbers represent the same or similar elements, and first referring to Figures 1A, 1B, and 1C, Figure 1A is a cross-sectional view of the semiconductor device 100 at an intermediate stage of the manufacturing process, taken along line X1-X2 of Figure 1B; Figure 1B is a simplified top view of the semiconductor device 100 of Figure 1A; and Figure 1C is a cross-sectional view of the semiconductor device 100 of Figure 1A taken along line Y1-Y2 of Figure 1B. As shown in Figures 1A and 1C, according to an embodiment, the semiconductor device 100, including a nanosheet stack NS, is shown at an intermediate stage of the manufacturing process. The simplified top view of Figure 1B shows the overall layout of the active region 196 and the channel region 198 of the semiconductor device 100.

[0053] As shown in Figures 1A and 1C, a substrate 102 is provided. The substrate 102 may be a bulk semiconductor substrate. In one example, the bulk semiconductor substrate may be a silicon-containing material. Illustrative examples of silicon-containing materials suitable for bulk semiconductor substrates include, but are not limited to, silicon, germanium silicon, germanium silicon carbide, silicon carbide, polycrystalline silicon, epitaxial silicon, amorphous silicon, and multilayers thereof. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials may be used, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide. Although not depicted in the figures of this invention, the semiconductor substrate 102 may also be a semiconductor-on-insulator (SOI) substrate. The substrate 102 may be constructed from any other suitable material besides those listed above.

[0054] As shown in Figures 1A and 1C, a temporary sacrificial layer 105 is formed on substrate 102. This temporary sacrificial layer 105 will later be removed and replaced by a bottom dielectric isolation (BDI) layer 104 shown in Figures 2A and 2B. The nanosheet stack NS includes alternating layers of sacrificial layers 106 and semiconductor layers 108. The bottom nanosheet stack NS initially includes a sacrificial layer 106 formed on the BDI layer 104, followed by the formation of the semiconductor layer 108. In one example, the sacrificial layer 106 is composed of silicon germanium (e.g., SiGe, or more generally, where Ge is in the range of about 15% to 35%). Furthermore, a first (or bottommost) semiconductor layer 108 is formed on the upper surface of the first of the sacrificial layers 106. In the example illustrated in Figures 1A and 1C, there are a total of three sacrificial layers 106 and three active semiconductor layers 108 alternately formed to form the nanosheet stack 103. However, it should be understood that any suitable number of alternating layers can be formed. While it is specifically considered that the sacrificial layer 106 can be formed of silicon-germanium and the active semiconductor layer 108 can be formed of silicon, it should be understood that any suitable materials can be used alternatively, provided that the two semiconductor materials have etch selectivity relative to each other. As used herein, the term "selectivity" in the context of material removal processes refers to a rate of material removal for the first material that is greater than the rate of removal for at least another material of the structure to which the material removal process is applied. The alternating semiconductor materials can be deposited by any suitable mechanism. It is specifically considered that the first and second semiconductor materials (i.e., the first and second semiconductor materials of the sacrificial layer 106 and the active semiconductor layer 108) can be epitaxially grown together, but alternative deposition processes such as CVD, PVD, ALD, or gas cluster ion beam (GCIB) deposition are also considered.

[0055] In some embodiments, the sacrificial layer 106 has a vertical thickness, for example, ranging from approximately 3 nm to approximately 20 nm. In some embodiments, the semiconductor layer 108 has a vertical thickness, for example, ranging from approximately 3 nanometers (nm) to approximately 10 nm. Although the range of 3 nm to 20 nm is cited as an example range of thicknesses, other thicknesses of these layers may be used. In some instances, one of the sacrificial layer 106 and / or the semiconductor layer 108 may have different thicknesses relative to each other. Therefore, multiple epitaxial growth processes may be performed to form the sacrificial layer 106 and the semiconductor layer 108.

[0056] In some embodiments, a small vertical spacing (VSP) between adjacent nanosheets in a nanosheet stack NS may be required to reduce parasitic capacitance and improve circuit speed. For example, the VSP (the distance between the bottom surface of the first nanosheet and the top surface of the adjacent second nanosheet) can be in the range of 5 nm to 15 nm. However, the VSP must have a sufficient value to accommodate the gate stack that will be formed in the space created by later removal of the sacrificial layer 106.

[0057] Referring now to Figures 2A and 2B, Figure 2A is a cross-sectional view of the semiconductor device 100 of Figure 1A taken along line X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 2B is a cross-sectional view of the semiconductor device 100 of Figure 1C taken along line Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figures 2A and 2B, the temporary sacrificial layer 105 is removed by any suitable material removal process and replaced with a bottom dielectric isolation layer 104. The bottom dielectric isolation layer 104 may comprise one or more insulating materials, such as low-k materials, silicon nitride (SiN), silicon boron carbonitride (SiBCN), silicon carbonitride oxynitride (SiOCN), silicon oxynitride (SiON), silicon carbide (SiC), and / or the like. However, it should be understood that the BDI layer 104 may comprise other suitable materials. Furthermore, in some embodiments, the BDI layer 104 may be omitted. Furthermore, the nanosheet stack NS patterning process is performed using any suitable combination of hard masking (not shown) and lithography and material removal operations. During the nanosheet patterning process, any suitable material removal process (e.g., reactive ion etching (RIE)) can be used to remove the individual layers of the nanosheet stack NS down to the level of the bottom dielectric isolation layer 104. The hard mask is removed after the patterning process used for the nanosheet stack 103 (e.g., all sacrificial layers 106 and semiconductor layer 108).

[0058] As shown in Figures 2A and 2B, a dummy gate 114 (or sacrificial gate) is formed on top of a nanosheet stack NS using any suitable deposition and / or patterning process known to those skilled in the art. In one example, the dummy gate 114 is formed by depositing a thin SiO2 dummy gate oxide layer (or sacrificial oxide layer), followed by depositing an amorphous silicon (a-Si) layer as the dummy gate 114. The dummy gate 114 can be made of polycrystalline silicon, amorphous silicon, and / or oxides (such as SiO2). A gate hard mask (not shown) can also be formed on the top side of the dummy gate 114. The gate hard mask can be formed for subsequent nanosheet patterning. The gate hard mask can be made of various nitride materials, including but not limited to nitrides, oxides, silicon nitride (SiN), and / or combinations of nitride and oxide materials. In some embodiments, as shown in FIG2A, the dummy gate 114 extends into and out of the page to surround the edge of the nanosheet stack NS, and the subsequent removal of the dummy gate 114 (see FIG6A and FIG6B) provides an access point for the later removal of the sacrificial layer 106.

[0059] As shown in Figure 2A, spacer 116 (or spacer layer, or gate spacer) is formed on the sidewall of the patterned dummy gate 114. In some instances, spacer 116 is formed to cover the topmost active semiconductor layer 108 of the nanosheet stack NS. Subsequently, the semiconductor device 100 undergoes a directional reactive ion etching (RIE) process, which selectively removes portions of the sacrificial layer 106. RIE may use boron-based or chlorine-based chemicals, for example, which selectively recess the exposed portions of the sacrificial layer 106 without significantly removing the active semiconductor layer 108. Thus, portions of the sacrificial layer 106 are recessed in the inward direction (i.e., an internal spacer indentation process), such that the processed width of the sacrificial layer 106 is smaller than the width of the active semiconductor layer 108.

[0060] As shown in Figure 2A, internal spacers 110 are added to the recesses previously formed in the sacrificial layer 106. In some embodiments, after forming the internal spacers 110, an isotropic etching process is performed to create the outer vertical edges of the internal spacers 110 aligned with the outer vertical edges of the active semiconductor layer 108. In some embodiments, the material of the internal spacers 110 is a dielectric material, such as SiN, SiO, SiBCN, SiOCN, SiCO, etc.

[0061] As shown in Figure 2B, a nitride layer 118 and a shallow trench isolation (STI) layer 120 may be formed in the semiconductor substrate 102. Generally, shallow trench isolation is an integrated circuit feature that prevents current leakage between adjacent semiconductor device components. STI is commonly used in CMOS process technology nodes of 250 nanometers and smaller. The STI region 120 is created early in the semiconductor device manufacturing process, before the transistor is formed. The STI process involves etching a pattern of trenches in silicon, depositing one or more dielectric materials (such as the nitride layer 118 and the STI layer 120) to fill the trenches, and removing excess dielectric using techniques such as chemical mechanical planarization. Also as shown in Figure 2B, material for a dummy gate 114 is formed to cover the nanosheet stack NS.

[0062] Referring now to Figures 3A and 3B, Figure 3A is a cross-sectional view of the semiconductor device 100 of Figure 2A taken along line X1-X2 of Figure 1B, representing a later stage of the manufacturing process, and Figure 3B is a cross-sectional view of the semiconductor device 100 of Figure 2B taken along line Y1-Y2 of Figure 1B, representing a later stage of the manufacturing process. As shown in Figure 3A, a conformally deposited liner layer 122 covers the bottom dielectric isolation layer 104, the sidewalls of the nanosheet stack NS, and the exposed surfaces of the dummy gate 114 and spacers 116. It should be noted that in the cross-sectional view shown in Figure 3B, the liner layer 122 does not cover the sidewalls of the nanosheet stack NS or the bottom dielectric isolation layer 104, because these are already covered by the dummy gate 114. In some embodiments, the liner layer 122 may comprise one or more suitable oxide materials.

[0063] Referring now to Figures 4A and 4B, Figure 4A is a cross-sectional view of the semiconductor device 100 of Figure 3A taken along line X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 4B is a cross-sectional view of the semiconductor device 100 of Figure 3B taken along line Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figure 4A, a suitable material removal process (such as reactive ion etching (RIE)) is used to remove the horizontal portion of the liner layer 122 and create a placeholder trench 126, which is formed by removing the bottom dielectric isolation layer 104 and the portion of the substrate 102 not covered by the nanosheet stack NS. The placeholder trench 126 will allow for the subsequent formation of the placeholder layer 128.

[0064] Referring now to Figures 5A and 5B, Figure 5A is a cross-sectional view of the semiconductor device 100 of Figure 4A taken along line X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 5B is a cross-sectional view of the semiconductor device 100 of Figure 4B taken along line Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figure 5A, a placeholder layer 128 is formed in the previously formed placeholder trench 126. In some embodiments, the placeholder layer 128 may comprise SiGe. However, it should be understood that other suitable materials besides SiGe can be used for the placeholder layer 128. In this embodiment, the placeholder layer 128 is formed to approximately correspond to the height of the interface between the substrate 102 and the BDI layer 104. However, it should be understood that in other embodiments, the height of the placeholder layer 128 may be slightly higher or lower than the height shown in Figure 5A. As will be explained in more detail below, the placeholder layer 128 on the right side (i.e., the X2 side) of Figure 5A will be removed to allow for the formation of other structures, while the placeholder layer 128 on the left side (i.e., the X1 side) will not be removed. It should be understood that the placeholder layer 128 on the left side will not serve as an active component for enabling the semiconductor device 100 to function. In some instances, a silicon layer 130 is deposited on the placeholder layer. The silicon layer 130 may serve as a barrier layer between the placeholder layer 128 and the epitaxial layer. There is no difference between Figure 5B and Figure 4B.

[0065] As also shown in Figure 5A, an epitaxial layer 132 is formed to cover the sidewalls of the nanosheet stack NS. The epitaxial layer 132 forms a junction in the semiconductor device 100. In some embodiments, the epitaxial layer 132 may be a p-type or n-type source / drain epitaxial layer, and it is deposited by epitaxial growth methods up to at least the top level of the nanosheet stack NS (or slightly higher, as shown in Figure 5A). In some embodiments, the material of the epitaxial layer 124 may be, for example, Si-P or Si / P based. However, it should be understood that any other suitable material may be used.

[0066] As shown in Figure 5A, an interlayer dielectric (ILD) layer 134 is formed around the nanosheet stack NS up to the top of the dummy gate 114. In some instances, after the formation of the ILD layer 134, a planarization process such as CMP can be performed to create a planar surface for the semiconductor device 100. The ILD layer 134 can be any suitable material, such as porous silicates, carbon-doped oxides, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. Any known method can be used to form the ILD layer 134. The ILD layer 134 can be formed using, for example, CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, flowable CVD, spin-coated dielectric, or PVD.

[0067] Referring now to Figures 6A and 6B, Figure 6A is a cross-sectional view of the semiconductor device 100 of Figure 5A taken along line X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 6B is a cross-sectional view of the semiconductor device 100 of Figure 5B taken along line Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figures 6A and 6B, after the formation of the ILD layer 134, selective removal of the dummy gate 114 and the sacrificial layer 106 (i.e., the SiGe levitation layer) is performed, and these layers are replaced by the gate 136. The dummy gate 114 is removed by any suitable material removal process known to those skilled in the art. For example, this removal can be achieved by an etching process, which may include dry etching processes such as reactive ion etching, plasma etching, ion etching, or laser ablation. The etching may further include a wet chemical etching process, in which one or more chemical etchants are used to remove portions of the blanket layer that are not protected by the patterned photoresist. Subsequently, the sacrificial layer 106 is removed (or released).

[0068] Although not shown in Figures 6A and 6B, immediately after the removal of sacrificial layer 106, void spaces exist between the active semiconductor layers 108 due to the removal of sacrificial layer 106. It should be understood that during the removal of the dummy gate 114 and sacrificial layer 106, an appropriate etchant is used that selectively but not significantly removes material from the semiconductor layers 108, silicon layer 130, or internal spacers 110 of sacrificial layer 106 and dummy gate 114 (i.e., the etchant is selected to selectively remove material from dummy gate 114 and sacrificial layer 106). Dry and wet etching processes can have adjustable etching parameters, such as the etchant used, etching temperature, etch solution concentration, etching pressure, power supply, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. Dry etching processes may include bias plasma etching processes using chlorine-based chemicals. Other dry etchant gases may include carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), helium (He), and chlorine trifluoride (ClF3). Dry etching can also be performed anisotropically using mechanisms such as deep reactive ion etching (DRIE). Chemical vapor deposition (CVD) can be used as a selective etching method, and the etching gas may include hydrogen chloride (HCl), carbon tetrafluoride (CF4), or a mixture of gases containing hydrogen (H2). CVD can be performed by CVD under suitable pressure and temperature conditions.

[0069] Next, as shown in Figures 6A and 6B, a gate 136 (or gate electrode, or work function metal (WFM) layer) is formed in a void space created by previously removing the dummy gate 114 and sacrificial layer 106. In some embodiments, the gate 136 comprises a WFM material that can be a p-type or n-type material. The gate 136 may be made of a metal, such as copper (Cu), cobalt (Co), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), nitrides, or any combination thereof. The metal may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. In various exemplary embodiments, the height of the gate 136 may be reduced by CMP and / or etching. Thus, a planarization process can be provided by CMP. Other planarization processes may include grinding and polishing. Generally, the threshold voltage (Vth) of the metal material setting device for the work function of gate 136 can provide a high-κ gate dielectric material (not shown) that separates the WFM material of gate 136 from the semiconductor layer 108 of the nanosheet stack NS, and can use other metals that may require further fine-tuning of the effective work function (eWF) and / or achieve the desired resistance value associated with the current flowing through the gate stack in the direction of the parallel nanosheet plane. Therefore, gate 136, epitaxial layer 132, nanosheet stack NS, and various metal contacts form a nanosheet field-effect transistor (FET), which can be a p-type device or an n-type device.

[0070] Referring now to Figures 7A and 7B, Figure 7A is a cross-sectional view of the semiconductor device 100 of Figure 6A taken along line X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 7B is a cross-sectional view of the semiconductor device 100 of Figure 6B taken along line Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figures 7A and 7B, additional material is deposited on the ILD layer 134 to increase the thickness of the ILD layer 134 above the top surface of the gate 136. The additional material on the ILD layer 134 allows coverage of the top surface of the gate 136 and allows for subsequent metal contact formation. After the formation of the ILD layer 134, a trench (not shown) is formed in the ILD layer 134 using a suitable material removal process. Subsequently, as shown in Figure 7A, a first metal contact 140 (sometimes referred to as a CA contact) is formed on the epitaxial layer 132. Simultaneously, as shown in FIG7B, a second metal contact 141 (sometimes referred to as a CB contact) is formed on the gate 135. In the example shown in FIG8A, the first contact 140 is formed on the left side (i.e., the X1 side) of the semiconductor device 100, but not on the right side (i.e., the X2 side). This allows for the subsequent formation of a back-side contact connected to the epitaxial layer 132 on the right side after the placeholder layer 128 on the right side is removed. In subsequent processing steps, a back-end process (BEOL) layer 142 is formed on the ILD layer 134 and on the first metal contact 140 and the second metal contact 141. As mentioned above, the BEOL layer 142 (or BEOL region) is a second part of the IC fabrication for interconnecting individual devices (transistors, capacitors, resistors, etc.) with wiring on the wafer. Then, in some embodiments, a heat sink 144 (e.g., a wafer disposal) is attached to the semiconductor device 100 on top of the BEOL layer 142. Generally speaking, a heat sink refers to any suitable device or substance used to absorb excess or unwanted heat.

[0071] Referring now to Figures 8A and 8B, Figure 8A is a cross-sectional view of the semiconductor device 100 of Figure 7A taken along line X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 8B is a cross-sectional view of the semiconductor device 100 of Figure 7B taken along line Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figures 8A and 8B, substrate 102 is removed using any suitable material removal process (such as RIE). This temporarily exposes the placeholder layer 128 and the BDI layer 104. Next, a high thermal conductivity dielectric layer 150 is formed to cover the placeholder layer 128 and the BDI layer 104. The high thermal conductivity dielectric layer 150 may comprise, for example, hexagonal boron nitride (hBN), which is a stable crystalline form of boron nitride having a layered structure similar to graphite. hBN is known to have high thermal conductivity, but it also has insulating properties. Therefore, the high thermal conductivity dielectric layer 150 allows the insulating layer to be integrated into the device (which is crucial for preventing electrical short circuits between adjacent transistors), and the insulating layer can also effectively transfer heat away from the device. Although not shown in Figure 8A (the scale of the cross-sectional view in Figure 8A does not allow for its depiction), the high thermal conductivity dielectric layer 150 is connected to a heat transfer column (see heat transfer column 420 in Figures 15A to 15E), which in turn transfers heat upward toward the cooling module (see heat exchanger 410 in Figures 15A to 15E). As shown in Figure 8B, the high thermal conductivity dielectric layer 150 covers the nitride layer 118.

[0072] Referring now to Figures 9A and 9B, Figure 9A is a cross-sectional view of the semiconductor device 100 of Figure 8A taken along line X1-X2 of Figure 1B, which is in a later stage of the manufacturing process, and Figure 9B is a cross-sectional view of the semiconductor device 100 of Figure 8B taken along line Y1-Y2 of Figure 1B, which is in a later stage of the manufacturing process. As shown in Figures 9A and 9B, a bottom ILD layer 154 is formed on the high thermal conductivity dielectric layer 150.

[0073] Referring now to Figures 10A and 10B, Figure 10A is a cross-sectional view of the semiconductor device 100 of Figure 9A taken along line X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 10B is a cross-sectional view of the semiconductor device 100 of Figure 9B taken along line Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figure 10A, a suitable material removal process is used to form a back-side contact opening 178 in the bottom ILD layer 154. The back-side contact opening 178 is formed to a sufficient depth to expose a portion of the placeholder layer 128 on the right side (i.e., the X2 side) of the semiconductor device, as shown in Figure 10A. This material removal process also removes a portion of the high thermal conductivity dielectric layer 150 in the area where the placeholder layer 128 is exposed. This material removal step allows for the subsequent removal of the placeholder layer 128 on the right side, which will be replaced with a back-side contact.

[0074] Referring now to Figures 11A and 11B, Figure 11A is a cross-sectional view of the semiconductor device 100 of Figure 10A taken along lines X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 11B is a cross-sectional view of the semiconductor device 100 of Figure 10B taken along lines Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figure 11A, one or more suitable material removal processes are used to remove the upper right side occupier layer 128, the upper right side silicon layer 130, and a portion of the upper right side epitaxial layer 132. It should be understood that these different layers can be removed sequentially using two or more different material removal processes. Therefore, at this stage of the manufacturing process, the back side (or bottom side) of the upper right side epitaxial layer 132 is exposed to allow for the subsequent formation of back side contacts.

[0075] Referring now to Figures 12A and 12B, Figure 12A is a cross-sectional view of the semiconductor device 100 of Figure 11A taken along line X1-X2 of Figure 1B at a later stage of the manufacturing process, and Figure 12B is a cross-sectional view of the semiconductor device 100 of Figure 11B taken along line Y1-Y2 of Figure 1B at a later stage of the manufacturing process. As shown in Figure 12A, a back-side metal contact 154 (sometimes referred to as BSCA) is formed in contact with the epitaxial layer 132 on the upper right side. Thus, referring to the contact, Figure 12A shows a first contact 140 formed on the upper left side to contact the top surface of the epitaxial layer 132, and a back-side metal contact 154 formed on the lower right side of the epitaxial layer 132. Furthermore, the presence of a high thermal conductivity dielectric layer 150 allows for efficient heat transfer from various transistors within the context of a back-side power distribution network (BSPDN). As discussed above, the use of BSPDN in semiconductor device 100 can result in an increase in heat resistance of approximately 15% compared to semiconductor devices using front-side power distribution network (FSPDN). Therefore, the high thermal conductivity dielectric layer 150 allows for the implementation of BSPDN with enhanced heat transfer properties, thereby achieving better operating temperatures for various transistors used in the device.

[0076] Referring now to Figures 13A and 13B, Figure 13A is a cross-sectional view of a semiconductor device 200 similar to the semiconductor device shown in Figure 12A, but the placement of the high thermal conductivity dielectric layer 250 differs from that of the high thermal conductivity dielectric layer 150 shown in Figure 12A. The high thermal conductivity dielectric layer 250 may contain, for example, hBN, and may be made of the same material as the high thermal conductivity dielectric layer 150 shown in Figure 12A. As shown in Figure 13A, the high thermal conductivity dielectric layer 250 is located between the ILD layer 134 and the BEOL layer 142. This different placement of the high thermal conductivity dielectric layer 250 allows for increased manufacturing flexibility while still achieving effective heat transfer. It should be understood that the high thermal conductivity dielectric layer 250 shown in Figures 13A and 13B has a flat / planar shape, which is the opposite of the irregular non-planar profile of the high thermal conductivity dielectric layer 150 shown in Figures 1A to 12B, and follows the profile of several other layers (e.g., placeholder layer 128).

[0077] Referring now to Figures 14A and 14B, Figure 14A is a cross-sectional view of a semiconductor device 300 similar to the semiconductor device shown in Figure 12A, but the placement of the high thermal conductivity dielectric layer 350 differs from that of the high thermal conductivity dielectric layer 150 shown in Figure 12A. The high thermal conductivity dielectric layer 350 may contain, for example, hBN, and may be made of the same material as the high thermal conductivity dielectric layer 150 shown in Figure 12A. As shown in Figure 14A, the high thermal conductivity dielectric layer 350 is located on the bottom of the bottom ILD layer 154. This different placement of the high thermal conductivity dielectric layer 350 allows for increased manufacturing flexibility while still achieving effective heat transfer.

[0078] Referring now to Figure 15A, this figure is a simplified cross-sectional view of a semiconductor device 400 according to an embodiment, including a high thermal conductivity dielectric layer 450 contacting a vertical heat transfer column 420. As discussed above with respect to Figures 1A to 14B, the scale of those figures does not allow for a depiction of how the high thermal conductivity dielectric layer connects to the vertical heat transfer column, and therefore Figures 15A to 15E present simplified schematic diagrams illustrating these additional features. Therefore, the concepts described with respect to Figures 15A to 15E apply to any of the examples shown in Figures 1A to 14B.

[0079] As shown in Figure 15A, the semiconductor device 400 includes a back-side power distribution network (BSPDN) 402, a front-end process (FEOL) region 404 on the BSPDN 402, a mid-end process / back-end process (MOL / BEOL) region 406 on the FEOL region 404, a heat sink 408 on the MOL / BEOL region 406, and a heat exchanger 410 on the heat sink 408. It should be understood that the BSPDN 402, FEOL region 404, and MOL / BEOL region 406 may each include a plurality of separation layers. The heat exchanger 410 may be any suitable device (e.g., a cooling fan or fluid cooling mechanism) capable of transferring heat away from the semiconductor device 400. As shown in Figure 15A, the semiconductor device 400 also includes a high thermal conductivity dielectric layer 450 located within the FEOL region 404. The semiconductor device also includes heat transfer pillars 420 in contact with the high thermal conductivity dielectric layer 450. In this example, the heat transfer column 420 extends at least partially through the FEOL region 404, through the MOL / BEOL region 406, and at least partially through the heat sink 408. Therefore, effective heat transfer can be achieved by heat transfer from one or more heat sources through the high thermal conductivity dielectric layer 450, then through the heat transfer column 420, then through the heat sink 408 to the heat exchanger 410.

[0080] Referring now to Figure 15B, this figure is a simplified cross-sectional view of a semiconductor device 400 including a high thermal conductivity dielectric layer 450 with a contact heat transfer column 420 according to an embodiment. Figure 15B differs from Figure 15A in the location of the high thermal conductivity dielectric layer 450 and the height of the heat transfer column 420. As shown in Figure 15B, the semiconductor device 400 also includes a high thermal conductivity dielectric layer 450 located at the interface between the FEOL region 404 and the MOL / BEOL region 408. The semiconductor device also includes a heat transfer column 420 contacting the high thermal conductivity dielectric layer 450. In this example, the heat transfer column 420 extends through the MOL / BEOL region 406 and at least partially through the heat sink 408. Therefore, effective heat transfer can be achieved by heat transfer from one or more heat sources through the high thermal conductivity dielectric layer 450, then through the heat transfer column 420, and then through the heat sink 408 to the heat exchanger 410.

[0081] Referring now to FIG15C, this figure is a simplified cross-sectional view of a semiconductor device 400 including a high thermal conductivity dielectric layer 450 with a contact heat transfer column 420 according to an embodiment. FIG15C differs from FIG15A in the location of the high thermal conductivity dielectric layer 450 and the height of the heat transfer column 420. As shown in FIG15C, the semiconductor device 400 also includes a high thermal conductivity dielectric layer 450 located within a MOL / BEOL region 408. The semiconductor device also includes a heat transfer column 420 contacting the high thermal conductivity dielectric layer 450. In this example, the heat transfer column 420 extends through a portion of the MOL / BEOL region 406 and at least partially through the heat sink 408. Therefore, effective heat transfer can be achieved by heat transfer from one or more heat sources through the high thermal conductivity dielectric layer 450, then through the heat transfer column 420, and then through the heat sink 408 to the heat exchanger 410.

[0082] Referring now to FIG15D, this figure is a simplified cross-sectional view of a semiconductor device 400 including a high thermal conductivity dielectric layer 450 with contact heat transfer pillars 420 according to an embodiment. FIG15D differs from FIG15A in the location of the high thermal conductivity dielectric layer 450 and the height of the heat transfer pillars 420. As shown in FIG15D, the semiconductor device 400 also includes a high thermal conductivity dielectric layer 450 located at the interface between BSPDN 402 and FEOL region 404. The semiconductor device 400 also includes heat transfer pillars 420 contacting the high thermal conductivity dielectric layer 450. In this example, the heat transfer pillars 420 extend at least partially through BSPDN 402, through FEOL region 404, through MOL / BEOL region 406, and at least partially through heat sink 408. Therefore, effective heat transfer can be achieved by passing through one or more heat sources through the high thermal conductivity dielectric layer 450, then through the heat transfer column 420, and then through the heat sink 408 to the heat exchanger 410.

[0083] Referring now to Figure 15E, this figure is a simplified cross-sectional view of a semiconductor device 400 according to an embodiment, including a high thermal conductivity dielectric layer 450 contacting a vertical heat transfer column 420. Figure 15E differs from Figure 15A in the location of the high thermal conductivity dielectric layer 450 and the height of the heat transfer column 420. As shown in Figure 15D, the semiconductor device 400 also includes a high thermal conductivity dielectric layer 450 positioned within BSPDN 402 and FEOL region 404. The semiconductor device 400 also includes a heat transfer column 420 contacting the high thermal conductivity dielectric layer 450. In this example, the heat transfer column 420 extends at least partially through BSPDN 402, through FEOL region 404, through MOL / BEOL region 406, and at least partially through heat sink 408. Therefore, effective heat transfer can be achieved by passing through one or more heat sources through the high thermal conductivity dielectric layer 450, then through the heat transfer column 420, and then through the heat sink 408 to the heat exchanger 410.

[0084] Some embodiments disclosed herein may be in the form of a first semiconductor device. The semiconductor device includes a back-side power distribution network (BSPDN), a high thermal conductivity dielectric layer, a heat sink, and heat transfer pillars. The heat transfer pillars are connected to the high thermal conductivity dielectric layer and extend to the heat sink. This allows for efficient heat transfer within the semiconductor device utilizing the BSPDN.

[0085] In some examples of the first semiconductor device, the semiconductor device further includes a front-end process (FEOL) region on the BSPDN and a mid-end process / back-end process (MOL / BEOL) region on the FEOL region. For semiconductor devices including the BSPDN, a high thermal conductivity dielectric layer allows for efficient heat transfer.

[0086] In some examples of the first semiconductor device, a high thermal conductivity dielectric layer is formed in the FEOL region, and a heat transfer pillar extends from the FEOL region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0087] In some examples of the first semiconductor device, a high thermal conductivity dielectric layer is formed at the interface between the FEOL region and the MOL / BEOL region, and a heat transfer pillar extends from the FEOL region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0088] In some examples of the first semiconductor device, a high thermal conductivity dielectric layer is formed in the MOL / BEOL region, and a heat transfer pillar extends from the MOL / BEOL region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0089] In some examples of the first semiconductor device, a high thermal conductivity dielectric layer is formed at the interface between the BSPDN and the FEOL region, and a heat transfer pillar extends from the BSPDN region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0090] In some examples of the first semiconductor device, a high thermal conductivity dielectric layer is formed in a BSPDN, and heat transfer pillars extend from the BSPDN to a heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0091] In some examples of the first semiconductor device, the high thermal conductivity dielectric layer comprises hexagonal boron nitride (hBN). For semiconductor devices including BSPDN, the high thermal conductivity dielectric layer including hBN allows for efficient heat transfer.

[0092] In some examples of the first semiconductor device, the first semiconductor device further includes a first nanometer field-effect transistor (FET) and a second nanometer field-effect transistor (FET). The first nanometer field-effect transistor (FET) includes a first nanometer stack, a first epitaxial layer in contact with the first nanometer stack, and a first metal contact on the top side of the first epitaxial layer. The second nanometer field-effect transistor (FET) includes a second nanometer stack, a second epitaxial layer in contact with the second nanometer stack, and a second metal contact on the bottom side of the second epitaxial layer.

[0093] In some embodiments of the first semiconductor device, the first semiconductor device further includes a SiGe-containing spacer layer formed adjacent to the first epitaxial layer. The spacer layer allows for the formation of back-side metal contacts for connection to the nanosheet field-effect transistor.

[0094] In some examples of the first semiconductor device, a high thermal conductivity dielectric layer is formed in contact with a placeholder layer. The placeholder layer allows for the formation of back-side metal contacts for connection to the nanosheet field-effect transistor.

[0095] Some embodiments disclosed herein may be in the form of an electronic device. The electronic device includes a semiconductor device comprising a back-side power distribution network (BSPDN), a high thermal conductivity dielectric layer, a heat sink, and heat transfer pillars. The heat transfer pillars are connected to the high thermal conductivity dielectric layer and extend to the heat sink. This allows for efficient heat transfer within the semiconductor device utilizing the BSPDN.

[0096] In some examples of electronic devices, the semiconductor device further includes a front-end process (FEOL) region on the BSPDN and a mid-end process / back-end process (MOL / BEOL) region on the FEOL region. For semiconductor devices including the BSPDN, a high thermal conductivity dielectric layer allows for efficient heat transfer.

[0097] In some examples of electronic devices, a high thermal conductivity dielectric layer is formed in the FEOL region, and heat transfer pillars extend from the FEOL region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0098] In some examples of electronic devices, a high thermal conductivity dielectric layer is formed at the interface between the FEOL region and the MOL / BEOL region, and heat transfer pillars extend from the FEOL region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0099] In some examples of electronic devices, a high thermal conductivity dielectric layer is formed in the MOL / BEOL region, and heat transfer pillars extend from the MOL / BEOL region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0100] In some examples of electronic devices, a high thermal conductivity dielectric layer is formed at the interface between the BSPDN and the FEOL region, and heat transfer pillars extend from the BSPDN region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0101] In some examples of electronic devices, a high thermal conductivity dielectric layer is formed within a BSPDN, and heat transfer pillars extend from the BSPDN to a heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0102] In some examples of electronic devices, high thermal conductivity dielectric layers comprise hexagonal boron nitride (hBN). For semiconductor devices including BSPDN, high thermal conductivity dielectric layers comprising hBN allow for efficient heat transfer.

[0103] In some examples of electronic devices, the first semiconductor device further includes a first nanometer field-effect transistor (FET) and a second nanometer field-effect transistor (FET). The first nanometer field-effect transistor (FET) includes a first nanometer stack, a first epitaxial layer in contact with the first nanometer stack, and a first metal contact on the top side of the first epitaxial layer. The second nanometer field-effect transistor (FET) includes a second nanometer stack, a second epitaxial layer in contact with the second nanometer stack, and a second metal contact on the bottom side of the second epitaxial layer.

[0104] In some examples of electronic devices, the first semiconductor device further includes a SiGe-containing spacer layer formed adjacent to the first epitaxial layer. The spacer layer allows for the formation of back-side metal contacts for connection to the nanosheet field-effect transistor.

[0105] In some examples of electronic devices, a high thermal conductivity dielectric layer is formed to contact a placeholder layer. The placeholder layer allows for the formation of back-side metal contacts for connection to the nanosheet field-effect transistor.

[0106] Some embodiments disclosed herein may take the form of a second semiconductor device. The second semiconductor device includes a back-side power distribution network (BSPDN), a front-end process (FEOL) region on the BSPDN, a mid-end process / back-end process (MOL / BEOL) region on the FEOL region, a heat sink on the MOL / BEOL region, a high thermal conductivity dielectric layer, and heat transfer pillars connected to the high thermal conductivity dielectric layer and extending to the heat sink. This allows for efficient heat transfer within the semiconductor device utilizing the BSPDN.

[0107] In some examples of the second semiconductor device, the high thermal conductivity dielectric layer comprises hexagonal boron nitride (hBN). This allows for efficient heat transfer in the semiconductor device utilizing BSPDN.

[0108] In some examples of the second semiconductor device, a high thermal conductivity dielectric layer is formed in the FEOL region, and a heat transfer pillar extends from the FEOL region to the heat sink. This allows for design flexibility in determining the location of the high thermal conductivity dielectric layer while still achieving effective heat transfer.

[0109] Various embodiments have been described for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles, practical applications, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0110] 100: Semiconductor devices 102:Substrate 103: Nanosheet Stacking 104: BDI layer 105: Temporary Sacrifice Layer 106: Sacrifice Layer 108: Semiconductor layer 110: Internal spacers 114: Dummy gate 116: Spacer 118: Nitride layer 120: STI layer 122: Lining layer 124: Epitaxial layer 126: Occupancy trench 128: Placeholder Layer 130: Silicon layer 132: Epitaxial layer 134: ILD layer 136: Gate 140: First metal contact 141: Second metal contact 142: BEOL layer 144: Heatsink 150: High thermal conductivity dielectric layer 154: Bottom ILD layer / backside metal contacts 178: Backside contact opening 196: Active Zone 198: Passage Area 200: Semiconductor devices 250: High thermal conductivity dielectric layer 300: Semiconductor Devices 350: High thermal conductivity dielectric layer 400: Semiconductor Devices 402:BSPDN 404:FEOL area 406: MOL / BEOL Zone 408: Heatsink 410: Heat exchanger 420: Heat transfer column 450: High thermal conductivity dielectric layer NS: Nanosheet Stacking X1-X2: Line Y1-Y2: Line

Claims

1. A semiconductor device comprising: a back-side power distribution network (BSPDN); a high thermal conductivity dielectric layer; a heat sink; and a heat transfer column connected to the high thermal conductivity dielectric layer and extending to the heat sink.

2. The semiconductor device of claim 1 further includes a front-end process (FEOL) area on the BSPDN and a mid-end process / back-end process (MOL / BEOL) area on the FEOL area.

3. The semiconductor device of claim 2, wherein the high thermal conductivity dielectric layer is formed in the FEOL region, and the heat transfer column extends from the FEOL region to the heat sink.

4. The semiconductor device of claim 2, wherein the high thermal conductivity dielectric layer is formed at an interface between the FEOL region and the MOL / BEOL region, and the heat transfer column extends from the FEOL region to the heat sink.

5. The semiconductor device of claim 2, wherein the high thermal conductivity dielectric layer is formed in the MOL / BEOL region, and the heat transfer column extends from the MOL / BEOL region to the heat sink.

6. The semiconductor device of claim 2, wherein the high thermal conductivity dielectric layer is formed at an interface between the BSPDN and the FEOL region, and the heat transfer column extends from the BSPDN to the heat sink.

7. The semiconductor device of claim 2, wherein the high thermal conductivity dielectric layer is formed in the BSPDN and the heat transfer column extends from the BSPDN to the heat sink.

8. The semiconductor device of claim 1, wherein the high thermal conductivity dielectric layer comprises hexagonal boron nitride (hBN).

9. The semiconductor device of claim 1, further comprising: a first nanosheet field-effect transistor (FET) including a first nanosheet stack, a first epitaxial layer in contact with the first nanosheet stack, and a first metal contact on a top side of the first epitaxial layer; and a second nanosheet field-effect transistor (FET) including a second nanosheet stack, a second epitaxial layer in contact with the second nanosheet stack, and a second metal contact on a bottom side of the second epitaxial layer.

10. The semiconductor device of claim 9, further comprising a SiGe-containing occupant layer formed adjacent to the first epitaxial layer.

11. The semiconductor device of claim 10, wherein the high thermal conductivity dielectric layer is formed in contact with the occupancy layer.

12. An electronic device comprising: a semiconductor device including a back-side power distribution network (BSPDN); a high thermal conductivity dielectric layer; a heat sink; and a heat transfer column connected to the high thermal conductivity dielectric layer and extending to the heat sink.

13. The electronic device of claim 12 further includes a front-end process (FEOL) area on the BSPDN and a mid-end process / back-end process (MOL / BEOL) area on the FEOL area.

14. The electronic device of claim 13, wherein the high thermal conductivity dielectric layer is formed in the FEOL region and the heat transfer column extends from the FEOL region to the heat sink.

15. The electronic device of claim 13, wherein the high thermal conductivity dielectric layer is formed at an interface between the FEOL region and the MOL / BEOL region, and the heat transfer column extends from the FEOL region to the heat sink.

16. The electronic device of claim 13, wherein the high thermal conductivity dielectric layer is formed in the MOL / BEOL region, and the heat transfer column extends from the MOL / BEOL region to the heat sink.

17. The electronic device of claim 13, wherein the high thermal conductivity dielectric layer is formed at an interface between the BSPDN and the FEOL region, and the heat transfer column extends from the BSPDN to the heat sink.

18. The electronic device of claim 13, wherein the high thermal conductivity dielectric layer is formed in the BSPDN and the heat transfer column extends from the BSPDN to the heat sink.

19. The electronic device of claim 12, wherein the high thermal conductivity dielectric layer comprises hexagonal boron nitride (hBN).

20. The electronic device of claim 12, further comprising: a first nanosheet field-effect transistor (FET) including a first nanosheet stack, a first epitaxial layer in contact with the first nanosheet stack, and a first metal contact on a top side of the first epitaxial layer; and a second nanosheet field-effect transistor (FET) including a second nanosheet stack, a second epitaxial layer in contact with the second nanosheet stack, and a second metal contact on a bottom side of the second epitaxial layer.

21. The electronic device of claim 20, further comprising a SiGe-containing occupant layer formed adjacent to the first epitaxial layer.

22. The electronic device of claim 21, wherein the high thermal conductivity dielectric layer is formed to contact the occupancy layer.

23. A semiconductor device comprising: a back-side power distribution network (BSPDN); a front-end process (FEOL) region located on the BSPDN; a mid-end process / back-end process (MOL / BEOL) region located on the FEOL region; a heat sink located on the MOL / BEOL region; a high thermal conductivity dielectric layer; and a heat transfer pillar connected to the high thermal conductivity dielectric layer and extending to the heat sink.

24. The semiconductor device of claim 23, wherein the high thermal conductivity dielectric layer comprises hexagonal boron nitride (hBN).

25. The semiconductor device of claim 23, wherein the high thermal conductivity dielectric layer is formed in the FEOL region and the heat transfer column extends from the FEOL region to the heat sink.