Semiconductor devices

Abstract

The embodiments relate to a transistor, a semiconductor memory device, and a method for manufacturing a transistor. The transistor of the embodiment comprises: a semiconductor layer; a convex element region disposed on the semiconductor layer, having a specific width in a first direction along the surface of the semiconductor layer and extending in a second direction along the surface of the semiconductor layer and intersecting the first direction; a gate electrode disposed above the element region; and a substrate covering the gate electrode; and element separation portions extending in the second direction on both sides of the element region in the first direction, with the substrate continuously extending from the gate electrode to the element separation portions and lying beneath the element separation portions.

Description

Technical Field

[0001] The present invention relates to a transistor, a semiconductor memory device, and a method for manufacturing a transistor. Prior Technology

[0002] CMOS (Complementary Metal Oxide Semiconductor) transistors, for example, have a device region and a gate electrode disposed on the device region. During the transistor manufacturing process, considering that the gate electrode may shift relative to the device region, the width of the gate electrode is sometimes made larger than the width of the device region. This can sometimes become a major factor hindering transistor miniaturization. Summary of the Invention

[0003] The embodiments provide a transistor, a semiconductor memory device, and a method for manufacturing the transistor that can suppress the positional displacement of the gate electrode relative to the component region.

[0004] The transistor of the embodiment includes: a semiconductor layer; a convex element region disposed on the semiconductor layer, having a specific width in a first direction along the surface of the semiconductor layer, and extending in a second direction along the surface of the semiconductor layer and intersecting the first direction; a gate electrode disposed above the element region; and a liner covering the gate electrode; element separation portions extending along the second direction on both sides of the element region in the first direction, and the liner continuously extending from the gate electrode to the element separation portions, and being concealed below the element separation portions. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram of the semiconductor memory device according to Embodiment 1. Figure 2 is an equivalent circuit diagram showing an example of the configuration of the memory cell array, sense amplifier circuit and latch circuit of the semiconductor memory device of Embodiment 1. Figure 3 is a schematic diagram showing an example of the layout of the sense amplifier module and data register of the semiconductor memory device in Embodiment 1. Figures 4A and 4B are schematic diagrams illustrating an example of the layout of the transistors in the semiconductor memory device of Embodiment 1. Figures 5A to 5D are diagrams illustrating an example of the configuration of a transistor used in the semiconductor memory device of Embodiment 1. Figures 6A and 6B are diagrams illustrating an example of the configuration of a template used to manufacture the transistor of Embodiment 1. Figures 7A-7D are diagrams illustrating an example of the sequence of the template manufacturing method in Embodiment 1. Figures 8Aa to 8Cb are examples of the sequence of the manufacturing method of the transistor in Embodiment 1. Figures 9Aa to 9Cb are examples of the sequence of the manufacturing method of the transistor in Embodiment 1. Figures 10Aa to 10Cb are diagrams illustrating an example of the sequence of the transistor manufacturing method according to Embodiment 1. Figures 11Aa to 11Cb are diagrams illustrating an example of the sequence of the transistor manufacturing method according to Embodiment 1. Figures 12A and 12B are schematic diagrams illustrating an example of the layout of the transistors in the semiconductor memory device of Embodiment 1 and the comparative example. Figures 13A-13C are diagrams showing an example of the configuration of the transistor used in the semiconductor memory device of Variation 1 of Embodiment 1. Figures 14Aa to 14Cb are diagrams illustrating one example of the sequence of the transistor manufacturing method in Variation 1 of Embodiment 1. Figures 15A and 15B are schematic diagrams showing an example of the layout of the transistors in the semiconductor memory device of Embodiment 1, Variation 2 and Comparative Example. Figure 16 is a circuit diagram showing an example of the configuration of the column decoder in the semiconductor memory device of Embodiment 2. Figures 17A and 17B are schematic diagrams illustrating an example of the layout of the transistors in the semiconductor memory device of Embodiment 2. Figure 18 is a block diagram of the semiconductor memory device according to Embodiment 3. Figure 19 is a circuit diagram showing an example of the circuit configuration of the sense amplifier circuit included in the semiconductor memory device of Embodiment 3. Figures 20A and 20B are schematic diagrams illustrating an example of the layout of the transistors in the semiconductor memory device of Embodiment 3 and the comparative example. Implementation

[0006] The present invention will now be described in detail with reference to the accompanying drawings. Furthermore, the present invention is not limited to the embodiments described below. Also, the constituent elements in the following embodiments include constituent elements that can be easily conceived by the industry or substantially the same constituent elements.

[0007] [Implementation Method 1]

[0008] Hereinafter, with reference to the accompanying drawings, Embodiment 1 will be described in detail.

[0009] (Brief Structure of a Semiconductor Memory Device)

[0010] Figure 1 is a block diagram of the semiconductor memory device 1 according to Embodiment 1. As shown in Figure 1, the semiconductor memory device 1 includes an input / output circuit 110, a logic control circuit 120, a status register 130, an address register 140, an instruction register 150, a sequencer 160, a ready / busy circuit 170, a voltage generation circuit 180, a memory cell array 10, a column decoder 20, a sense amplifier module 30, a data register 40, and a row decoder 50.

[0011] The input / output circuit 110 controls the input and output of signals DQ to external devices such as a memory controller (not shown) that controls the semiconductor memory device 1. The input / output circuit 110 includes input circuitry and output circuitry (not shown).

[0012] The input circuit sends the write data WD and other data DAT received from the external device to the data register 40, sends the address ADD to the address register 140, and sends the instruction CMD to the instruction register 150.

[0013] The output circuit sends the status information STS received from the status register 130, the read data RD received from the data register 40, and the address ADD received from the address register 140 to the external device.

[0014] The logic control circuit 120 receives signals from external devices, such as the chip enable signal CEn, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn. Furthermore, the logic control circuit 120 controls the input / output circuit 110 and the sequencer 160 based on the received signals.

[0015] The status register 130 temporarily stores status information (STS) for write, read, and erase operations, and notifies external devices whether the operation has been completed normally.

[0016] Address register 140 temporarily stores the address ADD received from the external device via input / output circuit 110. Additionally, address register 140 transmits the column address RA to column decoder 20 and the row address CA to row decoder 50.

[0017] The instruction register 150 temporarily stores the instruction CMD received from the external device via the input / output circuit 110 and transmits it to the sequencer 160.

[0018] The sequencer 160 controls the operation of the entire semiconductor memory device 1. More specifically, the sequencer 160 controls, according to the instruction CMD stored in the instruction register 150, components such as the status register 130, the ready / busy circuit 170, the voltage generation circuit 180, the column decoder 20, the sense amplifier module 30, the data register 40, and the row decoder 50, to perform write operations, read operations, and erase operations.

[0019] The ready / busy circuit 170 sends the ready / busy signal R / Bn to an external device based on the operating status of the sequencer 160.

[0020] The voltage generation circuit 180 generates the voltage required for write, read, and erase operations according to the control of the sequencer 160, and supplies the generated voltage to, for example, the memory cell array 10, the column decoder 20, and the sense amplifier module 30. The column decoder 20 and the sense amplifier module 30 apply the voltage supplied from the voltage generation circuit 180 to the memory cells in the memory cell array 10.

[0021] The memory cell array 10 contains a plurality of blocks BLK (BLK0~BLKn). n is an integer greater than or equal to 2. A block BLK is a collection of a plurality of memory cells associated with bit lines and word lines, serving as a data erasure unit, for example. The memory cells are constructed, for example, as transistors, to store non-volatile data.

[0022] By incorporating this type of memory cell, the semiconductor memory device 1 is configured as, for example, a NAND (Not AND) type non-volatile memory. However, the semiconductor memory device 1 can also be configured as, for example, a NOR (Not OR) type or other non-volatile memory.

[0023] Column decoder 20 decodes column address RA. Based on the decoding result, column decoder 20 selects any block BLK. Furthermore, column decoder 20 applies the required voltage to block BLK.

[0024] During a read operation, the sense amplifier module 30 senses the data read from the memory cell array 10. Furthermore, the sense amplifier module 30 sends the read data RD to the data buffer 40. During a write operation, the sense amplifier module 30 sends the write data WD to the memory cell array 10.

[0025] The data register 40 has a plurality of latching circuits. The latching circuits store write data WD and read data RRD. For example, during a write operation, the data register 40 temporarily stores the write data WD received from the input / output circuit 110 and sends it to the sense amplifier module 30. Similarly, for example, during a read operation, the data register 40 temporarily stores the read data RD received from the sense amplifier module 30 and sends it to the input / output circuit 110.

[0026] The row decoder 50 decodes the row address CA during write, read, and erase operations, and selects the latch circuit in the data register 40 based on the decoding result.

[0027] Furthermore, the aforementioned components of the semiconductor memory device 1, excluding the memory cell array 10, are also referred to as peripheral circuits. That is, the peripheral circuits include input / output circuits 110, logic control circuits 120, status registers 130, address registers 140, instruction registers 150, sequencers 160, ready / busy circuits 170, voltage generation circuits 180, column decoders 20, sense amplifier modules 30, data registers 40, and row decoders 50.

[0028] Thus, the semiconductor memory device 1 of Embodiment 1 includes a memory cell array 10 comprising a plurality of memory cells and peripheral circuitry for operating the plurality of memory cells.

[0029] (Circuit configuration of memory cell array)

[0030] Figure 2 is an equivalent circuit diagram showing an example of the configuration of the memory cell array 10, the sense amplifier circuit SA, and the latch circuits DL and XDL included in the semiconductor memory device 1 of Embodiment 1. First, an example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 will be described below.

[0031] As described above, the memory cell array 10 has a plurality of blocks BLK. Each of the plurality of blocks BLK has a plurality of serial units SU. Each of the plurality of serial units SU has a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to peripheral circuits such as the column decoder 20 and the sense amplifier module 30 via bit lines BL. The other end of each of the plurality of memory strings MS is connected to peripheral circuits via a common source line SL.

[0032] A memory string (MS) comprises a drain-select transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MC), and a source-select transistor (STS). Hereinafter, the drain-select transistor (STD) and the source-select transistor (STS) will sometimes be referred to simply as select transistors (STD, STS).

[0033] Memory cells (MCs) are, for example, field-effect transistors (FETs) whose gate insulating layer contains a charge storage layer. The threshold voltage of a memory cell (MC) varies depending on the amount of charge in the charge storage layer. By setting one or more threshold voltages, a memory cell (MC) can store one or more bits of data. Word lines (WLs) are connected to the gate electrodes of multiple memory cells (MCs) corresponding to one memory string (MS). These word lines (WLs) are all connected to all memory strings (MS) in a block (BLK).

[0034] Select transistors (STD, STS), such as field-effect transistors. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistors (STD, STS). The drain select line SGD connected to the drain select transistor STD corresponds to the serial cell SU and is connected to all memory strings MS in one serial cell SU. The source select line SGS connected to the source select transistor STS is connected to all memory strings MS in one block BLK.

[0035] (Composition of the sensing amplifier module)

[0036] Next, using Figures 2 and 3, an example of the configuration of the sensing amplifier module 30 will be described.

[0037] The aforementioned sensing amplifier module 30 includes a plurality of sensing amplifier circuits SA for each bit line BL. Each sensing amplifier circuit SA, for example, during a readout operation, senses the data that has been read to the corresponding bit line BL and determines whether the readout data is "0" or "1".

[0038] Furthermore, the aforementioned data buffer 40 includes a plurality of latch circuits DL and XDL corresponding to a plurality of sense amplifier circuits SA. Each latch circuit XDL is also configured for each bit line BL. On the other hand, a plurality of latch circuits DL are configured for each corresponding sense amplifier circuit SA. In this case, the number of latch circuits DL is designed, for example, based on the number of data bits that one memory cell MC can store. The latch circuits DL and XDL temporarily store data related to the corresponding bit line BL.

[0039] First, continuing with Figure 2, an example of the circuit configuration of the sense amplifier module 30 will be described. Figure 2 shows a sense amplifier circuit SA within the sense amplifier module 30 and latch circuits DL and XDL within the data register 40. Furthermore, a plurality of control signals supplied to the sense amplifier circuit SA, etc., are controlled by a sequencer 160.

[0040] As shown in Figure 2, the sense amplifier circuit SA includes transistors TR31 to TR38 and capacitor CAP. In the figure, transistor TR31 is a low-voltage P-channel MOS (Metal-Oxide-Semiconductor) transistor. Transistors TR32 to TR38 are low-voltage N-channel MOS transistors. Hereinafter, transistors TR31 to TR38 included in the sense amplifier circuit SA will sometimes be simply referred to as transistor TR.

[0041] One end of transistor TR31 is connected to the power supply line supplying the power supply voltage Vdd, and the gate electrode of transistor TR31 is connected to node INV. One end of transistor TR32 is connected to the other end of transistor TR31, and the other end of transistor TR32 is connected to node COM. A control signal BLX is input to the gate electrode of transistor TR32. One end of transistor TR33 is connected to node COM, and the other end of transistor TR33 is connected to the corresponding bit line BL. A control signal BLC is input to the gate electrode of transistor TR33.

[0042] One end of the transistor TR34 is connected to node COM, the other end of the transistor TR34 is connected to node SRC, and the gate electrode of the transistor TR34 is connected to node INV.

[0043] One end of transistor TR35 is connected to the other end of transistor TR31, and the other end of transistor TR35 is connected to node SEN. A control signal HLL is input to the gate electrode of transistor TR35. One end of transistor TR36 is connected to node SEN, and the other end of transistor TR36 is connected to node COM. A control signal XXL is input to the gate electrode of transistor TR36.

[0044] A clock signal CLK is input to one end of transistor TR37, and the gate electrode of transistor TR37 is connected to node SEN. One end of transistor TR38 is connected to the other end of transistor TR37, and the other end of transistor TR38 is connected to bus LBUS. A control signal STB is input to the gate electrode of transistor TR38. One end of capacitor CAP is connected to node SEN, and a clock signal CLK is input to the other end of capacitor CAP.

[0045] The latch circuit DL includes inverters IVa and IVb, and transistors TR41 and TR42. In the figure, transistors TR41 and TR42 are low-voltage N-channel MOS transistors. Hereinafter, transistors TR41 and TR42 included in the data register 40 will sometimes be simply referred to as transistor TR.

[0046] Furthermore, while Figure 2 shows one latch circuit DL, the data register 40 can also have multiple latch circuits DL relative to a sense amplifier circuit SA, as described above. Other latch circuits DL not shown have the same configuration as the latch circuit DL in Figure 2.

[0047] The input terminal of inverter IVa is connected to node LAT, and the output terminal is connected to node INV. The input terminal of inverter IVb is connected to node INV, and the output terminal is connected to node LAT.

[0048] One end of transistor TR41 is connected to node INV, and the other end is connected to bus LBUS, providing a control signal STI to the gate electrode. One end of transistor TR42 is connected to node LAT, and the other end is connected to bus LBUS, providing a control signal STL to the gate electrode.

[0049] The latch circuit XDL has a configuration substantially the same as that of the latch circuit DL, and is connected to the bus LBUS in a manner that allows it to transmit and receive data with the sense amplifier circuit SA and the latch circuit DL. Furthermore, the latch circuit XDL is connected to the aforementioned input / output circuit 110 and is used for the input and output of data between the sense amplifier circuit SA and the input / output circuit 110.

[0050] Furthermore, the latch circuit XDL is also used for the caching operation of the semiconductor memory device 1. That is, even if all the latch circuits DL corresponding to the sense amplifier circuit SA are in use, the semiconductor memory device 1 can still receive data from the outside as long as the latch circuit XDL is idle.

[0051] Thus, the sensing amplifier circuit SA and latching circuits DL and XDL, which belong to the peripheral circuits, have multiple transistors TR.

[0052] Next, the operation of the sensing amplifier circuit SA constructed above will be briefly explained.

[0053] As an example of writing data to the memory cell MC, when a charge is injected into the memory cell MC to raise the threshold, the "H" level ("1" data) is stored in the node INV of the latch circuit DL. This turns on the transistor TR34 and sets the bit line BL to 0 V.

[0054] As another example of writing data to the memory cell MC, when no charge is injected into the memory cell MC and the threshold is not changed, the "L" level ("0" data) is stored in the node INV of the latch circuit DL. This turns on the transistor TR31, applying a specific positive voltage to the bit line BL.

[0055] During readout, node INV is set to the "L" level, turning on transistor TR31. Furthermore, via transistors TR41 and TR42, bit line BL is pre-charged by transistor TR31. Also, transistor TR35 is turned on to charge node SEN to a specific potential.

[0056] Subsequently, transistor TR35 is turned off, signal XXL is set to the "H" level, and transistor TR36 is turned on. In this way, if the corresponding memory cell MC is turned on, the potential of node SEN decreases, and transistor TR37 is turned off. Conversely, if the corresponding memory cell MC is turned off, the potential of node SEN remains at the "H" level, and transistor TR37 is turned on.

[0057] Furthermore, by using the STB signal to turn on the transistor TR38, the potential corresponding to the on / off state of the transistor TR37 is read out to the bus LBUS and stored in the latch circuit DL.

[0058] Furthermore, the circuit configuration, interconnection, and data transmission method of the sense amplifier circuit SA and latch circuits DL and XDL shown in Figure 2 are just one example. Besides the above configuration, the sense amplifier circuit SA and latch circuits DL and XDL can also employ various other configurations, connection methods, or data transmission methods. In such cases, the number and type of transistors TR included in the sense amplifier circuit SA and latch circuits DL and XDL can also vary. For example, the sense amplifier circuit SA and latch circuits DL and XDL can also be configured to include high-voltage P-channel MOS transistors or high-voltage N-channel MOS transistors.

[0059] Figure 3 is a schematic diagram showing an example of the layout of the sense amplifier module 30 and the data register 40 included in the semiconductor memory device 1 of Embodiment 1. In Figure 3, as an example, the sense amplifier circuit SA and the latch circuits DL and XDL have the connection method and data transmission method shown in Figure 2 above.

[0060] Here, the direction along the plurality of bit lines BL that are connected to the plurality of memory cells MC is defined as the Y direction and is taken as the second direction. Furthermore, the direction intersecting the X direction, i.e., the direction along the plurality of word lines WL that are connected to the plurality of memory cells MC, is defined as the X direction and is taken as the first direction.

[0061] As shown in Figure 3, in the physical configuration of the semiconductor memory device 1, the plurality of latch circuits DL of the data temporary register 40 are combined with one sense amplifier circuit SA of the sense amplifier module 30 via the aforementioned bus LBUS to form a plurality of subgroups SA / DL (SA / DL). <0> ~SA / DL <15> ).

[0062] These groups of SA / DL are clustered together in units of a specific number of bit lines BL. In the example of Figure 3, there are 16 groups of SA / DL. <0> ~SA / DL <15> They converge and are arranged in a row along the Y direction of the 16-bit line BL.

[0063] Furthermore, the latch circuit XDL (XDL) of the data temporary register 40 <0> ~XDL <15> They are also arranged in groups of 16, corresponding to the group SA / DL of the sense amplifier circuit SA and latch circuit DL arranged in a row. <0> ~SA / DL <15> The ground planes are arranged in a row along the Y direction of the 16-bit line BL.

[0064] The sensor amplifier circuit SA and the latch circuit DL, specifically the subgroups SA / DL and their corresponding latch circuits XDL, are connected via a bus LBUS to enable data transmission and reception. In the example of Figure 3, 16 subgroups SA / DL are arranged in a row. <0> ~SA / DL <15> There is a total of 1 busbar LBUS.

[0065] (Composition of transistors)

[0066] Next, using Figures 4A to 5D, we will explain the physical configuration of the transistor TR contained in the sense amplifier circuit SA and the latch circuits DL and XDL.

[0067] Figures 4A and 4B are schematic diagrams illustrating an example of the layout of transistors TR in the semiconductor memory device 1 of Embodiment 1. Figure 4A is a simplified top view of a plurality of transistors TR, and Figure 4B is a simplified cross-sectional view of a plurality of transistors TR along the Y direction.

[0068] As shown in Figure 4A, the transistors TR contained in the sense amplifier circuit SA and latch circuits DL and XDL arranged in a row are arranged in a row, for example, within a distance of 16 bit lines BL. Each transistor TR has a component region AA and a gate electrode GC disposed above the component region AA.

[0069] The element region AA has a channel at a position overlapping the gate electrode GC in the vertical direction, and source / drain regions on both sides of the channel in the Y direction. However, the transistors TR arranged in a row share the source / drain regions with the transistors TR adjacent to each other in the Y direction along the bit line BL.

[0070] Figure 4A shows an example of four transistors (TRs) arranged in a row along the Y direction, sharing source / drain regions. However, the number of transistors (TRs) sharing source / drain regions is arbitrary and not limited to four.

[0071] Furthermore, a component separation section STI is provided between the component regions AA of adjacent transistors TR in the X direction.

[0072] Furthermore, in order to increase the gate width W of the transistor TR and suppress the threshold variation caused by the narrow channel effect (NCE) or the anti-narrow channel effect, it is preferable to increase the width of the element region AA in the Y direction as much as possible and minimize the width of the element separation part STI as much as possible.

[0073] Under the narrow-channel effect, a narrower gate width in a transistor leads to an increase in the threshold voltage. Therefore, the effect of the turn-on current being greater than that caused by a reduction in gate width is reduced. On the other hand, under the reverse narrow-channel effect, a narrower gate width in a transistor leads to an increase in leakage current flowing through the lower part of the channel, even when the transistor channel is turned off at a specific voltage. This threshold voltage variation is also caused by the short-channel effect resulting from a narrower gate length ("L" in Figure 4A). Generally, the threshold voltage deviation between transistors depends on 1 / √LW (where L represents the gate length and W represents the gate width). Since the sense amplifier and data latch have a large number of bit lines, it is desirable to have a small threshold voltage deviation from the perspective of readout stability. The gate electrode GC of transistor TR is connected to a gate contact CG, which is connected to upper-layer wiring (not shown). The element area AA is connected to a source / drain contact CS, which is connected to upper-layer wiring (not shown). The transistors TR arranged in a row in the Y direction share a common source / drain region, and similarly share a common source / drain junction CS with the transistors TR adjacent in the Y direction.

[0074] Furthermore, among the plurality of transistors TR, there are transistors TR whose gate electrodes GC are input with the same control signal. In this case, the gate electrodes GC of these transistors TR are electrically connected, for example, through upper layer wiring (not shown). Thus, even though the gate electrodes GC contained in the plurality of transistors TR of the sense amplifier circuit SA and the latch circuits DL and XDL are input with the same control signal, they are physically separated from each other at the level of the layer constituting the gate electrode GC (hereinafter, gate electrode layer GCr).

[0075] Figure 4B illustrates the following situation: a plurality of transistors TR share a source / drain region and a source / drain contact CS in the Y direction; and the gate electrodes GC of each transistor TR are separate. As shown in Figure 4B, the transistors TR arranged in a row in the Y direction, except for the transistors TR at the Y-direction ends, share a source / drain region and a source / drain contact CS among the plurality of transistors TR. Furthermore, a component separation section STI is disposed on the Y-direction side of the transistor TR at the Y-direction ends.

[0076] Figures 5A-5D are diagrams illustrating an example of the configuration of the transistor TR applied to the semiconductor memory device 1 of Embodiment 1. Figure 5A is a schematic top view showing the gate electrode GC and element region AA of the transistor TR. Figure 5B is a cross-sectional view of the transistor TR along the Y direction, i.e., along line A-A' in Figure 5A. Figure 5C is a cross-sectional view of the transistor TR along the X direction, i.e., along line B-B' in Figure 5A. Figure 5D is a cross-sectional view of a plurality of transistor TRs along the Y direction. In Figures 5A-5D, the gate contact CG and the source / drain contact CS are omitted.

[0077] Furthermore, in Figures 5A-5C, as an example of a transistor TR applicable to a semiconductor memory device 1, a single transistor TR is shown. However, when multiple transistor TRs are arranged in a row as described above, sharing source / drain regions, as shown in Figure 5D, in a cross-section along the Y direction, no element separation section (STI) is provided on either side of the transistor TRs except at the two ends of the arrangement. Moreover, the element separation section (STI) is only provided on one side of the transistor TRs at the two ends of the arrangement.

[0078] As shown in Figures 5A to 5C, the transistor TR of Embodiment 1 includes a substrate WF, a device region AA, a gate electrode GC, sidewalls SWg, SWa, SWga, and a substrate LR.

[0079] The substrate WF is, for example, a silicon substrate or other semiconductor substrate. A layer AAr is formed in the substrate WF, extending from its surface to a specific depth. The AAr layer is, for example, a layer containing impurities such as arsenic, phosphorus, or boron. The impurities are appropriately selected depending on whether the transistor TR is N-channel or P-channel.

[0080] The component region AA has a specific width in the X direction and is configured to be convex, extending along the Y direction. That is, the component region AA has a configuration in which the surface of the substrate WF on which the well AAr is formed is processed into a convex shape.

[0081] On both sides of the element region AA in the X direction and on both sides of the Y direction, a pair of element separation portions STIs are disposed in the recesses RCw recessed from the surface of the substrate WF. That is, the element separation portions STIs are disposed around a single transistor TR in a manner that surrounds the transistor TR.

[0082] The component separation section STI includes an interlayer insulating layer (ILD) such as a silicon oxide layer filled within the recessed RCw. In this way, the component separation section STI electrically separates each transistor TR in the X and Y directions.

[0083] On the component region AA, at a position overlapping the gate electrode GC when viewed from above, a gate insulating layer Gox is disposed. The gate insulating layer Gox is, for example, a silicon oxide layer, or a high-k layer containing hafnium oxide or zirconium oxide.

[0084] The gate electrode GC is disposed above the gate insulating layer Gox, which is located above the device region AA. More specifically, a polycrystalline silicon gate electrode GCp is disposed on the gate insulating layer Gox, and a metal gate electrode GCm is disposed on the polycrystalline silicon gate electrode GCp. The polycrystalline silicon gate electrode GCp is a conductive polycrystalline silicon layer doped with P-type or N-type impurities. The metal gate electrode GCm is a metal layer containing tungsten, tungsten silicon, or nickel silicon, etc.

[0085] Thus, the gate electrode GC system is configured as, for example, a multi-metal gate electrode composed of a polycrystalline silicon gate electrode GCp and a metal gate electrode GCm.

[0086] A capping layer CP is disposed on the gate electrode GC. The capping layer CP is, for example, a silicon nitride layer or a silicon oxide layer.

[0087] Furthermore, as shown in Figure 5B, in the Y direction, the gate insulating layer Gox, the polycrystalline silicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP have substantially equal widths, and their center positions in the Y direction are substantially the same. That is, the gate insulating layer Gox and the capping layer CP have widths substantially equal to the gate length L of the gate electrode GC.

[0088] Furthermore, in the Y direction, the two sides of the gate insulating layer Gox, the polycrystalline silicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP are substantially located on the same plane. That is, the end positions of the gate insulating layer Gox, the polycrystalline silicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP in the Y direction are substantially overlapping when viewed from their stacking direction.

[0089] Here, the fact that their widths are substantially equal and their center and end positions in the Y direction are substantially consistent means that within the processing error range of the gate insulating layer Gox, the polycrystalline silicon gate electrode GCp, the metal gate electrode GCm, and the top cover layer CP, their widths are equal and their center and end positions in the Y direction are consistent.

[0090] Furthermore, as shown in Figure 5C, in the X direction, the protruding upper surface of the element region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP have substantially equal widths, and their centers in the X direction are substantially aligned. That is, the upper surface of the element region AA, the gate insulating layer Gox, and the capping layer CP have widths substantially equal to the gate width W of the gate electrode GC.

[0091] Furthermore, in the X direction, the two sides of the element region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP are substantially located on the same plane. That is, the end positions of the element region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP in the X direction are substantially overlapping when viewed from their stacking direction.

[0092] Here, the widths of the components are substantially equal, and the center and end positions in the X direction are substantially consistent. This means that within the processing error range of the upper surface of the component region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the top cover layer CP, the widths of the components are equal, and the center and end positions in the X direction are consistent.

[0093] The first sidewall, SWg, covers the Y-direction facing sides of the gate insulating layer Gox, the polycrystalline silicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP. The second sidewall, SWa, covers the Y-direction facing sides of the element region AA.

[0094] On the other hand, in the X direction, the sidewall SWg that covers the side of the gate insulating layer Gox, the polycrystalline silicon gate electrode GCp, the metal gate electrode GCm and the top cap layer CP, and the sidewall SWa that covers the side of the element region AA, are integrated to form the first and second sidewalls, which cover each side of the element region AA, the gate insulating layer Gox, the polycrystalline silicon gate electrode GCp, the metal gate electrode GCm and the top cap layer CP.

[0095] The sidewalls SWg, SWA, and SWga are, for example, silicon oxide layers.

[0096] The substrate LR has, for example, a multilayer structure obtained by sequentially stacking a silicon oxide layer OL and a silicon nitride layer NL, covering the top cap layer CP, the gate electrode GC, the gate insulating layer Gox, and the component area AA protruding from the substrate WF.

[0097] More specifically, the liner LR extends from the upper surface of the top cap layer SP to the sides of the top cap layer SP, the gate electrode GC, and the gate insulating layer Gox. Furthermore, the liner LR has a dielectric sidewall SWg or a sidewall SWga covering the sides of the top cap layer SP, the gate electrode GC, and the gate insulating layer Gox.

[0098] Furthermore, the liner LR extends continuously from the gate electrode GC to the device separation section STI. At the device separation section STI, the liner LR lies beneath it. That is, the liner LR lies beneath the interlayer insulating layer ILD filled in the recess RCw of the substrate WF, and continuously covers the bottom surface of the recess RCw from the side of the gate electrode GC.

[0099] Including the gate electrode GC, the transistor TR is covered by an interlayer insulating layer (ILD). As described above, the interlayer insulating layer (ILD) also fills the recesses RCw on both sides of the X-direction and Y-direction of the device region AA, forming the device separation layer (STI). That is, the interlayer insulating layer (ILD) covering the transistor TR and the device separation layer (STI) that electrically separates each transistor TR are integrally formed. The substrate LR is located between the device separation layer (STI) formed by the interlayer insulating layer (ILD) and the recesses RCw of the substrate WF. The interlayer insulating layer (ILD) is, for example, an undoped silica (NSG: Non-doped Silicate Glass) layer.

[0100] As described above, the transistor TR in Embodiment 1 is configured as, for example, an N-channel or P-channel MOS transistor, and the aforementioned sense amplifier module 30 is configured to include, for example, a complementary MOS (CMOS) transistor.

[0101] (Manufacturing method of transistors)

[0102] Next, the manufacturing method of the transistor TR according to Embodiment 1 will be described using Figures 6A to 11Cb. The transistor TR is manufactured using an imprinting technique that transfers a pattern onto a resist layer or the like by forming a patterned template. First, the template used to manufacture the transistor TR will be described below.

[0103] Figures 6A and 6B are diagrams illustrating an example of the configuration of the template TM used to manufacture the transistor TR in Embodiment 1. Figure 6A is an oblique perspective view of the template TM, and Figure 6B is a top view taken from the transfer surface SBt side of the template TM.

[0104] As shown in Figures 6A and 6B, the template TM has a transparent substrate SB and a pattern PT. The transparent substrate SB is, for example, a quartz substrate that allows ultraviolet light to pass through, and has a transfer surface SBt on which the pattern PT is provided. The shape of the transistor TR is formed by transferring the pattern PT onto the substrate WF. Therefore, the pattern PT has a device region pattern PTaa that is transferred onto the substrate WF to become the device region AA, and a gate electrode pattern PTgc that becomes the gate electrode GC.

[0105] The component area pattern PTaa is a groove-shaped pattern with an opening on the transfer surface SBt of the transparent substrate SB, extending from the transfer surface SBt to a specific depth on the transparent substrate SB. That is, the component area pattern PTaa has a concave shape obtained by reversing the shape of the convex component area AA. Therefore, in Figure 6B, the component area pattern PTaa is recessed towards the inside of the paper.

[0106] The gate electrode pattern PTgc is positioned overlapping the element region pattern PTaa, reaching a further depth than the element region pattern PTaa. That is, the gate electrode pattern PTgc has a concave shape obtained by reversing the shape of the gate electrode GC protruding from the element region AA. Therefore, in Figure 6B, the gate electrode pattern PTgc is further recessed towards the inside of the paper from the element region pattern PTaa, which is recessed towards the inside of the paper.

[0107] Along the short side of the element region pattern PTaa extending in a specific direction, the width of the element region pattern PTaa is substantially equal to the width of the gate electrode pattern PTgc. Here, "substantially equal in width" means that within the range of processing errors of the element region pattern PTaa and the gate electrode pattern PTgc, their widths are equal.

[0108] Furthermore, in the examples of Figures 6A and 6B, only one gate electrode pattern PTgc and one element region pattern PTaa are shown. However, in the imprinting process, the wafer-state substrate WF is divided into specific regions called shot regions, and the template TM is pressed against each shot region to transfer the pattern PT. Therefore, one template TM has the same number of patterns PT as the number of element regions AA and gate electrodes GC formed in the shot regions.

[0109] Figures 7A-7D are illustrations showing an example of the manufacturing sequence of the template TM in Embodiment 1. Figure 7 shows an oblique perspective view of the substrate SB with the transfer surface SBt facing upwards.

[0110] As shown in Figure 7A, a masking layer MS, such as a cobalt layer, is formed on the transfer surface SBt of the substrate SB. Furthermore, by means of patterning, such as using an electron beam, an opening OPgc is formed at the formation position of the gate electrode pattern PTgc in the masking layer MS.

[0111] As shown in Figure 7B, the transfer surface SBt of the substrate SB exposed by the self-masking layer MS is processed to form a gate electrode pattern PTgc with an opening on the transfer surface SBt.

[0112] As shown in Figure 7C, by means of drawing, for example using an electron beam, an opening OPaa is formed at the formation position of the element region pattern PTaa in the mask layer MS.

[0113] As shown in Figure 7D, the portion of the substrate SB exposed from the masking layer MS is processed to form a component region pattern PTaa with an opening on the transfer surface SBt. At this time, the gate electrode pattern PTgc with an opening on the transfer surface SBt is further recessed, becoming a gate electrode pattern PTgc that is further recessed from the bottom surface of the component region pattern PTaa.

[0114] Through the above steps, the template TM of implementation method 1 is manufactured.

[0115] Next, the manufacturing method of the transistor TR using the above-mentioned template TM will be described. Furthermore, the manufacturing of the transistor TR is performed as part of the manufacturing steps of the semiconductor memory device 1 in Embodiment 1.

[0116] Figures 8Aa to 11Cb are illustrations showing an example of the manufacturing sequence of the transistor TR according to Embodiment 1. In Figures 8Aa to 11Cb, the figure labeled with the lowercase letter "a" is a cross-sectional view along the Y direction of the substrate WF, and the figure labeled with the lowercase letter "b" is a cross-sectional view along the X direction of the substrate WF.

[0117] As shown in Figures 8Aa and 8Ab, a well AAr is formed in a substrate WF, extending from the surface of the substrate WF to a specific depth. The well AAr is formed by implanting impurities such as arsenic, phosphorus, and boron into the substrate WF, which is a semiconductor substrate such as a silicon substrate, to a specific depth.

[0118] Furthermore, above the well AAr, a gate electrode layer GCr and a resist layer RS ​​are sequentially formed from the dielectric gate insulating layer Goxr. More specifically, a gate insulating layer Goxr is formed covering the entire surface of the well AAr. A polycrystalline silicon gate electrode layer GCpr is formed covering the entire surface of the gate insulating layer Goxr, and P-type or N-type impurities are appropriately doped into the polycrystalline silicon gate electrode layer GCpr. A metal gate electrode layer GCmr is formed covering the entire surface of the polycrystalline silicon gate electrode layer GCpr, and a capping layer CPr is formed covering the entire surface of the metal gate electrode layer GCmr. Finally, a resist layer RS ​​is formed covering the entire surface of the capping layer CPr.

[0119] The resist layer RS ​​used as a masking layer is, for example, a light-curing resist layer that is cured by irradiation with ultraviolet light.

[0120] Furthermore, the gate insulating layer Goxr, the polycrystalline silicon gate electrode layer GCpr, the metal gate electrode layer GCmr, and the capping layer CPr can be formed, for example, by chemical vapor deposition (CVD).

[0121] Furthermore, the resist layer RS ​​can be formed, for example, by spin coating. However, it is not limited to the examples in Figures 8Aa and 8Ab; for example, inkjet printing can be used to drop the resist material into each injection area in droplet form.

[0122] As shown in Figures 8Ba to 8Cb, the pattern PT of the template TM is pressed against the resist layer RS, thereby transferring the element area pattern RSpa and the gate electrode pattern RSpg to the resist layer RS.

[0123] More specifically, as shown in Figures 8Ba and 8Bb, the extension direction of the element area pattern PTaa of the template TM is aligned with the Y direction of the substrate WF, so that the transfer surface SBt of the template TM is aligned with the resist layer RS ​​on the substrate WF. In this state, the template TM is pressed against the resist layer RS. At this time, a gap is maintained between the top cover layer CPr of the substrate WF and the template TM, so that the substrate WF and its various components do not come into contact with the template TM.

[0124] As shown in Figures 8Ca and 8Cb, with the template TM pressed against the resist layer RSr, the resist layer RSr is hardened by irradiating the template TM with ultraviolet light. After the resist layer RSr has hardened, the template TM is demolded.

[0125] This forms a resist pattern RSp that has been transferred with the component area pattern RSpa and the gate electrode pattern RSpg. The resist pattern RSp, as a mask pattern, has the component area pattern RSpa and the gate electrode pattern RSpg.

[0126] The component area pattern RSpa is a pattern of the component area pattern PTaa transferred onto the stencil TM. Therefore, the component area pattern RSpa has a specific width in the X direction and a convex shape extending in the Y direction. Similarly, the gate electrode pattern RSpg is a pattern of the gate electrode pattern PTgc transferred onto the stencil TM. Therefore, the gate electrode pattern RSpg has a convex shape disposed on the upper surface of the component area pattern RSpa.

[0127] Furthermore, the resist pattern RSp has a resist residue layer RLT formed by hardening the resist layer RS ​​in the gap between the top cover layer CPr and the template TM.

[0128] As shown in Figures 9Aa and 9Ab, the resist pattern RSp is treated with oxygen plasma to remove the residual resist layer RLT. This exposes the capping layer CPr outside the formation location of the element region AA.

[0129] As shown in Figures 9Ba and 9Bb, the resist pattern RSp is used to transfer the element region pattern RSpa to the gate electrode layer GCr and the well AAr, forming a convex element region AA with a specific width in the X direction and extending along the Y direction.

[0130] More specifically, the top cap layer CPr, the metal gate electrode layer GCgr, the polysilicon gate electrode layer GCpr, the gate insulating layer Goxr, and the well AAr are sequentially processed on the exposed portion of the self-resist pattern RSp. This processing can be performed using methods such as reactive ion etching (RIE). The processing time is controlled to ensure the well AAr is processed to the desired depth.

[0131] This forms the device region AA with the processed well AAr. However, at this point in time, the source / drain regions of the device region AA have not yet been formed. Furthermore, by excavating around the device region AA, a recess RCw is formed in the substrate WF. Additionally, a gate electrode layer GCaa and a gate insulating layer Goxa are formed. The gate electrode layer GCaa includes a capping layer CPa, a metal gate electrode layer GCga, and a polycrystalline silicon gate electrode layer GCpa, which are substantially overlapping with the device region AA in the stacking direction of each layer.

[0132] Here, the configuration being substantially overlapping with the component region AA means that the top cover layer CPa, the metal gate electrode layer GCga, the polycrystalline silicon gate electrode layer GCpa, and the gate insulating layer Goxa are within the range of processing errors and are overlapping with the component region AA.

[0133] As shown in Figures 9Ca and 9Cb, the residual pattern RSpa in the component area is removed by treating the anti-etching pattern RSp with oxygen plasma, thereby exposing the capping layer CPa outside the formation location of the gate electrode GC.

[0134] As shown in Figures 10Aa and 10Ab, the gate electrode pattern RSpg is transferred to the gate electrode layer GCaa using the resist pattern RSp, forming the gate insulating layer Gox disposed above the device region AA as the gate electrode GC.

[0135] More specifically, the top cap layer CPa, the metal gate electrode layer GCga, the polysilicon gate electrode layer GCpa, and the gate insulating layer Goxa, which are exposed by the self-resist pattern RSp, are processed sequentially. The processing of these layers is performed in the same manner as described above, using methods such as RIE. During this process, while maintaining the selectivity relative to the well AAr, processing is performed to prevent the processing of the upper surface of the element region AA and the bottom surface of the recess RCw.

[0136] In this way, a top cover layer CP, a gate electrode GC, and a gate insulating layer Gox are formed above the component region AA. The width of these layers in the X direction is substantially equal to the width of the component region AA, and the center position in the X direction is substantially the same as the center position of the component region AA.

[0137] Here, the width of these components is substantially equal to the width of the component region AA, and their center positions are substantially consistent with the center position of the component region AA. This means that the top cover layer CP, the gate electrode GC, and the gate insulating layer Gox have a width equal to the width of the component region AA within the range of processing errors, and have a center position consistent with the center position of the component region AA within the range of processing errors.

[0138] Furthermore, sometimes due to processing errors, at least a portion of the capping layer CP, gate electrode GC, and gate insulating layer Gox may be eroded laterally, resulting in a reduction in at least one dimension in the X and Y directions. Also, sometimes due to processing errors, the apex of at least a portion of the capping layer CP, gate electrode GC, and gate insulating layer Gox, which are rectangular in top view, may become rounded corners.

[0139] As shown in Figures 10Ba and 10Bb, the residual resist pattern RSp is removed by ashing using oxygen plasma and the like.

[0140] Furthermore, a diffusion layer is formed in the element region AA to allow impurities such as arsenic, phosphorus, and boron to diffuse at low concentrations. The diffusion of any of these impurities is hindered by the capping layer CP, the gate electrode GC, and the gate insulating layer Gox, and does not diffuse directly below the gate insulating layer Gox.

[0141] As shown in Figures 10Ca and 10Cb, a sidewall layer SWr, such as a silicon oxide layer, is formed on the entire surface of a substrate WF containing a gate electrode GC. Herein, the sidewall layer SWr continuously covers the upper surface and side surface of the capping layer CP, the side surface of the gate electrode GC, the side surface of the gate insulating layer Gox, the upper surface and side surface of the element region AA, and the bottom surface of the recess RCw.

[0142] As shown in Figures 11Aa and 11Ab, the sidewall layer SWr is etched back using methods such as RIE. At this time, by processing under conditions that allow for anisotropy, the sidewall layer SWr is removed from the upper surface of the capping layer CP, the upper surface of the device region AA, and the bottom surface of the recess RCw. On the other hand, the sidewall layer SWr remains on the sides of the capping layer CP, the gate electrode GC, the gate insulating layer Gox, and the device region AA.

[0143] Therefore, a sidewall SWg is formed on the opposite side of the top cap layer CP, the gate electrode GC, and the gate insulating layer Gox in the Y direction. Also, a sidewall SWa is formed on the opposite side of the element region AA in the Y direction. Furthermore, a sidewall SWga is formed on the opposite side of the top cap layer CP, the gate electrode GC, the gate insulating layer Gox, and the element region AA in the X direction.

[0144] After the sidewalls SWg, SWA, and SWga are formed, a diffusion layer is formed in the element region AA to allow impurities such as arsenic, phosphorus, and boron to diffuse at high concentrations. The diffusion of any of these impurities is hindered by the capping layer CP, gate electrode GC, and gate insulating layer Gox, which include the sidewalls SWg, SWA, and SWga, and does not diffuse directly below the gate insulating layer Gox.

[0145] This allows for the formation of source / drain regions with high impurity concentrations in the device regions AA on both sides of the capping layer CP, gate electrode GC, and gate insulating layer Gox. Furthermore, the device region AA directly below the gate insulating layer Gox functions as a channel. Moreover, the type of impurity is determined by which type of transistor TR, either N-channel or P-channel, is formed.

[0146] As shown in Figures 11Ba and 11Bb, a substrate LR is formed to cover the gate electrode GC and the element region AA. At this time, the recesses RCw on both sides of the element region AA in the X direction and on both sides of the element region AA are also continuously covered by the substrate LR from the upper surface of the element region AA.

[0147] More specifically, a silicon oxide layer OL and a silicon nitride layer NL are sequentially deposited on the entire surface of the substrate WF, which includes the gate electrode GC. In this way, the silicon oxide layer OL and the silicon nitride layer NL continuously cover the upper surface and side surface of the capping layer CP, the side surface of the gate electrode GC, the side surface of the gate insulating layer Gox, the upper surface and side surface of the device region AA, and the bottom surface of the recess RCw.

[0148] Furthermore, on each side of the top cover layer CP, the gate electrode GC, and the gate insulating layer Gox, the sidewall SWg or sidewall SWga is located between the aforementioned sidewalls and the liner LR. Also, on the side of the element region AA, the sidewall SWA or sidewall SWga is located between that sidewall and the liner LR.

[0149] As shown in Figures 11Ca and 11Cb, an interlayer insulating layer (ILD) covers the gate electrode GC, the device region AA, and the recesses RCw on both sides of the device region AA in the X and Y directions. The ILD can be formed by supplying a raw material gas, such as polysilazane, to the substrate WF. At this time, the device separation portion (STI) is formed by the ILD covering the recesses RCw.

[0150] By following the above steps, the transistor TR of Embodiment 1 is manufactured.

[0151] (Effects of Implementation Method 1)

[0152] As mentioned above, miniaturization has been achieved in areas such as sense amplifier circuits and latch circuits that read data from memory cells. As part of this, for example, the number of sense amplifier circuits arranged along the Y direction, i.e., the number of tiers, has been reduced from 16 to 12 or 10, thus miniaturizing the circuit area. To reduce the number of tiers, the width of these circuits in the X direction must be reduced, limiting it to a specific number of bit lines.

[0153] Previously, during transistor fabrication, due to considerations such as alignment misalignment between the element region and the gate electrode, the width of the gate electrode in the X direction was sometimes larger than the width of the element region. In such cases, in order to ensure that the amount of gate electrode protruding from the element region and the distance between adjacent gate electrodes in the X direction are appropriate, and to reduce the width of the transistor in the X direction, it is sometimes necessary to reduce the width of the element region in the X direction.

[0154] However, if the above method is used, the gate width of the gate electrode will become smaller, resulting in a narrow-channel effect, which will prevent the desired current value from being achieved. Furthermore, depending on the transistor's construction, a reverse narrow-channel effect may also occur. In this case, there is a risk of increased leakage current, especially since there are many sense amplifiers connected to the bit lines and data latches connected to them, thus the impact of increased leakage current becomes very significant. Moreover, due to the narrow-channel and reverse narrow-channel effects, even a small gate width deviation can easily lead to a change in the threshold voltage, thus there is a risk of increased threshold voltage deviation due to manufacturing deviations. Furthermore, the threshold voltage deviation between transistors, which depends on 1 / √LW, will also increase, thus posing a risk of hindering operational stability. Therefore, it is more ideal to achieve transistor miniaturization by reducing the width of the component separation section in the X direction, rather than reducing the width of the component area.

[0155] According to the manufacturing method of transistor TR in Embodiment 1, the pattern PT of template TM is pressed against the resist layer RS, and the convex element area pattern RSpa and the convex gate electrode pattern RSpg disposed on the upper surface of the element area pattern RSpa are transferred to the resist layer RS.

[0156] By using the resist pattern RSp formed in this way, the positional offset of the gate electrode GC relative to the element region AA can be suppressed. Therefore, the portion of the gate electrode GC protruding from the element region AA can be eliminated, and the distance between adjacent gate electrodes GC in the X direction can be reduced. Therefore, the miniaturization of the transistor TR can be easily achieved by reducing the width of the element separation portion STI in the X direction, rather than reducing the width of the element region AA. That is, narrow-channel or anti-narrow-channel effects can be suppressed, and the transistor TR can be miniaturized.

[0157] Furthermore, as mentioned above, by using imprinting technology to manufacture transistors (TR), it is possible to simultaneously pattern the element region (AA) and the gate electrode (GC). This reduces the number of steps, such as photolithography, and thus lowers manufacturing costs.

[0158] Figures 12A and 12B show configuration examples of the semiconductor memory device of the comparative example and the semiconductor memory device 1 of Embodiment 1. Figures 12A and 12B are schematic diagrams showing an example of the layout of the transistors included in the semiconductor memory devices of Embodiment 1 and the comparative example.

[0159] As shown in Figure 12A, the transistor TR' of the comparative example semiconductor memory device has gate electrodes GC' protruding from the element region AA' at both ends in the X direction. As a result, the transistor TR' of the comparative example cannot sufficiently reduce the width of the element separation portion STI' in the X direction.

[0160] Furthermore, from the perspective of resolution when patterning gate electrodes GC', it is necessary to maintain a certain distance between adjacent gate electrodes GC' in the X direction, which also hinders the reduction of the width of the component separation section STI'.

[0161] Therefore, within the same 16 bit line BL spacing, the element region AA' and gate width W' of the transistor TR' in the comparative example are narrower than those of the transistor TR in Embodiment 1 shown in FIG12B.

[0162] Furthermore, in the manufacturing steps of the transistor TR' in the comparative example, firstly, the element region AA' is patterned, and then the gate electrode GC' is patterned. Therefore, in the recess formed by the patterning of the element region AA', an insulating layer is filled separately from the interlayer insulating layer, for example, the element separation portion STI' is formed before the patterning of the gate electrode GC'.

[0163] Therefore, in the comparative example transistor TR', transistors TR' with gate electrodes GC' input to the same control signal are adjacent to each other in the X direction, and the gate electrode GC' extends to the element separation section STI' between the two transistors TR', so that the two transistors TR' share a gate electrode GC'. Thus, the control signal input from the common gate contact CG' is distributed to the two transistors TR'.

[0164] Based on these circumstances, several differences between the transistor TR of Embodiment 1 and the transistor TR' of the comparative example are listed below.

[0165] According to the transistor TR of Embodiment 1, in the X direction, the upper surface of the element region AA and the gate electrode GC have substantially equal widths, and the center position of the upper surface of the element region AA and the center position of the gate electrode GC are substantially aligned in the X direction. According to the transistor TR' of the comparative example, considering the positional offset of the gate electrode GC' relative to the element region AA', the gate electrode GC' protrudes from the element region AA', and therefore, it does not have the configuration described above.

[0166] According to the transistor TR of Embodiment 1, the liner LR extends continuously from the gate electrode GC to the element separation portion STI, and lies beneath the element separation portion STI. According to the transistor TR' of the comparative example, after filling the recess that becomes the element separation portion STI' with an insulating layer, the gate electrode GC' and the liner are formed. Therefore, the liner is disposed on the element separation portion STI', and does not have the configuration described above.

[0167] Furthermore, according to the transistor TR of Embodiment 1, the substrate LR includes, for example, a silicon nitride layer NL. Thus, by having at least a portion of the substrate LR containing nitride, it is easy to identify that the substrate LR lies beneath the device separation section STI.

[0168] According to the transistor TR of Embodiment 1, the interlayer insulating layer ILD forms a device separation portion STI on both sides of the convex device region AA in the X direction. According to the transistor TR' of the comparative example, the interlayer insulating layer and the insulating layer of the device separation portion STI' are formed separately, and therefore, it does not have the configuration described above.

[0169] According to the transistor TR of Embodiment 1, it has sidewalls SWA and SWga covering the side of the element region AA. According to the transistor TR' of the comparative example, after filling the recess that becomes the element separation part STI' with an insulating layer, the gate electrode GC' and the sidewalls are formed. Therefore, no sidewalls are formed on the side of the element region AA', and it does not have the configuration described above.

[0170] According to the transistor TR of Embodiment 1, the gate electrodes GC included in the plurality of transistor TRs are physically separated from each other. According to the transistor TR' of the comparative example, the element separation section STI' is formed before the gate electrode GC' is patterned. Therefore, the gate electrode GC' that receives the common control signal is physically connected among the plurality of transistor TR', and does not have the configuration described above.

[0171] (Variation Example 1)

[0172] Next, the transistor TRa applied to the semiconductor memory device of Variation 1 of Embodiment 1 will be described using Figures 13A to 14Cb. The difference between the transistor TRa of Variation 1 and that of Embodiment 1 is that it has a miniaturized element region AAa.

[0173] If imprinting technology is used when manufacturing transistors, as described above, the width of the component area and the gate electrode in the X direction can be made substantially equal. However, as mentioned above, sometimes due to processing errors, side etching may occur on the gate electrode GC, or the apex portion of the gate electrode GC may become rounded.

[0174] In Variation Example 1, when the size of the gate electrode GCa, etc., becomes smaller due to such processing errors, the gate electrode GCa is prevented from entering the inner side of the element region AAa.

[0175] Figures 13A-13C are diagrams illustrating an example of the configuration of the transistor TRa in the semiconductor memory device of Variation 1 of Embodiment 1. Figure 13A is a schematic top view of the gate electrode GCa and the element region AAa of the transistor TRa. Figure 13B is a cross-sectional view of the transistor TRa along the Y direction, i.e., along line A-A' in Figure 13A. Figure 13C is a cross-sectional view of the transistor TRa along the X direction, i.e., along line B-B' in Figure 13A. Furthermore, the gate contact and source / drain contact are omitted in Figures 13A-13C. Also, Figures 13A-13C show an example where the gate electrode GCa is rounded into a shape RD.

[0176] As shown in Figure 13A, the gate electrode GCa of the transistor TRa is, for example, rectangular in shape when viewed from above, and the four apex portions of the gate electrode GCa are rounded into rounded corner shapes RD. More specifically, at least one of the polycrystalline silicon gate electrode GCp and the metal gate electrode GCm included in the gate electrode GCa has a rounded corner shape RD.

[0177] Furthermore, the gate electrode GCa has a shape that slightly protrudes from the element region AAa in the X direction. As described below, this is due to the side erosion of the opposing side of the element region AAa in the X direction. Thus, the transistor TRa of Variation Example 1 has a widened portion SE on both sides of the element region AAa in the X direction. Therefore, the width of the upper surface of the element region AAa in the X direction is narrower than the width of the gate electrode GCa. However, in this case, the positional offset of the gate electrode GCa relative to the element region AAa is also suppressed, so the center position of the upper surface of the element region AAa and the center position of the gate electrode GCa are substantially consistent in the X direction.

[0178] Since the element region AAa has a slightly narrower width than the gate electrode GCa, the rounded corner portion of the gate electrode GCa is separated from the element region AAa, thereby preventing the gate electrode GCa from entering the inner side of the element region AAa.

[0179] Figure 13C shows a cross-section of the narrowed portion SE of the transistor TRa. As shown in Figure 13C, by narrowing in the X direction, the element region AAa of Variation Example 1 has, for example, a width narrower in the X direction than the element region AA of Embodiment 1 described above.

[0180] Furthermore, although it is difficult to discern from Figure 13B, the dimension of the component region AAa in the Y direction is smaller than that of the component region AA in the Y direction in Embodiment 1 described above.

[0181] Figures 14Aa to 14Cb illustrate one example of the manufacturing sequence of the transistor TRa according to Variation 1 of Embodiment 1. In Figures 14Aa to 14Cb, the figure labeled with the lowercase letter "a" is a cross-sectional view along the Y direction of the substrate WF, and the figure labeled with the lowercase letter "b" is a cross-sectional view along the X direction of the substrate WF.

[0182] In the manufacturing steps of transistor TRa in Variation Example 1, the same manufacturing method as that used for transistor TR in Embodiment 1 is employed until the element region AA is formed. Figures 14Aa and 14Ab show the state after the processing of Figures 9Ba and 9Bb in Embodiment 1 has been completed.

[0183] As shown in Figures 14Ba and 14Bb, the manufacturing steps of the transistor TRa in Variation Example 1 include the following steps: side etching is performed on the side of the well AAr on which the element region pattern RSpa is transferred to form an element region AAa with a width in the X direction that is narrower than the width of the gate electrode GCa formed later.

[0184] More specifically, after forming the component region AA, the sides of the component region AA are etched to form a component region AAa that is narrower in the X and Y directions than the component region AA. The sides of the component region AA can be etched by, for example, using the RIE method under conditions that can achieve isotropy.

[0185] At this point, by maintaining the selectivity ratio of each layer except for the well AAr, and processing the element region AA, the sidewalls of the top cap layer CPr, gate electrode layer GCr, and gate insulating layer Goxr, which are processed into shapes that overlap with the element region AA in the stacking direction of each layer, can be prevented from being eroded laterally.

[0186] Furthermore, before removing the component area pattern RSpa, the surface above the top cover layer CPa is protected by the component area pattern RSpa while the component area AA is processed. Therefore, the processing error of the gate electrode GCa and the like can be minimized.

[0187] Therefore, the transistor TRa has a widened portion SE on the X-direction facing side and the Y-direction facing side of the element region AAa. Furthermore, through the processing of the element region AA, the bottom surface of the recess RCw is also slightly etched, and the recess RCw is slightly deepened.

[0188] However, it is also conceivable that the bottom surface of the recess RCw is etched, and the depth is pre-adjusted when the recess RCw is formed, so as to achieve, for example, the same depth as the recess RCw in embodiment 1.

[0189] As shown in Figures 14Ca and 14Cb, after forming the component region AAa, the remaining component region pattern RSpa is removed in the same way as in Embodiment 1 above, and the top cover layer CPa, the metal gate electrode layer GCga, the polycrystalline silicon gate electrode layer GCpa, and the gate insulating layer Goxa are processed sequentially using the gate electrode pattern RSpg.

[0190] In this way, a top cover layer CP, a gate electrode GCa, and a gate insulating layer Gox are formed on the element region AAa. The width of these layers in the X direction is wider than the width of the element region AA, and the center position in the X direction is substantially the same as the center position of the element region AAa.

[0191] Furthermore, the rounded corners of at least one of the polysilicon gate electrode GCp and the metal gate electrode GCg may be generated during the patterning process of the device region AA in Figures 14Aa and 14Ab. Alternatively, the rounded corners of at least one of the polysilicon gate electrode GCp and the metal gate electrode GCg may be generated during the patterning process of the gate electrode GC in Figures 14Ca and 14Cb. Alternatively, the rounded corners of at least one of the polysilicon gate electrode GCp and the metal gate electrode GCg may be generated during both the patterning process of the device region AA and the patterning process of the gate electrode GC.

[0192] At least at the point in time when the processing of Figure 14Ca and Figure 14Cb ends, it becomes a gate electrode GCa with a rounded corner shape RD.

[0193] Then, the same processing as that performed on Figures 10Ba and 10Bb of Embodiment 1 above, and the processing performed on these two figures, is carried out.

[0194] By following the above steps, the transistor TRa of Variation Example 1 is manufactured.

[0195] As mentioned above, for example, sometimes a processing error exceeding a specified value may occur in the gate electrode, causing the gate electrode to not completely cover the component area in the X direction, but instead to enter the inner side of the component area.

[0196] For example, when the gate electrode has a rounded corner shape, causing the apex portion of the gate electrode to extend into the inner side of the device region, the electric field from the gate electrode to the end of the device region that becomes the channel is considered to be weakened. In this case, the controllability of the gate electrode decreases, and the leakage current increases. Furthermore, if the gate electrode has a rounded corner shape, the gate length of that portion is shorter than the specified value. This will also cause an increase in leakage current.

[0197] Furthermore, for example, if lateral etching occurs in the gate electrode, causing the width of the gate electrode in the X direction to be narrower than that of the device region, it may also lead to the gate electrode control being completely ineffective at the X-direction end of the device region. In this case, the current continuously flows through the transistor, thus preventing it from functioning as a transistor.

[0198] According to the transistor TRa of Variation Example 1, in the X direction, the width of the upper surface of the element region AAa is narrower than the width of the gate electrode GCa. This suppresses the gate electrode GCa from entering the inner side of the element region AAa. Therefore, the controllability of the gate electrode GCa can be improved, and the gate length can be ensured to suppress the increase of leakage current in the transistor TRa.

[0199] According to the manufacturing method of transistor TRa in Variation Example 1, the side of the well AAr with the transferred element region pattern is etched to form an element region AAa with a width narrower than that of the gate electrode GCa in the X direction. In this way, the element region AAa with a width narrower than that of the gate electrode GCa can be easily formed based on the gate electrode GCa and the element region AA, which have substantially the same width in the X direction.

[0200] (Variation Example 2)

[0201] Next, the transistor TRb in the semiconductor memory device of Variation 2 of Embodiment 1 will be described using Figures 15A and 15B. Regarding the transistor TRb of Variation 2, the arrangement of the transistors TRb along the Y direction differs from that of Embodiment 1.

[0202] Regarding the latch circuits DL and XDL in the peripheral circuits of the semiconductor memory device 1 in Embodiment 1 described above, there is still room to further reduce the gate width of the transistor TR compared to the gate width of the transistor TR in the sense amplifier circuit SA. Therefore, in the future, it is also possible to consider, for example, arranging the transistors of the sense amplifier circuit SA in a row as described above within a certain number of bit lines BL, and arranging the transistors of the latch circuit in multiple rows. Examples of arranging the transistors of the latch circuit in multiple rows are shown in Figures 15A and 15B.

[0203] Figures 15A and 15B are schematic diagrams illustrating an example of the layout of transistors TRb and TRb' in the semiconductor memory device of Variation 2 and Comparative Example of Embodiment 1. Figure 15A shows the layout of transistor TRb' in the Comparative Example, and Figure 15B shows the layout of transistor TRb in Variation 2. In Figures 15A and 15B, the gate contacts and source / drain contacts connected to transistors TRb and TRb' are omitted.

[0204] As shown in Figures 15A and 15B, the transistors TRb and TRb' in Variation 2 and Comparative Example are arranged in multiple rows within a distance of 16 bit lines BL. As described above, these transistors TRb and TRb' are, for example, transistors belonging to latching circuits.

[0205] As shown in Figure 15A, the comparative example transistor TRb' has gate electrodes GCb' protruding from the element region AAb' at both ends in the X direction. Therefore, in order to ensure the required gate width, and to arrange multiple rows of transistors TRb' within the distance between 16 bit lines BL, the positions of the gate electrodes GCb' in the Y direction of adjacent transistors TRb' in the X direction are staggered. That is, the arrangement of the gate electrodes GCb' in the multiple rows of transistors TRb' is staggered.

[0206] However, if the gate electrodes GCb' are arranged in a misaligned manner, the overall arrangement of the transistor TRb' increases in the Y direction.

[0207] As shown in Figure 15B, the transistor TRb of Variation Example 2 has a gate electrode GCb with a width in the X direction substantially equal to that of the element region AAB. Therefore, even if the required gate width is ensured and multiple rows of transistor TRb are arranged within a distance between 16 bit lines BL, the positions of the gate electrodes GCb in the Y direction can be aligned in adjacent transistor TRb in the X direction. That is, the arrangement of the gate electrodes GCb in the multiple rows of transistor TRb can be set as a grid.

[0208] Thus, by arranging the gate electrodes GCb in a grid pattern, more transistors TRb can be arranged at shorter distances in the Y direction, thereby reducing the size of the transistor TRb arrangement in the Y direction.

[0209] [Implementation Method 2]

[0210] Hereinafter, Embodiment 2 will be described in detail with reference to the accompanying drawings. As will be explained below, the configuration of transistors TR and TRa in Embodiment 1 and Variation 1 can also be applied to the transistors of the column decoder 20.

[0211] (The structure of a column decoder)

[0212] First, the circuit configuration of the column decoder 20 provided in the semiconductor memory device of Embodiment 2 will be described using FIG16. FIG16 is a circuit diagram showing an example of the configuration of the column decoder 20 provided in the semiconductor memory device of Embodiment 2.

[0213] As shown in Figure 16, the semiconductor memory device of Embodiment 2 includes a memory cell array 10 configured in the same way as the semiconductor memory device 1 of Embodiment 1. The sequencer 160 and voltage generation circuit 180 of Embodiment 2 are also configured in the same way as those of Embodiment 1.

[0214] The column decoder 20 in Embodiment 2 includes an address decoder 21, a block selection circuit 22, and a voltage selection circuit 23. Furthermore, in terms of circuit configuration, the column decoder 20 can also be configured without change compared to the column decoder in Embodiment 1.

[0215] The address decoder 21 has a plurality of block select lines BLKSEL and a plurality of voltage select lines VOLSEL.

[0216] Address decoder 21, for example, refers to the address data of the address register (see Figure 1) included in the aforementioned peripheral circuitry, based on the control signal from sequencer 160.

[0217] Furthermore, the address decoder 21 decodes the referenced address data, turning on the transistors TR22 and TR23 corresponding to the address data, and turning off other transistors TR22 and TR23. Moreover, transistors TR22 and TR23 are included in the block selection circuit 22 and voltage selection circuit 23 described below, respectively.

[0218] Furthermore, the address decoder 21 sets the voltage of the block selection line BLKSEL and voltage selection line VOLSEL corresponding to the address data to, for example, "H" state, and sets all other voltages to "L" state. Moreover, the voltage applied to these lines depends on whether an N-channel or P-channel transistor is used in the block selection circuit 22 and voltage selection circuit 23. The above example uses an N-channel voltage transistor.

[0219] In the example of Figure 16, in the address decoder 21, each block BLK within the memory cell array 10 is provided with a block selection line BLKSEL. However, this configuration can be modified appropriately. For example, one block selection line BLKSEL can also be provided for each of two or more blocks BLK.

[0220] The block selection circuit 22 has a plurality of block selection units 220 corresponding to blocks BLK of the memory cell array 10. Each of the plurality of block selection units 220 has a plurality of transistors TR22 corresponding to the word line WL and the select gate line (SGD, SGS).

[0221] The TR22 is a high-voltage N-channel MOS transistor, functioning as a block driver transistor. The drain electrode of the TR22 is electrically connected to the corresponding word line WL or gate select line (SGD, SGS). The source electrode of the TR22 is electrically connected to the voltage output terminal OTM via wiring WR and voltage selection circuit 23. The gate electrode of the TR22 is connected to the corresponding block select line BLKSEL.

[0222] Furthermore, the block selection circuit 22 further includes a plurality of transistors (not shown). These plurality of transistors are high-voltage CMOS transistors connected between the select gate lines (SGD, SGS) and the ground voltage supply terminal. These plurality of transistors turn on the select gate lines (SGD, SGS) and the ground voltage supply terminal in the non-selected block BLK within the memory cell array 10. Moreover, the plurality of word lines WL in the non-selected block BLK are in a floating state.

[0223] The voltage selection circuit 23 has a plurality of voltage selection sections 230 corresponding to the character line WL and the selection gate lines (SGD, SGS). Each of the plurality of voltage selection sections 230 has a plurality of transistors TR23.

[0224] The TR23 is a high-voltage N-channel MOS transistor, functioning as a voltage-selective transistor. The drain terminals of the TR23 are electrically connected to the corresponding word line WL or select gate line (SGD, SGS) via wiring WR and block select circuit 22. The source terminals are electrically connected to the corresponding voltage output terminal OTM. The gate terminals are connected to the corresponding voltage select line VOLSEL.

[0225] Thus, the column decoder 20, which belongs to the peripheral circuit, has a plurality of transistors TR22, TR23, etc. However, the circuit configuration of the column decoder 20 shown in Figure 16 is an example, and the number and types of transistors TR22, TR23, etc. included in the column decoder 20 can also vary.

[0226] (Composition of transistors)

[0227] Next, using Figures 17A and 17B, we will describe an example of the physical configuration of the transistor TR22 included in the column decoder 20 of Embodiment 2.

[0228] Figures 17A and 17B are schematic diagrams illustrating an example of the layout of transistors TRc and TRc' in the semiconductor memory device of Embodiment 2 and the comparative example. Figure 17A shows the layout of transistor TRc in Embodiment 2, and Figure 17B shows the layout of transistor TRc' in the comparative example. The transistor TRc in the figures is included in the block selection circuit 22 of the column decoder 20, and functions as, for example, the aforementioned transistor TR22, which is a block driving transistor.

[0229] As shown in Figure 17A, the transistor TRc of Embodiment 2 is constructed using the same configuration as the transistor TR of Embodiment 1 described above. Specifically, the transistor TRc includes a device region AAc extending along the Y direction and a plurality of gate electrodes GCc disposed on the device region AAc. These plurality of gate electrodes GCc have a width substantially equal to the width of the device region AAc in the X direction. Between adjacent device regions AAc in the X direction, a device separation portion STIc extends along the Y direction.

[0230] A gate contact CGc is connected to the gate electrode GCc of the transistor TRc. The gate contact CGc is connected to the corresponding block select line BLKSEL.

[0231] A source / drain contact CSc is connected to the element region AAc of the transistor TRc. Transistors TRc arranged in a row share a source / drain contact CSc with adjacent transistors TRc in the Y direction. The source / drain contacts CSc on the drain electrode side of the transistor TRc are respectively connected to the corresponding word line WL. The source / drain contacts CSc on the source electrode side of the transistor TRc are respectively connected to the corresponding voltage selection section 230 via wiring WR.

[0232] As shown in Figure 17B, the comparative example transistor TRc' has gate electrodes GCc' protruding from the element region AAc' at both ends in the X direction. Therefore, when the width of the element separation portion STIc' in the X direction of the transistor TRc' is insufficient, the high voltage applied to the gate electrode GCc' may reach the bottom surface of the element separation portion STIc'. In this case, field reversal leakage occurs in the transistor TRc' adjacent in the X direction.

[0233] A high voltage, for example 30 V, is applied to the gate electrode GCc', which serves as the block drive transistor, via the block select line BLKSEL. When this high voltage is applied to the gate electrode GCc', an inversion layer is formed on the bottom surface of the device separation section STIc'. Field inversion leakage is the leakage current flowing through this inversion layer to the adjacent transistor TRc' in the X direction.

[0234] According to the transistor TRc in Embodiment 2, the gate electrode GCc does not have a protruding portion. Therefore, the high voltage applied to the gate electrode GCc is less likely to reach the bottom surface of the element separation section STIc, thereby suppressing field reversal leakage. Furthermore, suppressing field reversal leakage and reducing the width of the element separation section STIc in the X direction facilitates miniaturization of the block selection circuit 22.

[0235] Furthermore, the transistor TR22 included in the block selection circuit 22 of the column decoder 20 may also have the configuration of the transistor TRa of the variation 1 of the above embodiment 1.

[0236] Furthermore, the configuration of transistors TR and TRa in Embodiment 1 and Variation 1 described above can also be applied to other transistors in the column decoder 20. That is, transistor TR23 included in voltage selection circuit 23 or transistor included in block selection circuit 22 and connected between selection gate line (SGD, SGS) and ground voltage supply terminal can also have gate electrodes without the aforementioned protruding portion.

[0237] [Implementation Method 3]

[0238] Hereinafter, Embodiment 3 will be described in detail with reference to the accompanying drawings. As will be explained below, the configuration of transistors TR and TRa in Embodiment 1 and Variation 1 can also be applied to transistors in peripheral circuits of volatile memory such as DRAM (Dynamic Random Access Memory).

[0239] (Brief Structure of a Semiconductor Memory Device)

[0240] First, an example of the configuration of the semiconductor memory device 2 in Embodiment 3 will be described using FIG18. FIG18 is a block diagram of the semiconductor memory device 2 in Embodiment 3.

[0241] As shown in Figure 18, the semiconductor memory device 2 of Embodiment 3 includes peripheral circuits such as a memory cell array 201, an input / output circuit 210, a column decoder 222, a read / write amplifier 233, an instruction decoder 241, a row decoder 250, an instruction address input circuit 260, a clock input circuit 271, an internal clock generation circuit 272, and a voltage generation circuit 280, as well as a plurality of external terminals such as clock terminals CK, CK / , instruction / address terminal CAT, data terminal DQT, data mask terminal DMT, and power terminals VPP, VDD, VSS, VDDQ, and VSSQ.

[0242] The memory cell array 201 includes a plurality of memory banks BNK0-7. Each of the plurality of memory banks BNK0-1 has a plurality of word lines WLv and a plurality of bit lines BLv and / BLv, and a memory cell MCv is disposed at each intersection of the word line WLv and the bit line BLv. The memory cell MCv is configured, for example, as a transistor, to store volatile data. Therefore, in order to maintain the data stored in the memory cell array 201, it is periodically updated. In Figure 18, for ease of explanation, the update circuitry and other components disposed in the DRAM are omitted.

[0243] By incorporating this memory cell MCv, the semiconductor memory device 2 is configured as, for example, DRAM (Dynamic Random Access Memory). Furthermore, the semiconductor memory device 2 can also be configured as other volatile memory such as SRAM (Static RAM).

[0244] The sense amplifier circuit SAMP is configured corresponding to bit lines BLv and / BLv. Furthermore, the sense amplifier circuit SAMP is connected to the local input / output lines LIOT and LIOB via a row switch YSW, and to the main input / output lines MIOT and MIOB via a transmission gate TG. The transmission gate TG functions as a switch. Similar to the sense amplifier circuit SA in Embodiment 1 (see Figure 2), the sense amplifier circuit SAMP senses data read from the memory cell MCv.

[0245] Each of the plurality of memory cells MCv within the memory cell array 201 is associated with a memory address. Among the plurality of external terminals, the instruction / address terminal CAT receives the memory address from an external device such as a memory controller. The memory address received by the instruction / address terminal CAT is transmitted to the instruction address input circuit 260. When the instruction address input circuit 260 receives the memory address, it sends the decoded column address XADD to the column decoder 222 and the decoded row address YADD to the row decoder 250.

[0246] Furthermore, the instruction / address terminal CAT receives instructions, for example, from a memory controller. The instructions received by the instruction / address terminal CAT are sent as internal instruction signals ICMD to the instruction decoder 241 via the instruction address input circuit 260.

[0247] The instruction decoder 241 includes circuitry for decoding the internal instruction ICMD to generate signals for executing the internal instruction. For example, the instruction decoder 241 sends the initiated instruction ACT and the update instruction AREF to the column decoder 222. The column decoder 222 is connected to the character line WLv and selects the character line WLv based on the instruction ACT and update instruction AREF received from the instruction decoder 241.

[0248] Furthermore, instruction decoder 241, for example, sends read / write instructions R / W to line decoder 250. Line decoder 250 is connected to bit line BLv and selects bit line BLv according to the read / write instructions R / W received from instruction decoder 241.

[0249] When reading data, the instruction / address terminal CAT receives the read instruction and the memory address. Data is then read from the memory cell MCv within the memory cell array 201 specified by the memory address. The read data is output to the outside via the data terminal DQT through the read / write amplifier 233 and the input / output circuit 210.

[0250] During data writing, the instruction / address terminal CAT receives the write instruction and the memory address, and the data terminal DQT receives the write data. Additionally, a data mask is sent to the data mask terminal DMT as needed. The write data is sent to the memory cell array 201 via the input / output circuit 210 and the read / write amplifier 233. Thus, the write data is written to the memory cell MCv specified by the memory address.

[0251] The read / write amplifier 233 has various latching circuits for temporarily storing read data and writing data. The read / write amplifier 233 and the sense amplifier circuit SAMP form a configuration equivalent to the sense amplifier module 30 and data temporary register 40 in Embodiment 1 above (see Figure 1).

[0252] A power supply voltage is supplied to the power terminals VDD and VSS, which is then supplied to the voltage generation circuit 280. The voltage generation circuit 280 generates various internal voltages VPP, VOD, VARY, and VPERI based on the power supply voltage. The internal voltage VPP is mainly used in the column decoder 222, the internal voltages VOD and VARY are mainly used in the sense amplifier circuit SAMP of the memory cell array 201, and the internal voltage VPERI is used in other peripheral circuit blocks.

[0253] Furthermore, a power supply voltage is also supplied to the power terminals VDDQ and VSSQ, which is then supplied to the input / output circuit 210. A dedicated power supply voltage is applied to the power terminals VDDQ and VSSQ to prevent power noise generated in the input / output circuit 210 from propagating to other circuit blocks. Moreover, the power supply voltage supplied to the power terminals VDDQ and VSSQ can be the same voltage supplied to the power terminals VDD and VSS.

[0254] External clock signals are input to the clock terminals CK and / CK, which are complementary. These external clock signals are supplied to the clock input circuit 271. The clock input circuit 271 generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generation circuit 272 and the instruction decoder 241.

[0255] When the internal clock generation circuit 272 is activated by the clock enable CKE from the instruction address input circuit 260, it generates various internal clock signals LCLK. The internal clock signals LCLK are used to measure the timing of various internal actions. For example, the internal clock signals LCLK are output to the input / output circuit 210. The input / output circuit 210 operates based on the input internal clock signals LCLK, thereby sending and receiving data at the data terminal DQT.

[0256] (Structure of a sensing amplifier circuit)

[0257] Next, using FIG19, an example of the configuration of the sense amplifier circuit SAMP included in the semiconductor memory device 2 of Embodiment 3 will be described. FIG19 is a circuit diagram showing an example of the circuit configuration of the sense amplifier circuit SAMP included in the semiconductor memory device 2 of Embodiment 3.

[0258] As shown in Figure 19, the bit line BLv connected to the memory cell MCv and the bit line / BLv paired with the bit line BLv are connected to the sense amplifier circuit SAMP within the memory cell array 201.

[0259] The sense amplifier circuit (SAMP) includes transistors TR51 to TR54. Transistors TR51 and TR53 are low-voltage P-channel MOS transistors, while transistors TR52 and TR54 are low-voltage N-channel MOS transistors.

[0260] One end of transistor TR51 is connected to the signal line supplying the sensing signal SAP, and the other end is connected to one end of transistor TR52. The other end of transistor TR52 is connected to the signal line supplying the sensing signal SAN. A bit line BLv is connected between transistors TR51 and TR52.

[0261] One end of transistor TR53 is connected to the signal line supplying the sensing signal SAP, and the other end is connected to one end of transistor TR54. The other end of transistor TR54 is connected to the signal line supplying the sensing signal SAN. A bit line / BLv is connected between transistors TR53 and TR54.

[0262] Furthermore, the gate electrodes of transistors TR51 and TR52 are connected between transistors TR53 and TR54, and the gate electrodes of transistors TR53 and TR54 are connected between transistors TR51 and TR52.

[0263] A horizontal switch YSW is connected to the bit lines BLv and / BLv, which are located downstream of the sense amplifier circuit SAMP. The horizontal switch YSW includes transistors TR71 and TR72. Transistors TR71 and TR72 are low-voltage N-channel MOS transistors.

[0264] One end of transistor TR71 is connected to bit line BLv, and the other end is connected to local input / output line LIOB. One end of transistor TR72 is connected to bit line / BLv, and the other end is connected to local input / output line LIOT. The gate electrodes of transistors TR71 and TR72 are connected to the signal line supplying the row selection signal YS.

[0265] The bit lines BLv and / BLv, which are located further downstream of the row switch YSW, are connected to the equalization circuit EQ.

[0266] The equalization circuit (EQ) includes transistors TR81 to TR83. Transistors TR81 to TR83 are low-voltage N-channel MOS transistors.

[0267] One end of transistor TR81 is connected to bit line BLv, and the other end is connected to transistor TR82. The other end of transistor TR82 is connected to bit line / BLv. A power supply line for the equalization voltage BVBLEQ is connected between transistors TR81 and TR82. The magnitude of the equalization voltage BVBLEQ is half of the power supply voltage VDDSA used in the sense amplifier circuit SAMP.

[0268] One end of the transistor TR83 is connected to bit line BLv, and the other end is connected to bit line / BLv.

[0269] The gate electrodes of transistors TR81 to TR83 are connected to the signal line that supplies the equalization signal BLEQ.

[0270] Next, the operation of the circuit including the aforementioned sensing amplifier circuit SAMP will be briefly explained.

[0271] Normally, under steady-state conditions, the equalization signal BLEQ is driven to a high level. This activates transistors TR81~TR83 in the equalization circuit EQ, causing bit lines BLv and / BLv to be equalized to pre-charge potentials.

[0272] Subsequently, upon issuing the activation command, the equalization is deactivated, and the corresponding character line WL is driven to the VPP level based on the input column address XADD. The deactivation of equalization, i.e., the inactive state of the equalization circuit EQ, continues from the issuance of the activation command until the issuance of the precharge command.

[0273] Since the word line WL is driven to the VPP level, the transistor of the corresponding memory cell MCv is turned on. Therefore, the cell capacitor of the memory cell MCv is connected to the bit line BLv or bit line / BLv. As a result, the potential of the bit line BLv or bit line / BLv changes slightly depending on the cell voltage VCEL of the memory cell MCv. The example in Figure 19 shows the case where the potential of the bit line BLv increases slightly.

[0274] Subsequently, at a specific timing, the sensing signals SAN and SAP change to low and high levels, respectively, activating the sensing amplifier circuit SAMP. As a result, the potential difference between bit lines BLv and / BLv is amplified. In the example of Figure 19, the case where bit line / BL is driven to a low level and bit line BL is driven to a high level is shown.

[0275] Subsequently, when a read command is issued, the corresponding row selection signal YS is changed to a high level according to the row address YADD input synchronously with the read command. At the point in time before the row selection signal YS is activated, the local input / output lines LIOT and LIOB are pre-charged to the power supply voltage VCC.

[0276] When the row selection signal YS is activated, transistors TR71 and TR72 of the row switch YSW are turned on. Therefore, bit lines BL and / BL are connected to the corresponding local input / output lines LIOB and LIOT. As a result, local input / output line LIOB remains at the precharge level, while local input / output line LIOT drops from the precharge level to a low level.

[0277] Through the above steps, data is read from the memory cell MCv.

[0278] (Composition of transistors)

[0279] Next, using Figures 20A and 20B, we will describe an example of the physical configuration of the transistor TRd included in the sense amplifier circuit SAMP of Embodiment 3.

[0280] Figure 20A is a schematic diagram showing an example of the layout of the transistor TRd in the semiconductor memory device of Embodiment 3, and Figure 20B is a schematic diagram showing an example of the layout of the transistor TRd' in the comparative example.

[0281] As shown in Figure 20A, in the sense amplifier circuit SAMP, a plurality of transistors TRd each have a plurality of element regions AAd arranged in a grid pattern along the X and Y directions. The plurality of element regions AAd are electrically separated from each other by element separation sections STId.

[0282] On each element region AAd, a plurality of gate electrodes GCd are arranged along the X direction. In the example of Figure 20A, two gate electrodes GCd are arranged on element region AAd. Furthermore, element region AAd extends along the Y direction in the region sandwiched between the two gate electrodes GCd and is connected to adjacent element regions AAd.

[0283] The transistor TRd of the sense amplifier circuit SAMP in Embodiment 3 is configured using the same structure as the transistor TR in Embodiment 1. Specifically, in the transistor TRd, a plurality of gate electrodes GCd have a width substantially equal to the width of the element region AAD in the Y direction. In other words, in the transistor TRd of Embodiment 3, the plurality of gate electrodes GCd also have a gate width substantially equal to the width of the element region AAD in the Y direction.

[0284] A gate contact CGd is connected to the gate electrode GCd of the transistor TRd. A source / drain contact CSd is connected to the element region AAD of the transistor TRd. Transistors TRd arranged along the X direction share the source / drain contact CSd with adjacent transistors TRd. The source / drain contact CSd is also located in the connection portion of the element regions AAD that are connected to each other in the Y direction.

[0285] In a plurality of source / drain contacts CSd, the source / drain contacts CSd at one end of the transistor TRd located on one side of the X direction are connected to bit lines BL. The source / drain contacts CSd at the other end of the transistor TRd located on the other side of the X direction are connected to bit lines / BL. Figure 20A shows the case where the transistor TRd of one of the two element regions AAD arranged along the X direction is connected to the bit lines BL and / BL.

[0286] Adjacent transistors TRd in the X direction share a common source / drain contact CSd, which is connected to either the signal line supplying the sensing signal SAP or the signal line supplying the sensing signal SAN. Specifically, when the transistor TRd is a P-channel MOS transistor, the source / drain contact CSd is connected to the signal line supplying the sensing signal SAP. When the transistor TRd is an N-channel MOS transistor, the source / drain contact CSd is connected to the signal line supplying the sensing signal SAN.

[0287] When connected to the signal lines of the sensing signal SAP / SAN, the source / drain contact CSd is led out to the upper layer and then connected to any one of the signal lines extending along the X direction. That is, these signal lines are configured on different layers from the aforementioned bit lines BL and / BL. Figure 20A shows the case where the transistor TRd in one of the two element regions AAD arranged along the X direction is connected to the signal lines of the sensing signal SAP / SAN.

[0288] As shown in Figure 20B, the comparative example transistor TRd' has gate electrodes GCd' protruding from the element region AAD' at both ends in the Y direction.

[0289] According to embodiment 3, the gate electrode GCd of the transistor TRd does not have a protruding portion. This allows for a reduction in the area of ​​the transistor TRd. Furthermore, by reducing the size of the transistor TRd, design freedom is increased, making miniaturization of the semiconductor memory device 3 easier.

[0290] Furthermore, the sensing amplifier circuit SAMP of Embodiment 3 may also include a transistor configured using the transistor TRa of Variation 1 of Embodiment 1. Also, the configuration of the transistor TR of Embodiment 1 and Variation 1 described above can also be applied to the transistor included in the column decoder 222 of Embodiment 3.

[0291] In embodiments 1 to 3 described above, transistors TR, TRa to TRd are disposed on a substrate WF such as a silicon substrate. However, the substrate WF may not be a semiconductor substrate, and transistors TR, TRa to TRd may be configured to include a semiconductor layer formed on the substrate WF. In this case, the element regions AA, AAa to AAd of transistors TR, TRa to TRd are disposed on the semiconductor layer.

[0292] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0293] [Related Applications]

[0294] This application enjoys the benefit of priority to Japanese Patent Application No. 2021-99736, filed on June 15, 2021, the entire contents of which are incorporated herein by reference.

[0295] 1: Semiconductor memory devices 2: Semiconductor memory devices 10: Memory Cell Array 20: Column Decoder 21: Address Decoder 22: Block Selection Circuit 23: Voltage Selection Circuit 30: Sensing Amplifier Module 40: Data Temporary Memory 50: Line Decoder 110: Input / output circuit 120: Logic control circuit 130: Status Register 140: Address Register 150: Instruction Register 160: Sequencer 170: Ready / Busy Circuit 180: Voltage generation circuit 201: Memory Cell Array 210: Input / output circuit 220: Block Selection Department 222: Column Decoder 230: Voltage Selection Section 233: Read / Write Amplifier 241: Instruction Decoder 250: Line Decoder 260: Instruction address input circuit 271: Clock Input Circuit 272: Internal clock generation circuit 280: Voltage generation circuit AA: Component Area AA': Component area AAa: Component area AAb: Component Area AAb': Component area AAc: Component Area AAc': Component area AAd: Component Area AAd': Component area AAr: Well ACT: Instructions ADD: address ALE: Address latch enable signal AREF: Update command BL: Bitline BLC: Control Signal BLEQ: Equalized signal BLK: Block BLK0~BLKn: Blocks BLKSEL: Block Selection Line BLX: Control signal BLv:bitline / BL:bitline / BLv:bitline BNK0~7: Memory Bank CA: Row Address CAP: Capacitor CAT: Command / Address Terminal CEn: Chip Enable Signal CG: Gate Contact CG': Gate contact CGc: Gate contact CGd: Gate contact CK: Clock terminal CK / : Clock terminal CKE: Time Capsule Empowerment CLE: Instruction Latch Enable Signal CLK: Clock CMD command COM: Node CP: Top Cover Layer CPa: Top layer CPr: Top cap layer CS: Source / Drain junction CSc: Source / Drain Junction CSd: source / drain contact DAT: Data DMT: Data Mask Terminal DQ0~DQ7: Signals DQT: Data Terminal DL: Latch circuit EQ: Equalization circuit GC: Gate electrode GC': Gate electrode GCa: Gate electrode GCb: Gate electrode GCb': Gate electrode GCaa: Gate electrode layer GCc: Gate electrode GCc': Gate electrode GCd: Gate electrode GCd': Gate electrode GCm: Metal gate electrode GCmr: Metal gate electrode layer GCp: Polycrystalline silicon gate electrode GCpa: Polycrystalline silicon gate electrode layer GCpr: Polycrystalline silicon gate electrode layer GCr: Gate electrode layer Gox: Gate insulation layer Goxa: Gate insulation layer Goxr: Gate insulation layer HLL: Control Signal ICMD: Internal Command Signal ICLK: Internal Clock Signal ILD: Interlayer Insulation Layer INV: Node IVa: Inverter IVb: Inverter L: Gate length LAT: Node LBUS: Bus LCLK: Internal clock signal LIOB: Local Input / Output Line LIOT: Local Input / Output Line LR: Liner MC: Memory Cell MCv: memory cell MIOB: Main Input / Output Line MIOT: Main Input / Output Line MS: Memory String NL: Silicon Nitride Layer OL: Silicon oxide layer OPaa: Opening OPgc: Opening OTM: Voltage Output Terminal PT: Pattern PTaa: Component Area Pattern PTgc: Gate electrode pattern R / Bn: Ready / Busy Signal RA: Column address RCw: concave part RD: Read out the data REn: Read out the enable signal RLT: Resist Residue Layer RS: Anti-corrosion layer RSp: Anti-corrosion pattern RSpa: Component Area Pattern RSpg: Gate electrode pattern R / W: Read / Write command SA: Sensing amplifier circuit SA / DL <0> ~SA / DL <15> :group SAMP: Sensing Amplifier Circuit SAN: Sensing signal SAP: Sensing signal SAP / SAN: Sensing Signals SB: transparent substrate SBt: Transfer surface SE: Width Reduction Section SEN: node SGD: Select Gate Line SGS: Select Gate Line SL: Source Line SRC: Node STB: Control Signal STD: Drain Select Transistor STI: Control Signal STI': Component Separation Section STIc: Component Separation Section STIc': Component Separation Section STId: Component Separation Section STL: Control Signal STS: Status Information SU: Serial unit SWa: Sidewall SWg: Sidewall SWga: Sidewall SWr: Sidewall layer TG: Transmission Gate TM: Template TR: Transistor TR': Transistor TRb: Transistor TRb': Transistor TRc: Transistor TRc': Transistor TRd: Transistor TRd': Transistor TR22: Transistor TR23: Transistor TR31~TR38: Transistors TR41: Transistor TR42: Transistor TR51~TR54: Transistors TR71: Transistor TR72: Transistor TR81~TR83: Transistors TRa: Transistor VARY: Internal voltage VBLEQ: Equalizing Voltage VCEL: Cell Voltage Vdd: Power supply voltage VDD: Power terminal VDDQ: Power terminal VDDSA: Power supply voltage VOD: Internal Voltage VPERI: Internal Voltage VPP: Internal Voltage VSS: Power terminal VSSQ: Power terminal VOLSEL: Voltage Selection Line W: Gate width W': Gate width WD: Write data WEn: Write enable signal WF: substrate WL: Character Line WLv: Character Line WR: Wiring XADD: Column address XDL: Latch circuit XDL <0> ~XDL <15> Latch circuit XXL: Control signal YADD: row address YS: Row Selection Signal YSW: Row Switch

Claims

1. A semiconductor device comprising: a semiconductor layer; a first element separation portion disposed on a surface of the semiconductor layer; a first source / drain region disposed on the surface of the semiconductor layer; a second source / drain region disposed on the surface of the semiconductor layer; a third source / drain region disposed on the surface of the semiconductor layer; a first source / drain contact connected to the first source / drain region; a second source / drain contact connected to the second source / drain region; a third source / drain contact connected to the third source / drain region; and a first gate stack disposed on the surface of the semiconductor layer. The second gate stack is disposed on the surface of the semiconductor layer; and the substrate extends from the bottom of the first element separation portion, across the first source / drain region, the first gate stack, and the second source / drain region, to the top of the second gate stack; wherein the first element separation portion, the first source / drain contact, the first gate stack, the second source / drain contact, the second gate stack, and the third source / drain contact are arranged in this order in the first direction.

2. The semiconductor device of claim 1, wherein the liner contacts the top of the first gate stack.

3. The semiconductor device of claim 1, wherein the substrate comprises a silicon nitride layer.

4. The semiconductor device of claim 1, wherein the first gate stack includes a first metal gate electrode, and the second gate stack includes a second metal gate electrode.

5. The semiconductor device of claim 4, further comprising: a first gate contact connected to the first metal gate electrode, wherein the liner contacts the top of the second gate stack.

6. The semiconductor device of claim 1, wherein the first gate stack includes a first metal gate electrode and a first top cap layer.

7. The semiconductor device of claim 6, wherein the first top cover layer comprises a silicon nitride layer.

8. The semiconductor device of claim 6, wherein the liner contacts the top of the first capping layer.

9. The semiconductor device of claim 1, wherein the first gate stack comprises: Includes a stacked gate electrode layer of the first metal gate electrode.

10. The semiconductor device of claim 1, wherein, when viewed from a second direction perpendicular to the surface of the semiconductor layer, the boundary of the first gate stack in the first direction is located within the boundary of the first source / drain region in the first direction.

11. The semiconductor device of claim 1, wherein, when viewed from a second direction perpendicular to the surface of the semiconductor layer, the first gate stack at its end position in a third direction perpendicular to the first direction and the first source / drain region at its end position in the third direction overlap.

12. The semiconductor device of claim 1, further comprising: an insulating layer on the substrate, wherein the substrate separates the first source / drain region, the second source / drain region, the third source / drain region, the first gate stack and the second gate stack from the insulating layer.

13. The semiconductor device of claim 1, further comprising: a first transistor including the first source / drain region, the second source / drain region, and the first gate stack; a second transistor including the second source / drain region, the third source / drain region, and the second gate stack; and a third transistor including the third source / drain region, wherein the second source / drain region is shared by the first transistor and the second transistor, and the third source / drain region is shared by the second transistor and the third transistor.

14. The semiconductor device of claim 1, further comprising: a plurality of first source / drain regions including the aforementioned first source / drain regions, which are disposed in a third direction perpendicular to the aforementioned first direction; a plurality of second source / drain regions including the aforementioned second source / drain regions, which are disposed in the aforementioned third direction; and a plurality of second element separation portions disposed on the aforementioned surface of the aforementioned semiconductor layer, which are disposed in the aforementioned third direction; wherein each of the plurality of first source / drain regions and each of the plurality of second element separation portions are alternately disposed in the aforementioned third direction, and each of the plurality of second source / drain regions and each of the plurality of second element separation portions are alternately disposed in the aforementioned third direction.

15. The semiconductor device of claim 14, further comprising: a plurality of first gate stacks, including the first gate stacks, wherein the plurality of first gate stacks are disposed in the third direction.

16. The semiconductor device of claim 15, further comprising: a fourth source / drain region disposed on the surface of the semiconductor layer; a fourth source / drain contact connected to the fourth source / drain region; and a third gate stack disposed on the surface of the semiconductor layer; and a third element separation portion disposed on the surface of the semiconductor layer; wherein the third source / drain contact, the third gate stack, the fourth source / drain contact, and the third element separation portion are arranged in that order in the first direction, and the substrate extends beyond the third source / drain region, the third gate stack, and the fourth source / drain region to the bottom of the third element separation portion.

17. The semiconductor device of claim 1, further comprising: a plurality of gate stacks, including the first gate stack and the second gate stack, wherein the plurality of gate stacks are configured in a grid pattern.

18. The semiconductor device of claim 1 further includes: a first power supply terminal; a second power supply terminal; and a third power supply terminal.

19. The semiconductor device of claim 18 further includes: a fourth power supply terminal; and a fifth power supply terminal.

20. The semiconductor device of claim 1 further includes: an internal clock generation circuit.