Systems and methods for process-induced displacement characterization during semiconductor production

Abstract

A controller is configured to: perform at least one first characterization process on a semiconductor wafer prior to at least one patterned back-side film deposition process; perform at least one additional characterization process after the at least one patterned back-side film deposition process; determine, based on at least the first characterization process and at least the additional characterization process, at least one of a film force or at least one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer by the at least one patterned back-side film deposition process; and provide the film force or at least one of the in-plane displacements to at least one process tool via at least one feedforward loop or at least one feedback loop to improve the performance of one or more fabrication processes.

Description

[Technical Field] This invention relates generally to the manufacture of semiconductor devices, and more specifically to the characterization of process-induced displacement during semiconductor manufacturing. [Previous Technology] The fabrication of semiconductor devices, such as logic and memory devices, typically involves processing a semiconductor device using numerous fabrication and characterization processes to form various features and multiple layers. The chosen fabrication process utilizes photomasks / reduction masks to print features onto a semiconductor device, such as a wafer. As semiconductor devices become increasingly smaller laterally and extend vertically, the development of enhanced characterization processes with increased sensitivity and throughput becomes crucial. A semiconductor device fabrication technique includes fabricating a semiconductor device by depositing films to form layers on one or more surfaces. Semiconductor devices are typically fabricated to meet a selected set of device shape and / or size requirements (e.g., wafer flatness or wafer thickness). Variations in the film force / stress of the deposited films can induce in-plane displacement / deformation (IPD) of the semiconductor device, characterized as a stacking error. One approach to monitoring and controlling film force / stress-induced IPD involves characterizing changes in wafer geometry and applying board theory to convert these characterizations into overlay errors. Conventional wafer geometry fabrication processes involve two characterizations of the semiconductor device. The first characterization occurs at the beginning of a layer, before a first fabrication process (e.g., lithography). The second characterization occurs at the end of the layer, before a second fabrication process (e.g., lithography). Using these two characterizations, the overall change in wafer geometry for that layer can be determined. This conventional method can be used in a set of fabrication processes that induce only membrane force / stress changes on a front membrane (e.g., discrete front membrane processes). Similarly, it can be used in a set of fabrication processes that induce only membrane force / stress changes on a back membrane (e.g., discrete back membrane processes). However, this conventional method cannot be used in a set of fabrication processes that induce membrane force / stress changes on both a front and a back membrane (e.g., parallel front and back membrane processes). This is because when determining overlay errors (e.g., residual back membrane changes to a front membrane process, or vice versa), the method cannot take into account the parallel changes in residual stress. In this respect, the accuracy of overlay error estimation is significantly reduced. Therefore, it would be advantageous to provide a system and method that addresses the aforementioned shortcomings. [Summary of the Invention] A system according to one or more embodiments of the present invention is disclosed. In one embodiment, the system includes a controller. In another embodiment, the controller includes one or more processors and memory configured to store one or more program instruction sets. In another embodiment, the one or more processors are configured to execute the one or more program instruction sets. In another embodiment, the one or more program instruction sets are configured to cause the one or more processors to perform at least one first characterization process on a semiconductor wafer via one or more characterization subsystems prior to at least one discrete back-side film deposition process. In another embodiment, the one or more program instruction sets are configured to cause the one or more processors to perform at least one additional characterization process on the semiconductor wafer via one or more characterization subsystems after the at least one discrete back-side film deposition process. In another embodiment, the one or more instruction sets are configured to cause the one or more processors to determine, based on at least the first characterization process and at least the additional characterization process, at least one of a film force or one or more in-plane displacements of at least one discrete back-side film deposited on the semiconductor wafer via the at least one discrete back-side film deposition process. In another embodiment, the one or more instruction sets are configured to cause the one or more processors to provide the film force or at least one of the one or more in-plane displacements to at least one process tool via at least one feedforward loop or one feedback loop to improve the performance of one or more fabrication processes. In another embodiment, at least one of the first characterization process or at least one of the additional characterization processes includes at least one of one or more film property characterization processes or at least one of one or more intensity spectrum characterization processes. A system according to one or more embodiments of the present invention is disclosed. In one embodiment, the system includes a characterization subsystem. In another embodiment, the system includes a controller. In another embodiment, the controller includes one or more processors and memory configured to store one or more program instruction sets. In another embodiment, the one or more processors are configured to execute the one or more program instruction sets. In another embodiment, the one or more program instruction sets are configured to cause the one or more processors to perform at least one first characterization process on a semiconductor wafer via the one or more characterization subsystems prior to at least one discrete back-side film deposition process. In another embodiment, the one or more program instruction sets are configured to cause the one or more processors to perform at least one additional characterization process on the semiconductor wafer via the one or more characterization subsystems after the at least one discrete back-side film deposition process. In another embodiment, the one or more instruction sets are configured to cause the one or more processors to determine, based on at least the first characterization process and at least the additional characterization process, at least one of a film force or one or more in-plane displacements of at least one discrete back-side film deposited on the semiconductor wafer via the at least one discrete back-side film deposition process. In another embodiment, the one or more instruction sets are configured to cause the one or more processors to provide the film force or at least one of the one or more in-plane displacements to at least one process tool via at least one feedforward loop or one feedback loop to improve the performance of one or more fabrication processes. In another embodiment, at least one of the first characterization process or at least one of the additional characterization processes includes at least one of one or more film property characterization processes or at least one of one or more intensity spectrum characterization processes. This invention discloses a method according to one or more embodiments of the present invention. In one embodiment, the method may include, but is not limited to, performing at least one first characterization process on a semiconductor wafer via one or more characterization subsystems prior to at least one discrete back-side film deposition process. In another embodiment, the method may include, but is not limited to, performing at least one additional characterization process on the semiconductor wafer via the one or more characterization subsystems after the at least one discrete back-side film deposition process. In another embodiment, the method may include, but is not limited to, determining, based on at least the first characterization process and at least the additional characterization process, at least one of a film force or one or more in-plane displacements of at least one discrete back-side film deposited on the semiconductor wafer via the at least one discrete back-side film deposition process. In another embodiment, the method may include, but is not limited to, providing the film force or at least one of the one or more in-plane displacements to at least one process tool via at least one feedforward loop or one feedback loop to improve the performance of one or more fabrication processes. In another embodiment, at least one of the first characterization process or at least one of the additional characterization processes includes one or more membrane property characterization processes or one or more intensity spectrum characterization processes. A system according to one or more embodiments of the present invention is disclosed. In one embodiment, the system includes a controller. In another embodiment, the controller includes one or more processors and memory configured to store one or more program instruction sets. In another embodiment, the one or more processors are configured to execute the one or more program instruction sets. In another embodiment, the one or more program instruction sets are configured to cause the one or more processors to perform at least one first characterization process on a semiconductor wafer via one or more characterization subsystems prior to at least one discrete back-side film deposition process. In another embodiment, the one or more program instruction sets are configured to cause the one or more processors to perform at least one additional characterization process on the semiconductor wafer via one or more characterization subsystems after the at least one discrete back-side film deposition process. In another embodiment, the one or more instruction sets are configured to cause the one or more processors to determine, based on at least the first characterization process and at least the additional characterization process, at least one of a film force or one or more in-plane displacements of at least one discrete back-side film deposited on the semiconductor wafer via the at least one discrete back-side film deposition process. In another embodiment, the one or more instruction sets are configured to cause the one or more processors to provide the film force or at least one of the in-plane displacements to at least one process tool via at least one feedforward loop or one feedback loop to improve the performance of one or more fabrication processes. In another embodiment, at least the first characterization process and at least the additional characterization process include one or more wafer geometry characterization processes. A system according to one or more embodiments of the present invention is disclosed. In one embodiment, the system includes a characterization subsystem. In another embodiment, the system includes a controller. In another embodiment, the controller includes one or more processors and memory configured to store one or more program instruction sets. In another embodiment, the one or more processors are configured to execute the one or more program instruction sets. In another embodiment, the one or more program instruction sets are configured to cause the one or more processors to perform at least one first characterization process on a semiconductor wafer via one or more characterization subsystems prior to at least one discrete back-side film deposition process. In another embodiment, the one or more program instruction sets are configured to cause the one or more processors to perform at least one additional characterization process on the semiconductor wafer via one or more characterization subsystems after the at least one discrete back-side film deposition process. In another embodiment, the one or more instruction sets are configured to cause the one or more processors to determine, based on at least the first characterization process and at least the additional characterization process, at least one of a film force or one or more in-plane displacements of at least one discrete back-side film deposited on the semiconductor wafer via the at least one discrete back-side film deposition process. In another embodiment, the one or more instruction sets are configured to cause the one or more processors to provide the film force or at least one of the in-plane displacements to at least one process tool via at least one feedforward loop or one feedback loop to improve the performance of one or more fabrication processes. In another embodiment, at least the first characterization process and at least the additional characterization process include one or more wafer geometry characterization processes. This invention discloses a method according to one or more embodiments of the present invention. In one embodiment, the method may include, but is not limited to, performing at least one first characterization process on a semiconductor wafer via one or more characterization subsystems prior to at least one discrete back-side film deposition process. In another embodiment, the method may include, but is not limited to, performing at least one additional characterization process on the semiconductor wafer via the one or more characterization subsystems after the at least one discrete back-side film deposition process. In another embodiment, the method may include, but is not limited to, determining, based on at least the first characterization process and at least the additional characterization process, at least one of a film force or at least one or more in-plane displacements of at least one discrete back-side film deposited on the semiconductor wafer via the at least one discrete back-side film deposition process. In another embodiment, the method may include, but is not limited to, providing at least one of the film force or at least one of the in-plane displacements to at least one process tool via at least one feedforward loop or at least one feedback loop to improve the performance of one or more fabrication processes. In another embodiment, at least the first characterization process and at least the additional characterization process include one or more wafer geometry characterization processes.

Implementation Method

Claims

1. A system for characterizing process-induced displacement during semiconductor manufacturing, comprising: A controller, wherein the controller includes one or more processors and memory configured to store one or more program instruction sets, wherein the one or more processors are configured to execute the one or more program instruction sets, wherein the one or more program instruction sets are configured to cause the one or more processors to: perform a first wafer geometry characterization process on a semiconductor wafer via at least one interferometer tool of one or more characterization subsystems prior to a first lithography process; and perform at least one characterization process on the semiconductor wafer via at least one reflection mode characterization tool of one or more characterization subsystems after the first lithography process and before at least one patterned backside film deposition process, wherein the at least one characterization process includes a film property characterization process or an intensity spectra characterization process; After the at least one patterned back-side film deposition process and before a second lithography process, at least one additional characterization process is performed on the semiconductor wafer via the at least one reflection mode characterization tool of the one or more characterization subsystems, wherein the at least one additional characterization process includes a film property characterization process or an intensity spectrum characterization process; before the second lithography process, a second wafer geometry characterization process is performed on the semiconductor wafer via the at least one interferometer tool of the one or more characterization subsystems; based on the first wafer geometry characterization process, the at least one characterization process, the at least one additional characterization process, and the second wafer geometry characterization process, a film force or at least one of one or more in-plane displacements of the at least one patterned back-side film deposited on the semiconductor wafer by the at least one patterned back-side film deposition process is determined; and the film force or at least one of the one or more in-plane displacements is provided to at least one process tool via at least one feedforward loop or a feedback loop to improve the performance of one or more fabrication processes.

2. The system of claim 1, wherein the one or more film property characterization processes are configured to characterize a thickness, a real component of a refractive index and a complex component of the refractive index of the at least one patterned backside film deposited on the semiconductor wafer via the at least one patterned backside film deposition process.

3. The system of claim 2, wherein the refractive index of the semiconductor wafer is calibrated with respect to reference data obtained for a set of calibration wafers.

4. The system of claim 1, wherein the at least one characterization process or at least one of the additional characterization processes further includes performing one or more wafer geometric characterization processes on the semiconductor wafer via the at least one interferometer tool of the one or more geometric characterization subsystems.

5. The system of claim 4, wherein the at least one process tool is configured to perform the one or more fabrication processes on the semiconductor wafer.

6. The system of claim 5, wherein the at least one process tool includes at least one film deposition tool configured to perform one or more patterned front-side film deposition processes on the semiconductor wafer.

7. The system of claim 5, wherein the at least one process tool includes at least one film deposition tool configured to perform one or more patterned back-side film deposition processes on the semiconductor wafer.

8. The system of claim 5, wherein the at least one process tool includes at least one lithography tool configured to perform one or more lithography processes on the semiconductor wafer.

9. The system of claim 8, wherein the one or more program instruction sets are further configured to cause the one or more processors to: provide the film force or at least one of the one or more in-plane displacements to the one or more characterization subsystems via at least one of the feedforward loop or the feedback loop to improve the performance of the first wafer geometry characterization process or the at least the additional characterization process.

10. The system of claim 5, wherein the semiconductor wafer is transferred between one or more characterization subsystems and the at least one process tool for the first wafer geometry characterization process, the first lithography process, the at least one characterization process, the at least one patterned backside film deposition process, the at least one additional characterization process, the second wafer geometry characterization process and the second lithography process.

11. The system of claim 10, wherein the semiconductor wafer is transferred between one or more characterization subsystems and the at least one process tool for the first wafer geometry characterization process, the first lithography process, the at least one characterization process, the at least one patterned back-side film deposition process, the at least one patterned front-side film deposition process, the at least one additional characterization process, the second wafer geometry characterization process and the second lithography process.

12. The system of claim 1, wherein the at least one reflection mode characterization tool and the at least one interferometer tool are integrated characterization tools within the characterization subsystem.

13. The system of claim 1, wherein the at least one reflection mode characterization tool and the at least one interferometer tool are independent characterization tools within the characterization subsystem.

14. The system of claim 1, wherein data from the at least one characterization process or at least one of the at least additional characterization processes is input into a learning algorithm, wherein the learning algorithm generates a learning model based on reference data and data from the at least one characterization process or at least one of the additional characterization processes, wherein the learning model determines at least one of the film forces or one or more in-plane displacements of the at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process.

15. A system for characterizing process-induced displacement during semiconductor manufacturing, comprising: One or more characterization subsystems; And a controller, wherein the controller includes one or more processors and memory configured to store one or more program instruction sets, wherein the one or more processors are configured to execute the one or more program instruction sets, wherein the one or more program instruction sets are configured to cause the one or more processors to: perform a first wafer geometry characterization process on a semiconductor wafer via at least one interferometer tool of the one or more characterization subsystems prior to a first lithography process; perform at least one characterization process on the semiconductor wafer via at least one reflection mode characterization tool of the one or more characterization subsystems after the first lithography process and before at least one patterned back-side film deposition process, wherein the at least one characterization process includes a film property characterization process or an intensity spectrum characterization process; and perform at least one additional characterization process on the semiconductor wafer via the at least one reflection mode characterization tool of the one or more characterization subsystems after the at least one patterned back-side film deposition process and before a second lithography process, wherein the at least one additional characterization process includes a film property characterization process or an intensity spectrum characterization process. Prior to the second lithography process, a second wafer geometry characterization process is performed on the semiconductor wafer via at least one interferometer tool of the one or more characterization subsystems; based on the first wafer geometry characterization process, the at least one characterization process, the at least one additional characterization process, and the second wafer geometry characterization process, a film force or at least one of one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process is determined; and the film force or at least one of one or more in-plane displacements is provided to at least one process tool via at least one feedforward loop or one feedback loop to improve the performance of one or more fabrication processes.

16. The system of claim 15, wherein the one or more program instruction sets are further configured to cause the one or more processors to: provide the film force or at least one of the one or more in-plane displacements to the one or more characterization subsystems via at least one of the feedforward loop or the feedback loop to improve the performance of the first wafer geometry characterization process or at least the additional characterization process.

17. A method for characterizing process-induced displacement during semiconductor manufacturing, comprising: A first wafer geometry characterization process is performed on a semiconductor wafer using at least one interferometer tool of one or more characterization subsystems prior to a first lithography process; After the first lithography process and before at least one patterned back-side film deposition process, at least one characterization process is performed on the semiconductor wafer using at least one reflection mode characterization tool of one or more characterization subsystems, wherein the at least one characterization process includes a film property characterization process or an intensity spectrum characterization process; After the at least one patterned back-side film deposition process and before a second lithography process, at least one additional characterization process is performed on the semiconductor wafer using the at least one reflection mode characterization tool of one or more characterization subsystems, wherein the at least one additional characterization process includes a film property characterization process or an intensity spectrum characterization process; A second wafer geometry characterization process is performed on the semiconductor wafer using the at least one interferometer tool of one or more characterization subsystems prior to the second lithography process. Based on the first wafer geometry characterization process, the at least one characterization process, the at least one additional characterization process, and the second wafer geometry characterization process, it is determined that at least one of the film forces or at least one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process is provided to at least one process tool via at least one feedforward loop or at least one feedback loop to improve the performance of one or more fabrication processes.

18. The method of claim 17, wherein the one or more film property characterization processes are configured to characterize a thickness, a real component of a refractive index and a complex component of the refractive index of the at least one patterned backside film deposited on the semiconductor wafer via the at least one patterned backside film deposition process.

19. The method of claim 17, wherein the first wafer geometry characterization process includes performing one or more semiconductor characterization processes on the semiconductor wafer prior to the at least one patterned backside film deposition process, wherein the at least one additional characterization process includes performing one or more semiconductor characterization processes on the semiconductor wafer after the at least one patterned backside film deposition process.

20. The method of claim 17, wherein the first wafer geometry characterization process includes performing one or more semiconductor characterization processes on the semiconductor wafer prior to the at least one patterned back-side film deposition process, wherein the at least one additional characterization process includes performing one or more semiconductor characterization processes on the semiconductor wafer after each patterned back-side film deposition process of the at least one patterned back-side film deposition process.

21. The method of claim 17, wherein the semiconductor process further includes at least one patterned front-side film deposition process on the semiconductor wafer.

22. The method of claim 21, wherein the at least one patterned front-side film deposition process comprises one or more patterned front-side film deposition processes on the semiconductor wafer after the first lithography process and before the at least one patterned back-side film deposition process, wherein the at least one characterization process is performed before the one or more patterned front-side film deposition processes.

23. The method of claim 21, wherein the at least one patterned front-side film deposition process comprises one or more patterned front-side film deposition processes on the semiconductor wafer after the at least one patterned back-side film deposition process and before the second lithography process, wherein the at least one additional characterization process is performed before the one or more patterned front-side film deposition processes.

24. The method of claim 17, wherein the first wafer geometry characterization process and the at least the additional characterization process further include performing one or more wafer geometry characterization processes on the semiconductor wafer via the at least one interferometer tool of the one or more characterization subsystems.

25. The method of claim 24, wherein the semiconductor manufacturing process further includes one or more lithography processes on the semiconductor wafer.

26. The method of claim 25, wherein the one or more lithography processes comprise a first lithography process prior to the at least one patterned back-side film process on the semiconductor wafer.

27. The method of claim 26, wherein the first wafer geometry characterization process includes one or more semiconductor characterization processes preceding the first lithography process on the semiconductor wafer.

28. The method of claim 27, wherein the one or more lithography processes comprise an additional lithography process following the at least one patterned back-side film process on the semiconductor wafer.

29. The method of claim 28, wherein the additional characterization process is included in one or more semiconductor characterization processes prior to the additional lithography process on the semiconductor wafer.

30. The method of claim 25, wherein one or more of the at least patterned front-side film deposition process, the at least patterned back-side film deposition process, or the at least lithography process are performed via the at least one process tool.

31. The method of claim 17, further comprising: The film force or at least one of the one or more in-plane displacements is provided to the one or more characterization subsystems via the feedforward loop or the feedback loop to improve the performance of the first wafer geometry characterization process or the at least the additional characterization process.

32. A system for characterizing process-induced displacement during semiconductor manufacturing, comprising: A controller, comprising one or more processors and memory configured to store one or more program instruction sets, wherein the one or more processors are configured to execute the one or more program instruction sets, wherein the one or more program instruction sets are configured to cause the one or more processors to: perform a first pre-lithography characterization process on a semiconductor wafer via at least one reflective mode characterization tool of one or more characterization subsystems prior to a first lithography process; perform at least one characterization process on the semiconductor wafer via the at least one reflective mode characterization tool of one or more characterization subsystems after the first lithography process and before at least one patterned back-side film deposition process; perform at least one additional characterization process on the semiconductor wafer via the at least one reflective mode characterization tool of one or more characterization subsystems after the at least one patterned back-side film deposition process and before a second lithography process; and perform a second pre-lithography characterization process on the semiconductor wafer via the at least one reflective mode characterization tool of one or more characterization subsystems before the second lithography process. Based on the first lithography characterization process, the at least one characterization process, the at least one additional characterization process, and the second lithography characterization process, it is determined that at least one of the film forces or at least one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process is provided to at least one process tool via a feedforward loop or a feedback loop to improve the performance of one or more fabrication processes, wherein the first lithography characterization process, the at least one characterization process, the at least one additional characterization process, and the second lithography characterization process include a film property characterization process or an intensity spectrum characterization process.

33. A system for characterizing process-induced displacement during semiconductor manufacturing, comprising: One or more characterization subsystems; And a controller, wherein the controller includes one or more processors and memory configured to store one or more program instruction sets, wherein the one or more processors are configured to execute the one or more program instruction sets, wherein the one or more program instruction sets are configured to cause the one or more processors to: perform a first pre-lithography characterization process on a semiconductor wafer via at least one reflective mode characterization tool of the one or more characterization subsystems before a first lithography process; perform at least one characterization process on the semiconductor wafer via the at least one reflective mode characterization tool of the one or more characterization subsystems after the first lithography process and before at least one patterned back-side film deposition process; perform at least one additional characterization process on the semiconductor wafer via the at least one reflective mode characterization tool of the one or more characterization subsystems after the at least one patterned back-side film deposition process and before a second lithography process; and perform a second pre-lithography characterization process on the semiconductor wafer via the at least one reflective mode characterization tool of the one or more characterization subsystems before the second lithography process. Based on the first lithography characterization process, the at least one characterization process, the at least one additional characterization process, and the second lithography characterization process, it is determined that at least one of the film forces or at least one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process is provided to at least one process tool via a feedforward loop or a feedback loop to improve the performance of one or more fabrication processes, wherein the first lithography characterization process, the at least one characterization process, the at least one additional characterization process, and the second lithography characterization process include a film property characterization process or an intensity spectrum characterization process.

34. A method for characterizing process-induced displacement during semiconductor manufacturing, comprising: A first pre-lithography characterization process is performed on a semiconductor wafer using at least one reflective mode characterization tool of one or more characterization subsystems prior to a first lithography process; at least one characterization process is performed on the semiconductor wafer using the at least one reflective mode characterization tool of one or more characterization subsystems after the first lithography process and before at least one patterned back-side film deposition process; at least one additional characterization process is performed on the semiconductor wafer using the at least one reflective mode characterization tool of one or more characterization subsystems after the at least one patterned back-side film deposition process and before a second lithography process; a second pre-lithography characterization process is performed on the semiconductor wafer using the at least one reflective mode characterization tool of one or more characterization subsystems before the second lithography process. Based on the first lithography characterization process, the at least one characterization process, the at least one additional characterization process, and the second lithography characterization process, it is determined that at least one of the film forces or at least one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process is provided to at least one process tool via a feedforward loop or a feedback loop to improve the performance of one or more fabrication processes, wherein the first lithography characterization process, the at least one characterization process, the at least one additional characterization process, and the second lithography characterization process include a film property characterization process or an intensity spectrum characterization process.

35. A system for characterizing process-induced displacement during semiconductor manufacturing, comprising: A controller, comprising one or more processors and memory configured to store one or more program instruction sets, wherein the one or more processors are configured to execute the one or more program instruction sets, wherein the one or more program instruction sets are configured to cause the one or more processors to: perform a first wafer geometry characterization process via at least one tool of one or more characterization subsystems prior to a first lithography process on a semiconductor wafer; perform at least one characterization process via at least one reflective mode characterization tool of one or more characterization subsystems after the first lithography process on the semiconductor wafer and before at least one patterned back-side film deposition process, wherein the at least one characterization process includes at least one of a film property characterization process or an intensity spectrum characterization process; and perform at least one additional characterization process via at least one reflective mode characterization tool of one or more characterization subsystems after the at least one patterned back-side film deposition process on the semiconductor wafer and before a second lithography process, wherein the at least one additional characterization process includes at least one of a film property characterization process or an intensity spectrum characterization process. Prior to the second lithography process on the semiconductor wafer, a second wafer geometry characterization process is performed via at least one tool of the one or more characterization subsystems; based on at least one of the first wafer geometry characterization process, the at least one characterization process, the at least one additional characterization process, or the second wafer geometry characterization process, a film force or at least one of one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process is determined; and the film force or at least one of one or more in-plane displacements is provided to at least one process tool via at least one feedforward loop or a feedback loop to improve the performance of one or more fabrication processes.

36. The system of claim 35, wherein the one or more film property characterization processes are configured to characterize at least one of the thickness, a real component of a refractive index, or a complex component of a refractive index of the at least one patterned backside film deposited on the semiconductor wafer via the at least one patterned backside film deposition process.

37. The system of claim 35, wherein at least one of the at least one characterization process or at least one additional characterization process further includes one or more wafer geometry characterization processes on the semiconductor wafer.

38. The system of claim 35, wherein the at least one process tool is configured to perform the one or more fabrication processes on the semiconductor wafer.

39. The system of claim 35, wherein the at least one process tool includes at least one film deposition tool configured to perform one or more patterned front-side film deposition processes on the semiconductor wafer.

40. The system of claim 35, wherein the at least one process tool includes at least one film deposition tool configured to perform one or more patterned back-side film deposition processes on the semiconductor wafer.

41. The system of claim 35, wherein the at least one process tool includes at least one lithography tool configured to perform one or more lithography processes on the semiconductor wafer.

42. The system of claim 35, wherein the at least one tool and the at least one reflection mode characterization tool of the one or more characterization subsystems performing the first wafer geometry characterization process are integrated into a common tool.

43. The system of claim 35, wherein the at least one tool and the at least one reflection mode characterization tool of the one or more characterization subsystems performing the first wafer geometry characterization process are independent characterization tools.

44. The system of claim 35, wherein the one or more program instruction sets are further configured to cause the one or more processors to: provide the membrane force or at least one of the one or more in-plane displacements to the one or more characterization subsystems via at least one of the feedforward loop or the feedback loop to improve the performance of the at least one characterization process or the at least one additional characterization process.

45. A system for characterizing process-induced displacement during semiconductor manufacturing, comprising: One or more characterization subsystems; And a controller, wherein the controller includes one or more processors and memory configured to store one or more program instruction sets, wherein the one or more processors are configured to execute the one or more program instruction sets, wherein the one or more program instruction sets are configured to cause the one or more processors to: perform a first wafer geometry characterization process via at least one tool of the one or more characterization subsystems prior to a first lithography process on a semiconductor wafer; perform at least one characterization process via at least one reflective mode characterization tool of the one or more characterization subsystems after the first lithography process on the semiconductor wafer and before at least one patterned back-side film deposition process, wherein the at least one characterization process includes at least one of a film property characterization process or an intensity spectrum characterization process; and perform at least one additional characterization process via at least one reflective mode characterization tool of the one or more characterization subsystems after the at least one patterned back-side film deposition process on the semiconductor wafer and before a second lithography process, wherein the at least one additional characterization process includes at least one of a film property characterization process or an intensity spectrum characterization process. Prior to the second lithography process on the semiconductor wafer, a second wafer geometry characterization process is performed via at least one tool of the one or more characterization subsystems; based on at least one of the first wafer geometry characterization process, the at least one characterization process, the at least one additional characterization process, or the second wafer geometry characterization process, a film force or at least one of one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process is determined; and the film force or at least one of one or more in-plane displacements is provided to at least one process tool via at least one feedforward loop or a feedback loop to improve the performance of one or more fabrication processes.

46. ​​The system of claim 45, wherein the one or more program instruction sets are further configured to cause the one or more processors to: provide the membrane force or at least one of the one or more in-plane displacements to the one or more characterization subsystems via at least one of the feedforward loop or the feedback loop to improve the performance of the at least one characterization process or the at least one additional characterization process.

47. A method for characterizing process-induced displacement during semiconductor manufacturing, comprising: A first wafer geometry characterization process is performed via at least one tool of one or more characterization subsystems prior to a first lithography process on one of the semiconductor wafers; at least one characterization process is performed via at least one reflection mode characterization tool of one or more characterization subsystems after the first lithography process on the semiconductor wafer and before at least one patterned back-side film deposition process, wherein the at least one characterization process includes at least one of a film property characterization process or an intensity spectrum characterization process; at least one additional characterization process is performed via at least one reflection mode characterization tool of one or more characterization subsystems after the at least one patterned back-side film deposition process on the semiconductor wafer and before a second lithography process, wherein the at least one additional characterization process includes at least one of a film property characterization process or an intensity spectrum characterization process; a second wafer geometry characterization process is performed via at least one tool of one or more characterization subsystems prior to the second lithography process on the semiconductor wafer. Based on at least one of the first wafer geometry characterization process, the at least one characterization process, the at least one additional characterization process, or the second wafer geometry characterization process, determine at least one of the film forces or at least one or more in-plane displacements of at least one patterned back-side film deposited on the semiconductor wafer via the at least one patterned back-side film deposition process; and provide the film force or at least one of the in-plane displacements to at least one process tool via at least one feedforward loop or a feedback loop to improve the performance of one or more fabrication processes.

48. The method of claim 47, wherein the one or more film property characterization processes are configured to characterize at least one of a thickness, a real component of a refractive index, or a complex component of a refractive index of the at least one patterned backside film deposited on the semiconductor wafer via the at least one patterned backside film deposition process.

49. The method of claim 47, wherein the at least one characterization process includes performing one or more semiconductor characterization processes on the semiconductor wafer prior to the at least one patterned back-side film deposition process, wherein the at least one additional characterization process includes performing one or more semiconductor characterization processes on the semiconductor wafer after the at least one patterned back-side film deposition process.

50. The method of claim 47, wherein the at least one characterization process includes performing one or more semiconductor characterization processes on the semiconductor wafer prior to the at least one patterned back-side film deposition process, wherein the at least one additional characterization process includes performing one or more semiconductor characterization processes on the semiconductor wafer after each patterned back-side film deposition process of the at least one patterned back-side film deposition process.

51. The method of claim 47, wherein the semiconductor process further includes at least one patterned front-side film deposition process on the semiconductor wafer.

52. The method of claim 51, wherein the at least one patterned front-side film deposition process comprises one or more patterned front-side film deposition processes after the first lithography process on the semiconductor wafer and before the at least one patterned back-side film deposition process, wherein the at least one characterization process is performed after the one or more patterned front-side film deposition processes.

53. The method of claim 51, wherein the at least one patterned front-side film deposition process comprises one or more patterned front-side film deposition processes following the at least one patterned back-side film deposition process on the semiconductor wafer and preceding the second lithography process, wherein the at least one additional characterization process is performed prior to the one or more patterned front-side film deposition processes.

54. The method of claim 47, wherein at least one of the at least one characterization process or at least one additional characterization process further includes one or more wafer geometry characterization processes on the semiconductor wafer.

55. The method of claim 54, wherein the semiconductor manufacturing process further includes one or more lithography processes on the semiconductor wafer.

56. The method of claim 55, wherein the one or more lithography processes comprise a first lithography process prior to the at least one patterned back-side film process on the semiconductor wafer.

57. The method of claim 56, wherein the at least one characterization process comprises one or more semiconductor characterization processes prior to the first lithography process on the semiconductor wafer.

58. The method of claim 57, wherein the one or more lithography processes comprise an additional lithography process following the at least one patterned back-side film process on the semiconductor wafer.

59. The method of claim 58, wherein the at least one additional characterization process is included in one or more semiconductor characterization processes prior to the additional lithography process on the semiconductor wafer.

60. The method of claim 55, wherein one or more of the at least one patterned front-side film deposition process, the at least one patterned back-side film deposition process, or the at least one lithography process are performed via the at least one process tool.

61. The method of claim 47, further comprising: The membrane force or at least one of the one or more in-plane displacements is provided to the one or more characterization subsystems via the feedforward loop or the feedback loop to improve the performance of the at least one characterization process or the at least one additional characterization process.

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