Integrated device comprising transistor coupled to a dummy gate contact

Abstract

An integrated device includes a substrate and a first transistor located above the substrate, wherein the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, wherein the second gate contact is directly electrically coupled to the gate only.

Description

[Technical Field]

[0001] Various features relate to transistors, and more specifically, to integrated devices including transistors coupled to dummy gate contacts. [Previous Technology]

[0002] Figure 1 shows a planar field-effect transistor (FET) 100. The FET 100 is formed over a substrate 102 and an oxide 104. The FET 100 includes a source 106, a drain 108, and a gate 110. The source 106 and drain 108 are located over the substrate 102. When a minimum voltage is applied between the gate 110 and the substrate 102, current can flow between the source 106 and the drain 108. There is a need to improve the performance of transistors, such as being able to better control when current flows between the source and drain of the transistor. [Summary of the Invention]

[0003] Various features relate to transistors, and more specifically, to integrated devices including transistors coupled to dummy gate contacts.

[0004] One example provides an integrated device including a substrate and a first transistor located above the substrate, wherein the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, wherein the second gate contact is directly electrically coupled to the gate only.

[0005] Another example provides an apparatus including a substrate and a first transistor located above the substrate, wherein the first transistor includes a gate. The apparatus includes a first gate contact coupled to the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of an integrated device. The apparatus includes a member for regulating a voltage required to induce a first current in the first transistor, wherein the regulating member is directly electrically coupled to the gate only.

[0006] Another example provides an integrated device including a substrate and a first transistor located above the substrate, wherein the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, and contact interconnects coupled to the second gate contact, wherein the contact interconnects are directly electrically coupled to the gate contact only.

[0007] Another example provides a method for manufacturing an integrated device. The method provides a substrate. The method forms a first transistor over the substrate, wherein the first transistor includes a gate. The method forms a first gate contact over the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The method forms a second gate contact over the gate, wherein the second gate contact is directly electrically coupled to the gate only.

Implementation Method

[0008] Specific details are set forth in the following description to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not have been shown in detail to avoid obscuring aspects of this disclosure.

[0009] This disclosure describes an integrated device including a substrate and a first transistor located above the substrate, wherein the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, wherein the second gate contact is directly electrically coupled to the gate only. The integrated device may include a second transistor located above the substrate, wherein the second transistor includes a gate. The second gate contact is configured to regulate (e.g., reduce) a threshold voltage required to induce a first current in the first transistor and a second current in the second transistor. The first transistor may be a p-channel field-effect transistor (PFET), and the second transistor may be an n-channel field-effect transistor (NFET). The integrated device in the device can operate under different operating conditions, and therefore, the ability to regulate the threshold voltage required to induce current in one or more transistors can help optimize the performance of the integrated device in the device. Exemplary transistors coupled to gate contacts and dummy gate contacts.

[0010] Figure 2 illustrates an example of a transistor 200 formed in an integrated device. The transistor 200 may include a fin field-effect transistor (FET). The transistor 200 includes a substrate 202, an oxide 204, a fin 205, a source 206, a drain 208, a gate oxide 209, and a gate 210. The oxide 204 is located above the substrate 202. The source 206 may be a portion of the fin 205 configured as a source of the transistor 200. The drain 208 may be a portion of the fin 205 configured as a drain of the transistor 200. The fin 205 is located above the substrate 202. The fin 205 may be a portion of the substrate 202. The fin 205 may be at least partially located in the oxide 204. The source 206 may be defined by a first portion of the fin 205, and the drain 208 may be defined by a second portion of the fin 205. Gate oxide 209 is located between oxide 204 and fin 205. Gate 210 is located above oxide 204 and fin 205. Gate oxide 209 may be located between gate 210 and oxide 204 and fin 205. Although not shown, substrate 202 may include a well doped with N-type or P-type dopant. The type of dopant used in the well may specify whether transistor 200 is an N-type transistor or a P-type transistor.

[0011] Gate contact 250 is coupled to transistor 200. Specifically, gate contact 250 is coupled to gate 210 of transistor 200. Contact interconnect 260 is coupled to gate contact 250. Interconnect 270 (e.g., M1 layer interconnect of an integrated device) may be coupled to contact interconnect 260.

[0012] When a voltage is applied between gate 210 and substrate 202, current can be induced to flow between source 206 and drain 208. The voltage can be applied to gate 210 through interconnect 270, contact interconnect 260, and gate contact 250. Gate contact 250 can be a driving gate contact where the voltage is applied. Transistor 200 may need to apply a threshold voltage (Vt) to gate 210 to allow current to flow between source 206 and drain 208. The threshold voltage can be a minimum voltage. In some embodiments, the minimum voltage applied to the gate (e.g., gate 210) may be equal to or greater than the threshold voltage of the gate. As will be further described below, one or more transistors of the integrated device may be configured in a manner requiring a low threshold voltage to induce current in one or more transistors. Similarly, one or more transistors of the integrated device may be configured in a manner requiring a high threshold voltage to induce current in one or more transistors.

[0013] Figure 3 illustrates a structure 300 including a first transistor 301 and a second transistor 302. Structure 300 can be implemented in an integrated device. Structure 300 can be part of a device-level unit of the integrated device.

[0014] Structure 300 includes a substrate 202, an oxide 204, and a plurality of fins 205. Gate oxide 209 and gate 210 are also present. The plurality of fins 205 include fins (e.g., 205a, 205b, 205c, 205d). Each of the plurality of fins 205 may include a corresponding source and a corresponding drain, as shown in FIG2.

[0015] The first transistor 301 includes a substrate 202, an oxide 204, fins 205a and 205b, a gate oxide 209, and a gate 210. Fin 205a may have an active electrode and a drain electrode. Similarly, fin 205b may have an active electrode and a drain electrode. The second transistor 302 includes a substrate 202, an oxide 204, fins 205c and 205d, a gate oxide 209, and a gate 210. Fin 205c may have an active electrode and a drain electrode. Similarly, fin 205d may have an active electrode and a drain electrode. In the example described, the first transistor 301 and the second transistor 302 share the same gate (e.g., 210). However, in some embodiments, the first transistor 301 and the second transistor 302 may have different gates. Note that for clarity, not all components are shown in FIG3. For example, a dielectric layer may be formed above and / or around the fin 205, gate 210, gate contact 250, contact interconnect 260 and / or interconnect 270.

[0016] Figure 3 illustrates a p-channel field-effect transistor (PFET) active region 310, an n-channel field-effect transistor (NFET) active region 320, and a field region 330. The field region 330 is located between the PFET active region 310 and the NFET active region 320. Although not shown, the substrate 202 may include wells doped with N-type or P-type dopant. The type of dopant used in the wells may specify whether the transistor is an N-type or P-type transistor. The PFET active region 310 may include a portion of the substrate 202, the portion including one or more wells with N-type dopant. The NFET active region 320 may include a portion of the substrate 202, the portion including one or more wells with P-type dopant. A first transistor 301 includes and / or is located within the PFET active region 310. The first transistor 301 may be configured as a p-type metal-oxide-semiconductor (PMOS) transistor. A second transistor 302 includes and / or is located within the NFET active region 320. The second transistor 302 may be configured as an n-type metal-oxide-semiconductor (NMOS) transistor. The first transistor 301 and the second transistor 302 are each defined by two fins (e.g., a first fin and a second fin). However, different embodiments may define transistors with different numbers of fins (e.g., one or more fins).

[0017] Figure 3 shows several gate contacts coupled to gate 210. Specifically, gate contacts 250a, 250b, 250c, 250d, and 250e are coupled to gate 210 (e.g., to different portions of gate 210). Gate contacts 250a and 250b are located above the PFET active region 310. Specifically, gate contact 250a is located above fin 205a, while gate contact 250b is located above fin 205b. Gate contacts 250c and 250d are located above the NFET active region 320. Specifically, gate contact 250c is located above fin 205c, while gate contact 250d is located above fin 205d. Gate contact 250e is located above field region 330. Contact interconnect 260e is coupled to gate contact 250e. In some embodiments, contact interconnect 260e may be considered part of gate contact 250e. Interconnect 270e is coupled to contact interconnect 260e. In some embodiments, interconnect 270e may be directly coupled to gate contact 250e. The gate contact (e.g., 250) may be configured to be electrically coupled to the interconnect of the integrated device (e.g., the interconnect of the M1 metal layer).

[0018] Voltage can be applied to gate 210 through interconnect 270e, contact interconnect 260e, and gate contact 250e. Gate contact 250e can be a driving gate contact where voltage is applied. When a threshold voltage (Vt) is applied between gate 210 and substrate 202, a first current can flow through the source and drain of the first transistor 301 (as defined by fins 205a and 205b), and a second current can flow through the source and drain of the second transistor 302 (as defined by fins 205c and 205d). As described above, the first transistor 301 can operate as a different transistor than the second transistor 302. Therefore, each transistor may require a different threshold voltage to induce current. In some embodiments, in order to induce current in both transistors, the voltage provided at gate 210 must be the higher of the threshold voltages of the first transistor 301 and the second transistor 302.

[0019] By positioning the gate contact coupled to gate 210 and / or coupling one or more dummy gate contacts (e.g., and / or dummy contact interconnects), the threshold voltage required to induce current can be adjusted and / or regulated. In the example of FIG3, gate contact 250e is approximately located at the center of field region 330. However, in other embodiments, gate contact 250e may be located in different portions of field region 330. FIG3 shows that gate contact 250e is a driving gate contact. However, different embodiments may use any gate contact as a driving gate contact. FIG3 shows that some of the gate contacts coupled (e.g., directly coupled) to gate 210 (e.g., 250a, 250b, 250c, 250d) are not directly coupled to other interconnects. That is, these gate contacts are only directly coupled to gate 210 and not directly coupled to other interconnects (e.g., contact interconnects 260, interconnects 270). These gate contacts (e.g., 250a, 250b, 250c, 250d) can be considered dummy gate contacts. Interconnects (e.g., 270b, 270d) can be located above some of the gate contacts (e.g., 250a, 250b, 250c, 250d). Contact interconnects 260a and 260c are coupled to gate contacts 250a and 250c, respectively. However, contact interconnects 260a and 260c are not directly coupled to another interconnect (e.g., an interconnect on layer M1). Although gate contacts 250a and 250c are coupled to their respective contact interconnects 260a and 260c, gate contacts 250a and 250c can each be considered dummy gate contacts. Gate contacts 250a and 250c can each be considered dummy gate contacts because neither of them is a driving gate contact. In some implementations, contact interconnect 260a is considered to be part of gate contact 250a, and contact interconnect 260c is considered to be part of gate contact 250c.

[0020] As will be further described below, the formation or fabrication process of the gate contact (e.g., a dummy gate contact) can cause ions (e.g., oxygen ions) to diffuse into the gate and / or fins, which alters the working metallic function of the transistor and thus modulates the transistor's drive strength and / or voltage threshold. For example, forming at least one gate contact (e.g., a dummy gate contact) closer to the PFET can result in more ions diffusing into the PFET than into the NFET. Forming at least one gate contact (e.g., a dummy gate contact) closer to the NFET can result in more ions diffusing into the NFET than into the PFET. At least one dummy gate contact can be a component for regulating the voltage required to induce a current (e.g., a first current, a second current) in at least one transistor (e.g., a first transistor, a second transistor).

[0021] Virtual gate contacts (e.g., 250a, 250b, 250c, 250d) are coupled (e.g., directly coupled) to different portions of gate 210 to adjust (e.g., decrease, increase) the threshold voltage required to induce current flow in the first transistor 301 and / or the second transistor 302. In the example of FIG3, four virtual gate contacts are present. However, as will be further described below, different embodiments may have different numbers of virtual gate contacts. Furthermore, the location of the virtual gate contacts may vary with different embodiments. Different embodiments may have different dimensions for the fins, (multiple) gate contacts, and / or the gate. For example, in some embodiments, the fins (e.g., 205a, 205b, 205c, 205d) may have a fin width of about 4 to 10 nanometers (nm). In some embodiments, the gate (e.g., 210) may have a length of about 8 to 14 nanometers (nm). In some implementations, the gate contacts (e.g., 250a, 250b, 250c, 250d) may have a lateral dimension of about 15 to 25 nanometers (nm) (e.g., along the X and Y axes). However, different implementations may have different dimensions for the fins, gate contacts, and / or gates.

[0022] Figure 4 illustrates three examples of how the location of the gate contact affects the threshold voltage (Vt) required to induce current in the PFET and NFET. Figure 4 shows (i) a first configuration 401, in which the gate contact is located near the NFET and offset from the PFET, (ii) a second configuration 402, in which the gate contact is located at an intermediate position between the PFET and the NFET, and (iii) a third configuration 403, in which the gate contact is located near the PFET and offset from the NFET.

[0023] As shown in graph 410, when the gate contact is close to the PFET (C), the threshold voltage required to induce current in the PFET decreases by approximately 7 millivolts (mV). When the gate contact is between the PFET and the NFET (B), the threshold voltage required to induce current in the PFET does not change much. When the gate contact is close to the NFET (A) and offset from the PFET, the threshold voltage required to induce current in the PFET increases by approximately 4 millivolts (mV).

[0024] As shown in graph 420, when the gate contact is close to the NFET (D), the threshold voltage required to induce current in the NFET increases by approximately 15 millivolts (mV). When the gate contact is between the PFET and the NFET (E), the threshold voltage required to induce current in the PFET does not change much. When the gate contact is close to the PFET (F) and offset from the NFET, the threshold voltage required to induce current in the PFET decreases by approximately 7 millivolts (mV).

[0025] The arrangement of the gate contacts is important because the formation or fabrication process of the gate contacts can cause ions (e.g., oxygen ions) to diffuse into the gate and / or fins, which alters the working metallic function of the transistor and thus modulates the transistor's drive strength and / or voltage threshold. Gate contacts closer to the PFET can result in more ion diffusion in the PFET than in the NFET. Gate contacts closer to the NFET can result in more ion diffusion in the NFET than in the PFET.

[0026] Therefore, as shown in graphs 410 and 420, positioning the gate contact closer to the PFET reduces the threshold voltage required to induce current in both the PFET and NFET. This means that positioning the gate contact closer to the PFET increases the drive strength of both the PFET and NFET. Conversely, positioning the gate contact closer to the NFET increases the threshold voltage required to induce current in both the PFET and NFET. This means that positioning the gate contact closer to the PFET reduces the drive strength of both the PFET and NFET.

[0027] To further adjust the transistor, change the drive strength of the gate contact, and / or change the threshold voltage of the transistor, a dummy gate contact can be coupled to the gate. Providing and forming at least a dummy gate contact above the gate allows additional ions (e.g., oxygen ions) to diffuse into the gate and / or fins. This ion diffusion can be referred to as a change in the metal gate function from the gate contact and / or dummy gate contact etching process, which will be further described below at least in Figure 13C. For example, forming at least one gate contact (and / or at least one dummy gate contact) closer to the PFET can result in more ion diffusion into the PFET than into the NFET. Forming at least one gate contact (and / or at least one dummy gate contact) closer to the NFET can result in more ion diffusion into the NFET than into the PFET. As described above, at least one dummy gate contact can be a component for adjusting the threshold voltage required to induce current in the transistor.

[0028] Figures 5 through 11 illustrate various examples of how gate contacts and / or dummy gate contacts can be coupled to the gate. Note that the examples shown in Figures 3 and 5 through 11 are not limiting, and other implementations may include other configurations. As shown below, forming dummy gate contacts can result in more ion diffusion into the NFET and / or PFET, which modulates the transistor, alters the drive strength of the gate contact, and / or alters the threshold voltage of the transistor. How many ions diffuse into the NFET and / or PFET can depend on the location and size of the gate contacts and / or dummy gate contacts, as well as the number of dummy gate contacts. For example, more dummy gate contacts can mean more ion diffusion. Larger gate contacts and / or dummy gate contacts can mean more ion diffusion.

[0029] Figure 5 shows a structure 500 including a first transistor 501 and a second transistor 502. Structure 500 is similar to structure 300 and includes the same or similar components as structure 300. The first transistor 501 is similar to the first transistor 301 and includes similar components as the first transistor 301. The second transistor 502 is similar to the second transistor 302 and includes similar components as the second transistor 302. Figure 5 shows a gate contact 250f coupled to a portion of the gate 210 near the fin 205c. The gate contact 250f is located in the field region 330 between the PFET active region 310 and the NFET active region 320. A contact interconnect 260f is coupled to the gate contact 250f. An interconnect 270f is coupled to the contact interconnect 260f.

[0030] Figure 6 shows a structure 600 including a first transistor 601 and a second transistor 602. Structure 600 is similar to structure 300 and includes the same or similar components as structure 300. The first transistor 601 is similar to the first transistor 301 and includes similar components as the first transistor 301. The second transistor 602 is similar to the second transistor 302 and includes similar components as the second transistor 302. Figure 6 shows a gate contact 250g coupled to a portion of the gate 210 near the fin 205b. The gate contact 250g is located in the field region 330 between the PFET active region 310 and the NFET active region 320. A contact interconnect 260g is coupled to the gate contact 250g. An interconnect 270g is coupled to the contact interconnect 260g.

[0031] Figure 7 shows a structure 700 including a first transistor 701 and a second transistor 702. Structure 700 is similar to structure 300 and includes the same or similar components as structure 300. The first transistor 701 is similar to the first transistor 301 and includes similar components as the first transistor 301. The second transistor 702 is similar to the second transistor 302 and includes similar components as the second transistor 302. Figure 7 shows a gate contact 250g, which is coupled to a portion of the gate 210 near the fin 205b. A gate contact 250h is coupled to another portion of the gate 210 near the fin 205c. The gate contact 250h may be a dummy gate contact. The gate contact 250g and the gate contact 250h are located in a field region 330 between the PFET active region 310 and the NFET active region 320. A contact interconnect 260g is coupled to the gate contact 250g. Interconnect 270g is coupled to contact interconnect 260g. Gate contact 250h is directly coupled (e.g., directly electrically coupled) only to gate 210, which may mean that gate contact 250h is not directly coupled (e.g., not directly electrically coupled) to other interconnects. Interconnect 270h may be located above gate contact 250h. Gate contact 250h may not be used as a driving gate contact.

[0032] FIG8 shows a structure 800 including a first transistor 801 and a second transistor 802. Structure 800 is similar to structure 300 and includes the same or similar components as structure 300. The first transistor 801 is similar to the first transistor 301 and includes similar components as the first transistor 301. The second transistor 802 is similar to the second transistor 302 and includes similar components as the second transistor 302. FIG8 shows a gate contact 250i, which is coupled to a portion of the gate 210 near the fin 205c. Gate contact 250j is coupled to another portion of the gate 210 near the fin 205b. Gate contact 250j may be a dummy gate contact. Gate contacts 250i and 250j are located in a field region 330 between the PFET active region 310 and the NFET active region 320. Contact interconnect 260i is coupled to gate contact 250i. Interconnect 270i is coupled to contact interconnect 260i. Gate contact 250j is directly coupled (e.g., directly electrically coupled) only to gate 210 and is not directly coupled to other interconnects (e.g., not directly electrically coupled). Interconnect 270j may be located above gate contact 250h.

[0033] Figure 9 shows structures 900a and 900b, each including a first transistor 901 and a second transistor 902. The first transistor 901 is similar to the first transistor 301 and includes components similar to those of the first transistor 301. The second transistor 902 is similar to the second transistor 302 and includes components similar to those of the second transistor 302. Figure 9 shows an example of a structure with low drive strength (e.g., high threshold voltage (Vt)) for NFETs and PFETs.

[0034] Figure 9 shows gate contact 250n, which is coupled to the portion of gate 210 between fins 205c and 205d of structure 900a. Gate contact 250n is located above NFET active region 320. Contact interconnect 260n is coupled to gate contact 250n. Interconnect 270n is coupled to contact interconnect 260n.

[0035] Figure 9 shows (i) a gate contact 250c coupled to the portion of gate 210 above fin 205c of structure 900b, and (ii) a gate contact 250d coupled to the portion of gate 210 above fin 205d of structure 900b. Gate contacts 250c and 250d are located in the NFET active region 320. Gate contact 250c is a dummy gate. Contact interconnect 260d is coupled to gate contact 250d. Interconnect 270d is coupled to contact interconnect 260d. In some embodiments, gate contact 250d may be a dummy gate, and gate contact 250c may be coupled to an interconnect. In this case, contact interconnect (e.g., 260c) may be coupled to gate contact 250c, and gate contact 250d may not be coupled to contact interconnect 260d.

[0036] Figure 10 shows structures 1000a and 1000b, each including a first transistor 1001 and a second transistor 1002. The first transistor 1001 is similar to the first transistor 301 and includes components similar to those of the first transistor 301. The second transistor 1002 is similar to the second transistor 302 and includes components similar to those of the second transistor 302. Figure 10 shows an example of a structure with high drive strength (e.g., low threshold voltage (Vt)) for NFETs and PFETs.

[0037] Figure 10 shows gate contact 250p, which is coupled to the portion of gate 210 between fins 205a and 205b of structure 1000a. Gate contact 250p is located above the PFET active region 310. Contact interconnect 260p is coupled to gate contact 250p. Interconnect 270p is coupled to contact interconnect 260p.

[0038] Figure 10 shows (i) gate contact 250a, which is coupled to the portion of gate 210 above fin 205a of structure 1000b, and (ii) gate contact 250b, which is coupled to the portion of gate 210 above fin 205b of structure 1000b. Gate contact 250a and gate contact 250b are located in the PFET active region 310. Gate contact 250a is a dummy gate. Contact interconnect 260b is coupled to gate contact 250b. Interconnect 270b is coupled to contact interconnect 260b. In some embodiments, gate contact 250b may be a dummy gate, and gate contact 250a may be coupled to an interconnect. In this case, contact interconnect (e.g., 260a) may be coupled to gate contact 250a, and gate contact 250b may not be coupled to contact interconnect 260b.

[0039] FIG11 shows structures 1100a and 1100b, each including a first transistor 1101 and a second transistor 1102. The first transistor 1101 is similar to the first transistor 301 and includes components similar to those of the first transistor 301. The second transistor 1102 is similar to the second transistor 302 and includes components similar to those of the second transistor 302. FIG11 shows an example of a structure having a high drive strength (e.g., a low threshold voltage (Vt)) for a PFET and a low drive strength (e.g., a high threshold voltage (Vt)) for an NFET.

[0040] Figure 11 shows a gate contact 250p coupled to the portion of gate 210 between fins 205a and 205b of structure 1100a. Gate contact 250p is located in the PFET active region 310. Contact interconnect 260p is coupled to gate contact 250p. Interconnect 270p is coupled to contact interconnect 260p.

[0041] Figure 11 also shows a gate contact 250n, which is coupled to the portion of the gate 210 between fins 205c and 205d of structure 1100a. The gate contact 250n is located in the NFET active region 320. The gate contact 250n may be a dummy gate contact.

[0042] In some embodiments, the configuration shown for structure 1100A may differ. That is, structure 1100a may be modified such that gate contact 250p is a dummy gate and gate contact 250n is a driving gate contact. In an example of such modification, contact interconnect (e.g., 260p) may be coupled to gate contact 250n (instead of gate contact 250p), and gate contact 250p may not be coupled to contact interconnect 260p.

[0043] Figure 11 shows (i) gate contact 250a, which is coupled to the portion of gate 210 above fin 205a of structure 1100b; (ii) gate contact 250b, which is coupled to the portion of gate 210 above fin 205b of structure 1100b; (iii) gate contact 250c, which is coupled to the portion of gate 210 above fin 205c of structure 1100b; and (iv) gate contact 250d, which is coupled to the portion of gate 210 above fin 205d of structure 1100b. Gate contacts 250a and 250b are located in the PFET active region 310. Gate contacts 250c and 250d are located in the NFET active region 320. Gate contacts 250a, 250b, and 250c are dummy gate contacts. Contact interconnect 260b is coupled to gate contact 250b. Since contact interconnect 260b is not directly coupled to an interconnect, it can be a dummy contact interconnect. Contact interconnect 260d is coupled to gate contact 250d. Interconnect 270d is coupled to contact interconnect 260d. Gate contact 250d is a driven gate contact where voltage travels through gate 210. However, any gate contact can be a driven gate contact. An exemplary sequence for fabricating a transistor including a dummy gate contact is provided.

[0044] In some embodiments, manufacturing a structure coupled to a dummy gate includes several procedures. FIG12 illustrates an exemplary sequence for providing or manufacturing a structure coupled to a dummy gate. In some embodiments, the sequence of FIG12 can be used to provide or manufacture the structures of FIG3 and 5-11 described in this disclosure. Furthermore, the sequence for manufacturing the structures can be used to manufacture several structures simultaneously.

[0045] It should be noted that the sequence of FIG12 may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a structure coupled to a dummy gate. In some embodiments, the order of the procedures may be changed or modified. In some embodiments, one or more procedures may be replaced or substituted without departing from the spirit of this disclosure.

[0046] As shown in FIG12, stage 1 illustrates the state after structure 1200 is provided. Structure 1200 includes a substrate, a plurality of fins 205, a plurality of gates 210, a PFET active region 310, an NFET active region 320, and a plurality of gate contacts 250. A front-end process (FEOL) can be used to provide (e.g., manufacture) the plurality of fins 205, the plurality of gates 210, the PFET active region 310, the NFET active region 320, and the plurality of gate contacts 250.

[0047] Stage 2 shows the state after contact interconnects 260 are formed over some gate contacts 250. When contact interconnects 260 are not formed over the gate contacts, those gate contacts can be considered dummy gate contacts. Contact interconnects can be formed using an electroplating process.

[0048] Stage 3 shows the state after interconnect 270 is formed above contact interconnect 260. Interconnect 270 may be an M1 layer interconnect of an integrated device. Contact interconnect can be formed using an electroplating process.

[0049] A high-level description of how to manufacture the structure and dummy gate contact has already been described; a more detailed sequence for manufacturing the structure and dummy gate contact will now be described below. An exemplary sequence for manufacturing a structure including a transistor coupled to a dummy gate contact.

[0050] In some embodiments, manufacturing the structure coupled to the dummy gate contact includes several procedures. Figure 13 (including Figures 13A-13D) illustrates the sequence for providing or manufacturing the structures coupled to the dummy gate contacts of Figures 3 and 5-11. In some embodiments, the sequence of Figures 13A-13D can be used to provide or manufacture the structures coupled to the dummy gate contacts of Figures 3 and 5-11. Furthermore, the sequence for manufacturing the structures coupled to the dummy gate contacts can be used to manufacture several structures simultaneously. However, for clarity, the sequence of Figure 13 illustrates the manufacture of one structure.

[0051] It should be noted that the sequences of Figures 13A to 13D may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a structure coupled to a dummy gate. In some embodiments, the sequence of procedures may be changed or modified. In some embodiments, one or more procedures may be replaced or substituted without departing from the spirit of this disclosure.

[0052] As shown in FIG13A, stage 1 illustrates the state after substrate 202 is provided. Different embodiments may provide different materials for substrate 202. In some embodiments, substrate 202 may include silicon (Si). In some embodiments, substrate 202 may already include dopants. In some embodiments, substrate 202 may be doped with p-type dopants or n-type dopants. Substrate 202 may include wells (e.g., n-type wells, p-type wells).

[0053] Stage 2 shows the state after the fins 205 are formed over the substrate 202. The process of forming the fins 205 includes forming trenches 1305 in the substrate 202. Hard markings and a resist (e.g., a patterned resist) may be located over the substrate 202. The fins 205 may be etched by an etching process (e.g., an anisotropic etching process). The fins 205 may include fins (e.g., 205a, 205b, 205c, 205d).

[0054] Stage 3 shows the state after oxide 204 is formed over substrate 202 and trench 1305, such that oxide 204 is between fins 205. Oxide deposition process can be used to form oxide 204. Planarization process, such as chemical mechanical polishing (CMP) process, can be used to planarize oxide 204.

[0055] As shown in Figure 13B, stage 4 illustrates the state after the oxide recess, where a portion of the oxide 204 is further removed. Another etching process can be used to remove a portion of the oxide 204, leaving the sides of the fin 205 exposed.

[0056] Stage 5 shows the state after the gate oxide 209 is formed over the portion of oxide 204 and the portion of fin 205. The gate oxide 209 can be formed using a deposition process.

[0057] Stage 6 shows the state after the gate 210 is formed over the fin 205 and oxide 204. The gate 210 may be formed over the gate oxide 209. The gate 210 may include a polycrystalline silicon layer doped with a dopant (e.g., N+ dopant). As shown in Stage 6, the gate 210 surrounds three sides of the fin 205.

[0058] As shown in FIG13C, stage 7 illustrates the state after one or more gate contacts 250 (e.g., 250a, 250b, 250c, 250d, 250e) have been formed over various portions of gate 210. In this example, gate contact 250a is located over fin 205a, gate contact 250b is located over fin 205b, gate contact 250c is located over fin 205c, and gate contact 250d is located over fin 205d. Gate contact 250e is located between gate contact 250b and gate contact 250c. The gate contacts 250 can be formed using electroplating and etching processes. As will be further described below, at least one gate contact may be a dummy gate contact. As described above, the process of forming the gate contacts 250 can cause ions (e.g., oxygen ions) to diffuse into fin 205. The amount of ions diffusing from a corresponding gate contact (e.g., a dummy gate contact) into a corresponding fin can depend on the size and location of each particular gate contact (e.g., a dummy gate contact). The number and / or amount of ions in fin 205 can affect the working metallic function of the transistor, which in turn affects the drive strength and threshold voltage of the transistor's gate contacts. Stage 7 conceptually illustrates an example of how ions from a gate contact (e.g., a dummy gate contact) can diffuse into the fin.

[0059] Stage 8 shows the state after at least one contact interconnect 260 is formed above the gate contact 250. The contact interconnect 260 can be formed using an electroplating process. The contact interconnect 260e is coupled to the gate contact 250e.

[0060] As shown in Figure 13D, stage 9 illustrates the state after interconnect 270 has been formed. Interconnect 270 can be formed using an electroplating process. Interconnect 270 can be an M1 layer interconnect of an integrated device. Interconnect 270 can be formed such that interconnect 270e is coupled to contact interconnect 260e. Stage 9 can illustrate an example of a structure 300 coupled to at least one dummy gate contact. The dummy gate contact can be considered part of structure 300.

[0061] Although not shown for clarity, one or more dielectric layers may be formed above and / or around the fin 205, gate 210, gate contact 250, contact interconnect 260, and / or interconnect 270. An exemplary flowchart of a method for fabricating a structure including a transistor coupled to a dummy gate contact.

[0062] In some embodiments, manufacturing a structure coupled to a dummy gate contact includes several procedures. FIG14 shows an exemplary flowchart of a method 1400 for providing or manufacturing a structure coupled to a dummy gate contact. In some embodiments, the method 1400 of FIG14 can be used to provide or manufacture the structures coupled to dummy gate contacts of FIG3 and 5-11 described in this disclosure.

[0063] It should be noted that the method of FIG14 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing a structure coupled to a dummy gate contact. In some embodiments, the order of procedures may be changed or modified.

[0064] The method provides (at 1405) a substrate 202. The substrate 202 may include silicon. The substrate 202 may be doped with a P-type dopant or an N-type dopant. The substrate 202 may include a well (e.g., an N-type well, a P-type well). Stage 1 of FIG13A may illustrate an example of providing the substrate 202.

[0065] The method forms fins 205 in the substrate (at 1410). The fins can be formed using a photomask, photoresist, and etching process. The fins 205 can be formed by forming trenches 1305 in the substrate 202. Separated portions of the fins can form the basis for the source and drain electrodes of a transistor. Stage 2 of FIG13A can illustrate an example of forming fins in the substrate.

[0066] The method forms oxide 204 (at 1415) over substrate 202 and in trench 1305, such that oxide 204 is between fins 205. An oxide deposition process can be used to form oxide 204. A planarization process, such as a chemical mechanical polishing (CMP) process, can be used to planarize oxide 204. Stage 3 of Figure 13A can illustrate an example of oxide formation.

[0067] The method described removes (at 1420) portions of oxide 204. An oxide recessing process can be used to remove portions of oxide 204. An etching process can be used to remove portions of oxide 204, exposing the sides of fin 205. Stage 4 of Figure 13B can show the state after oxide recessing.

[0068] The method forms a gate oxide 209 (at 1425) over portions of oxide 204 and fin 205. A deposition process can be used to form the gate oxide 209. Stage 5 of Figure 13B can illustrate an example of the formation of the gate oxide.

[0069] The method forms a gate 210 (at 1430) over the fin 205 and oxide 204. The gate 210 may be formed over the gate oxide 209. The gate 210 may comprise a polycrystalline silicon layer doped with a dopant (e.g., N+ dopant). The gate 210 may be formed using a deposition process. Stage 6 of Figure 13B may illustrate an example of a gate formed over the fin.

[0070] The method forms a gate contact 250 (at 1435) above the gate 210. At least one gate contact may be a dummy gate contact, and at least one gate contact may be a drive gate contact configured to provide voltage to the gate 210. The gate contact 250 may be formed using an electroplating process. Stage 7 of Figure 13C may illustrate an example of providing a dummy gate contact.

[0071] The method forms at least one contact interconnect 260 over at least one gate contact 250 (at 1440). The contact interconnect 260 can be formed using an electroplating process. In some embodiments, a gate contact defined as a dummy gate contact may not have a contact interconnect coupled thereto. Stage 8 of FIG13C can illustrate an example of forming a contact interconnect. In some embodiments, at least one contact interconnect may be a dummy contact interconnect.

[0072] The method forms an interconnect 270 over the structure (at 1445). Specifically, the interconnect 270 can be formed over at least one gate contact 250 and / or at least one contact interconnect 260. An electroplating process can be used to form the interconnect 270. The interconnect 270 can be an M1 layer interconnect of the integrated device. Stage 9 of Figure 13D can illustrate the state after the interconnect 270 has been formed. An exemplary integrated device including a transistor and a dummy gate contact.

[0073] The use of dummy gate contacts is not limited to finFETs. Dummy gate contacts as described in this disclosure can be applied to other transistors, such as planar FET transistors 200 and gate-all-loop (GAA) FETs. Figure 15 shows an example of a structure 1500 including a first GAA FET 1501 and a second GAA FET 1502. The first GAA FET 1501 includes a substrate 202, a source 1506a, a drain 1508a, a plurality of channels 1509a, and a gate 1510. The second GAA FET 1502 includes a substrate 202, a source 1506b (not shown), a drain 1508b, a plurality of channels 1509b, and a gate 1510.

[0074] Gate contacts 1550a and 1550b are coupled to gate 1510. Gate contact 1550a may be a dummy gate contact, and gate contact 1550b may be a driven gate contact. Contact interconnect 1560 is coupled to gate contact 1550b. Interconnect 1570 is coupled to contact interconnect 1560. Structure 1500, the first GAA FET 1501, and / or the second GAA FET 1502 may be implemented in any integrated device described herein. Any dummy gate contact described herein may be implemented above structure 1500, the first GAA FET 1501, and / or the second GAA FET 1502. Procedures known to those skilled in the art can be used to fabricate GAA FETs. Exemplary integrated devices including transistors and dummy gate contacts.

[0075] FIG16 shows a cross-sectional view of an integrated device 1600 including a transistor and a dummy gate contact. The integrated device 1600 includes a substrate 1620, a plurality of device level cells 1622 (e.g., logic cells), an interconnect portion 1604, and a package portion 1606. The plurality of device level cells 1622 are formed over the substrate 1620. The plurality of device level cells 1622 may form a device level layer of the integrated device 1600. In some embodiments, the plurality of device level cells 1622 may include portions of the substrate 1620. In some embodiments, the substrate 1620, the device level layer, and the plurality of device level cells 1622 may be referred to as a substrate portion 1602 of the integrated device 1600.

[0076] Multiple device-level units 1622 may include one or more transistors. As shown in FIG16, one of the device-level units includes a structure 700 (shown and described in FIG7) that includes a transistor coupled to a dummy gate contact. Note that the integrated device 1600 may include other types of devices, structures, and / or transistors as described in this disclosure. In some embodiments, different units of the integrated device 1600 may use transistors of different or identical structures with various configurations coupled to gate contacts, contact interconnects, and / or interconnects. The integrated device 1600 may include any configuration of transistors, gate contacts, dummy gate contacts, contact interconnects, and / or dummy contact interconnects described in this disclosure. The integrated device 1600 may include device-level units 1622 having transistors, gate contacts, dummy gate contacts, contact interconnects, and / or dummy contact interconnects with identical configurations, transistors, gate contacts, dummy gate contacts, contact interconnects, and / or dummy contact interconnects with different configurations, and / or combinations thereof. Gate contacts (e.g., 250) can be configured to be electrically coupled to interconnects of the integrated device (e.g., interconnects of the M1 metal layer). For example, gate contacts can be configured to be electrically coupled to contact interconnects that are coupled to M1 layer interconnects.

[0077] An interconnect portion 1604 is formed over the substrate portion 1602. Specifically, the interconnect portion 1604 is formed over a plurality of device-level cells 1622. The interconnect portion 1604 includes a wiring layer. The interconnect portion 1604 includes a plurality of interconnects 1640 (e.g., traces, pads, vias) and at least one dielectric layer 1642. The interconnect portion 1604 can provide interconnections between a plurality of transistors. An M1 layer interconnect may be part of the interconnect portion 1604. The interconnect portion 1604 may include other metal layers (e.g., M2 layer interconnects, M3 layer interconnects).

[0078] A package portion 1606 is formed over the interconnect portion 1604. The package portion 1606 includes a passivation layer 1660, an under-bump metallization (UBM) layer 1662, and solder interconnects 1664. Note that the size and shape of the integrated device 1600 are exemplary. Furthermore, the components of the integrated device 1600 shown may not be to scale. Exemplary sequence for manufacturing an integrated device including a transistor and a dummy gate contact.

[0079] In some embodiments, manufacturing an integrated device including a transistor and a dummy gate contact includes several procedures. FIG17 (including FIG17A-17B) illustrates an exemplary sequence for providing or manufacturing an integrated device including a transistor and a dummy gate contact. In some embodiments, the sequence of FIG17A-17B can be used to provide or manufacture the integrated device of FIG16 and / or other integrated devices described in this disclosure.

[0080] It should be noted that the sequences of Figures 17A-17B may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing an integrated device including a transistor and a dummy gate contact. In some embodiments, the order of the procedures may be changed or modified. In some embodiments, one or more procedures may be replaced or substituted without departing from the spirit of this disclosure.

[0081] As shown in FIG17A, stage 1 illustrates the state after substrate 1620 is provided. Different embodiments may provide different materials for substrate 1620. In some embodiments, substrate 1620 may include silicon (Si). Substrate 1620 may be doped or undoped. Substrate 1620 may be a semi-insulating substrate. As used herein, the term "undoped" may mean that the component has no dopant or may include a low level of dopant. The low level of doping may be a residual doping level.

[0082] Stage 2 illustrates the state after a device-level layer is formed over the substrate 1620. The device-level layer includes a plurality of device-level cells 1622. Therefore, Stage 2 illustrates the state after a plurality of device-level cells 1622 are formed over the substrate 1620. In some embodiments, a front-end process (FEOL) can be used to fabricate the device-level layer (e.g., the plurality of device-level cells 1622). As described above, one or more cells in the plurality of device-level cells may include transistors and / or gate contacts. Device-level cells may include at least a portion of the structures described in this disclosure (e.g., 300, 500, 600, 700, 800, 900a, 900b, 1000a, 1000b, etc.). Figures 13A-13D illustrate the sequence of fabricating transistors and dummy gate contacts. In some embodiments, interconnects may be formed over the gates, sources, and / or drains of one or more transistors and over gate contacts and / or contact interconnects.

[0083] Stage 3 illustrates the state after the interconnect portion 1604 has been formed. The interconnect portion 1604 may include a plurality of interconnects 1640 (located on different metal layers) and at least one dielectric layer 1642. In some embodiments, a back-end process (BEOL) procedure may be used to fabricate the interconnect portion 1604. The interconnect portion 1604 may be configured to electrically couple one or more transistors.

[0084] As shown in Figure 17B, stage 4 shows the state after the passivation layer 1660 and the under-bump metallization (UBM) layer 1662 are formed over the interconnect portion 1604.

[0085] Stage 5 illustrates the state after the solder interconnect is coupled to the under-bump metallization (UBM) layer 1662. An exemplary flowchart of a method for manufacturing an integrated device including transistors and dummy gate contacts.

[0086] In some embodiments, providing an integrated device including a transistor and a dummy gate contact includes several procedures. FIG18 shows an exemplary flowchart of a method 1800 for providing or manufacturing an integrated device including a transistor and a dummy gate contact. In some embodiments, the method 1800 of FIG18 can be used to provide or manufacture the integrated device of FIG16 and / or other integrated devices described in this disclosure.

[0087] It should be noted that the method of FIG18 can be combined with one or more procedures to simplify and / or clarify the method for providing or manufacturing an integrated device including a transistor and a dummy gate contact. In some embodiments, the order of the procedures may be changed or modified.

[0088] The method provides (at 1805) a substrate (e.g., 1620). Different embodiments may provide different materials for the substrate. In some embodiments, the substrate may include silicon (Si). The substrate may be doped with an N-type dopant or a P-type dopant. The substrate may be a semi-insulating substrate. Stage 1 of FIG17A illustrates an example of providing a substrate.

[0089] The method forms (at 1810) a device-level layer (e.g., a plurality of device-level cells 1622) over a substrate. In some embodiments, a front-end process (FEOL) can be used to fabricate the device-level layer (e.g., the plurality of device-level cells 1622). The device-level layer may include a plurality of device-level cells. A device-level cell may include one or more active devices. One or more device-level cells may include transistors (e.g., 1102), as described in this disclosure. Forming the device-level layer may include forming one or more transistors and one or more dummy gate contacts. In some embodiments, forming the device-level layer includes forming a transistor over a substrate. In some embodiments, forming a transistor over a substrate (e.g., a first transistor) includes forming a transistor including a source, a drain, and a gate. The method may form a first gate contact over the gate of the transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of an integrated device (e.g., an interconnect of the M1 layer). The method may form a second gate contact over the gate, wherein the second gate contact is directly electrically coupled to the gate only. Examples of forming transistors and dummy gate contacts over a substrate are shown and described in Stage 2 of Figures 13A-13D and Figure 17A.

[0090] The method forms (at 1815) interconnect portions 1604 over a device-level layer (e.g., multiple device-level cells 1622) and / or a substrate 1620. Interconnect portions 1604 may include multiple interconnects 1640 and at least one dielectric layer 1642. In some embodiments, a back-end process (BEOL) procedure may be used to form the interconnect portions 1604. Interconnect portions 1604 may include an M1 layer. Interconnect portions 1604 may be configured to electrically couple one or more transistors. Stage 3 of FIG20A illustrates an example of forming interconnect portions 1604.

[0091] The method forms a package portion 1606 (at 1820) over the interconnect portion 1604. The package portion 1606 may include a passivation layer 1660 and an under-bump metallization (UBM) layer 1662. The passivation layer 1660 and the under-bump metallization (UBM) layer 1662 are formed over the interconnect portion 1604. Stage 4 of FIG20B shows an example of forming the package portion 1606.

[0092] The method provides (at 1825) solder interconnect 1664. In some embodiments, solder interconnect 1664 is coupled to under-bump metallization (UBM) layer 1662. Phase 5 of FIG20B illustrates an example of coupling solder interconnect to package portion 1604.

[0093] It should also be noted that the method 1800 of Figure 18 can be used to fabricate (e.g., fabricate simultaneously) several integrated devices on a wafer. The wafer is then diced (e.g., diced) into individual integrated devices. These diced integrated devices can then be coupled to other integrated devices and / or printed circuit boards (PcBs). Exemplary electronic device

[0094] Figure 19 illustrates various electronic devices that can integrate any of the above-described transistors, devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, or PoPs. For example, mobile phone device 1902, laptop computer device 1904, fixed-location terminal device 1906, or wearable device 1908 may include device 1900 as described herein. Device 1900 may be any device and / or integrated circuit (IC) package as described herein. Devices 1902, 1904, 1906, and 1908 shown in Figure 19 are merely exemplary. Other electronic devices may also be characterized by device 1900, including but not limited to groups of devices (e.g., electronic devices) that include mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices with global positioning system (GPS) functionality, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0095] One or more components, programs, features, and / or functions shown in Figures 2 to 12, 13A to 13D, 14 to 16, 17A to 17B, and / or 18 to 19 may be rearranged and / or combined into a single component, program, feature, or function, or included in several components, programs, or functions. Additional elements, components, programs, and / or functions may also be added without departing from the scope of this disclosure. It should also be noted that Figures 2 to 12, 13A to 13D, 14 to 16, 17A to 17B, and / or 18 to 19, and their corresponding descriptions in this disclosure, are not limited to dies and / or ICs. In some embodiments, Figures 2 to 12, 13A to 13D, 14 to 16, 17A to 17B, and / or 18 to 19, and their corresponding descriptions, may be used to manufacture, create, provide, and / or produce devices and / or integrate devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, and / or an interposer.

[0096] Note that the drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the drawings may not be to scale. In some cases, not all components and / or parts may be shown for clarity. In some cases, the location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some embodiments, the various parts and / or parts in the drawings may be optional.

[0097] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as being more preferred or advantageous than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, objects A and C can still be considered coupled to each other—even if they do not directly and physically touch each other. The term “electrically coupled” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The term “encapsulation” means that an object can partially or completely encapsulate another object. The use of the terms “first,” “second,” “third,” and “fourth” (and / or any of the fourth and above) is arbitrary. Any component described may be a first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. It should also be noted that the term “above” as used in this application in the context of one component being above another component may be used to refer to a component on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component above a second component may mean (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is in the second component (e.g., embedded in the second component). As used in this disclosure, the terms “about 'value X'” or “approximately value X” mean within 10% of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0098] In some embodiments, an interconnect is a device or package element or component that allows or facilitates an electrical connection between two points, elements, and / or parts. In some embodiments, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., a seed layer + metal layer). In some embodiments, an interconnect is a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different embodiments may use similar or different procedures to form interconnects. In some embodiments, chemical vapor deposition (CVD) procedures and / or physical vapor deposition (PVD) procedures are used to form interconnects. For example, sputtering, spraying, and / or electroplating procedures may be used to form interconnects.

[0099] Furthermore, note that the various disclosures contained herein may be described as programs shown as flowcharts, block diagrams, structure diagrams, or block diagrams. Although a flowchart may describe operations as a sequential procedure, many operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. The program terminates when its operations are completed.

[0100] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely examples and should not be construed as limiting the scope of this disclosure. The descriptions of various aspects of this disclosure are intended to be illustrative and not to limit the scope of the claims. Therefore, the teachings herein can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

[0101] Further embodiments are described below to facilitate understanding of the present invention.

[0102] An integrated device includes a substrate and a first transistor located above the substrate, wherein the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, wherein the second gate contact is directly electrically coupled to the gate only. The integrated device further includes a second transistor located above the substrate, wherein the second transistor includes a gate. The second gate contact is configured to adjust a threshold voltage required to induce a first current in the first transistor and a second current in the second transistor. The first transistor includes a first fin and a second fin. The first gate contact may be located above a region including the first fin and the second fin. The second gate contact may be located above a region including the first fin and the second fin. The second gate contact may be a dummy gate contact.

[0103] An apparatus includes a substrate and a first transistor located above the substrate, wherein the first transistor includes a gate. The apparatus includes a first gate contact coupled to the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of an integrated device. The apparatus includes a member for regulating a voltage required to induce a first current in the first transistor, wherein the regulating member is directly electrically coupled to the gate only.

[0104] An integrated device includes a substrate and a first transistor located above the substrate, wherein the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, and contact interconnects coupled to the second gate contact, wherein the contact interconnects are directly electrically coupled to the gate contact only.

[0105] A method for manufacturing an integrated device. The method provides a substrate. The method forms a first transistor over the substrate, wherein the first transistor includes a gate. The method forms a first gate contact over the gate of the first transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The method forms a second gate contact over the gate, wherein the second gate contact is directly electrically coupled to the gate only. [Simplified Explanation of the Diagram]

[0107] When considered in conjunction with the drawings, various features, properties and advantages may become apparent according to the specific implementation methods described below, in which the same schematic symbols are always correspondingly identified.

[0108] Figure 1 shows a planar field-effect transistor (FET).

[0109] Figure 2 shows an example of a fin field-effect transistor (FET) coupled to a gate contact.

[0110] Figure 3 shows an example of a finFET coupled to at least one dummy gate contact.

[0111] Figure 4 shows examples of various positions of the gate contact relative to the transistor.

[0112] Figure 5 shows an example of a finFET coupled to the gate contact.

[0113] Figure 6 shows an example of a finFET coupled to the gate contact.

[0114] Figure 7 shows an example of a finFET coupled to a gate contact and a dummy gate contact.

[0115] Figure 8 shows an example of a finFET coupled to a gate contact and a dummy gate contact.

[0116] Figure 9 shows an example of a finFET coupled to a gate contact and a dummy gate contact.

[0117] Figure 10 shows an example of a finFET coupled to a gate contact and a dummy gate contact.

[0118] Figure 11 shows an example of a finFET coupled to a gate contact and a dummy gate contact.

[0119] Figure 12 shows the sequence of coupling the gate contact and the dummy gate contact to the transistor.

[0120] Figure 13 (including Figures 13A to 13D) illustrates an exemplary sequence for manufacturing a finFET coupled to a dummy gate contact.

[0121] Figure 14 shows an exemplary flowchart of a method for manufacturing a finFET coupled to a dummy gate contact.

[0122] Figure 15 shows a gate full-loop (GAA) FET coupled to a dummy gate contact.

[0123] Figure 16 shows a view of an integrated device including a transistor coupled to a dummy gate contact.

[0124] Figure 17 (including Figures 17A to 17B) illustrates an exemplary sequence for manufacturing an integrated device including a transistor coupled to a dummy gate contact.

[0125] Figure 18 shows an exemplary flowchart of a method for manufacturing an integrated device including a transistor coupled to a dummy gate contact.

[0126] Figure 19 illustrates various electronic devices that can integrate as described herein, such as dies, integrated devices, integrated passive devices (IPDs), device packages, packages, integrated circuits and / or PCBs.

Claims

1. An integrated device, comprising: A substrate, comprising a first active region, a second active region, and a field region located between the first active region and the second active region; A first transistor, located above the substrate, wherein the first transistor includes a first active region and a gate; a second transistor, located above the substrate, wherein the second transistor includes a second active region and a gate; a first gate contact coupled to the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device; and a second gate contact coupled to the gate, wherein the second gate contact is completely located above the field region of the substrate, wherein the second gate contact is directly electrically coupled to the gate only, and wherein the first gate contact is located above the field region of the substrate.

2. The integrated device according to claim 1 further includes a contact interconnect coupled to the first gate contact.

3. The integrated device according to claim 1, wherein, The second gate contact is configured to adjust the threshold voltage required to induce a first current in the first transistor and a second current in the second transistor.

4. The integrated device according to claim 1, wherein, The first transistor includes a p-channel field-effect transistor (PFET), and the second transistor includes an n-channel field-effect transistor (NFET).

5. The integrated device according to claim 1, wherein, The first transistor includes an n-channel field-effect transistor (NFET), and the second transistor includes a p-channel field-effect transistor (PFET).

6. The integrated device according to claim 1, wherein, The first transistor includes a first fin and a second fin.

7. The integrated device according to claim 6, wherein, The first gate contact is located above the region including the first fin and the second fin.

8. The integrated device according to claim 6, wherein, The second transistor includes a third fin and a fourth fin.

9. The integrated device according to claim 6, wherein, The first transistor includes a p-channel field-effect transistor (PFET).

10. The integrated device according to claim 6, wherein, The first transistor includes an n-channel field-effect transistor (NFET).

11. The integrated device according to claim 1, further comprising a third gate contact coupled to the gate, wherein, The third gate contact is directly electrically coupled to the gate, while the second gate contact is a dummy gate contact.

12. The integrated device according to claim 1, wherein, The first transistor is a p-channel field-effect transistor (PFET), the second transistor is an n-channel field-effect transistor (NFET), and the first gate contact is located above the first transistor.

13. The integrated device according to claim 1, wherein, The first transistor is a p-channel field-effect transistor (PFET), the second transistor is an n-channel field-effect transistor (NFET), and the first gate contact is located above the second transistor.

14. The integrated device according to claim 1, wherein, The first transistor includes a planar transistor, a field-effect transistor (FET), or a gate-all-loop (GAA) FET.

15. An integrated device, comprising: A substrate includes: a first active region, a second active region, and a field region located between the first active region and the second active region; a third active region, a fourth active region, and a second field region located between the third active region and the fourth active region; a first transistor located above the substrate, wherein the first transistor includes the first active region and a gate; a second transistor located above the substrate, wherein the second transistor includes the second active region and the gate; a first gate contact coupled to the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device; a second gate contact coupled to the gate, wherein the second gate contact is located above the field region of the substrate, and wherein the second gate contact is directly electrically coupled to the gate only; a third transistor located above the substrate, wherein the third transistor includes the third active region and the second gate; and a fourth transistor located above the substrate, wherein the fourth transistor includes the fourth active region and the second gate. A third gate contact coupled to the second gate of the third transistor and the fourth transistor, wherein the third gate contact is configured to be electrically coupled to another interconnect of the integrated device; and a fourth gate contact coupled to the second gate, wherein the fourth gate contact is directly electrically coupled to the second gate only, wherein the third gate contact and the fourth gate contact are located above the third active region of the substrate or the fourth active region of the substrate.

16. The integrated device according to claim 15, wherein, The integrated device is included in a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, and devices in motor vehicles.

17. The integrated device according to claim 15, wherein, The first transistor includes a planar transistor, a field-effect transistor (FET), or a gate-all-loop (GAA) FET.

18. A device for adjusting a threshold voltage, comprising: A substrate, comprising a first active region, a second active region, and a field region located between the first active region and the second active region; A first transistor, located above the substrate, wherein the first transistor includes a first active region and a gate; a second transistor, located above the substrate, wherein the second transistor includes a second active region and the gate; a first gate contact coupled to the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of an integrated device; and a member for adjusting the threshold voltage required to induce a first current in the first transistor, wherein the member for adjustment is directly electrically coupled to the gate only, wherein the first gate contact and the member for adjusting the threshold voltage are located above the first active region.

19. The apparatus according to claim 18 further includes a third gate contact located coupled to the gate.

20. The apparatus according to claim 18, wherein, The component for adjusting the threshold voltage is configured to adjust the threshold voltage required to induce the first current in the first transistor and the second current in the second transistor.

21. The apparatus according to claim 20, wherein, The first transistor includes a p-channel field-effect transistor (PFET), and the second transistor includes an n-channel field-effect transistor (NFET).

22. The apparatus according to claim 20, wherein, The first transistor includes an n-channel field-effect transistor (NFET), and the second transistor includes a p-channel field-effect transistor (PFET).

23. The apparatus according to claim 18, wherein, The component used to adjust the threshold voltage includes a dummy gate contact.

24. The apparatus according to claim 18, wherein, The component for regulating the threshold voltage includes dummy contact interconnects.

25. An integrated device, comprising: A substrate, comprising a first active region, a second active region, and a field region located between the first active region and the second active region; A first transistor, located above the substrate, includes a first active region and a gate; a second transistor, located above the substrate, includes a second active region and a gate; a first gate contact coupled to the gates of the first and second transistors, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device; a second gate contact coupled to the gate; and a contact interconnect coupled to the second gate contact, wherein the contact interconnect is directly electrically coupled to the gate contact only, wherein the first gate contact, the second gate contact, and the contact interconnect are located above the first active region of the substrate.

26. The integrated device according to claim 25 further includes a third gate contact coupled to the gate.

27. The integrated device according to claim 25, wherein, The second gate contact is configured to adjust the threshold voltage required to induce a first current in the first transistor and a second current in the second transistor.

28. The integrated device according to claim 27, wherein, The first transistor includes a p-channel field-effect transistor (PFET), and the second transistor includes an n-channel field-effect transistor (NFET).

29. The integrated device according to claim 27, wherein, The first transistor includes an n-channel field-effect transistor (NFET), and the second transistor includes a p-channel field-effect transistor (PFET).

30. The integrated device according to claim 25, wherein, The substrate further includes a third active region, a fourth active region, and a second field region located between the third active region and the fourth active region; The integrated device further includes: a third transistor located above the substrate, wherein the third transistor includes the third active region and a second gate; a fourth transistor located above the substrate, wherein the fourth transistor includes the fourth active region and a second gate; a third gate contact coupled to the second gate of the third transistor and the fourth transistor, wherein the third gate contact is configured to be electrically coupled to another interconnect of the integrated device; and a fourth gate contact coupled to the second gate, wherein the fourth gate contact is directly electrically coupled to the second gate only, wherein the third gate contact and the fourth gate contact are located above the third active region of the substrate or the fourth active region of the substrate.

31. A method for manufacturing an integrated device, comprising: A substrate is provided that includes a first active region, a second active region, and a field region located between the first active region and the second active region; A first transistor is formed above the substrate, wherein the first transistor includes a first active region and a gate; a second transistor is formed above the substrate, wherein the second transistor includes a second active region and a gate; a first gate contact is formed above the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device; and a second gate contact is formed above the gate, wherein the second gate contact is directly electrically coupled to the gate only, wherein the first gate contact and the second gate contact are formed such that the first gate contact and the second gate contact are located above the first active region of the substrate.

32. The method according to claim 31 further includes forming a third gate contact above the gate, such that the third gate contact is directly electrically coupled to the gate only.

33. The method according to request item 31, wherein, The second gate contact is configured to adjust the threshold voltage required to induce a first current in the first transistor and a second current in the second transistor.

34. The method according to claim 33, wherein, The first transistor includes a p-channel field-effect transistor (PFET), and the second transistor includes an n-channel field-effect transistor (NFET).

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