Method for mask synthesis using design guided offsets, and apparatus and nontransitory computer-readable medium for mask synthesis thereof

Abstract

The state described herein pertains to mask synthesis using design-guided offset. A target shape is obtained on an image surface to be fabricated using a mask based on an integrated circuit design. Rays are generated emanating from individual anchor points. These anchor points are located on either a boundary of the target shape or a boundary of a mask shape within the mask. For each of these rays, a distance is defined between a first intersection point of the ray with the boundary of the target shape and a second intersection point of the ray with the boundary of the mask shape. An analysis is performed by one or more processors, wherein the analysis is configured to modify the isochronous distance based on an error between the target shape and a simulated shape on the image surface produced by the mask shape.

Description

Technical Field

[0001] This document pertains to masking synthesis of designs derived from integrated circuits, and more specifically, to masking synthesis using design-guided offsets. Prior Technology

[0002] With the increasing complexity of masks in recent years, there is a growing ability to synthesize and manufacture curved masks compared to traditional linear mask shapes. These curved mask shapes have imposed new demands on the geometric processing algorithms within the mask synthesis process, as the mask optimization step requires the evolution of more complex shapes. Summary of the Invention

[0003] Some aspects of this description relate to a method for circuit design. The method generally includes: obtaining a target shape on an image surface to be manufactured using a mask based on a design of an integrated circuit; generating rays emanating from individual anchor points located on a boundary of the target shape or a boundary of a mask shape of the mask; defining, for each of the rays, a distance between a first intersection point of the individual ray with the boundary of the target shape and a second intersection point of the individual ray with the boundary of the mask shape; modifying the distance by one or more processors based on an error between the target shape and a obtained shape simulated on the image surface generated by the mask shape; and generating a mask design based on the modified distance for use in manufacturing the target shape on the image surface.

[0004] Some aspects of this description relate to a device for circuit design. The device generally includes a memory and one or more processors coupled to the memory. The memory and the one or more processors are configured to: obtain a target shape on an image surface to be manufactured using a mask based on an integrated circuit design; generate rays emanating from individual anchor points located on a boundary of the target shape or a boundary of a mask shape of the mask; for each of the rays, define a distance between a first intersection point of the individual ray with the boundary of the target shape and a second intersection point of the individual ray with the boundary of the mask shape; and perform an analysis by the one or more processors, the analysis being configured to modify the distance based on an error between the target shape and a resulting shape simulated on the image surface generated by the mask shape.

[0005] Some aspects of this description relate to a non-transitory computer-readable medium containing executable instructions that, when executed by one or more processors of a device, cause the device to: obtain a target shape on an image surface to be manufactured using a mask based on an integrated circuit design; generate rays emanating from individual anchor points located on a boundary of the target shape or on a boundary of a mask shape of the mask; for each of the rays, define a distance between a first intersection point of the individual ray with the boundary of the target shape and a second intersection point of the individual ray with the boundary of the mask shape; and perform an analysis by one or more processors configured to modify the distance based on an error between the target shape and a resulting shape simulated on the image surface generated by the mask shape.

[0006] Other forms of provision include: an apparatus operable, configured, or otherwise adapted to perform the foregoing methods and the methods described elsewhere herein; a non-transitory computer-readable medium having instructions, when executed by one or more processors of a device, to cause the device to perform the foregoing methods and the methods described elsewhere herein; a computer program product embodied on a computer-readable storage medium, including program code for performing the foregoing methods and the methods described elsewhere herein; and an apparatus having components for performing the foregoing methods and the methods described elsewhere herein. By way of example, an apparatus may include a processing system, a device having a processing system, or a processing system cooperating via one or more networks.

[0007] The following description and accompanying illustrations are for illustrative purposes and illustrate certain features. Simple Explanation of the Diagram

[0008] The contents of this description will be more fully understood from the detailed description given below and the accompanying drawings of the examples described herein. These drawings are intended to provide an understanding of the examples described herein and do not limit the scope of this description to these specific examples. Furthermore, these drawings are not necessarily drawn to scale.

[0009] [Figure 1] is a flowchart of a method for mask composition using design-guided offsets, based on some examples of the contents of this document.

[0010] [Figure 2] Depicts a layout of a method for masking composition in Figure 1, based on some examples of the content of this document.

[0011] [Figure 3] shows some examples of custom-owned area boundaries based on the contents of this record.

[0012] [Figure 4] shows rays emanating from anchor points on a self-mask, according to some examples of the contents of this record.

[0013] [Figure 5] Depicts a layout used to illustrate the negative distance of a ray, based on some examples of the contents of this record.

[0014] [Figure 6] Depicts some examples of the layout used to illustrate the mask shape formed after removing the degenerate portion of Figure 5, based on the contents of this record.

[0015] [Figure 7] Depicts some examples of layouts used to illustrate the appearance of mask shapes with Manhattan and / or straight edges, based on the contents of this document.

[0016] [Figure 8] illustrates the boundary of an area formed in the space between a design objective and another design objective.

[0017] [Figure 9] A flowchart depicting various processes used in the design and manufacture of integrated circuits according to some examples of the contents of this document.

[0018] [Figure 10] A diagram illustrating an example computer system in which the contents of this document can be operated. Implementation

[0019] The patterns described herein pertain to mask synthesis using design-guided offsets. This document describes how to trace mask evolution, generalized from a more typical optical proximity correction (OPC) technique for a given wafer design target / target offset segment. Optical proximity correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors attributed to diffraction or procedural effects. In some patterns, a data structure of rays emanating from anchor points (e.g., edges and corners of the design target) is used, and for each ray, the distance between the intersection point of the ray and the boundary of the mask shape and the intersection point of the ray and the boundary of the design target is traced. Using these distances, a method is introduced that benefits from correspondence between the design target and the mask location without using the same edge orientation of the mask and the design edge, thus allowing for a curve solution with better quality of lithography (QOR).

[0020] Various methods for evolving curve masking may involve using pixel-based approaches, such as level sets. These are computationally more intensive than the patterns described herein and are susceptible to inconsistencies related to shift differences. Other methods may include free-form point tracing methods for points on polygon edges. These are computationally difficult, struggle to generate illegal or unclear point intersections, and may lose connectivity between the mask and the design edges, a characteristic required for typical OPC operations.

[0021] The method used for typical OPC mask shape tracking is applied across multiple mask compositing applications, including but not limited to rule-based OPC, model-based OPC, rule-based retargeting, and model-based etch-retargeting correction. Curved versions of these applications can be implemented using the methods described herein.

[0022] For rule-based OPC, this method constructs a set of geometric rules that determine modifications to the design that produces the mask. For example, measurable geometric quantities such as pattern density, polygon edge length, distance from a sub-segment of an edge to a corner vertex, etc., can be used. A rule table or function can be constructed that takes these various geometric quantities as input and outputs the amount of local modification to the design. This modification can be specified by assigning edge or sub-edge perturbations to polygon boundaries or other geometric manipulations in the normal direction. Various patterns can be used as algorithms to perform polygon manipulation to generate rule-based curve-masked polygons.

[0023] For model-based OPC, masking is produced similarly to rule-based OPC, except that the method for determining the amount of polygon manipulation is based on model simulation feedback, such as wafer targeting error or other wafer-level image characteristics. Various patterns can be used as algorithms to manipulate a given input polygon to produce a corrected masked polygon. Typically, model-based OPC will have iterative steps, allowing the same polygon to be recorrected given additional model-based feedback from previous iterations of polygon movement.

[0024] Rule-based retargeting methods are similar to rule-based OPC, except that the output polygon shape is used as the input wafer target for subsequent lithography correction algorithms (e.g., OPC or Inverse Lithography (ILT)). Therefore, the contents of the rule table or function may have different targets, but the procedure for determining geometric measurements, assigning geometric changes to various parts of the design, and modifying the design is similar to rule-based OPC.

[0025] Similarly, etching models are often used to modify design objectives to produce wafer targets for lithography algorithms (such as OPC or ILT). Various specific instances can be used as algorithms to manipulate input design objectives to produce wafer targets.

[0026] The various features are described below with reference to the diagrams. It should be noted that these diagrams may be drawn to scale or not, and throughout the diagrams, elements with similar structures or functions are represented by the same element symbols. It should be noted that the diagrams are intended only to aid in the description of the features. They are not intended as an exhaustive description of the claimed subject matter or as a limitation on the scope of the claimed subject matter. Furthermore, the examples shown need not possess all the states or advantages demonstrated. States or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so illustrated or so explicitly described. Additionally, the methods described herein may be described in a specific order of operation, but other methods according to other examples may be implemented by more or fewer operations in various other orders (e.g., including different sequences or parallel executions of various operations).

[0027] Furthermore, this document uses various terms as used in this technique. For example, as used in this technique and as understood by one of ordinary skill in the art, "optimization" refers to the selection of a certain improvement (if available) of a mathematical formula for a problem within the structure of the implemented algorithm for a particular identified characteristic, without implying an absolute or global optimum improvement of the characteristic (as the term is more commonly used). For example, in some cases where optimization can determine a minimum, the minimum may be a local minimum rather than a global minimum.

[0028] Figure 1 is a flowchart of a method 100 for mask composition using design-guided offsets, based on some examples. The method 100 is described below in the context of various figures, specifically Figure 2, to illustrate its characteristics. These figures are provided only as examples, and those skilled in the art will readily understand the application of method 100 in other examples. Various figures, specifically Figure 2, may show a portion or fewer of all certain types of components depicted in the respective figures. This is to avoid confusion among the various depicted characteristics. Those skilled in the art will readily understand how the content depicted and described throughout the embodiments applies.

[0029] As described in more detail below, method 100 may be embodied by one or more instruction sets, which may be one or more software modules stored on a non-transitory computer-readable medium. One or more processors of a computer system may be configured to read and execute one or more instruction sets, which cause one or more processors to perform various operations or steps of method 100. Further details are provided below. In some instances, some operations or steps of method 100 may be embodied as one or more instruction sets as one or more software modules, and other operations or steps of method 100 may be embodied as one or more other instruction sets as one or more other software modules. In some instances, different software modules may be distributed and stored on different non-transitory computer-readable media on different computer systems for execution by different processors of different computer systems.

[0030] Referring to Figure 1, at 102, an electronic representation of the integrated circuit design is obtained. The electronic representation may be, for example, a GDS file or something similar. The integrated circuit design may include or indicate design target features (or design targets) patterned in a photosensitive material (e.g., photoresist) by a lithography process during the fabrication of the integrated circuit on a semiconductor die (e.g., also a portion of a wafer). The design targets can be used to form a mask used during the lithography process. Figure 2 depicts a polygon (e.g., a feature to be printed in a photosensitive material) of design target 202 as an example.

[0031] Referring to Figure 1, at point 104, the edge corresponding to each design target of the mask is segmented. Referring to Figure 2, segment 204 is along the edge of design target 202 and represents a segmentation of the design. Segmentation of one or more design targets can be the first step in an OPC solution, specifying the granularity of the lithography target points on the wafer and the mask coarseness. For simplicity, three segments 204 are shown, with multiple identical segments extending along the edge of design target 202. The method used to determine the segments 204 along the polygonal edge of OPC uses a rule-based or model-based function that collects geometric measurements or lithography simulation feedback, respectively, and determines the positions where the segment endpoints should be placed along the edge of the design polygon to decompose the design edge into a series of end-to-end segments. The input to this function is similar to the input described above with the rule-based and model-based OPC methods.

[0032] Referring back to Figure 1, rays emanating from individual anchor points are generated at point 106. The anchor points can vary depending on the implementation. In an example implementing mask evolution, the anchor points may be along the edges and corners of the design target 202. In an example implementing retargeting, the anchor points may be along the edges and corners (if present) of the mask shape corresponding to the design target. In these retargeting implementations, the mask shape corresponding to the design target can be initialized, for example, by laterally perturbing the edges of the design target by a certain amount.

[0033] Figure 2 is illustrated in the context of anchor points along the edges and corners of design target 202. The concepts described herein can be modified for application to retargeting implementations. Rays 206 are illustrated in Figure 2. Each ray 206 in Figure 2 emanates from an anchor point on the edge of design target 202 or on the outer convex corner formed by the edge. In the example of Figure 2, one or more rays may emanate from an anchor point (e.g., anchor point 290) on the concave corner of the polygon of design target 202 on the inner side of the polygon. Rays 206 emanating from anchor points on the edge (e.g., anchor point 292) emanate in a direction perpendicular to the respective edge of design target 202. In some instances, each segment 204 along the edge of design target 202 has one or more rays 206 emanating from respective anchor points on the respective segment 204.

[0034] In some instances, each corner of the polygon of design target 202 (whether convex or concave) may be an anchor point and may have one or more rays 206 emanating from it. An example corner 208 is illustrated in Figure 2, and its shape is described herein for illustrative purposes. The description provided for corner 208 also applies to other corners, whether convex or concave. An angular span 210 is located at corner 208 and is formed between respective directions 212, 214, which extend from corner 208 and are perpendicular to the two segments that satisfy the formation of corner 208. Rays 206 emanating from the anchor point on corner 208 are emanating in respective directions, which form an equal angle 216 between each adjacent pair of rays 206 from corner 208. Angle 218 is formed between the respective normal directions 212, 214 and the corresponding nearest ray 206 emanating from corner 208. In some instances, each of angles 218 may be half of angle 216 or equal to angle 216.

[0035] The polygon orientation, such as the order of points on the exterior of the polygon surrounding design target 202 in a counterclockwise direction, can be selected so that by examining the normal direction of the edges that meet at the corners, it can be determined whether a particular corner of design target 202 should have rays extending outside the polygon (at convex corners) or inside (at concave corners). A finite number of corners can be selected to generate rays fanning out over the angular span.

[0036] Referring to Figure 1, at point 108, a possessing region boundary is generated. This possessing region boundary is formed within design target 202. In some configurations, one or more other possessing region boundaries are formed in the space between the design target and one or more other design targets, as described in more detail with reference to Figure 8. Each possessing region boundary may be a midline transformation (MAT) of the design target or generate the space between the design targets to which the possessing region boundary is directed.

[0037] Referring to Figure 2, a via-owned area boundary 220 is formed in the design target 202. The via-owned area boundary 220 (and any other via-owned area boundary) indicates which areas the ray 206 is permitted to reach; for example, the via-owned area boundary 220 (and any other via-owned area boundary) can act as a constraint on the extent to which the ray 206 extends. In the illustrated example, the ray 206 emanating from an anchor point on segment 204 extends both outside and inside the polygon of the design target 202, and the ray 206 emanating from segment 204 extending inside the polygon cannot cross the via-owned area boundary 220. In some instances, the space between adjacent features may also have via-owned area boundaries that the ray 206 cannot cross, as shown in Figure 8.

[0038] In some instances, for each corner of design target 202, when the respective corner is a concave corner, the axis of the design target contacting the respective corner, through the boundary of the area, is used to determine the direction of a generalized ray extending outside the design target; or when the respective corner is a convex corner, the axis is used to determine the direction of a generalized ray extending inside the design target. The generalized ray emanates from the corner along the axis of the contacting corner through the boundary of the area. The generalized ray used for each corner can serve as the corresponding ray of each ray emanating from the respective corner, which extends in a generalized direction opposite to those rays. Such a generalized ray can be used when any ray emanating from the corner is degenerate, as described below. Referring to Figure 2, as an example of a convex corner, corner 208 is contacted through axis 221 of the boundary of the area 220, and a generalized ray (not explicitly shown) emanates from corner 208 inside design target 202 and extends along axis 221. This generalized ray can be used as the corresponding generalized ray of each ray 206 shown within the angular span 210. For the purposes of the following description, the generalized ray can be considered as part of each ray emanating from the individual corners, even if extending in generally opposite directions.

[0039] Owned area boundaries can be user-defined and customizable. In some instances, owned area boundaries can also be generated between OPC iterations from the MAT of the current mask shape generated by the stitching process (described later). Figure 3 shows a custom owned area boundary 302 off-center from the center of the polygon of design target 202 as an example. This owned area boundary 302 allows the mask to move beyond the center of the design polygon. Maintaining the topological connectivity of the custom owned area boundary 302 helps ensure that rays from multiple segments and corners do not intersect. Topological connectivity generally refers to the graphical connectivity between two unordered nodes having one, three, or more edges that meet at individual nodes. It should be noted that the input design can be a previously corrected mask, in which case the topological connectivity of the original design can be useful for constructing the custom owned area.

[0040] Referring back to Figure 1, at 110, for each ray, the distance between the individual anchor point of the ray and the analysis point along the ray is defined. The analysis point may vary depending on the implementation. In some implementations, such as in mask evolution where the anchor point is located on the edge of the design target, the analysis point may be the intersection of the mask boundary and the ray. In some implementations, such as in retargeting where the anchor point is located on the boundary of the mask, the analysis point may be the intersection of the edge of the design target and the ray. In these examples, the distance is defined between (i) the intersection of the mask boundary and the ray and (ii) the intersection of the edge of the design target and the ray. In any implementation, the mask shape corresponding to the design target may be initialized, for example, by laterally perturbing the edge of the design target outward by some amount.

[0041] Continuing with the embodiment shown in Figure 2, intersection point 222 represents the individual intersection point of the mask shape 230 and the ray 206. For each ray 206, a distance (labeled d_i for the following description) is generated from the edge or corner of the design target 202, which can be positive or negative. Each ray 206 emanates from that edge or corner to the intersection point 222 on that ray 206, where the positive distance is outside the design target 202 and the negative distance is inside the design target 202. Example positive distance 224 and example negative distance 226 are illustrated. For a ray emanating from a convex corner, the negative distance d_i of the ray indicates ray degeneracy, and the negative distance d_i is inside the design target and measured along the corresponding generalized ray. For a ray emanating from a concave corner, the positive distance d_i of the ray indicates ray degeneracy, and the positive distance d_i is outside the design target and measured along the corresponding generalized ray. Those with ordinary knowledge in the relevant technical field will easily understand the distance of other rays 206.

[0042] Referring back to Figure 2, the mask shape 230 is formed by connecting the intersection points 222 of adjacent rays 206. This is referred to as the spliced ​​mask shape. The mask shape can be initialized to a shape as mentioned above, and the various iterations of the analysis described herein can modify the mask shape.

[0043] Although Figure 2 illustrates rays emanating from anchor points on the edges and corners of the design target, these rays can also emanate from anchor points on the mask, as described. Figure 4 illustrates the spliced ​​mask 406 (e.g., corresponding to mask 230 shown in Figure 2) and the initial mask 410. As shown in Figure 4, ray 404 emanates from anchor points (e.g., anchor point 408) on the initial mask 410. Intersection points 402 represent the respective intersection points of the spliced ​​mask 406 and ray 404. The spliced ​​mask 406 is formed by connecting the intersection points 402 of adjacent rays 404.

[0044] Referring to Figure 1, at 112, an analysis is performed whereby the mask shape is perturbed (e.g., modified) based on distance and corresponding error. In some instances, the analysis (e.g., mask evolution) may require using iterative algorithms to calculate the movement of intersection point 222 or adjustments for each distance d_i along each ray 206. Such an analysis can be performed using mask perturbation or lithography cost function gradients to obtain any amount of change in distance d_i to improve lithography QOR. In some cases, at 114, a mask design is generated based on the modified distance for use in creating a target shape on the image surface.

[0045] This analysis may include obtaining an image profile based on a mask shape. The image profile can be obtained by simulating a lithography process, where the image profile is the shape of a feature patterned in a photosensitive material using a mask shape during the lithography process. For each ray, an error (denoted as e_i for the following description) is obtained, which is the distance between the target point associated with the ray and the intersection point of the ray and the wafer image profile. Each target point can be associated with a ray and can be constructed independently of the ray. Target points can be positioned to represent the boundary of an ideal wafer profile that meets the specifications of the corresponding manufacturing process. Each ray can be associated with one or more target points, and / or each target point can be associated with one or more rays. A sensitivity (denoted as s_i for the following description) to changes in distance d_i can be determined for each ray, where the sensitivity s_i is the ratio of the change in error e_i to the change in distance d_i. This sensitivity s_i can then be used to modify the distance d_i. Modifying the distance d_i will interfere with the mask shape.

[0046] Figure 2 further illustrates the image contour 250 and target points 252 that can be used in the OPC optimization algorithm. As shown, some of the targets 252 are located on the target shape 202, and some of the target points are offset from the target shape 202. For example, some target points near the corners of the target shape 202 may be offset because forming features with sharp corners may be impossible (or at least difficult). The image contour 250 is a feature or image formed in a photosensitive material by simulation using the mask shape 230. Figure 2 shows the constructed target points 252, and typically each target point 252 is associated with the nearest target point 252 and / or the ray 206 incident on the target point 252. The distance between the image contour 250 and the individual target points 252 associated with the individual rays 206 (e.g., plotted example distance 254) is the error e_i (e.g., a signed error) for each target point. If the distance is inside the design target 202, the error is negative; if the distance is outside the design target 202, the error is positive. Sensitivity s_i can be assigned based on prior iterative feedback regarding the masking effect of contour images or other numerical differentiation techniques, or set based on user knowledge or trial and error. Pseudocode for an example (where each ray has an associated target point) is provided below. [For] each ray index i d_i = Distance from ray index i e_i = Error of the target point of ray index i s_i = Δe_i / Δd_i = sensitivity of e_i to changes in d_i d_i += e_i / s_i

[0047] There are also rule-based techniques that use geometric probing methods such as local width, spacing, polygon density, etc., to offset the design edges in order to obtain a non-simulation-based masking synthesis method.

[0048] In some cases, one or more rays 206 may exist with negative distances d_i, which have a larger value than the corresponding distance from the edge of the design feature 202 to the boundary 220 of the possessing region. In this case, the connected mask shape may be constructed to coincide with the boundary 220 of the possessing region of those rays. Figure 5 shows an example of this case, where some rays 206 (e.g., ray 206') have negative distances d_i (e.g., distance 502) such that the value of distance d_i is greater than or equal to the distance along the ray 206 from the edge of the design target 202 to the boundary 220 of the possessing region. As shown in Figure 5, the mask 504 may have an edge 506 that partially coincides with one of the boundaries 220 of the possessing region. Figure 6 shows the mask shapes 602, 604 after the degenerate portion of the boundary 220 of the possessing region (e.g., the edge 506 that coincides with the boundary 220 of the possessing region). For example, a mask design can be generated by modifying the mask shape to form multiple non-overlapping mask shapes (e.g., mask shapes 602, 604) or by merging one mask shape with another mask shape (e.g., merging mask shape 602 with mask shape 604).

[0049] Similarly, in some cases, if the distance d_i of one or more rays 206 is equal to or greater than the distance along the corresponding ray 206 from the respective edge of the design target 202 to the space between different design targets through the boundary of the area, then two mask shapes can be merged into one mask shape.

[0050] In some instances, the connections between intersection points 222 are Manhattan and / or linear or have other geometrical constraints. As shown in Figure 7, a Manhattan mask 702 (partially shown) can be constructed. For rays 206 emanating from the edge of design target 202, linear segments 704 parallel to the respective edges of design target 202 are used to form the Manhattan mask 702. Segments 704 are placed at the corresponding intersection points 222 of rays 206 and have a length corresponding to the length of the edge segment 204 of design target 202 from which rays 206 emanate.

[0051] For a ray 206 emanating from a corner of a design target 202, a segment 704 of ray 206 is parallel to the edge of the design target 202, which is connected to form a corner (from which ray 206 emanates) and forms a minimum angle with each individual ray 206. For a ray 206 that is the central axis of an angular span 210, segment 704 may be parallel to any edge of the design target 202 connected to form the corner. Segment 704 is placed at the corresponding intersection point 222 of the rays 206 and has a length determined by the distance d_i of the ray 206. For example, the length of segment 704 may be proportional to the distance d_i. The larger the distance d_i, the larger it can be positioned to be close to the masking edge of each individual ray 206.

[0052] When adjacent segments 704 are parallel, they are connected at their adjacent ends by splicing segments 706 perpendicular to each other. When adjacent segments 704 are perpendicular (e.g., at a corner), they extend until they intersect. Compared to conventional OPC masking methods, this ray-based method offers the advantage of significantly increasing the range of possible mask shapes while maintaining a direct link between the degrees of freedom (rays) and the design objective.

[0053] Those skilled in the art will readily understand the various data structures that can be implemented in the above processes. For example, the categories of masking objects can be defined based on the polygons and / or edges of the masking pattern. The categories of segments 204 can be defined based on segments 206. The categories of rays 206 may include anchor points, intersection points 222 and corresponding distances d_i (e.g., distances 224, 226), target points 242 and corresponding errors e_i (e.g., distance 254), etc. The methods and / or algorithms described above can operate for these categories and / or in the case of these categories. Different data structures and / or modified data structures can be used in different instances.

[0054] Figure 8 illustrates one or more possessed regions forming a boundary in the space between a design target and one or more other design targets. For example, possessed region 808 is formed between design targets 802, 804, and 806, as shown. Ray 810 emanates from design targets 802, 804, and 806 and terminates at possessed region 808. In other words, possessed region 808 provides a boundary between design targets 802, 804, and 806, at which rays 810 emanating from those design targets terminate.

[0055] Those skilled in the art will readily understand the various modifications to the logical and / or mathematical expressions of the examples described herein. Other examples cover such modifications.

[0056] Figure 9 illustrates a set of examples of processes 900 used to transform and verify design data and instructions representing integrated circuits during the design, verification, and manufacturing of integrated circuits on a semiconductor die. Each of these processes can be structured and enabled as multiple modules or operations. The term "EDA" stands for Electronic Design Automation. At block 910, these processes begin by generating product ideas using information provided by the designer. At block 912, this information is transformed to generate integrated circuits using a set of EDA processes. When the design is complete, at block 934, the design is taped out, i.e., when the original drawing (e.g., geometric pattern) for the integrated circuit is sent to the manufacturing facility to create a mask set, which is then used to manufacture the integrated circuit. After production begins, at block 936, the integrated circuit is fabricated on the semiconductor die, and at block 938, the packaging and assembly process is executed to produce the finished integrated circuit (often referred to as a "chip" or "integrated circuit chip") at block 940.

[0057] Specifications of circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ​​(HDLs) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be transformed into logic-level register transfer level (RTL) descriptions, gate level descriptions, placement level descriptions, or masking level descriptions. Each lower level of representation, as a more detailed description, adds more useful details to the design description, such as more details about the modules being described. Lower levels of representation, as more detailed descriptions, can be generated by a computer, exported from a design library, or generated by another design automation process. One example of a specification language used to specify more detailed descriptions at lower-level detail levels is SPICE, which is used for detailed descriptions of circuits with many analog components. Descriptions at each detail level are enabled for use by the corresponding tools (e.g., formal verification tools) at that level. Design processes can use the sequence depicted in Figure 9. The described process can be enabled by EDA products (or tools).

[0058] During system design, at block 914, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, range (physical and / or number of run-codes), and cost reduction. At this stage, the design can be partitioned into different types of modules or components.

[0059] During logic design and functional verification, at block 916, modules or components in the circuit are specified using one or more description languages, and the functional accuracy of the specifications is checked. For example, components of the circuit can be verified to produce outputs that match the specifications of the circuit or system being designed. Functional verification can be performed using simulators and other programs, such as benchtop generators, static HDL checkers, and formal verifiers. In some instances, specialized systems for components (referred to as simulators or prototyping systems) are used to accelerate functional verification.

[0060] During the synthesis and design phase for testing, at block 918, the HDL code is transformed into a netlist. In some instances, the netlist can be a graphical structure, where the edges of the graphical structure represent components of the circuit, and the nodes of the graphical structure represent how the components are interconnected. Both the HDL code and the netlist can be used by EDA products to verify the hierarchical fabrication of integrated circuits according to a specified design during manufacturing. The netlist can be optimized for use with target semiconductor manufacturing technologies. Additionally, finished integrated circuits can be tested to verify that the integrated circuits meet specifications.

[0061] During netlist verification, at block 920, the netlist is checked to ensure it meets timing constraints and corresponds to the HDL code. During design planning, at block 922, the overall planar layout of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0062] During layout or physical implementation, at block 924, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connection of circuit components via multiple conductors) occur, and a library-selected cell can be executed to enable a specific logic function. As used herein, the term "cell" can specify a set of transistors, other components, and interconnects that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or stored functions (e.g., flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are enabled as both physical structures and analog structures. Parameters are specified for selected cells (based on standard cells) and are accessible in a library for use in EDA products.

[0063] During analysis and extraction, at block 926, the circuit functions are verified at the layout level, allowing for improvements to the layout design. During physical verification, at block 928, the layout design is checked to ensure correct manufacturing constraints, such as Design Rule Check (DRC) constraints, electrical constraints, lithography constraints, and to ensure that the circuit functions match the HDL design specifications. During resolution enhancement, at block 930, the layout geometry is transformed to improve the way the manufacturing circuit design is made. For example, method 100 of Figure 1 can be performed in block 930.

[0064] During the production run, data is generated for use (after applying lithography enhancement where appropriate) to produce a lithography mask. During mask data preparation, at block 932, the production run data is used to produce a lithography mask, which is then used to produce the finished integrated circuit.

[0065] The storage subsystem of a computer system (such as computer system 1000 in Figure 10) may be used for stored programs and data structures, which are used by some or all of the EDA products described herein and products developed by units for the design of libraries and the physical and logical design of the libraries.

[0066] Figure 10 illustrates an example of a computer system 1000, within which a set of instructions can be executed to cause the computer system to perform any or more of the methods discussed herein. In some embodiments, the computer system may be connected (e.g., via a network connection) to other machines or computer systems in a local area network (LAN), an intranet, an inter-enterprise network, and / or the Internet. The computer system may operate as a server or client computer system in a master-slave network environment, as a peer computer system in a peer (or distributed) network environment, or as a server or client computer system in a cloud computing infrastructure or environment.

[0067] A computer system may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a networked appliance, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be performed by the computer system. Furthermore, although only a single computer system is described, the term "computer system" should also be considered as any collection of computer systems that individually or jointly execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0068] Example computer system 1000 includes a processing device 1002, main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage device 1018, which communicate with each other via bus 1030. Main memory 1004 includes or is a non-transitory computer-readable medium. Main memory 1004 (e.g., non-transitory computer-readable medium) may store one or more instruction sets 1026, which, when executed by processing device 1002, cause processing device 1002 to perform some or all of the operations, steps, methods, and processes described herein.

[0069] Processing device 1002 represents one or more processors, such as microprocessors, central processing units, or the like. More specifically, processing device 1002 may be or include complex instruction set computing (CISC) microprocessors, reduced instruction set computing (RISC) microprocessors, very long instruction word (VLIW) microprocessors, processors implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 1002 may be configured to execute some or all of the instructions 1026 for performing some or all of the operations, steps, methods, and processes described herein.

[0070] The computer system 1000 may further include a network interface device 1008 for communication via a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), a text input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), a graphics processing unit 1022, a video processing unit 1028, and an audio processing unit 1032.

[0071] Data storage device 1018 may include machine-readable storage medium 1024 (e.g., non-transitory computer-readable medium) storing one or more sets of instructions 1026 or software embodying any one or more of the methods or functions described herein. Instructions 1026 may also reside wholly or at least partially in main memory 1004 and / or processing device 1002 during execution by computer system 1000, both of which also include machine-readable storage media.

[0072] In some implementations, instruction 1026 includes instructions for performing the functionality described above. Although machine-readable storage medium 1024 is shown as a single medium in exemplary embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated cache and server) storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a computer system and causing the computer system and processing device 1002 to perform any one or more of the methods described above. The term "machine-readable storage medium" should accordingly be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0073] Some parts of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations performed on data bits within computer memory. These algorithmic descriptions and representations are methods used by data processors to effectively communicate the essence of their work to others with general knowledge in the field. An algorithm may be a series of operations that produce a desired result. These operations require the physical manipulation of physical quantities. Such physical quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. These signals may be referred to as bits, values, elements, symbols, characters, items, numbers, or the like.

[0074] However, it should be remembered that all such terms and similar terms are associated with appropriate physical quantities and are merely convenient notations for application to such physical quantities. Unless otherwise specifically stated, it should be understood that throughout the description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memory of a computer system into other data similarly represented as physical quantities in the memory or registers or other such information storage devices of a computer system.

[0075] This description also relates to a device for performing the operations described herein. Such a device may be specifically configured for the intended purpose, or may include a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium such as, but not limited to, the following, each coupled to a computer system bus: any type of magnetic disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks; read-only memory (ROM); random access memory (RAM); EPROM; EEPROM; magnetic cards or optical cards; or any type of media suitable for storing electronic instructions.

[0076] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program based on the teachings herein, or may prove suitable for constructing more specialized devices to execute the methods. Furthermore, the contents of this document are described without reference to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of this document as described herein.

[0077] This description may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, such instructions being used to program a computer system (or other electronic device) to perform a process according to this description. Machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0078] In the foregoing description, embodiments of the present description have been described with reference to specific examples. It will be apparent that various modifications can be made to the present description without departing from the broader spirit and scope of the embodiments set forth in the following claims. Where the present description refers to elements in a singular tense, more than one element may be depicted in the drawings and labeled with the same number. Therefore, the present description and drawings should be viewed in an illustrative rather than restrictive sense.

[0079] 100: Method 202: Design Goals 204: Section 206: Rays 206': Ray 208:Corner 210: Angular span 212: Individual directions 214: Individual directions 216: Angle 218: Angle 220: By possessing regional boundaries 221: Axis 222: Intersection point 224: Positive distance of instances 226: Instance Negative Distance 230: Mask Shape 242: Target Point 250: Image Outline 252: Target Point 254: Instance distance 290: Anchor point 292: Anchor Point 302: By possessing the area boundary 402: Intersection Point 404: X-ray 406: Spliced ​​mask 408: Anchor Point 410: Initial Mask 502: Distance 504: Mask 506: Edge 602: Polygon 604: Polygon 702: Manhattan Mask 704: Section 706: Splicing Section 802: Design Goals 804: Design Goals 806: Design Goals 808: Area 810: Rays 900: Process 910: Block 912: Block 914: Block 916: Block 918: Block 920: Block 922: Block 924: Block 926: Block 928: Block 930: Block 932: Block 934: Block 936: Block 938: Block 940: Block 1000: Computer System 1002: Processing device 1004: Main Memory 1006: Static Memory 1008: Network Interface Device 1010: Video display unit 1012: Document Input Device 1014: Vernier control device 1016: Signal generating device 1018: Data storage device 1020: Internet 1022: Graphics Processing Unit 1024: Machine-readable storage media 1026: Instruction 1028: Video Processing Unit 1030: Busbar 1032: Audio Processing Unit

Claims

1. A method for mask composition, comprising: obtaining a target shape on an image surface to be manufactured using a mask based on an integrated circuit design; generating rays emanating from individual anchor points located on a boundary of the target shape or on a boundary of a mask shape of the mask; defining a distance between: a first intersection point of the individual ray with the boundary of the target shape, and a second intersection point of the individual ray with the boundary of the mask shape for each ray; modifying the distance by one or more processors based on an error between the target shape and a shape simulated on the image surface generated by the mask shape; and generating a mask design based on the modified distance for use in manufacturing the target shape on the image surface.

2. The method of claim 1, further comprising generating an owned region boundary in the target shape, wherein the ray does not extend beyond the owned region boundary.

3. The method of claim 1, further comprising generating an owned region boundary in a space disposed between the target shape and one or more other target shapes, wherein the ray does not extend across the owned region boundary.

4. The method of claim 3, wherein the boundary of the region is generated by the central axis transformation of the target shape.

5. The method of request item 4, wherein the boundary of the area being owned is defined by the user.

6. The method of claim 3, wherein the mask shape includes an edge that coincides with a portion of the boundary of the owned region.

7. The method of claim 1, wherein generating the mask design includes modifying the mask shape such that the mask shape is formed as a plurality of non-overlapping mask shapes, or such that the mask shape is merged with another mask shape.

8. The method of claim 1, wherein one or more of the rays are emitted from a corner of the target shape or the mask shape.

9. The method of claim 8, wherein one or more of the rays comprise a first ray, a second ray, and a third ray emanating from the corner, and wherein the corner between the first ray and the second ray is the same as the corner between the second ray and the third ray.

10. The method of request item 1, wherein the distance between the target shape and the resulting shape is modified based on a rule table.

11. The method of claim 1, further comprising determining a sensitivity, the sensitivity representing the ratio of the change in error to the change in distance, wherein the distance is modified based on the sensitivity.

12. The method of claim 1, wherein the mask shape comprises lines parallel to the edge of the target shape, each of the lines passing through the second intersection point of one of the rays with the mask shape.

13. The method of claim 12, wherein the two of the lines are connected by another line perpendicular to the edge of the target shape.

14. An apparatus for mask compositing, comprising: a memory; and one or more processors coupled to the memory, the memory and the one or more processors being configured to: obtain a target shape on an image surface to be manufactured using a mask based on an integrated circuit design; generate rays emanating from individual anchor points located on a boundary of the target shape or on a boundary of a mask shape of the mask; for each ray, define a distance between: a first intersection point of the individual ray with the boundary of the target shape, and a second intersection point of the individual ray with the boundary of the mask shape; and perform an analysis configured to modify the distance based on an error between the target shape and a shape simulated as being generated on the image surface from the mask shape.

15. The device of claim 14, wherein the memory and the one or more processors are further configured to generate an owned region boundary in the target shape, wherein the ray does not extend beyond the owned region boundary.

16. The device of claim 15, wherein the boundary of the possessing region is generated by a central axis transformation of the target shape.

17. The device as claimed in claim 16, wherein the boundary of the owned area is defined by the user.

18. The device of claim 15, wherein the mask shape includes an edge that coincides with a portion of the boundary of the owned area.

19. The device of claim 14, wherein the memory and the one or more processors are further configured to generate an owned region boundary in a space disposed between the target shape and one or more other target shapes, wherein the ray does not extend across the owned region boundary.

20. A non-transitory computer-readable medium for mask compositing, comprising executable instructions that, when executed by one or more processors of a device, cause the device to: obtain a target shape on an image surface to be manufactured using a mask based on an integrated circuit design; generate rays emanating from individual anchor points located on a boundary of the target shape or on a boundary of a mask shape of the mask; for each ray, define a distance between: a first intersection point of the individual ray with the boundary of the target shape, and a second intersection point of the individual ray with the boundary of the mask shape; and perform an analysis by the one or more processors, the analysis being configured to modify the distance based on an error between the target shape and a shape simulated as being generated on the image surface from the mask shape.

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