Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes an insulating layer having a via opening and a conductive line opening. The semiconductor device further includes a via located within the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line located within the conductive line opening. The conductive line includes a first pad layer, wherein a first thickness of the first pad layer over the via is less than a second thickness of the first pad layer over the insulating layer; and a conductive fill layer including a second conductive material, wherein the second conductive material is different from the first conductive material.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to reducing the thickness of the bottom pad layer of vias. [Previous Technology]

[0002] Contacts are used to provide electrical connections to the gate and source / drain regions of a device such as a transistor. In some methods, vias are used to provide electrical connections to the device. In some methods, vias connect to conductive lines, such as portions of a dual damascene structure. As technology nodes shrink, the via size of contact devices also shrinks. Shrinking the via size increases the aspect ratio of the via.

[0003] A backing layer is used when forming vias to improve the consistency of the conductive material deposited in the via and to help prevent the conductive material from migrating into the surrounding insulating material during the process. The backing layer also increases the aspect ratio of the conductive material filling the via, making it more difficult to ensure that the conductive material filling the via is free of voids. In some cases, voids can increase via resistance and, in extreme cases, cause open circuits. [Summary of the Invention]

[0004] One embodiment of the present invention relates to a semiconductor device. The semiconductor device includes an insulating layer having a via opening and a conductive line opening. The semiconductor device further includes a via located in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line located in the conductive line opening. The conductive line includes a first pad layer, wherein a first thickness of the first pad layer over the via is less than a second thickness of the first pad layer over the insulating layer, and a conductive fill layer including a second conductive material, wherein the second conductive material is different from the first conductive material.

[0005] An embodiment of the present invention relates to a method for manufacturing a semiconductor device. The method includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface conditioning process on the conductive material. The method further includes, after the surface conditioning process, depositing a first pad layer in the second opening, wherein the first pad layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill layer on the first pad layer, wherein the conductive fill layer and the conductive material comprise different materials.

[0006] One embodiment of the present invention relates to a semiconductor device. The semiconductor device includes an insulating layer having a via opening and a conductive line opening. The semiconductor device further includes a via located in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line located in the conductive line opening. The conductive line includes a first pad layer; a second pad layer located on the first pad layer, wherein the second pad layer is continuous with the first conductive material; and a conductive fill layer including a second conductive material, wherein the second conductive material is different from the first conductive material.

Implementation Method

[0008] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] The different embodiments or examples provided below can implement different structures of the present invention. The specific components and arrangements described below are intended to simplify the content of the present invention and not to limit the present invention. For example, the description of forming a first component on a second component includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by other additional components and are not in direct contact. Furthermore, multiple embodiments of the present invention may use the same reference numerals repeatedly for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] Furthermore, spatial relative terms such as "below," "below," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another element in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90˚ or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0011] Barrier-free vias in contact structures (such as vias without a backing layer or with a very thin backing layer) help reduce the thickness of the bottom backing layer of the via and even reduce the aspect ratio of the via. This reduces the risk of void formation when depositing the conductive material used in the via. Consequently, vias in contact structures exhibit reduced resistance and increased yield because there are fewer open circuits in the manufactured product.

[0012] In some embodiments, ruthenium is used to fill the through-holes of the contact structure. Compared to other conductive materials (such as copper), ruthenium has a lower risk of migrating into the surrounding insulating material. This allows the use of ruthenium to eliminate the need for a liner layer in the through-holes used in the contact structure, thereby increasing the aspect ratio and providing related advantages.

[0013] In some embodiments, surface conditioning is performed on ruthenium to deposit material for conductive lines. The conductive lines expand the size of the contact structure to increase line selection and reduce the risk of misalignment errors. Misalignment errors can cause high-resistance contact structures or open circuits. In some embodiments, the surface conditioning method includes depositing a monolayer of benzotriazole or other long-chain organic molecules on ruthenium. The benzotriazole monolayer helps reduce the deposition thickness of the backing layer when forming conductive lines. In some embodiments, the benzotriazole monolayer helps to completely eliminate the need for a backing layer when forming conductive lines.

[0014] FIG1 is a cross-sectional view of the contact structure 110 in some embodiments. The contact structure 110 is a portion of a semiconductor device 100. The semiconductor device 100 includes a substrate 102. An etch stop layer 104 is located on the substrate 102. In some embodiments, the etch stop layer 104 may be referred to as a contact etch stop layer. An insulating layer 106 is located on the etch stop layer 104. In some embodiments, the insulating layer 106 is an interlayer dielectric layer. In some embodiments, the insulating layer 106 is an intermetallic dielectric layer. An etch stop layer 108 is located on the insulating layer 106. The contact structure 110 extends through the insulating layer 106 and the etch stop layer 104 to contact the substrate 102. The contact structure 110 includes a via 120 and a conductive line 130. The via 120 extends through the etch stop layer 104 to contact the substrate 102.

[0015] FIG1 does not include any specific device in the substrate 102. Those skilled in the art will understand that in some embodiments, the substrate 102 includes a source / drain region, a gate, or another conductive unit in the device electrically connected to the via 120. In some embodiments, the substrate 102 includes an isolation structure such as a shallow trench isolation that contacts the via 120. FIG1 is a cross-sectional view of the contact structure of the zeroth metal layer. The zeroth metal layer is a portion of the interconnect structure directly connected to the substrate. However, in some embodiments, the contact structure 110 is a portion of a first metal layer, a second metal layer, or a third metal layer. The first metal layer is a layer of interconnect structure directly located on the zeroth metal layer. The second metal layer is a layer of interconnect structure directly located on the first metal layer. The third metal layer is a layer of interconnect structure directly located on the second metal layer. In some embodiments, the contact structure 110 is a portion of the first to third metal layers, and the substrate 102 is replaced by a layer of interconnect structure not directly under the contact structure 110.

[0016] In some embodiments, substrate 102 comprises semiconductor elements such as crystalline, polycrystalline, or amorphous silicon or germanium; semiconductor compounds such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; semiconductor alloys such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, or gallium arsenide phosphide; any other suitable material, or a combination thereof. In some embodiments, the semiconductor alloy substrate has a silicon germanium structure with a compositional gradient, wherein the composition of silicon and germanium changes from one ratio to another ratio at another location. In some embodiments, a silicon germanium alloy is formed on a silicon substrate. In some embodiments, substrate 102 is a strained silicon germanium substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, such as a silicon-on-insulator structure. In some embodiments, the semiconductor substrate includes a doped epitaxial layer or a buried layer. In some embodiments, the semiconductor compound substrate has a multilayer structure, or the substrate includes a multilayer semiconductor compound structure.

[0017] The etch stop layer 104 helps to avoid damage to the substrate 102 when forming the openings used for the contact structure 110. The etch stop layer 104 has a different etch selectivity than the insulating layer 106, therefore the risk of the etching process in the insulating layer 106 etching through the etch stop layer 104 and damaging the substrate 102 is low. In some embodiments, the etch stop layer 104 comprises silicon oxide, silicon nitride, silicon oxynitride, or another suitable material. In some embodiments, the thickness of the etch stop layer 104 is from about 1 nm to about 15 nm. In some examples, if the etch stop layer 104 is too thin, the risk of damage to the substrate 102 increases. In some examples, if the etch stop layer is too thick, the size of the semiconductor device 100 increases without a significant increase in performance. In some embodiments, the etch stop layer 104 is formed by chemical vapor deposition, physical vapor deposition, spin coating, printing, spraying, sintering, thermal oxidation, or another suitable process.

[0018] The insulating layer 106 includes a dielectric material to provide electrical insulation between the contact structure 110 in the semiconductor device 100 and other conductive units. In some embodiments, the insulating layer 106 includes silicon carbide, silicon carbide, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, spin-coated glass, fluorosilicate glass, carbon-doped silicon oxide such as silicon hydroxide, Black Diamond® (purchased from Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene, FLARE, Silk® (purchased from Dow Chemical, Midland, Michigan), polyimide, or another suitable material. In some embodiments, the thickness of the insulating layer 106 is from about 30 nm to about 45 nm. In some examples, if the insulating layer 106 is too thin, the size of the contact structure is reduced and the resistance increases, which will impair the function of the semiconductor device. In some cases, if the insulating layer 106 is too thick, the size of the semiconductor device 100 increases without a significant increase in performance. In some embodiments, the insulating layer 106 is formed by chemical vapor deposition, physical vapor deposition, spin coating, high-density plasma chemical vapor deposition, sub-pressure chemical vapor deposition, sputtering, or another suitable process.

[0019] The etch stop layer 108 helps avoid damage to the insulating layer in subsequent manufacturing processes. The etch stop layer 108 has a different etch selectivity than the insulating layer 106, therefore the risk of the etching process etching through the etch stop layer 108 and damaging the insulating layer 106 is low. In some embodiments, the etch stop layer 108 comprises silicon oxide, silicon nitride, silicon oxynitride, or another suitable material. In some embodiments, the etch stop layer 108 is made of the same material as the etch stop layer 104. In some embodiments, the etch stop layer 108 is made of a different material than the etch stop layer 104. In some embodiments, the thickness of the etch stop layer 108 is from about 1 nm to about 10 nm. In some examples, if the etch stop layer 108 is too thin, the risk of damage to the insulating layer 106 increases. In some examples, if the thickness of the etch stop layer 108 is too thick, the size of the semiconductor device 100 increases without a significant increase in performance. In some embodiments, the etch stop layer 108 is the same thickness as the etch stop layer 104. In some embodiments, the etch stop layer 108 is different thickness from the etch stop layer 104. In some embodiments, the etch stop layer 108 may be formed by chemical vapor deposition, physical vapor deposition, spin coating, printing, spraying, sintering, thermal oxidation, or another suitable process. In some embodiments, the etch stop layer 108 is formed using the same process as the etch stop layer 104. In some embodiments, the etch stop layer 108 is formed using a different process than the etch stop layer 104.

[0020] The contact structure 110 includes a via 120 and a conductive line 130. The via 120 extends from the inside of the insulating layer 106 through the etch stop layer 104 and contacts the substrate 102. As described above, in some embodiments, the contact structure 110 is located in the first to third metal layers, while the via 120 may contact the lower layer of the interconnect structure rather than the substrate 102. The via 120 does not have a padding layer. In some embodiments, the via 120 is referred to as a barrier-free via. The height H1 of the opening used by the via 120 is greater than the height H2 of the via 120. In some embodiments, the height H2 is equal to the height H1. In some examples, the height H2 is at least 50% of the height H1. In some examples, if the height H2 of the via 120 is too small, the risk of forming a void in the contact structure 110 increases because the conductive filler layer and padding layer of the conductive line extend to a greater depth into the via opening. In some examples, if the height H2 of the via 120 is too large, material is wasted without significantly improving performance. In some embodiments, the height H1 is greater than the height H2, and the via 120 extends into the opening used by the conductive line 130. In some embodiments, the via 120 comprises ruthenium. In some embodiments, the via 120 comprises tungsten. In some embodiments, the via 120 may be formed using atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0021] The conductive line 130 includes at least one pad layer and a conductive material. The contact structure 110 includes three pad layers, such as a first pad layer 132, a second pad layer 134, and a third pad layer 136, which may be collectively referred to as the pad layers. After depositing the pad layers, a conductive fill layer 138 is used to fill the opening used by the conductive line 130. In some embodiments, if the height H2 is less than the height H1, then at least one pad layer extends into the via opening. In some embodiments, if the height H2 is less than the height H1, then the conductive fill layer 138 extends into the via opening.

[0022] The first pad layer 132 directly contacts the insulating layer 106 and the via 120. The first pad layer 132 helps prevent the conductive fill layer 138 from migrating into the insulating layer 106. In some embodiments, the thickness of the first pad layer 132 is from about 8 Å to about 25 Å. In some embodiments, the contact structure 110 is in a first metal layer or a second metal layer, and the thickness of the first pad layer 132 is from about 8 Å to about 15 Å. In some embodiments, the contact structure 110 is in a third metal layer, and the thickness of the first pad layer 132 is from about 10 Å to about 25 Å. In some examples, if the first pad layer 132 is too thick, the size of the semiconductor device 100 increases without a significant increase in performance. In some examples, if the first pad layer 132 is too thin, the risk of material from the conductive fill layer 138 migrating into the insulating layer 106 increases.

[0023] In some embodiments, the thickness of the first pad layer 132 on the via 120 is less than the thickness of the first pad layer 132 at other locations due to surface adjustments of the via 120. In some embodiments, the surface adjustment method includes depositing a monolayer of benzotriazole. Reducing the thickness of the first pad layer 132 helps to reduce the aspect ratio of any portion of the conductive line 130 extending into the via opening, thereby reducing the risk of forming voids in the contact structure 110. In some embodiments, the first pad layer 132 comprises tantalum nitride, titanium nitride, or another suitable material. In some embodiments, the thickness of the first pad layer 132 on the via 120 is from about 3 Å to about 15 Å. In some embodiments, the contact structure 110 is in a first metal layer or a second metal layer, and the thickness of the first pad layer 132 on the via 120 is from about 3 Å to about 10 Å. In some embodiments, the contact structure 110 is in a third metal layer, and the thickness of the first pad layer 132 on the via 120 is from about 5 Å to 15 Å. In some examples, if the first pad layer 132 is too thick, the size of the semiconductor device 100 increases without a significant increase in performance. In some examples, if the first pad layer 132 is too thin, the risk of material migration from the conductive fill layer 138 into the insulating layer 106 increases. In some embodiments, the first pad layer 132 may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or another suitable process.

[0024] The second pad layer 134 is in direct contact with the first pad layer 132. The second pad layer 134 also helps prevent the conductive fill layer 138 from migrating into the insulating layer 106 and helps provide the adhesion required for the deposited layer. In some embodiments, the thickness of the second pad layer 134 is from about 5 Å to about 15 Å. In some examples, if the second pad layer 134 is too thick, the size of the semiconductor device 100 increases without a significant increase in performance. In some examples, if the second pad layer 134 is too thin, the risk of material migration of the conductive fill layer 138 into the insulating layer 106 increases. In some embodiments, the thickness of the second pad layer 134 is substantially uniform, such as within manufacturing tolerances. In some embodiments, the thickness of the second pad layer 134 is uniform for each of the zeroth metal layer to the third metal layer. In some embodiments, the second pad layer 134 comprises ruthenium, cobalt, tungsten nitride, or another suitable material. In some embodiments, the second liner layer 134 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or another suitable process.

[0025] The third pad layer 136 directly contacts the second pad layer 134. The third pad layer 136 helps reduce the migration of the conductive fill layer 138 into the insulating layer 106 and facilitates the formation of the conductive fill layer 138. The third pad layer 136 also extends on the upper surface of the conductive fill layer 138 to reduce the risk of the conductive fill layer 138 migrating into the etch stop layer 108. In some embodiments, the thickness of the third pad layer 136 is from about 5 Å to about 15 Å. In some examples, if the third pad layer 136 is too thick, the size of the semiconductor device 100 increases without a significant increase in performance. In some examples, if the third pad layer 136 is too thin, the risk of forming an inconsistent conductive fill layer 138 increases. In some embodiments, the thickness of the third pad layer 136 is substantially uniform, such as within the fabrication tolerances. In some embodiments, the thickness of the third pad layer 136 is uniform for each of the zero metal layer to the third metal layer. In some embodiments, the third pad layer 136 comprises cobalt, a cobalt alloy, or another suitable material. In some embodiments, the third liner layer 136 may be formed by electroplating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or another suitable process.

[0026] The conductive filler layer 138 is a conductive material that allows electronic signals to move between the via 120 and other units in the semiconductor device 100. In some embodiments, the thickness of the conductive filler layer 138 is from about 10 Å to about 100 nm. In some examples, if the conductive filler layer 138 is too thick, the size of the semiconductor device 100 increases without a significant increase in performance. In some examples, if the conductive filler layer 138 is too thin, the resistance of the contact structure 110 increases and the function of the semiconductor device 100 is impaired. In some embodiments, the conductive filler layer 138 includes copper, a copper alloy, tungsten, aluminum, cobalt, ruthenium, iridium, or another suitable material. In some embodiments, the conductive filler layer 138 may be formed by electroplating, physical vapor deposition, atomic layer deposition, or another suitable process.

[0027] Figure 2 is a flowchart of a method 200 for manufacturing a contact structure in some embodiments. Step 205 etches an insulating layer to form a dual damascene opening to expose the underlying material. The dual damascene opening includes two components, such as a via opening and a conductive line opening. The etching process extends through an etch stop layer to expose the underlying material. In some embodiments, the underlying material includes conductive units in a substrate (such as substrate 102 in Figure 1). In some embodiments, the underlying material includes an isolation structure in a substrate (such as substrate 102 in Figure 1). In some embodiments, the etching includes a series of photolithography and etching processes to form the dual damascene opening.

[0028] FIG3A is a cross-sectional view of the contact structure after etching the dual damascene opening in some embodiments. The semiconductor device 300A includes a dual damascene opening 310 extending through the insulating layer 106 and the etch stop layer 104 to expose a portion of the substrate 102. The dual damascene opening 310 includes a via opening 320 and a conductive line opening 330. The via opening 320 extends from the insulating layer 106 through the etch stop layer 104.

[0029] As shown in FIG. 2, method 200 further includes step 210, to fill the via opening with a conductive material. In some embodiments, the conductive material includes ruthenium, tungsten, or another suitable material. The conductive material fills at least 50% of the via opening. In some embodiments, the conductive material fills the entire via opening. In some embodiments, the conductive material extends into the conductive line opening. In some embodiments, the filling method is atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable process.

[0030] FIG3B is a cross-sectional view of the contact structure after conductive material is filled into the via opening in some embodiments. Semiconductor device 300B includes a via 120 to fill the via opening. The via 120 may not completely fill the via opening. In some embodiments, the via 120 completely fills the via opening. In some embodiments, the via 120 extends into the conductive line opening 330.

[0031] As shown in FIG. 2, method 200 further includes step 215 to perform surface conditioning on the surface of a conductive material. In some embodiments, the conductive material includes ruthenium, tungsten, or another suitable material. The conductive material fills at least 50% of the via openings. The surface conditioning method includes depositing a monolayer of benzotriazole. In some embodiments, the surface conditioning method includes depositing a material other than benzotriazole. The surface conditioning is selective for the conductive material, so a monolayer is not formed on the insulating layer 106.

[0032] Step 220: Deposit one or more pad layers. In some embodiments, a single pad layer is deposited. In some embodiments, multiple pad layers are deposited. The surface adjustment in step 215 makes the thickness of the first pad layer deposited on the conductive material in step 220 less than the thickness of the first pad layer deposited on the insulating layer. In some embodiments, the first pad layer comprises tantalum nitride, titanium nitride, or another suitable material. In some embodiments, an additional pad layer comprises ruthenium, cobalt, or other suitable materials. In some embodiments, one or more pad layers extend into the via opening. In some embodiments, the method of depositing one or more pad layers may each employ atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0033] Figure 3C is a cross-sectional view of the contact structure after surface conditioning and deposition of a pad layer in some embodiments. Semiconductor device 300C includes a first pad layer 132 in a conductive line opening 330. The thickness of the first pad layer 132 on the via 120 is less than the thickness of the first pad layer 132 in other portions of the conductive line opening 330.

[0034] As shown in FIG2, method 200 further includes step 225 to fill the remaining portion of the dual damascene opening with a conductive filler layer. The conductive filler layer fills the portion of the conductive line opening not occupied by one or more pad layers or conductive materials. In some embodiments, the conductive filler layer comprises copper, a copper alloy, tungsten, aluminum, or another suitable material. In some embodiments, the filling method employs atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable process. In some embodiments, method 200 includes additional steps such as annealing or planarization processes.

[0035] FIG3D is a cross-sectional view of the contact structure after the conductive filler layer has filled the remainder of the opening in some embodiments. The semiconductor device 300D includes a first pad layer 132, a second pad layer 134, a third pad layer 136, and a conductive filler layer 138 in the conductive line opening. The conductive filler layer 138 fills the first pad layer 132, the second pad layer 134, the third pad layer 136, and the conductive line opening not occupied by the via 120.

[0036] In some embodiments, a second liner layer 134 may be formed (or even omitted) as appropriate. In summary, the third liner layer 136 directly contacts the first liner layer 132, as shown in FIG3E. For example, the third liner layer 136 of cobalt directly contacts the first liner layer 132 of tantalum nitride, but is not limited thereto.

[0037] FIG4A is a cross-sectional view of the contact structure in the circuit area in some embodiments. Semiconductor device 400A is similar to semiconductor device 100 (FIG. 1). Compared with semiconductor device 100, semiconductor device 400A includes a conductive structure 410, such as a portion of substrate 102. In some embodiments, conductive structure 410 replaces substrate 102. Conductive structure 410 includes a first pad layer 412, which is similar to first pad layer 132 (FIG. 1). Conductive structure 410 further includes a second pad layer 416, which is similar to third pad layer 136 (FIG. 1). Conductive structure 410 further includes a conductive fill layer 418, which is similar to conductive fill layer 138 (FIG. 1). Via 120 is electrically connected to conductive fill layer 418. In semiconductor device 400A, the sidewalls of the first pad layer 132 and the sidewalls of the via 120 are continuous in shape.

[0038] In some embodiments, the width W1 of the interface between the via 120 and the conductive filling layer 418 is approximately 10 nm to about 22 nm. In some embodiments, the semiconductor device 400A is in a first metal layer, and the width W1 is approximately 8 nm to about 15 nm. In some embodiments, the semiconductor device 400A is in a second metal layer, and the width W1 is approximately 12 nm to about 18 nm. In some embodiments, the semiconductor device 400A is in a third metal layer, and the width W1 is approximately 12 nm to about 16 nm. In some examples, if the width W1 is too small, the interface resistance between the via 120 and the conductive filling layer 418 increases and the function of the semiconductor device 400A is impaired. In some examples, if the width W1 is too large, the size of the semiconductor device 400A increases without a significant increase in performance. Similar to the semiconductor device 100 (FIG. 1), the height H2 of the via 120 is at least 50% of the height of the via opening.

[0039] FIG4B is a cross-sectional view of the contact structure in the sealing ring region in some embodiments. Semiconductor device 400B is similar to semiconductor device 100 (FIG. 1). Compared with semiconductor device 100, semiconductor device 400B includes a portion of conductive structure 410, such as substrate 102. In some embodiments, conductive structure 410 replaces substrate 102. In semiconductor device 400B, the sidewall of the first pad layer 132 is offset from the sidewall of the via 120.

[0040] In some embodiments, the width W2 of the interface between the via 120 and the conductive filling layer 418 is about 100 nm to about 180 nm. In some examples, if the width W2 is too small, the interface resistance between the via 120 and the conductive filling layer 418 increases and the function of the semiconductor device 400B is impaired. In some examples, if the width W2 is too large, the size of the semiconductor device 400B increases without a significant increase in performance. Compared to the semiconductor device 400A, the via 120 included in the semiconductor device 400B has a height H3, which is at least 80% of the height of the via opening. The wider opening of the semiconductor device 400B compared to the height H2 results in an increase in height H3, for example, the difference between the width W1 and the width W2. When the same process is performed on the semiconductor device 400A, the wider opening facilitates faster material deposition in the via 120 and results in an increase in height.

[0041] FIG5 is a cross-sectional view of the contact structure in some embodiments. Semiconductor device 500 is similar to semiconductor device 100 (FIG. 1). Compared with semiconductor device 100, semiconductor device 500 includes contact structure 110', which includes through-hole 120'. Through-hole 120' is similar to through-hole 120 (FIG. 1), however, through-hole 120' includes tungsten instead of ruthenium as in through-hole 120.

[0042] FIG6A is a cross-sectional view of the contact structure in the circuit area in some embodiments. Semiconductor device 600A is similar to semiconductor device 400A (FIG. 4A). Compared with semiconductor device 400A, semiconductor device 600A includes a through-hole 120' which contains tungsten instead of ruthenium in the through-hole 120.

[0043] Figure 6B is a cross-sectional view of the contact structure in the sealing ring region in some embodiments. Semiconductor device 600B is similar to semiconductor device 400B (Figure 4B). Compared with semiconductor device 400B, semiconductor device 600B includes a via 120' which contains tungsten instead of ruthenium in the via 120.

[0044] FIG7 is a cross-sectional view of the contact structure in some embodiments. Semiconductor device 700 is similar to semiconductor device 100 (FIG. 1). Compared to semiconductor device 100, semiconductor device 700 includes a contact structure 110”, which includes a via 120” continuous with a second pad layer 134”. Compared to semiconductor device 100 (FIG. 1), semiconductor device 700 includes a first pad layer 132” extending along the entire sidewall of the via opening. The via opening separates the via 120” from the insulating layer 106 and separates the via 120” from the etch stop layer 104.

[0045] The via 120” is similar in material, thickness, and formation method to the via 120 (FIG. 1). However, the via 120” is continuous with the second pad layer 134”. In some embodiments, there is no interface between the via 120” and the second pad layer 134”. In some embodiments, the total thickness of the via 120” and the second pad layer 134” in the direction perpendicular to the upper surface of the substrate 102 is about 16 Å to about 60 Å. In some examples, if the total thickness is too small, the conductive material of the via 120” cannot adequately fill the via opening, increasing the risk of voids forming in the contact structure 110”. In some examples, if the total thickness is too large, the size of the semiconductor device 700 increases without significantly improving the performance of the semiconductor device 700.

[0046] The material and formation method of the first pad layer 132” are similar to those of the first pad layer 132 (FIG. 1). However, the first pad layer 132” is thinner than the first pad layer 132. In some embodiments, the thickness of the first pad layer 132” along the sidewall of the via opening and the sidewall of the conductive line opening is about 5 Å to about 10 Å. In some examples, if the first pad layer 132” is too thin, the risk of material migration from the conductive fill layer 138 into the insulating layer 106 increases. In some examples, if the first pad layer 132” is too thick, the size of the semiconductor device 700 increases without significantly improving its functionality. In some embodiments, the first pad layer 132” extends between the substrate 102 and the via 120”. In some embodiments, the thickness of the first pad layer 132” between the substrate and the via 120” is about 2 Å to about 5 Å. In some examples, if the first pad layer 132” is too thin, the risk of conductive material from the via 120” migrating into the substrate 102 increases. In some examples, if the first pad layer 132” is too thick, the size of the semiconductor device 700 increases without significantly improving its functionality.

[0047] The material and formation method of the second pad layer 134” are similar to those of the second pad layer 134 (FIG. 1). However, the second pad layer 134” is thicker than the second pad layer 134. In some embodiments, the thickness of the second pad layer 134” along the sidewall of the conductive line opening is about 10 Å to about 35 Å. In some examples, if the second pad layer 134” is too thin, the risk of material migration from the conductive fill layer 138 into the insulating layer 106 increases. In some examples, if the second pad layer 134” is too thick, the size of the semiconductor device 700 increases without significantly improving the function of the semiconductor device 700.

[0048] Figure 8 is a flowchart of a method 800 for manufacturing a contact structure in some embodiments. Step 805 involves etching an insulating layer to form a double damascene opening to expose the underlying material. In some embodiments, step 805 is similar to step 205 (Figure 2).

[0049] Figure 9A is a cross-sectional view of the contact structure after etching the dual damascene openings in some embodiments. Semiconductor device 900A is similar to semiconductor device 300A (Figure 3A).

[0050] As shown in FIG8, method 800 further includes step 810 to perform surface conditioning on the underlying material. In some embodiments, the underlying material includes a conductive material, an insulating structure, or a semiconductor structure. The method of conditioning the surface includes depositing a monolayer of benzotriazole. In some embodiments, the method of conditioning the surface includes depositing a material other than benzotriazole. Surface conditioning is selective for conductive materials, so a monolayer is not formed on the insulating layer 106.

[0051] FIG9B is a cross-sectional view of the contact structure during a surface conditioning process in some embodiments. A surface conditioning process 910 is performed on a substrate 102 of the semiconductor device 900B. In some embodiments, the surface conditioning process 910 is performed on a layer of a conductive unit, an isolation structure in the substrate 102, or an interconnect structure on the substrate 102.

[0052] As shown in FIG8, step 815 of method 800 deposits one or more pad layers. In some embodiments, a single pad layer is deposited. In some embodiments, multiple pad layers are deposited. The surface adjustment in step 810 causes the thickness of the first pad layer deposited in step 815 on the underlying material to be less than its thickness on the insulating layer. In some embodiments, the surface adjustment in step 810 may prevent the formation of a pad layer on the underlying material. In some embodiments, the first pad layer comprises tantalum nitride, titanium nitride, or another suitable material. In some embodiments, an additional pad layer comprises ruthenium, cobalt, or other suitable materials. In some embodiments, the method of depositing one or more pad layers may each employ atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0053] FIG9C is a cross-sectional view of the contact structure after the deposition of the pad layer in some embodiments. The semiconductor device 900C includes a first pad layer 132” in the via opening 320 and the conductive line opening 330. The thickness of the first pad layer 132” on the substrate 102 is less than the thickness of the first pad layer 132” on the sidewalls of the via opening 320 and the conductive line opening 330. In some embodiments, the first pad layer 132” is not on the surface of the substrate 102.

[0054] As shown in FIG8, method 800 further includes step 820, to fill a via opening with a conductive material. In some embodiments, the conductive material includes ruthenium, tungsten, or another suitable material. The conductive material fills at least 50% of the via opening. In some embodiments, the conductive material fills the entire via opening. In some embodiments, the conductive material extends into the conductive line opening. Step 820 further includes depositing a conductive material layer on one or more pad layers formed in step 815. In some embodiments, the conductive material is ruthenium or another suitable material. In some embodiments, the method of depositing the conductive material employs atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0055] Step 825 involves filling the portion of the dual damascene opening with a conductive filler layer. The conductive filler layer fills one or more spacer layers or conductive material-unoccupied conductive line openings. In some embodiments, the conductive filler layer comprises copper, a copper alloy, tungsten, aluminum, or another suitable material. In some embodiments, the filling method employs atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process. In some embodiments, method 800 includes additional steps such as annealing or planarization processes. In some embodiments, an additional spacer layer is formed between steps 820 and 825.

[0056] FIG9D is a cross-sectional view of the contact structure after the conductive filler layer has been filled into the remainder of the opening in some embodiments. The semiconductor device 900D includes a first pad layer 132”, a second pad layer 134”, and a conductive filler layer 138 in the conductive line opening. In some embodiments, the semiconductor device 900D further includes a third pad layer such as a third pad layer 136 (FIGs 1 and 7). The conductive filler layer 138 fills the portion of the conductive line opening not occupied by the first pad layer 132”, the second pad layer 134”, and the via 120”.

[0057] FIG10A is a cross-sectional view of the contact structure in the circuit area in some embodiments. Semiconductor device 1000A is similar to semiconductor device 700 (FIG. 7). Compared with semiconductor device 700, semiconductor device 1000A includes a portion of conductive structure 410, such as substrate 102. Through-hole 120” is electrically connected to conductive fill layer 418. In semiconductor device 1000A, the sidewall of first pad layer 132” is continuous with the sidewall of through-hole 120”.

[0058] In some embodiments, the total height H4 of the via 120" and the second pad layer 134" in a direction perpendicular to the upper surface of the substrate 102 is about 20 Å to about 60 Å. In some examples, if the height H4 is too small, the conductive material of the via 120" cannot adequately fill the conductive opening, increasing the risk of voids forming in the contact structure 110". In some examples, if the height H4 is too large, the size of the semiconductor device 1000A increases without significantly improving the performance of the semiconductor device 1000A. In some embodiments, the semiconductor device 1000A is in a first metal layer, and the width W1 is about 8 nm to 15 nm. In some embodiments, the semiconductor device 1000A is in a second metal layer, and the width W1 is about 14 nm to 22 nm. In some embodiments, the semiconductor device 1000A is in a third metal layer, and the width W1 is about 12 nm to 16 nm. In some cases, if the width W1 is too small, the interface resistance between the via 120 and the conductive fill layer 418 increases, and the function of the semiconductor device 1000A is impaired. In some cases, if the width W1 is too large, the size of the semiconductor device 1000A increases without a significant increase in performance.

[0059] FIG10B is a cross-sectional view of the contact structure in the sealing region in some embodiments. Semiconductor device 1000B is similar to semiconductor device 700 (FIG. 7). Compared with semiconductor device 700, semiconductor device 1000B includes a portion of conductive structure 410, such as substrate 102. In some embodiments, conductive structure 410 replaces substrate 102.

[0060] In some embodiments, the total height H5 of the via 120” and the second pad layer 134” in a direction perpendicular to the upper surface of the substrate 102 is about 16 Å to about 48 Å. In some examples, if the height H5 is too small, the conductive material of the via 120” cannot adequately fill the via opening, increasing the risk of voids forming in the contact structure 110”. In some examples, if the height H5 is too large, the size of the semiconductor device 1000B increases without significantly improving the performance of the semiconductor device 1000B.

[0061] The via 120” to the second liner layer 134” has tapered sidewalls. The tapered sidewalls result from a change in the deposition process between the conductive material used to deposit the via 120” and the conductive material used to deposit the second liner layer 134”. The angle of the tapered sidewalls relative to the upper surface of the via 120” is approximately 30 degrees to approximately 60 degrees. In some cases, if the angle is too small, the interface stress between the second liner layer 134” and the via 120” increases the risk of breakage. In some cases, if the angle is too large, the size of the conductive filler layer 138 decreases, increasing the resistance of the contact structure.

[0062] FIG11 is a cross-sectional view of the contact structure in some embodiments. Semiconductor device 1100 is similar to semiconductor device 100 (FIG. 1). Compared to semiconductor device 100, semiconductor device 1100 does not contain via 120. Instead, the first pad layer 132*, the second pad layer 134*, the third pad layer 136, and the conductive fill layer 138 are continuous in the conductive line openings and via openings used to form the contact structure 110*. The materials and forming processes of the first pad layer 132* and the first pad layer 132 (FIG. 1) are similar. The materials and forming processes of the second pad layer 134* and the second pad layer 134 (FIG. 1) are similar.

[0063] Compared to the first pad layer 132 (FIG. 1), the thickness of the first pad layer 132* along the sidewalls of the via opening and the conductive line opening is approximately 8 Å to approximately 20 Å. In some examples, if the thickness of the first pad layer 132* along the sidewalls is too thin, the risk of the conductive fill layer 138 migrating into the insulating layer 106 increases. In some examples, if the thickness of the first pad layer 132* along the sidewalls is too thick, the size of the semiconductor device 1100 increases without significantly increasing the performance of the semiconductor device 1100. In some embodiments, the thickness of the first pad layer 132* adjacent to the substrate 102 is approximately 3 Å to 8 Å. In some embodiments, the thickness of the first pad layer 132* adjacent to the substrate 102 is less than 50% of the thickness of the first pad layer 132* along the sidewalls. In some examples, if the thickness of the first pad layer 132* adjacent to the substrate 102 is too thin, the risk of the conductive fill layer 138 migrating into the substrate 102 increases. In some cases, if the thickness of the first pad layer 132* adjacent to the substrate 102 is too thick, the size of the semiconductor device 1100 increases without significantly increasing the performance of the semiconductor device 1100.

[0064] Compared to the second pad layer 134 (FIG. 1), the thickness of the second pad layer 134* along the sidewalls of the via opening and the conductive line opening can be from about 5 Å to about 15 Å. In some examples, if the thickness of the second pad layer 134* along the sidewalls is too thin, the risk of the conductive fill layer 138 migrating into the insulating layer 106 increases. In some examples, if the thickness of the second pad layer 134* along the sidewalls is too thick, the size of the semiconductor device 1100 increases without significantly increasing the performance of the semiconductor device 1100. In some embodiments, the thickness of the second pad layer 134* adjacent to the substrate 102 is from about 3 Å to about 8 Å. In some embodiments, the thickness of the second pad layer 134* adjacent to the substrate 102 is less than 50% of the thickness of the second pad layer 134* along the sidewalls. In some examples, if the thickness of the second pad layer 134* adjacent to the substrate 102 is too thin, the risk of the conductive fill layer 138 migrating into the substrate 102 increases. In some cases, if the thickness of the second pad layer 134* adjacent to the substrate 102 is too thick, the size of the semiconductor device 1100 increases without significantly increasing the performance of the semiconductor device 1100.

[0065] Figure 12 is a flowchart of a method 1200 for manufacturing a contact structure in some embodiments. Step 1205 involves etching an insulating layer to form a double damascene opening to expose the underlying material. In some embodiments, step 1205 is similar to step 205.

[0066] Figure 13A is a cross-sectional view of the contact structure after etching the dual damascene openings in some embodiments. Semiconductor device 1300A is similar to semiconductor device 300A (Figure 3A).

[0067] As shown in FIG12, method 1200 further includes step 1210 to perform surface conditioning on the underlying material. In some embodiments, the underlying material includes a conductive material, an insulating structure, or a semiconductor structure. The method of conditioning the surface includes depositing a monolayer of benzotriazole. In some embodiments, the method of conditioning the surface includes depositing a material other than benzotriazole. Surface conditioning is selective for conductive materials, so a monolayer is not formed on the insulating layer 106.

[0068] FIG13B is a cross-sectional view of the contact structure during surface adjustment in some embodiments. Surface adjustment process 910 is performed on substrate 102 of semiconductor device 1300B. In some embodiments, surface adjustment process 910 is performed on a layer of conductive unit, isolation structure in substrate 102, or interconnect structure on substrate 102.

[0069] As shown in FIG12, step 1215 of method 1200 deposits one or more pad layers. In some embodiments, a single pad layer is deposited. In some embodiments, multiple pad layers are deposited. The surface preparation in step 1210 causes the thickness of the first pad layer deposited in step 1215 on the underlying material to be less than the thickness along the sidewalls of the insulating layer. In some embodiments, the first pad layer comprises tantalum nitride, titanium nitride, or another suitable material. In some embodiments, an additional pad layer comprises ruthenium, cobalt, or other suitable materials. In some embodiments, the surface treatment in step 1210 may avoid the formation of a pad layer adjacent to the substrate 102. In some embodiments, the method of depositing one or more pad layers may each employ atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0070] Figure 13C is a cross-sectional view of the contact structure after depositing two pad layers in some embodiments. Semiconductor device 1300C includes a first pad layer 132* in the via opening 320 and the conductive line opening 330. The thickness of the first pad layer 132* on the substrate 102 is less than the thickness of the first pad layer 132* on the sidewalls of the via opening 320 and the conductive line opening 330. Semiconductor device 1300C includes a second pad layer 134* in the via opening 320 and the conductive line opening 330. The thickness of the second pad layer 134* on the substrate 102 is less than the thickness of the second pad layer 134* on the sidewalls of the via opening 320 and the conductive line opening 330.

[0071] As shown in FIG12, method 1200 further includes step 1220, to fill the remainder of the dual damascene opening with a conductive filler layer. The conductive filler layer may fill the remainder of the conductive line opening not occupied by one or more pad layers. In some embodiments, the conductive filler layer comprises copper, a copper alloy, tungsten, aluminum, or another suitable material. In some embodiments, the filling method employs atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process. In some embodiments, method 1200 includes additional steps such as annealing or planarization processes.

[0072] FIG13D is a cross-sectional view of the contact structure after the conductive filler layer has filled the remainder of the opening in some embodiments. Semiconductor device 1300D includes a third pad layer 136 and a conductive filler layer 138 in the conductive line opening and via opening. The third pad layer 136 separates the conductive filler layer 138 from the second pad layer 134*. The conductive filler layer 138 fills the remainder of the conductive line opening not occupied by the first pad layer 132*, the second pad layer 134*, and the third pad layer 136.

[0073] FIG14A is a cross-sectional view of the contact structure in the circuit region in some embodiments. Semiconductor device 1400A is similar to semiconductor device 1100 (FIG. 11). Compared with semiconductor device 1100, semiconductor device 1400A includes a portion of conductive structure 410 such as substrate 102. Semiconductor device 1400A does not contain vias such as via 120 (FIG. 1). Instead, a first pad layer 132*, a second pad layer 134*, a third pad layer 136, and a conductive fill layer 138 fill all openings in insulating layer 106 and etch stop layer 104. In some embodiments, semiconductor device 1400A is in a first metal layer, and the width W1 is about 8 nm to about 15 nm. In some embodiments, semiconductor device 1400A is in a second metal layer, and the width W1 is about 14 nm to about 22 nm. In some embodiments, semiconductor device 1400A is in a third metal layer, and the width W1 is about 12 nm to about 16 nm. In some cases, if the width W1 is too small, the interface resistance between the via 120 and the conductive fill layer 418 increases, and the function of the semiconductor device 1400A is impaired. In some cases, if the width W1 is too large, the size of the semiconductor device 1400A increases without a significant increase in performance.

[0074] Figure 14B is a cross-sectional view of the contact structure in the sealing region in some embodiments. Semiconductor device 1400B is similar to semiconductor device 1100 (Figure 11). Compared to semiconductor device 1100, semiconductor device 1400B includes a portion of conductive structure 410, such as substrate 102. In some embodiments, conductive structure 410 replaces substrate 102. Semiconductor device 1400B does not contain vias such as via 120 (Figure 1). Instead, first pad layer 132*, second pad layer 134*, third pad layer 136, and conductive fill layer 138 fill all openings in insulating layer 106 and etch stop layer 104.

[0075] FIG. 15 is a cross-sectional view of the contact structure in some embodiments. Semiconductor device 1500 is similar to semiconductor device 1100 (FIG. 11). Compared to semiconductor device 1100, semiconductor device 1500 does not have a pad layer between conductive fill layer 138 and substrate 102. The materials and formation processes of first pad layer 132^ and first pad layer 132 (FIG. 1) are similar. The materials and formation processes of second pad layer 134^ and second pad layer 134 (FIG. 1) are similar. In some embodiments, semiconductor device 1500 includes conductive materials (such as the conductive lines or silicon regions below) such as substrate 102.

[0076] Compared to the first pad layer 132 (FIG. 1), the thickness of the first pad layer 132^ along the sidewalls of the via opening and the conductive line opening is about 8 Å to about 20 Å. In some examples, if the thickness of the first pad layer 132^ along the sidewalls is too thin, the risk of the conductive fill layer 138 migrating into the insulating layer 106 increases. In some examples, if the thickness of the first pad layer 132^ along the sidewalls is too thick, the size of the semiconductor device 1500 increases without significantly increasing the performance of the semiconductor device 1500. In FIG. 15, the first pad layer 132^ does not completely cover the substrate 102. In some embodiments, a thin layer of the first pad layer 132^ covers the substrate 102. In some embodiments, the thickness of the first pad layer 132^ adjacent to the substrate 102 is about 1 Å to about 3 Å. In some embodiments, the thickness of the first pad layer 132^ adjacent to the substrate 102 is less than 50% of the thickness of the first pad layer 132^ along the sidewalls. In some examples, if the thickness of the first pad layer 132^ adjacent to the substrate 102 is too thin, the first pad layer 132^ is not actually present in the structure of the semiconductor device 1500. In some examples, if the thickness of the first pad layer 132^ adjacent to the substrate 102 is too thick, the resistance between the conductive fill layer 138 and the substrate 102 increases, and the function of the semiconductor device 1500 is damaged.

[0077] Compared to the second pad layer 134 (FIG. 1), the thickness of the second pad layer 134^ along the sidewalls of the via opening and the conductive line opening is from about 5 Å to about 25 Å. In some examples, if the thickness of the second pad layer 134^ along the sidewalls is too thin, the risk of the conductive fill layer 138 migrating into the insulating layer 106 increases. In some examples, if the thickness of the second pad layer 134^ along the sidewalls is too thick, the size of the semiconductor device 1500 increases without significantly increasing the performance of the semiconductor device 1500. In FIG. 15, the second pad layer 134^ does not completely cover the substrate 102. In some embodiments, the thin layer of the second pad layer 134^ does not cover the substrate 102. In some embodiments, the thickness of the second pad layer 134^ adjacent to the substrate 102 is from about 1 Å to about 3 Å. In some embodiments, the thickness of the second pad layer 134^ adjacent to the substrate 102 is less than 50% of the thickness of the second pad layer 134^ along the sidewalls. In some examples, if the thickness of the second pad layer 134^ adjacent to the substrate 102 is too thin, the second pad layer 134^ is not actually present in the structure of the semiconductor device 1500. In some examples, if the thickness of the second pad layer 134^ adjacent to the substrate 102 is too thick, the resistance between the conductive fill layer 138 and the substrate 102 increases, and the function of the semiconductor device 1500 is damaged.

[0078] The semiconductor device 1500 further includes a capping layer 1510. In some embodiments, the capping layer 1510 is similar to a third pad layer 136 (FIG. 1) of the conductive structure beneath the contact structure. The capping layer 1510 is located between the substrate 102 and the etch stop layer 104. In some embodiments, the capping layer 1510 comprises cobalt or another suitable material. In some embodiments, the thickness of the capping layer is from about 15 Å to about 40 Å. In some examples, if the thickness of the capping layer 1510 is too thick, the size of the semiconductor device 1500 increases without significantly improving the functionality of the semiconductor device 1500. In some examples, if the thickness of the capping layer 1510 is too thin, the risk of conductive material migrating from the substrate 102 into the etch stop layer 104 increases.

[0079] The method for forming the semiconductor device 1500 is similar to the method 1200 described above. For the semiconductor device 1500, surface adjustment can prevent the formation of a pad layer along the lower surface of the via opening.

[0080] FIG. 16A is a cross-sectional view of the contact structure after etching the dual damascene opening in some embodiments. Semiconductor device 1600A is similar to semiconductor device 300A (FIG. 3A). The capping layer portion 1610 of the semiconductor device is removed by an etching process. In some embodiments, the etching process for removing the capping layer portion 1610 is the same as the process used to form the dual damascene opening 310. In some embodiments, the etching process for removing the capping layer portion 1610 is different from the process used to form the dual damascene opening 310.

[0081] FIG16B is a cross-sectional view of the contact structure during the surface conditioning process in some embodiments. The surface conditioning process 910 is performed on the substrate 102 of the semiconductor device 1600B. In some embodiments, the surface conditioning process 910 is performed on a layer of the conductive unit, the isolation structure of the substrate 102, or the interconnect structure on the substrate 102.

[0082] FIG. 16C is a cross-sectional view of the contact structure after deposition of two pad layers in some embodiments. The semiconductor device 1600C includes a first pad layer 132^ along the sidewalls of the via opening 320 and the conductive line opening 330. The first pad layer 132^ exposes a portion of the substrate 102. The semiconductor device 1600C includes a second pad layer 134^ along the sidewalls of the via opening 320 and the conductive line opening 330. The second pad layer 134^ exposes a portion of the substrate 102.

[0083] FIG16D is a cross-sectional view of the contact structure after the conductive filler layer has filled the remaining portion of the opening in some embodiments. The semiconductor device 1600D includes a conductive filler layer 138 in the conductive line opening and the via opening. The conductive filler layer 138 fills the remaining portion of the conductive line opening not occupied by the first pad layer 132^ and the second pad layer 134^. The conductive filler layer 138 is in direct contact with the substrate 102.

[0084] FIG17A is a cross-sectional view of the contact structure in the circuit region in some embodiments. Semiconductor device 1700A is similar to semiconductor device 1500 (FIG. 15). Compared to semiconductor device 1500, semiconductor device 1700A includes a portion of conductive structure 410 such as substrate 102. Semiconductor device 1700A does not contain vias such as via 120 (FIG. 1). Instead, a first pad layer 132^, a second pad layer 134^, and a conductive fill layer 138 fill all openings in insulating layer 106 and etch stop layer 104. In some embodiments, the semiconductor device is a portion of a zero metal layer, and the width W1 is about 8 nm to about 12 nm. In some embodiments, semiconductor device 1700A is in a first metal layer, and the width W1 is about 10 nm to about 15 nm. In some embodiments, semiconductor device 1700A is in a second metal layer, and the width W1 is about 14 nm to about 22 nm. In some embodiments, the semiconductor device 1700A is located in a third metal layer, and the width W1 is approximately 12 nm to approximately 16 nm. In some examples, if the width W1 is too small, the interface resistance between the via 120 and the conductive filling layer 418 increases, and the function of the semiconductor device 1700A is impaired. In some examples, if the width W1 is too large, the size of the semiconductor device 1700A increases without significantly improving performance.

[0085] Figure 17B is a cross-sectional view of the contact structure in the sealing region in some embodiments. Semiconductor device 1700B is similar to semiconductor device 1500 (Figure 15). Compared to semiconductor device 1500, semiconductor device 1700B includes a portion of conductive structure 410, such as substrate 102. In some embodiments, conductive structure 410 replaces substrate 102. Semiconductor device 1700B does not contain vias such as via 120 (Figure 1). Instead, first pad layer 132^, second pad layer 134^, and conductive fill layer 138 fill all openings in insulating layer 106 and etch stop layer 104.

[0086] Figure 18 is a cross-sectional view of the contact structure in some embodiments. Semiconductor device 1800 is similar to semiconductor device 1100 (Figure 11). Compared to semiconductor device 1100, semiconductor device 1800 includes a different first pad layer. Semiconductor device 1800 includes a first pad layer 1810 instead of a first pad layer 132* (Figure 11). Furthermore, the third pad layer 136* of semiconductor device 1800 extends only along the upper surface of conductive fill layer 138. The third pad layer 136* is similar in material, thickness, and formation process to the third pad layer 136 (Figure 1).

[0087] The first pad layer 1810 comprises ruthenium-doped tantalum nitride. In some embodiments, the method of doping ruthenium with tantalum nitride may be in-situ doping. In some embodiments, the method of doping ruthenium with tantalum nitride may be depositing a ruthenium layer on the tantalum nitride layer and annealing to drive ruthenium into the tantalum nitride. The thickness of the first pad layer 1810 along the sidewalls of the via opening and the conductive line opening may be from about 5 Å to about 15 Å. In some examples, if the thickness of the first pad layer 1810 is too thin, the risk of the conductive fill layer 138 migrating into the insulating layer 106 increases. In some examples, if the thickness of the first pad layer 1810 is too thick, the size of the semiconductor device 1800 increases without a significant increase in performance. The thickness of the first pad layer 1810 adjacent to the substrate 102 may be from about 3 Å to about 8 Å. In some examples, if the first pad layer 1810 is too thin, the risk of the conductive fill layer 138 migrating into the substrate 102 increases. In some cases, if the first pad layer 1810 is too thick, the resistance between the conductive fill layer 138 and the substrate 102 increases and the semiconductor device 1800 malfunctions.

[0088] Figure 19 is a flowchart of a method 1900 for manufacturing a contact structure in some embodiments. Step 1905 involves etching an insulating layer to form a double damascene opening to expose the underlying material. In some embodiments, step 1905 is similar to step 205 (Figure 2).

[0089] Figure 20A is a cross-sectional view of the contact structure after etching the dual damascene openings in some embodiments. Semiconductor device 2000A is similar to semiconductor device 300A (Figure 3A).

[0090] As shown in FIG19, method 1900 further includes step 1910 to perform surface conditioning on the underlying material. In some embodiments, the underlying material includes a conductive material, an insulating structure, or a semiconductor structure. The method of conditioning the surface includes depositing a monolayer of benzotriazole. In some embodiments, the method of conditioning the surface includes depositing a material other than benzotriazole. Surface conditioning is selective for conductive materials, so a monolayer is not formed on the insulating layer 106.

[0091] FIG20B is a cross-sectional view of the contact structure during a surface conditioning process in some embodiments. A surface conditioning process 910 is performed on a substrate 102 of a semiconductor device 2000B. In some embodiments, the surface conditioning process 910 is performed on a layer of a conductive unit, an isolation structure in the substrate 102, or an interconnect structure on the substrate 102.

[0092] As shown in FIG19, step 1915 of method 1900 deposits one or more pad layers. In some embodiments, a single pad layer is deposited. In some embodiments, multiple pad layers are deposited. A surface conditioning process causes the thickness of the first pad layer deposited in step 1915 on the underlying material to be less than the thickness along the sidewalls of the insulating layer. In some embodiments, the first pad layer comprises ruthenium-doped tantalum nitride or another suitable material. In some embodiments, additional pad layers comprise ruthenium, cobalt, or other suitable materials. In some embodiments, the surface treatment in step 1910 may prevent the formation of a pad layer adjacent to the substrate 102. In some embodiments, the method of depositing one or more pad layers may each employ atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0093] Figure 20C is a cross-sectional view of the contact structure after depositing two pad layers in some embodiments. The semiconductor device 2000C includes a first pad layer 1810 in the via opening 320 and the conductive line opening 330. The thickness of the first pad layer 1810 on the substrate 102 is less than the thickness of the first pad layer 1810 on the sidewalls of the via opening 320 and the conductive line opening 330. The semiconductor device 2000C includes a second pad layer 134* in the via opening 320 and the conductive line opening 330. The thickness of the second pad layer 134* on the substrate 102 is less than the thickness of the second pad layer 134* on the sidewalls of the via opening 320 and the conductive line opening 330.

[0094] As shown in FIG19, method 1900 further includes step 1920, to fill the remainder of the dual damascene opening with a conductive filler layer. The conductive filler layer may fill the remainder of the conductive line opening not occupied by one or more pad layers. In some embodiments, the conductive filler layer comprises copper, a copper alloy, tungsten, aluminum, or another suitable material. In some embodiments, the filling method employs atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process. In some embodiments, method 1900 includes additional steps such as annealing or planarization processes.

[0095] FIG20D is a cross-sectional view of the contact structure after the conductive filler layer has filled the remainder of the opening in some embodiments. The semiconductor device 2000D includes a conductive filler layer 138 in the conductive line opening and the via opening. The conductive filler layer 138 fills the remainder of the conductive line opening not occupied by the first pad layer 1810 and the second pad layer 134*.

[0096] FIG21A is a cross-sectional view of the contact structure in the circuit region in some embodiments. Semiconductor device 2100A is similar to semiconductor device 1800 (FIG. 18). Compared to semiconductor device 1800, semiconductor device 2100A includes a portion of conductive structure 410, such as substrate 102. Semiconductor device 2100A does not contain vias such as via 120 (FIG. 1). Instead, a first pad layer 1810, a second pad layer 134*, and a conductive fill layer 138 fill all openings in insulating layer 106 and etch stop layer 104. In some embodiments, semiconductor device 2100A is in a first metal layer, and the width W1 is about 10 nm to about 15 nm. In some embodiments, semiconductor device 2100A is in a second metal layer, and the width W1 is about 14 nm to about 22 nm. In some embodiments, semiconductor device 2100A is in a third metal layer, and the width W1 is about 12 nm to about 16 nm. In some cases, if the width W1 is too small, the resistance between the conductive filler layer 418 and the substrate 102 increases and the function of the semiconductor device 2100A is impaired. In some cases, if the width W1 is too large, the size of the semiconductor device 2100A increases without significantly improving performance.

[0097] Figure 21B is a cross-sectional view of the contact structure in the sealing region in some embodiments. Semiconductor device 2100B is similar to semiconductor device 1800 (Figure 18). Compared to semiconductor device 1800, semiconductor device 2100B includes a portion of conductive structure 410, such as substrate 102. In some embodiments, conductive structure 410 replaces substrate 102. Semiconductor device 2100B does not contain vias such as via 120 (Figure 1). Instead, first pad layer 1810, second pad layer 134*, and conductive fill layer 138 fill all openings in insulating layer 106 and etch stop layer 104.

[0098] Figure 22 is a cross-sectional view of the contact structure in some embodiments. Semiconductor device 2200 is similar to semiconductor device 1800 (Figure 18). Compared to semiconductor device 1800, semiconductor device 2200 does not include a first pad layer 1810 (Figure 18) or a third pad layer 136* (Figure 18). Instead, semiconductor device 2200 includes a second pad layer 134* that directly contacts the substrate 102 and the conductive fill layer 138. In some embodiments, the second pad layer 134* includes ruthenium. The thickness of the second pad layer 134* along the sidewalls of the via opening and the conductive line opening can be from about 10 Å to about 35 Å. In some examples, if the thickness of the second pad layer 134* is too thin, the risk of the conductive fill layer 138 migrating into the insulating layer 106 increases. In some examples, if the thickness of the second pad layer 134* is too thick, the size of semiconductor device 2200 increases without a significant increase in performance. The thickness of the second pad layer 134* adjacent to the substrate 102 is from about 3 Å to about 8 Å. In some examples, if the second pad layer 134* is too thin, the risk of material migration from the conductive fill layer 138 into the substrate 102 increases. In some examples, if the second pad layer 134* is too thick, the resistance between the conductive fill layer 138 and the substrate 102 increases and the semiconductor device 2200 malfunctions.

[0099] Figure 23 is a flowchart of a method 2300 for manufacturing a contact structure in some embodiments. Step 2305 involves etching an insulating layer to form a double damascene opening to expose the underlying material. In some embodiments, step 2305 is similar to step 205 (Figure 2).

[0100] Figure 24A is a cross-sectional view of the contact structure after etching the dual damascene openings in some embodiments. Semiconductor device 2400A is similar to semiconductor device 300A (Figure 3A).

[0101] As shown in FIG23, method 2300 further includes step 2310 to perform surface conditioning on the underlying material. In some embodiments, the underlying material includes a conductive material, an insulating structure, or a semiconductor structure. The method of conditioning the surface includes depositing a monolayer of benzotriazole. In some embodiments, the method of conditioning the surface includes depositing a material other than benzotriazole. Surface conditioning is selective for conductive materials, so a monolayer is not formed on the insulating layer 106.

[0102] FIG24B is a cross-sectional view of the contact structure after a surface conditioning process in some embodiments. A surface conditioning process 910 is performed on a substrate 102 of the semiconductor device 2400B. In some embodiments, the surface conditioning process 910 is performed on a layer of a conductive unit, an isolation structure in the substrate 102, or an interconnect structure on the substrate 102.

[0103] As shown in FIG23, method 2300 includes step 2315 to deposit one or more pad layers. In some embodiments, a single pad layer is deposited. In some embodiments, multiple pad layers are deposited. The surface preparation of step 2310 causes the pad layer deposited in step 2315 to have a thickness on the underlying material greater than the thickness along the sidewalls of the insulating layer. In some embodiments, the pad layer comprises ruthenium or another suitable material. In some embodiments, an additional pad layer comprises cobalt or other suitable material. In some embodiments, the surface treatment of step 2310 may prevent the formation of a pad layer adjacent to the substrate 102. In some embodiments, the method of depositing one or more pad layers may each employ atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0104] FIG24C is a cross-sectional view of the contact structure after the deposition of the pad layer in some embodiments. The semiconductor device 2400C includes a second pad layer 134* in the via opening 320 and the conductive line opening 330. The thickness of the second pad layer 134* on the substrate 102 is less than the thickness of the second pad layer 134* on the sidewalls of the via opening 320 and the conductive line opening 330.

[0105] As shown in FIG23, method 2300 further includes step 2320 to fill the remainder of the dual damascene opening with a conductive filler layer. The conductive filler layer may fill the remainder of the conductive line opening not occupied by one or more pad layers. In some embodiments, the conductive filler layer comprises copper, a copper alloy, tungsten, aluminum, or another suitable material. In some embodiments, the filling method employs atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process. In some embodiments, method 2300 includes additional steps such as annealing or planarization processes.

[0106] Figure 24D is a cross-sectional view of the contact structure after the conductive filler layer has been filled into the remaining portion of the opening. The semiconductor device 2400D includes a conductive filler layer 138 in the conductive line opening and the via opening. The conductive filler layer 138 fills the remaining portion of the conductive line opening that is not occupied by the second pad layer 134*.

[0107] FIG25A is a cross-sectional view of the contact structure in the circuit area in some embodiments. Semiconductor device 2500A is similar to semiconductor device 2200 (FIG. 22). Compared with semiconductor device 2200, semiconductor device 2500A includes a portion of conductive structure 410, such as substrate 102.

[0108] Semiconductor device 2500A does not contain vias such as via 120 (FIG. 1). Instead, a second pad layer 134* and a conductive fill layer 138 fill all openings in the insulating layer 106 and the etch stop layer 104. In some embodiments, semiconductor device 2500A is in a first metal layer, and the width W1 is about 10 nm to about 15 nm. In some embodiments, semiconductor device 2500A is in a second metal layer, and the width W1 is about 14 nm to about 22 nm. In some embodiments, semiconductor device 2500A is in a third metal layer, and the width W1 is about 12 nm to about 16 nm. In some examples, if the width W1 is too small, the interface resistance between the conductive fill layer 418 and the substrate 102 increases, and the function of semiconductor device 2500A is impaired. In some examples, if the width W1 is too large, the size of semiconductor device 2500A increases without significantly improving performance.

[0109] Figure 25B is a cross-sectional view of the contact structure in the sealing region in some embodiments. Semiconductor device 2500B is similar to semiconductor device 2200 (Figure 22). Compared to semiconductor device 2200, semiconductor device 2500B includes a portion of conductive structure 410, such as substrate 102. In some embodiments, conductive structure 410 replaces substrate 102. Semiconductor device 2500B does not contain vias such as via 120 (Figure 1). Instead, second pad layer 134* and conductive fill layer 138 fill all openings in insulating layer 106 and etch stop layer 104.

[0110] FIG26 is a cross-sectional view of a contact structure in some embodiments. The contact structure is a portion of a semiconductor device 2600. The semiconductor device 2600 includes a substrate (not shown) containing a first source / drain region 2610a and a second source / drain region 2610b. An etch stop layer 2620 is located on the substrate 102. In some embodiments, the etch stop layer 2620 is referred to as a contact etch stop layer. An insulating layer 2630 is located on the etch stop layer 2620. In some embodiments, the insulating layer 2630 is an interlayer dielectric layer. In some embodiments, the insulating layer 2630 is an intermetallic dielectric layer. An etch stop layer 2640 is located on the insulating layer 2630. An insulating layer 2650 is located on the etch stop layer 2640. A first via 2660a extends from the insulating layer 2630 through the etch stop layer 2620 to connect to the first source / drain region 2610a. A second via 2660b extends from the insulating layer 2630 through the etch stop layer 2620 to connect to the second source / drain region 2610b. A first conductive line 2670a extends from the insulating layer 2650 through the etch stop layer 2640 to connect to the first via 2660a. A second conductive line 2670b extends from the insulating layer 2650 through the etch stop layer 2640 to connect to the second via 2660b.

[0111] In some embodiments, at least one of the first source / drain region 2610a or the second source / drain region 2610b is replaced with another conductive unit, such as a gate. In some embodiments, at least one of the first source / drain region 2610a or the second source / drain region 2610b is replaced with an isolation structure, such as a shallow trench isolation. Figure 26 is a cross-sectional view of the contact structure in the zeroth metal layer. In some embodiments, the contact structure is a portion of the first to third metal layers, and the substrate is replaced by a layer of interconnect structure directly below the contact structure.

[0112] Etching stop layer 2620 and 2640 are each similar to etch stop layer 104 (FIG. 1). In some embodiments, etch stop layer 2620 and etch stop layer 2640 comprise the same material and the same thickness. In some embodiments, the thickness of etch stop layer 2620 and etch stop layer 2640 differs from at least one of the materials.

[0113] Insulating layer 2630 and insulating layer 2650 are each similar to insulating layer 106 (FIG. 1). In some embodiments, insulating layer 2630 and insulating layer 2650 comprise the same material and the same thickness. In some embodiments, the thickness of insulating layer 2630 and insulating layer 2650 differs from at least one of the materials.

[0114] The first via 2660a includes a first pad layer 2662a and a first conductive fill layer 2664a. The first pad layer 2662a helps prevent the first conductive fill layer 2664a from migrating into the insulating layer 2630 or the etch stop layer 2620. The first conductive fill layer 2664a includes a conductive material to transmit signals from the first conductive line 2670a to the first source / drain region 2610a. In some embodiments, the first pad layer 2662a is similar to the second pad layer 134 (FIG. 1). In some embodiments, the first conductive fill layer 2664a is similar to the conductive fill layer 138 (FIG. 1) and includes copper, a copper alloy, or another suitable material.

[0115] The second via 2660b includes a second pad layer 2662b and a second conductive fill layer 2664b. The second pad layer 2662b helps prevent the second conductive fill layer 2664b from migrating into the insulating layer 2630 or the etch stop layer 2620. The second conductive fill layer 2664b includes a conductive material to transmit signals from the second conductive line 2670b to the second source / drain region 2610b. In some embodiments, the second pad layer 2662b is similar to the second pad layer 134 (FIG. 1). In some embodiments, the second conductive fill layer 2664b includes cobalt or another suitable material. In some embodiments, the first via 2660a and the second via 2660b include the same conductive fill material.

[0116] The first conductive line 2670a includes a first pad layer 2672, a second pad layer 2674, a third pad layer 2676, and a conductive filler layer 2678. In some embodiments, the first pad layer 2672 is similar to the first pad layer 132 (FIG. 1). In some embodiments, the second pad layer 2674 is similar to the second pad layer 134 (FIG. 1). In some embodiments, the third pad layer 2676 is similar to the third pad layer 136 (FIG. 1). In some embodiments, the conductive filler layer 2678 is similar to the conductive filler layer 138 (FIG. 1). The first pad layer 2672 extends along the sidewall of the second pad layer 2674. The lower surface of the second pad layer 2674 directly contacts the first pad layer 2662a of the first through-hole 2660a. The second conductive line 2670b is similar to the first conductive line 2670a.

[0117] FIG27 is a cross-sectional view of the contact structure in some embodiments. The contact structure is a portion of semiconductor device 2700. Semiconductor device 2700 is similar to semiconductor device 2600 (FIG. 26). Compared to semiconductor device 2600, the first conductive line 2770a and the second conductive line 2770b include a first pad layer 2772 extending beneath a second pad layer 2674. The first pad layer 2772 separates the second pad layer 2674 from the first pad layer 2662a of the first via 2660a. In FIG27, the first pad layer 2772 extends beneath the entire second pad layer 2674. In some embodiments, the inner edge of the first pad layer 2772 is aligned with the inner sidewall of the first pad layer 2662a of the first via 2660a. The second pad layer 2674 directly contacts the first conductive fill layer 2664a but is separated from the first pad layer 2662a. The configuration of the second conductive line 2770b and the second via 2660b is similar to the configuration of the first conductive line 2770a and the first via 2660a described above. Compared to the semiconductor device 2600, the contact structure of the semiconductor device 2700 helps to improve performance because the bottom corner of the first pad layer 2772 separating the second pad layer 2674 and the insulating layer 2630 can reduce or eliminate the diffusion of the metal filler layer.

[0118] Figure 28 is a flowchart of a method 2800 for manufacturing a contact structure in some embodiments. In step 2805, an insulating layer is etched to form a single damascene opening to expose the underlying material. In some embodiments, step 2805 is similar to step 205 (Figure 2). Compared to step 205, step 2805 forms a single damascene opening for the conductive lines, rather than a double damascene opening.

[0119] FIG29A is a cross-sectional view of the contact structure after etching a single damascene opening in some embodiments. Semiconductor device 2900A includes a single damascene opening 2910 on each of a first via 2660a and a second via 2660b.

[0120] As shown in FIG28, method 2800 further includes step 2810 to perform surface conditioning on the underlying material. In some embodiments, the underlying material includes a conductive material, an insulating structure, or a semiconductor structure. The method of conditioning the surface includes depositing a monolayer of benzotriazole. In some embodiments, the method of conditioning the surface includes depositing a material other than benzotriazole. The surface conditioning is selective for conductive materials, so a monolayer is not formed on the insulating layer 2650.

[0121] FIG29B is a cross-sectional view of the contact structure during a surface trimming process in some embodiments. A surface trimming process 2920 is performed on each of the first via 2660a and the second via 2660b of the semiconductor device 2900B. In some embodiments, the surface trimming process 2920 is performed on a layer of a conductive unit, an isolation structure in a substrate, or an interconnect structure on a substrate.

[0122] As shown in FIG28, step 2815 of method 2800 deposits one or more pad layers. In some embodiments, a single pad layer is deposited. In some embodiments, multiple pad layers are deposited. The surface adjustment in step 2810 causes the thickness of the pad layer deposited in step 2815 on the underlying material to be less than the thickness along the sidewall of the insulating layer. In some embodiments, the first pad layer comprises tantalum nitride or another suitable material. In some embodiments, the additional pad layer comprises ruthenium, cobalt, or other suitable materials. In some embodiments, the surface treatment in step 2810 may prevent the formation of a first pad layer adjacent to the first via 2660a or the second via 2660b. In some embodiments, the method of depositing one or more pad layers may each employ atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0123] Figure 29C is a cross-sectional view of the contact structure after the deposition of the pad layer in some embodiments. Semiconductor device 2900C includes a first pad layer 2772 on a first via 2660a and a second via 2660b. The thickness of the first pad layer 2772 on the first conductive fill layer 2664a and the second conductive fill layer 2664b is less than the thickness of the first pad layer 2772 on the first pad layer 2662a and the second pad layer 2662b along the sidewall of the insulating layer 2650.

[0124] As shown in FIG28, method 2800 further includes step 2820, to fill the remainder of the dual damascene opening with a conductive filler layer. The conductive filler layer may fill the remainder of the opening not occupied by one or more pad layers. In some embodiments, the conductive filler layer comprises copper, a copper alloy, tungsten, aluminum, or another suitable material. In some embodiments, the filling method employs atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process. In some embodiments, method 2800 includes additional steps such as annealing or planarization processes.

[0125] Figure 30 is a cross-sectional view of the contact structure in some embodiments. The contact structure is a portion of the semiconductor device 3000. The semiconductor device 3000 is similar to the semiconductor device 2700 (Figure 27). Compared to the semiconductor device 2700, the third pad layer 3076 only covers the upper surface of the conductive fill layer 2678. The second pad layer 2674 directly contacts the sidewall of the conductive fill layer 2678.

[0126] FIG31 is a cross-sectional view of the contact structure in some embodiments. The contact structure is a portion of the semiconductor device 3100. The semiconductor device 3100 is similar to the semiconductor device 2700 (FIG. 27). Compared to the semiconductor device 2700, the second pad layer 2674 (FIG. 27) is omitted. The third pad layer 2676 directly contacts the first pad layer 2772.

[0127] FIG32 is a cross-sectional view of a contact structure in some embodiments. The contact structure is a portion of a semiconductor device 3200. The semiconductor device 3200 includes an insulating layer 3210. In some embodiments, the insulating layer 3210 is located on a substrate. In some embodiments, the insulating layer 3210 is a portion of an interconnect structure. In some embodiments, the insulating layer 3210 is an interlayer dielectric layer. In some embodiments, the insulating layer 3210 is an intermetallic dielectric layer. The semiconductor device 3200 further includes an insulating layer 3220 on the insulating layer 3210. In some embodiments, the insulating layer 3210 and the insulating layer 3220 are the same layer without an interface between them. In some embodiments, an interface exists between the insulating layers 3210 and 3220. An etch stop layer 3230 is located on the insulating layer 3220. A first via 3240a extends through the insulating layer 3210 to connect to another unit in the semiconductor device 3200. In some embodiments, the first via 3240a is connected to a substrate, a conductive unit, an isolation structure, or another device in the semiconductor device 3200. The second via 3240b extends through the insulating layer 3210 to connect to another unit in the semiconductor device 3200. In some embodiments, the second via 3240b is connected to a substrate, a conductive unit, an isolation structure, or another device in the semiconductor device 3200. In some embodiments, the first via 3240a and the second via 3240b are connected to the same unit. In some embodiments, the first via 3240a and the second via 3240b are connected to different units. A first conductive line 3250a extends through the insulating layer 3220 to connect to the first via 3240a. A second conductive line 3250b extends through the insulating layer 3220 to connect to the second via 3240b.

[0128] Insulating layers 3210 and 3220 are each similar to insulating layer 106 (FIG. 1). In some embodiments, insulating layers 3210 and 3220 comprise the same material and the same thickness. In some embodiments, the thickness of insulating layers 3210 and 3220 differs from at least one of the materials. Etch stop layer 3230 is similar to etch stop layer 104 (FIG. 1).

[0129] The first through-hole 3240a comprises tungsten. In some embodiments, the first through-hole 3240a further comprises at least one padding layer between the tungsten and the insulating layer 3210. The second through-hole 3240b comprises ruthenium. In some embodiments, the second through-hole 3240b further comprises at least one padding layer between the ruthenium and the insulating layer 3210. In some embodiments, both the first through-hole 3240a and the second through-hole 3240b comprise tungsten. In some embodiments, both the first through-hole 3240a and the second through-hole 3240b comprise ruthenium.

[0130] The first conductive line 3250a includes a first pad layer 3252 and a first conductive fill layer 3254. The first pad layer 3252 separates the first conductive fill layer 3254 from the first via 3240a. The first pad layer 3252 extends over an insulating layer 3210 surrounding the first via 3240a. In some embodiments, the first pad layer 3252 includes titanium nitride. The thickness of the first pad layer 3252 is substantially uniform. In some embodiments, the thickness of the first pad layer 3252 over the first via 3240a is less than the thickness of the first pad layer 3252 over the insulating layer 3210. The first conductive fill layer 3254 is located on the first pad layer 3252 and is configured to transmit signals from the first conductive fill layer 3254 to the first via 3240a in the final device structure. In some embodiments, the first conductive fill layer 3254 includes ruthenium.

[0131] The second conductive line 3250b is similar to the first conductive line 3250a. Compared to the first conductive line 3250a, the second conductive line 3250b includes a second conductive filler layer 3256. In some embodiments, the second conductive filler layer 3256 includes tungsten. In some embodiments, the first conductive filler layer 3254 and the second conductive filler layer 3256 include ruthenium. In some embodiments, the first conductive filler layer 3254 and the second conductive filler layer 3256 include tungsten.

[0132] In some embodiments, the thickness of the first pad layer 3252 may be from about 5 Å to about 15 Å. In some examples, if the thickness is too small, the risk of material migration from the first conductive fill layer 3254 or the second conductive fill layer 3256 into the insulating layer 3210 increases. In some examples, if the thickness is too large, the size of the semiconductor device 3200 increases without significantly improving the function of the semiconductor device 3200. In some embodiments, the first conductive fill layer 3254 or the second conductive fill layer 3256 is from about 10 Å to about 30 Å. In some examples, if the thickness is too small, the resistance in the conductive fill layer increases, and the function of the semiconductor device 3200 is impaired. In some examples, if the thickness is too large, the size of the semiconductor device 3200 increases without significantly improving the function of the semiconductor device 3200.

[0133] Figure 33 is a cross-sectional view of the contact structure in some embodiments. The contact structure is a portion of the semiconductor device 3300. The semiconductor device 3300 is similar to the semiconductor device 3200 (Figure 32). Compared to the semiconductor device 3200, the first conductive line 3350a and the second conductive line 3350b include a first pad layer 3352 containing tantalum nitride. The thickness of the first pad layer 3352 on the first via 3240a and the second via 3240b is less than the thickness of the first pad layer 3352 on the insulating layer 3210. In some embodiments, the first pad layer 3352 is discontinuous on the first via 3240a or the second via 3240b. Compared to the semiconductor device 3200 (Figure 32), the contact resistance of the semiconductor device 3300 is lower.

[0134] In some embodiments, the thickness of the first pad layer 3352 is from about 5 Å to about 15 Å. In some examples, if the thickness is too small, the risk of the first conductive fill layer 3254 or the second conductive fill layer 3256 migrating into the insulating layer 3210 increases. In some examples, if the thickness is too large, the size of the semiconductor device 3300 increases without significantly improving the function of the semiconductor device 3300. In some embodiments, the thickness of the first conductive fill layer 3254 or the second conductive fill layer 3256 is from about 10 Å to about 30 Å. In some examples, if the thickness is too small, the resistance in the conductive fill layer increases, and the function of the semiconductor device 3300 is impaired. In some examples, if the thickness is too large, the size of the semiconductor device 3300 increases without significantly improving the function of the semiconductor device 3300.

[0135] Figure 34 is a flowchart of a method 3400 for manufacturing a contact structure in some embodiments. Step 3405 involves surface conditioning on a substrate material. In some embodiments, the substrate material includes a conductive material, an isolation structure, or a semiconductor structure. The surface conditioning method includes depositing a monolayer of benzotriazole. In some embodiments, the surface conditioning method includes depositing a material other than benzotriazole. The surface conditioning is selective for conductive materials, so the monolayer is not formed on an insulating layer (such as insulating layer 3210), see Figure 33.

[0136] FIG35A is a cross-sectional view of the contact structure during a surface trimming process in some embodiments. A surface trimming process 3510 is performed on each of the first via 3240a and the second via 3240b of the semiconductor device 3500A. In some embodiments, the surface trimming process 3510 is performed on a layer of a conductive unit, an isolation structure in a substrate, or an interconnect structure on a substrate.

[0137] As shown in FIG34, step 3410 of method 3400 deposits one or more pad layers. In some embodiments, a single pad layer is deposited. In some embodiments, multiple pad layers are deposited. Surface preparation in step 3405 causes the thickness of the pad layer deposited in step 3410 on the underlying material to be less than the thickness along the insulating layer. In some embodiments, the first pad layer comprises tantalum nitride, titanium nitride, or another suitable material. In some embodiments, the additional pad layer comprises ruthenium, cobalt, or other suitable materials. In some embodiments, the surface treatment in step 3405 may prevent the formation of a first pad layer adjacent to a via (as shown in FIG33, the first via 3240a or the second via 3240b). In some embodiments, the method of depositing one or more pad layers may each employ atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0138] Figure 35B is a cross-sectional view of the contact structure after the deposition of the pad layer in some embodiments. The semiconductor device 3500B includes a first pad layer 3352 on a first via 3240a and a second via 3240b. The thickness of the first pad layer 3352 on the first via 3240a and the second via 3240b is less than the thickness of the first pad layer 3352 on the insulating layer 3210.

[0139] As shown in FIG34, method 3400 further includes step 3415, to deposit a conductive filler layer on one or more pad layers. The conductive filler layer may be deposited blanket-like on one or more pad layers. In some embodiments, the conductive filler layer comprises copper, a copper alloy, tungsten, aluminum, or another suitable material. In some embodiments, the filling method employs atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or another suitable deposition process.

[0140] Figure 35C is a cross-sectional view of the contact structure after deposition of the conductive filler layer in some embodiments. Semiconductor device 3500C includes a conductive filler layer 3520 blanket-deposited on a first pad layer 3352.

[0141] As shown in FIG34, method 3400 further includes step 3420 of forming a separate contact structure by patterning a conductive fill layer. In some embodiments, the patterning step employs a series of photolithography and etching processes. In some embodiments, the etching process is a wet etching process. In some embodiments, the etching process is a dry etching process.

[0142] Figure 35D is a cross-sectional view of the contact structure after the patterned conductive filler layer in some embodiments. The patterned conductive filler layer 3520 is used to form two separate contact structures or a first conductive line 3350a.

[0143] In some embodiments, method 3400 includes additional steps such as annealing and planarization processes. In some embodiments, additional deposition and patterning processes are used to form conductive lines of different materials in a semiconductor device.

[0144] FIG36A is a cross-sectional view of the contact structure in the circuit region in some embodiments. Semiconductor device 3600A is similar to semiconductor device 3300 (FIG. 33). Compared to semiconductor device 3300, semiconductor device 3600A includes a portion of conductive structure 3640, such as a first via 3240a. Semiconductor device 3600A does not include the first via 3240a (FIG. 33). Instead, conductive structure 3640 includes a first pad layer 3642, a second pad layer 3644, and a conductive fill layer 3646. The first pad layer 3642 is similar to the first pad layer 132 (FIG. 1). The second pad layer 3644 is similar to the second pad layer 134 (FIG. 1). The conductive fill layer 3646 is similar to the conductive fill layer 138 (FIG. 1). In some embodiments, conductive structure 3640 directly contacts the gate or source / drain region. In some embodiments, the width W3 of the conductive structure 3640 is from about 6 nm to about 15 nm. In some examples, if the width W3 is too small, the resistance of the conductive structure 3640 increases, and the function of the semiconductor device 3600A is impaired. In some examples, if the width W3 is too large, the size of the semiconductor device 3600A increases without significantly improving its function. In some embodiments, the width W4 of the first pad layer 3352 is from about 8 nm to about 22 nm. In some examples, if the width W4 is too small, the resistance of the conductive line 3350a increases, and the function of the semiconductor device 3600A is impaired. In some examples, if the width W4 is too large, the size of the semiconductor device 3600A increases without significantly improving its performance.

[0145] Figure 36B is a cross-sectional view of the contact structure in the wind tunnel region in some embodiments. Semiconductor device 3600B is similar to semiconductor device 3300 (Figure 33). Compared to semiconductor device 3300, semiconductor device 3600B includes a conductive structure 3640 instead of a first via 3240a or a second via 3240b. In some embodiments, the width W5 of the conductive structure 3640 is from about 6 nm to about 15 nm. In some examples, if the width W5 is too small, the resistance of the conductive structure 3640 increases, and the function of semiconductor device 3600B is impaired. In some examples, if the width W5 is too large, the size of semiconductor device 3600B increases without significantly improving the function of semiconductor device 3600B. In some embodiments, the width W6 of the first pad layer 3352 is from about 100 nm to about 180 nm. In some examples, if the width W6 is too small, the resistance of the conductive line 3350a increases, and the function of semiconductor device 3600B is impaired. In some embodiments, if the width W6 is too large, the size of the semiconductor device 3600B increases without significantly improving the functionality of the semiconductor device 3600B.

[0146] One embodiment of the present invention relates to a semiconductor device. The semiconductor device includes an insulating layer having a via opening and a conductive line opening. The semiconductor device further includes a via located in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line located in the conductive line opening. The conductive line includes a first pad layer, wherein a first thickness of the first pad layer over the via is less than a second thickness of the first pad layer over the insulating layer, and a conductive fill layer including a second conductive material, wherein the second conductive material is different from the first conductive material. In some embodiments, the first pad layer includes tantalum nitride. In some embodiments, the first conductive material is in direct contact with the insulating layer. In some embodiments, the first conductive material includes ruthenium or tungsten. In some embodiments, the conductive line further includes a second pad layer between the first pad layer and the conductive fill layer. In some embodiments, the second pad layer includes the first conductive material. In some embodiments, the first pad layer extends into the via opening. In some embodiments, the conductive fill layer extends into the via opening. In some embodiments, the first thickness is less than 50% of the second thickness. In some embodiments, a third thickness of the first pad layer along the sidewall of the insulating layer is equal to the second thickness.

[0147] An embodiment of the present invention relates to a method for manufacturing a semiconductor device. The method includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface conditioning process on the conductive material. The method further includes, after the surface conditioning process, depositing a first pad layer in the second opening, wherein the first pad layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill layer on the first pad layer, wherein the conductive fill layer and the conductive material comprise different materials. In some embodiments, the step of depositing the first pad layer includes depositing a first pad layer of a first thickness on the conductive material and depositing a first pad layer of a second thickness on the insulating layer, wherein the second thickness is greater than the first thickness. In some embodiments, the step of depositing the conductive material includes depositing ruthenium or tungsten. In some embodiments, the surface conditioning process includes depositing a monolayer of organic long-chain molecules. In some embodiments, the method further includes depositing a second pad layer on the first pad layer, wherein the second pad layer is located between the first pad layer and the conductive fill layer, and the thickness of the second pad layer is substantially uniform.

[0148] One embodiment of the present invention relates to a semiconductor device. The semiconductor device includes an insulating layer having a via opening and a conductive line opening. The semiconductor device further includes a via located in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line located in the conductive line opening. The conductive line includes a first pad layer; a second pad layer located on the first pad layer, wherein the second pad layer is continuous with the first conductive material; and a conductive fill layer including a second conductive material, wherein the second conductive material is different from the first conductive material. In some embodiments, the first pad layer extends into the via opening. In some embodiments, the first pad layer is located between the via and the insulating layer. In some embodiments, the first conductive material includes ruthenium. In some embodiments, the first pad layer extends along the bottommost surface of the via.

[0149] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a cross-sectional view of the contact structure in some embodiments. Figure 2 is a flowchart of a method for manufacturing the contact structure in some embodiments. Figures 3A to 3D are cross-sectional views of the contact structure at various manufacturing stages in some embodiments. Figure 3E is a cross-sectional view during the manufacturing of the contact structure in some embodiments. Figure 4A is a cross-sectional view of the contact structure in a circuit region in some embodiments. Figure 4B is a cross-sectional view of the contact structure in a closed-loop region in some embodiments. Figure 5 is a cross-sectional view of the contact structure in some embodiments. Figure 6A is a cross-sectional view of the contact structure in a circuit region in some embodiments. Figure 6B is a cross-sectional view of the contact structure in a closed-loop region in some embodiments. Figure 7 is a cross-sectional view of the contact structure in some embodiments. Figure 8 is a flowchart of a method for manufacturing the contact structure in some embodiments. Figures 9A to 9D are cross-sectional views of the contact structure at various manufacturing stages in some embodiments. Figure 10A is a cross-sectional view of the contact structure in a circuit region in some embodiments. Figure 10B is a cross-sectional view of the contact structure in a closed-loop region in some embodiments. Figure 11 is a cross-sectional view of the contact structure in some embodiments. Figure 12 is a flowchart of a method for manufacturing a contact structure in some embodiments. Figures 13A to 13D are cross-sectional views of contact structures at various manufacturing stages in some embodiments. Figure 14A is a cross-sectional view of a contact structure in a circuit region in some embodiments. Figure 14B is a cross-sectional view of a contact structure in a closed-loop region in some embodiments. Figure 15 is a flowchart of a method for manufacturing a contact structure in some embodiments. Figures 16A to 16D are cross-sectional views of contact structures at various manufacturing stages in some embodiments. Figure 17A is a cross-sectional view of a contact structure in a circuit region in some embodiments. Figure 17B is a cross-sectional view of a contact structure in a closed-loop region in some embodiments. Figure 18 is a cross-sectional view of a contact structure in some embodiments. Figure 19 is a flowchart of a method for manufacturing a contact structure in some embodiments. Figures 20A to 20D are cross-sectional views of contact structures at various manufacturing stages in some embodiments. Figure 21A is a cross-sectional view of a contact structure in a circuit region in some embodiments. Figure 21B is a cross-sectional view of a contact structure in a closed-loop region in some embodiments. Figure 22 is a cross-sectional view of a contact structure in some embodiments. Figure 23 is a flowchart of a method for manufacturing a contact structure in some embodiments. Figures 24A to 24D are cross-sectional views of contact structures at various manufacturing stages in some embodiments. Figure 25A is a cross-sectional view of a contact structure in a circuit region in some embodiments. Figure 25B is a cross-sectional view of a contact structure in a closed-loop region in some embodiments. Figure 26 is a cross-sectional view of a contact structure in some embodiments. Figure 27 is a cross-sectional view of a contact structure in some embodiments. Figure 28 is a flowchart of a method for manufacturing a contact structure in some embodiments. Figures 29A to 29C are cross-sectional views of contact structures at various manufacturing stages in some embodiments.Figure 30 is a cross-sectional view of the contact structure in some embodiments. Figure 31 is a cross-sectional view of the contact structure in some embodiments. Figure 32 is a cross-sectional view of the contact structure in some embodiments. Figure 33 is a cross-sectional view of the contact structure in some embodiments. Figure 34 is a flowchart of a method for manufacturing a contact structure in some embodiments. Figures 35A to 35D are cross-sectional views of the contact structure at various manufacturing stages in some embodiments. Figure 36A is a cross-sectional view of the contact structure in a circuit region in some embodiments. Figure 36B is a cross-sectional view of the contact structure in a closed-loop region in some embodiments.

Claims

1. A semiconductor device, comprising: An insulating layer having a through-hole opening and a conductive line opening; A through hole, located in the opening of the through hole, wherein the through hole includes a first conductive material; and a conductive line located in the opening of the conductive line, wherein the conductive line includes: a first pad layer, wherein a first thickness of the first pad layer on the through hole is less than a second thickness of the first pad layer on the insulating layer; a second pad layer located on the first pad layer and the through hole, wherein a portion of the sidewall of the second pad layer is substantially aligned with the sidewall of the through hole, and the material of the second pad layer is the same as the material of the through hole; and a conductive filler layer including a second conductive material, wherein the second conductive material is different from the first conductive material.

2. The semiconductor device as claimed in claim 1, wherein the first conductive material is in direct contact with the insulating layer.

3. A semiconductor device, comprising: An insulating layer having a through-hole opening and a conductive line opening; A through hole is located in the opening of the through hole, wherein the through hole includes a first conductive material; and a conductive line located in the opening of the conductive line, wherein the conductive line includes: a first pad layer having a variable thickness; a second pad layer located on the first pad layer and the through hole, wherein a portion of the sidewall of the second pad layer is substantially aligned with the sidewall of the through hole, and the material of the second pad layer is the same as the material of the through hole; and a conductive fill layer including a second conductive material, wherein the second conductive material is different from the first conductive material, wherein the second pad layer is located between the first pad layer and the conductive fill layer.

4. A semiconductor device, comprising: An insulating layer having a through-hole opening and a conductive line opening; A through hole, located in the opening of the through hole, wherein the through hole includes a first conductive material; and a conductive line located in the opening of the conductive line, wherein the conductive line includes: a first pad layer having a variable thickness; a second pad layer located on the first pad layer and the through hole, wherein the second pad layer has a uniform thickness, wherein a portion of the sidewall of the second pad layer is substantially aligned with the sidewall of the through hole, and the material of the second pad layer is the same as the material of the through hole; and a conductive filler layer including a second conductive material, wherein the second conductive material is different from the first conductive material.

5. A method for manufacturing a semiconductor device, comprising: An insulating layer is etched to form a first opening and a second opening; After the second opening is formed, a conductive material is deposited in the first opening; A surface conditioning deposition process is performed on the conductive material; after the surface conditioning deposition process, a first pad layer is deposited in the second opening, wherein the first pad layer extends on the conductive material and the insulating layer; a second pad layer is deposited on the first pad layer and the conductive material, wherein a portion of the sidewall of the second pad layer is substantially aligned with the sidewall of the conductive material, and the material of the second pad layer is the same as the material of the conductive material; and a conductive filler layer is deposited on the second pad layer, wherein the conductive filler layer and the conductive material comprise different materials.

6. A method for manufacturing a semiconductor device, comprising: An insulating layer is etched to form a first opening and a second opening; A surface conditioning deposition process is performed on a conductive material exposed by the first opening; After the surface conditioning deposition process, a first pad layer is deposited, wherein the first pad layer extends on the conductive material and the thickness of the first pad layer on the conductive material is less than the thickness of the first pad layer on the upper surface of the insulating layer; a second pad layer is deposited on the first pad layer and the conductive material, wherein a portion of the sidewall of the second pad layer is substantially aligned with the sidewall of the conductive material and the material of the second pad layer is the same as the material of the conductive material; and a conductive filler layer is deposited on the second pad layer, wherein the conductive filler layer comprises a material different from the conductive material.

7. A method for manufacturing a semiconductor device, comprising: An insulating layer is etched to form a first opening and a second opening; A surface conditioning deposition process is performed on a conductive material exposed at the first opening; a first backing layer is deposited after the surface conditioning deposition process, wherein the first backing layer extends from within the first opening to the second opening; a second backing layer is deposited on the first backing layer and the conductive material, wherein a portion of the sidewall of the second backing layer is substantially aligned with the sidewall of the conductive material, and the material of the second backing layer is the same as that of the conductive material; and a conductive filler layer is deposited on the second backing layer, wherein the conductive filler layer comprises a material different from the conductive material.

8. A semiconductor device, comprising: An insulating layer having a through-hole opening and a conductive line opening; A through hole, located in the opening of the through hole; and a conductive line located in the opening of the conductive line, wherein the conductive line includes: a first pad layer, wherein a first thickness of the first pad layer on the through hole is less than a second thickness of the first pad layer on the insulating layer; a second pad layer located on the first pad layer and the through hole, wherein a portion of the sidewall of the second pad layer is substantially aligned with the sidewall of the through hole, and the material of the second pad layer is the same as the material of the through hole; and a conductive fill layer, wherein the first pad layer surrounds the conductive fill layer.

9. A semiconductor device, comprising: An insulating layer having a through-hole opening and a conductive line opening; A through hole, located in the opening of the through hole, wherein the through hole includes a first conductive material; and a conductive line located in the opening of the conductive line, wherein the conductive line includes: a first pad layer having a variable thickness; a second pad layer located on the first pad layer and the through hole, wherein a portion of the sidewall of the second pad layer is substantially aligned with the sidewall of the through hole, and the material of the second pad layer is the same as the material of the through hole; and a conductive fill layer including a second conductive material, wherein the first pad layer is located between a portion of the insulating layer and the conductive fill layer in a direction perpendicular to the upper surface of the insulating layer.

10. A semiconductor device, comprising: An insulating layer having a through-hole opening and a conductive line opening; a through-hole located in the through-hole opening, wherein the through-hole opening includes a first conductive material; and a conductive line located in the opening of the conductive line, wherein the conductive line includes: a first pad layer having a variable thickness, wherein a portion of the first pad layer on the insulating layer has a uniform thickness; a second pad layer located on the first pad layer and the through hole, wherein a portion of the sidewall of the second pad layer is substantially aligned with the sidewall of the through hole, and the material of the second pad layer is the same as the material of the through hole; and a conductive filler layer including a second conductive material, wherein the second conductive material is different from the first conductive material.

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