Low dropout regulator

Abstract

A low-dropout regulator includes: a power supply voltage connection for receiving a power supply voltage; a load voltage output connection for providing a load voltage to a load; a load voltage output control circuit system including a transmission transistor configured to regulate the load voltage based on a voltage at its gate; an adaptive bias circuit system including a bias transistor configured to regulate a voltage provided to the gate of the transmission transistor based on a voltage provided to the gate of the bias transistor; and an operational transconductance amplifier (OTA) circuit system including a first OTA transistor and a second OTA transistor, wherein the gate of the first OTA transistor is configured to receive a reference voltage, and the gate of the second OTA transistor is configured to receive an indication of the load voltage. A voltage-adaptive compensation circuit system, comprising: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is coupled to a first terminal of the first compensation transistor, and wherein the first electrode of the second compensation capacitor is coupled to both a second terminal and a gate of the first compensation transistor, wherein the first terminal of the second OTA transistor is coupled to: (i) a power supply voltage connector, (ii) the first electrode of the first compensation capacitor, and (iii) the gate of a bias transistor, and wherein the second electrode of the second compensation capacitor is coupled to the first terminal of the bias transistor.

Description

Technical Field

[0001] This disclosure pertains to the field of voltage regulators, and in particular, to the field of low-dropout voltage regulators. Prior Technology

[0002] Voltage regulators can be used to provide a more stable power supply voltage. For example, a power source such as a battery can be connected to a load to power it. The power supply voltage supplied to the load can vary due to variations in the characteristics of the power source and the load. Examples of these possible variations include load impedance, temperature, the output voltage from the battery, and the length of time they have been connected. For example, the output voltage from a nearly discharged battery may be half the output voltage from the battery when it is fully charged. Voltage regulators are designed to receive the power supply voltage from the power source and supply the load voltage to the load, where the power supply voltage is intended to remain relatively constant over a period of time. It is advantageous to provide improved low-dropout regulators, where the load voltage from the regulator is more consistent than with previous low-dropout regulators, i.e., providing better load voltage regulation. Summary of the Invention

[0003] Various forms of this disclosure are proposed in the independent request and optional features are proposed in the supplementary request. The various forms of this disclosure may be provided in combination with each other, and various features of one form may be applied to other forms.

[0004] In one embodiment, a low-dropout regulator is provided, comprising: a power supply voltage connection for receiving a power supply voltage; a load voltage output connection for providing a load voltage to a load; a load voltage output control circuit system including a transmission transistor configured to regulate the load voltage based on the voltage in its gate region; an adaptive bias circuit system including: a bias transistor configured to regulate the voltage provided to the gate region of the transmission transistor based on the voltage provided to the gate region of the bias transistor; and an operational transconductance amplifier (OTA), the circuit system including a first OTA transistor and a second OTA transistor. The first OTA transistor has its gate region configured to receive a reference voltage, and the second OTA transistor has its gate region configured to receive a voltage indicating a load voltage; and an adaptive compensation circuit system includes: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is coupled to a first region of the first compensation transistor, and wherein the first electrode of the second compensation capacitor is coupled to both the second and gate regions of the first compensation transistor. The first region of the second OTA transistor is coupled to: (i) a power supply voltage connector, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of a bias transistor. The second electrode of the second compensation capacitor is coupled to the first region of the bias transistor.

[0005] The embodiments enable the provision of improved low-dropout regulators because the low-dropout regulators of this disclosure can have greater stability. That is, the low-dropout regulators of this disclosure allow the output poles (for the regulator's transfer function) to be compensated (e.g., canceled) by the zeros of the regulator. Low-dropout regulators with good phase margin across all operating conditions can be provided. Split compensation capacitors can increase this stability and allow for good phase margin without affecting the DC operating conditions of the regulator.

[0006] The first region of the transmitting transistor may be coupled to a power supply voltage connection, and the second region of the transmitting transistor may be coupled to a load voltage output connection. The regulator may further include a sensing circuit system, wherein the sensing circuit system includes a sensing transistor having a gate region coupled to the gate region of the transmitting transistor and a first region coupled to the power supply voltage connection. The sensing circuit system may include a first current mirror coupled to both the sensing transistor and the adaptive compensation circuit system. The first current mirror may include a first mirror transistor having a first region coupled to: (i) a first electrode of a second compensation capacitor, (ii) a gate region of a first compensation transistor, and (iii) a second region of the first compensation transistor. The first current mirror may include a first mirror radio transistor. The second region of the sensing transistor may be coupled to: (i) the first region of the first mirror radio transistor, (ii) the gate region of the first mirror radio transistor, and (iii) the gate region of the first mirror transistor.

[0007] The adaptive compensation circuit system may include a second compensation transistor. A first region of the first compensation transistor may be coupled to a power supply voltage connection via the second compensation transistor. The first region of the second compensation transistor may be coupled to the power supply voltage connection, and its second and gate regions are short-circuited and coupled to both the second electrode of the first compensation capacitor and the first region of the first compensation transistor. The adaptive compensation circuit system may further include a compensation resistor disposed between the second electrode of the second compensation capacitor and the first region of the bias transistor.

[0008] The gate region of the transmission transistor can be coupled to a power supply voltage connection via one or more resistors. A first region of the bias transistor can be coupled to the power supply voltage connection via the one or more resistors. The regulator may further include a resistive transistor having a gate region coupled to the gate region of the transmission transistor and first and second regions coupled to the power supply voltage connection. At least one of the first and second regions can be coupled to the power supply voltage connection via one of the one or more resistors. The gate and second region of the resistive transistor can be short-circuited. The first region of the bias transistor can be coupled to the second region of the resistive transistor.

[0009] An adaptive bias circuit system may include a current buffer. The gate region of a bias transistor may be coupled via the current buffer to a power supply voltage connection, a first electrode of a first compensation capacitor, and a first region of a second OTA transistor. The current buffer may include a first transistor having a first region coupled to: (i) the power supply voltage connection, (ii) the first electrode of the first compensation capacitor, and (iii) the first region of the second OTA transistor; and a second region coupled to the gate region of the bias transistor. The current buffer may include a second transistor having a first region coupled to both the power supply voltage connection and the first region of the first OTA transistor. The gate region of the first transistor of the current buffer may be coupled to the gate region of the second transistor of the current buffer. The second region of the second transistor of the current buffer may be coupled to the first electrode of a third compensation capacitor. The second electrode of the third compensation capacitor may be coupled to a load voltage output connection. A regulator may include a tail transistor. The second region of each of the first and second OTA regions may be coupled to the first region of the tail transistor. The gate region of the tail transistor can be configured to receive bias voltage.

[0010] The load voltage output connection may be coupled to: (i) a coupling port for connecting the regulator to a load, and (ii) a first electrode of an output capacitor. The second electrode of the output capacitor may be coupled to a reference voltage such as ground. The regulator may include a second current mirror. The second current mirror may be coupled to a current buffer and the gate region of a bias transistor. The second current mirror may also be coupled to the first electrode of a third compensation capacitor. The regulator may include a controlled current source configured to couple the power supply voltage connection to first regions of first and second OTA transistors, the first electrode of the first compensation capacitor, and the gate region of the bias transistor. The controlled current source includes: a first transistor having a first region coupled to the power supply voltage connection and a second region coupled to the first region of the first OTA transistor; and a second transistor having a first region coupled to the power supply voltage connection and a second region coupled to the first electrode of the compensation capacitor, the first region of the second OTA transistor, and the gate region of the bias transistor. The gate region of the first transistor of the controlled current source can be the gate region of the second transistor coupled to the controlled current source.

[0011] In one embodiment, a circuit including a load and a low-dropout regulator is provided. The regulator is coupled to the load and configured to regulate the load voltage supplied to the load. The regulator includes: a voltage input connection for receiving a power supply voltage; a load voltage output circuit system including a transmission transistor comprising a first region, a second region, and a gate region, wherein the second region of the transmission transistor is coupled to the load, and wherein the transmission transistor is configured to regulate the load voltage supplied to the load based on the voltage in its gate region; an adaptive bias circuit system including: a bias transistor configured to regulate the voltage supplied to the gate region of the transmission transistor based on the voltage supplied to the gate region of the bias transistor; and an operational transconductance amplifier (OTA) circuit system including a first OTA transistor. The first OTA transistor and a second OTA transistor, wherein the gate region of the first OTA transistor is configured to receive a reference voltage, and the gate region of the second OTA transistor is configured to receive a voltage indicating a load voltage; and an adaptive compensation circuit system comprising: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a compensation transistor, wherein the second electrode of the first compensation capacitor is coupled to a first region of the compensation transistor, and wherein the first electrode of the second compensation capacitor is coupled to both the second region of the compensation transistor and the gate region of the compensation transistor. The first region of the second OTA transistor is coupled to: (i) a power supply voltage connector, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of a bias transistor. The second electrode of the second compensation capacitor is coupled to the first region of the bias transistor. Simple Explanation of the Diagram

[0012] The following are some examples of the content disclosed herein, illustrated but not limited to:

[0013] Figure 1 shows a schematic circuit diagram for an exemplary low-dropout regulator.

[0014] Figure 2 shows a schematic diagram to illustrate the relationship between the different components of the exemplary low-dropout regulator.

[0015] Figure 3 shows a schematic circuit diagram for an exemplary low-dropout regulator.

[0016] In many of the accompanying drawings, similar reference numerals are used to indicate similar elements. Implementation

[0017] This document discloses an example of a low-dropout regulator, which includes an adaptive compensation circuitry to provide a variable time constant for the regulator's operation. The adaptive compensation circuitry includes first and second compensation capacitors, separated by a first compensation resistor. A first region of the first compensation transistor is coupled to the first compensation capacitor, and both the gate region and the second region of the first compensation transistor are coupled to the second compensation capacitor. The regulator of this disclosure also includes a load voltage output control circuitry for regulating the load voltage output from the regulator. An adaptive bias circuitry is included to control the operation of the voltage output control circuitry. A sensing circuitry is also included, which can act to vary the time constant of the adaptive compensation circuitry.

[0018] The load voltage output control circuit system includes a transmission transistor that varies the load voltage output from the regulator based on the voltage applied to its gate region. The adaptive bias circuit system includes a bias transistor that varies the voltage at the gate region of the transmission transistor based on the voltage applied to its own gate region. If a larger voltage is applied to the gate region of the bias transistor, more current will flow through the bias transistor and away from the transmission transistor, thereby reducing the voltage at the gate region of the transmission transistor. This, in turn, will cause more current to flow through the transmission transistor, thereby increasing the load voltage output from the regulator.

[0019] Adaptive bias circuitry systems include voltage-controlled current sources and circuitry such as transconductance operational amplifiers. The voltage-controlled current source is configured to receive a load voltage and, depending on this load voltage, controls the current flowing through it. As the load voltage increases, the current flowing through the voltage-controlled current source increases (and vice versa). The voltage-controlled current source is coupled to the gate region of a bias transistor such that the voltage at the gate region of the bias transistor depends on the current flowing through the voltage-controlled current source, and therefore on the load voltage. As more current flows through the voltage-controlled current source (in response to an increase in load voltage), the voltage applied to the gate region of the bias transistor decreases, resulting in a decrease in the voltage applied to the gate region of the transmission transistor, and consequently, a decrease in the load voltage output.

[0020] The sensing circuit system includes a configuration to control the current flowing through the adaptive compensation circuit system. The sensing circuit system includes a sensing transistor having a gate region coupled to a gate region of a transmitting transistor. Therefore, the amount of current flowing through the sensing transistor will correspond to the amount of current flowing through the transmitting transistor. The sensing circuit system is configured to vary the current flowing through the adaptive compensation circuit system based on this current flowing through the sensing transistor.

[0021] The adaptive compensation circuit system is configured to be coupled to the adaptive bias circuit system and the sensing circuit system. A first compensation capacitor is coupled to the voltage-controlled current source and the gate region of the bias transistor. A second compensation capacitor is coupled to the first region of the bias transistor. Both the second compensation capacitor and the second and gate regions of the first compensation transistor are coupled to the sensing circuit system. The operation of the sensing circuit system controls the current flowing through the adaptive compensation circuit system, which in turn affects the current flowing to the bias transistor, thereby varying the load voltage output from the regulator.

[0022] This configuration, featuring adaptive compensation circuitry that provides a variable time constant for the regulator, enables the regulator to achieve good phase margin across all operating conditions. The adaptive compensation circuitry with split capacitors provides tracking of its associated zeros without compromising the regulator's DC operation, as the regulator is constructed to provide appropriate output pole tracking using the load voltage output control circuitry and adaptive bias circuitry. Therefore, numerous embodiments can provide a more stable low-dropout regulator. [Detailed description]

[0023] An example of a low-dropout regulator will now be described with reference to Figure 1. The functionality and operation of this low-dropout regulator will then be described with reference to Figure 2, and additional and alternative features of this low-dropout regulator will be described later with reference to Figure 3.

[0024] Figure 1 shows a low-dropout regulator 100. The regulator 100 includes an adaptive compensation circuit system 130, which includes a first compensation capacitor 131, a second compensation capacitor 132, a first compensation transistor 133, a compensation resistor 134, and a second compensation transistor 135.

[0025] The voltage regulator 100 includes a power supply voltage connector 101 for receiving a power supply voltage VDD. The voltage regulator 100 also includes a load voltage output control circuitry 110, which includes a load voltage output connector 112, a transmission transistor 111, a third compensation capacitor 113, an output capacitor 114, and a load coupling port 115. A load 116 is also shown in Figure 1. The voltage regulator 100 also includes a first resistor 170.

[0026] The voltage regulator 100 includes a sensing circuit system 140, which includes a sensing transistor 141 and a first current mirror 145. The first current mirror 145 includes a first mirror transistor 146 and a first mirror radio transistor 147.

[0027] The regulator 100 includes an adaptive bias circuit system. The adaptive bias circuit system includes a voltage-controlled current source, shown as an operational transconductance amplifier ('OTA') circuit system 120. The OTA circuit system 120 includes a first OTA transistor 121, a second OTA transistor 122, and a tail transistor 125. The adaptive bias circuit system also includes a bias transistor 150 and a current buffer 160. The current buffer 160 includes a first transistor 161 and a second transistor 162. The adaptive bias circuit system also includes a second current mirror 180, which includes a second mirror transistor 181 and a second mirror radio transistor 182. The adaptive bias circuit system also includes a controlled current source 190, which includes a first transistor 191 and a second transistor 192.

[0028] In the voltage regulator 100 of Figure 1, each transistor is a field-effect transistor, such as a metal-oxide-semiconductor (MOS) field-effect transistor. All transistors in Figure 1 have source connectors (indicated by arrows) for connection to the source region of the transistor, drain connectors for connection to the drain region of the transistor, and gate connectors (between the source and drain connectors) for connection to the gate region of the transistor. The N-channel transistor system of Figure 1 shows arrows guiding the source connectors away from their gate regions, and the P-channel transistor system of Figure 1 shows arrows guiding the source connectors towards their gate regions. Connectors between conductors are indicated by black circles.

[0029] In the circuit shown in Figure 1, voltages are supplied to three regions of the circuit. These three voltages are the power supply voltage VDD, the reference voltage Vref, and the bias voltage VNbias. The power supply voltage VDD can be received from a DC power source, such as a battery. The power supply voltage VDD is supplied to components of the circuit via power supply voltage connector 101, which is coupled to the source regions of the first resistor 170 and the following: the first and second transistors 191 and 192 of the controlled current source 190, the second compensation transistor 135, the sensing transistor 141, and the transmission transistor 111. The gate connector of the first OTA transistor 121 is configured to receive the reference voltage. The gate connector of the tail transistor 125 is configured to receive the bias voltage.

[0030] The first OTA transistor 121 and the second OTA transistor 122 are N-channel transistors. The drain region of each of the first and second OTA transistors is coupled to the power supply voltage connector 101 via one of the controlled current source transistors 191 and 192, respectively. The source region of the first OTA transistor 121 is coupled to the source region of the second OTA transistor 122. The connector between the source regions of the two OTA transistors is coupled to the drain region of the tail transistor 125. The source region of the tail transistor 125 is coupled to ground.

[0031] The first OTA transistor 121 is coupled to the power supply voltage connector 101 via the first transistor 191 of the controlled current source 190. The drain region of the first OTA transistor 121 is coupled to the drain region of the first transistor 191 of the controlled current source 190. Both the first transistor 191 and the second transistor 192 of the controlled current source 190 are P-channel transistors. The source region of the first transistor 191 of the controlled current source 190 is coupled to the power supply voltage connector 101, and the source region of the second transistor 192 of the controlled current source 190 is also coupled to the gate region of the first transistor 191 of the controlled current source 190. The gate region of the first transistor 191 of the controlled current source 190 is coupled to the gate region of the second transistor 192 of the controlled current source 190. The second OTA transistor 122 is coupled to the power supply voltage connector 101 of the controlled current source 190 via the second transistor 192 of the controlled current source 190. The drain region of the second OTA transistor 122 is coupled to the drain region of the second transistor 192 of the controlled current source 190.

[0032] The first transistor 191 of the controlled current source 190 is also coupled to the current buffer 160. Specifically, the drain region of the first transistor 191 of the controlled current source 190 is coupled to the source region of the second transistor 162 of the current buffer 160. Both the first transistor 161 and the second transistor 162 of the current buffer 160 are P-channel transistors. When the first transistor 191 of the controlled current source 190 is also coupled to the first OTA transistor 121, the connector between the first OTA transistor 121 and the first transistor 191 of the controlled current source 190 is coupled to the second transistor 162 of the current buffer 160. In other words, there is a conduction path from the drain region of the first transistor 191 of the controlled current source 190, which is divided between a path to the drain region of the first OTA transistor 121 and a path to the source region of the second transistor 162 of the current buffer.

[0033] The second transistor 192 of the controlled current source 190 is also coupled to each of the current buffer 160, the compensation circuit system 130, and the OTA circuit system 120. Specifically, the drain region of the second transistor 192 of the controlled current source 190 is coupled to the first electrode of the first compensation capacitor 131, the source region of the first transistor 161 of the current buffer 160, and the drain region of the second OTA transistor 122. In other words, there is a conduction path from the drain region of the second transistor 192 of the controlled current source 190, which is divided into a first path to the first electrode of the first compensation capacitor 131, a second path to the drain region of the second OTA transistor 122, and a third path to the source region of the first transistor 161 of the current buffer 160.

[0034] The first transistor 161 of the current buffer 160 is also coupled to each of the bias transistor 150 and the second current mirror 180. Specifically, the drain region of the first transistor 161 of the current buffer 160 is coupled to both the drain region of the second mirror transistor 181 and the gate region of the bias transistor 150. Both the second mirror transistor 181 and the second mirror transistor 182 are N-channel transistors. The bias transistor 150 is an N-channel transistor.

[0035] The second transistor 162 of the current buffer 160 is also coupled to each of the third compensation capacitor 113 and the second current mirror 180. Specifically, the drain region of the second transistor 162 of the current buffer 160 is coupled to both the first electrode of the third compensation capacitor 113 and the drain region of the second mirror radio transistor 182 of the second current mirror 180. The gate and drain regions of the second mirror radio transistor 182 are short-circuited in a diode-connected manner. The gate regions of the second mirror radio transistor 182 and the gate regions of the second mirror radio transistor 181 are also interconnected. Therefore, there is a connection between the second transistor 162 of the current buffer 160, the third compensation capacitor 113, the gate and drain regions of the second mirror radio transistor 182, and the gate region of the second mirror radio transistor 181. The source regions of each of the second mirror radio transistor 182 and the second mirror radio transistor 181 are respectively coupled to ground.

[0036] The adaptive compensation circuit system 130 is coupled to the power supply voltage connector 101. Specifically, the source region of the second compensation transistor 135 is coupled to the power supply voltage connector 101. The second compensation transistor 135 includes a P-channel transistor with its gate region short-circuited to its drain region. The second electrode of the first compensation capacitor 131 is coupled to the connector between the gate and drain regions of the second compensation transistor 135. The first compensation transistor 133 includes a P-channel transistor. The drain and gate regions of the second compensation transistor 135 and the second electrode of the first compensation capacitor 131 are coupled to the source region of the first compensation transistor 133. The gate and drain regions of the first compensation transistor 133 are coupled to each other (e.g., they are diode-coupled). The second and gate regions of the first compensation transistor 133 are also coupled to the first electrode of the second compensation capacitor 132. Therefore, the first and second compensation capacitors actually represent a combined compensation capacitor spanning the first compensation transistor 133.

[0037] The gate and drain regions of the first compensation transistor 133 are also coupled to the drain region of the first mirror transistor 146. The first mirror transistor 146 and the first mirror radio transistor 147 of the first current mirror 145 are both N-channel transistors. The second electrode of the second compensation capacitor 132 is coupled to the compensation resistor 134.

[0038] The bias transistor 150 is coupled to the power supply voltage connector 101 via a first resistor 170. Specifically, the drain region of the bias transistor 150 is coupled to each of the compensation resistor 134, the gate region of the sensing transistor 141, the gate region of the transmission transistor 111, and the first resistor 170. Both the transmission transistor 111 and the sensing transistor 141 are P-channel transistors, and for example, they may be identical (e.g., they may have the same width-to-length ratio). The power supply voltage connector 101 is coupled to the gate regions of the transmission transistor 111 and the sensing transistor 141 via the first resistor 170. In other words, there is a conduction path from the power supply voltage connector 101 through the first resistor 170, where this path is divided into paths leading to the respective gate regions of each of the sensing transistor 141 and the transmission transistor 111, and a path leading to the drain region of the bias transistor 150 and the compensation resistor 134. The source region of the bias transistor 150 is coupled to the ground.

[0039] The source region of sensing transistor 141 is coupled to power supply voltage connector 101. The gate region of sensing transistor 141 is coupled to the gate region of transmission transistor 111. Sensing transistor 141 is coupled to first current mirror 145. The drain region of sensing transistor 141 is coupled to the drain and gate regions of first mirror radio transistor 147 of first current mirror 145 (the gate and drain regions of first mirror radio transistor 147 are diode short-circuited). The gate region of first mirror radio transistor 147 and first mirror transistor 146 are interconnected. The source region of each of first mirror radio transistor 147 and first mirror transistor 146 is coupled to ground.

[0040] The source region of the transmission transistor 111 is coupled to the power supply voltage connection 101. The drain region of the transmission transistor 111 is also coupled to the load output voltage connection. The load voltage output connection 112 is coupled to the second electrode of the third compensation capacitor 113, the first electrode of the output capacitor 114, and the load 116. The output capacitor 114 is connected in parallel with the load 116. The voltage output connection 112 is coupled to the load 116 via a coupling port 115. The second electrode of the output capacitor 114 is coupled to ground. In the example shown in FIG1, the second electrode of the output capacitor 114 is coupled to the output from the load 116, and the connection between the two is coupled to ground. Although not explicitly shown in FIG1, a coupling is provided between the gate region of the second OTA transistor 122 and the load voltage output connection 112 for the second OTA transistor 122 to receive the load voltage or its indication.

[0041] The controlled current source 190 is configured to receive a power supply voltage VDD and provide a controlled current output. Transistors 191 and 192 of the controlled current source 190 are gate-coupled to provide a consistent current output. The two transistors of the controlled current source 190 can be identical, such that the current output from the drain region of each transistor is the same. The regulator 100 is configured to allow the current output from the first transistor 191 of the controlled current source 190 to flow to each of the first OTA transistor 121 and the second transistor 162 of the current buffer 160. The regulator 100 is configured to allow the current output from the second transistor 192 of the controlled current source 190 to flow to each of the first compensation capacitor 131, the second OTA transistor 122, and the first transistor 161 of the current buffer 160.

[0042] The reference voltage applied to the first OTA transistor 121 can be constant, for example, so that the amount of current drawn by the first OTA transistor 121 remains constant. The first OTA resistor is configured to draw a certain amount of current through its drain region, which is proportional to the reference voltage applied to its gate region. Similarly, the second OTA resistor is configured to draw a certain amount of current through its drain region, which is proportional to the voltage applied to its gate region, i.e., proportional to the load voltage. The second OTA resistor is configured to draw more current through its gate region when the load voltage increases, and less current when the load voltage decreases. Therefore, the regulator 100 is configured such that the current flow between the second transistor 192 of the controlled current source 190 and the first electrode of the first compensation capacitor 131 and the second transistor 162 of the current buffer 160 will vary depending on the load voltage. In particular, the regulator 100 is configured such that the current flowing from the second transistor 192 of the controlled current source 190 to the gate region of the bias transistor 150 will vary depending on the current flowing through the second OTA transistor 122 (and therefore depend on the load voltage). The tail transistor 125 can, for example, receive a constant bias voltage to provide a consistent current output (to ground).

[0043] The current buffer 160 is configured as a common-gate current buffer 160 (the gates of the two transistors of the current buffer 160 are mutually coupled). The current buffer 160 is configured to suppress the operation of components coupled to the output of the current buffer 160 (e.g., the second current mirror 180, the third compensation capacitor 113, and / or the bias transistor 150) from interfering with the operation of components coupled to the input of the current buffer 160 (e.g., preventing this output from loading this input). Therefore, the current buffer 160 can be configured to suppress the current flowing to the third compensation capacitor 113 / bias transistor 150 from interfering with the current flowing to the first OTA transistor 121 / second OTA transistor 122.

[0044] The voltage at the gate region of the bias transistor 150 will depend on the amount of current drawn through the second OTA transistor 122. In other words, the regulator 100 is configured such that the voltage at the gate region of the bias transistor 150 will vary depending on the load voltage. For example, the regulator 100 is configured such that when the load voltage increases, the voltage supplied to the gate region of the bias transistor 150 will decrease, and when the load voltage decreases, the voltage supplied to the gate region of the bias transistor 150 will increase.

[0045] A second current mirror 180 is constructed such that the output current from the second mirror transistor 181 (e.g., from its source region) corresponds to the output current from the second mirror radio transistor 182. For example, the two transistors of the second current mirror 180 can be identical (e.g., they can have the same width-to-length ratio). Therefore, the amount of current directed from the first transistor 161 of the current buffer 160 toward the gate region of the bias transistor 150 will also depend on the amount of current flowing through the second mirror radio transistor 182. This is because the amount of current flowing from the first transistor 161 of the current buffer 160 to the second mirror transistor 181 will correspond to the amount of current flowing through the second mirror radio transistor 182. The amount of current flowing through the second mirror radio transistor 182 will also depend on the amount of current flowing to / from the first electrode of the third compensation capacitor 113.

[0046] The second compensation transistor 135 is configured to provide a unidirectional conduction path from the power supply voltage connector 101 to the source region of the first compensation transistor 133 and the second electrode of the first compensation capacitor 131. An adaptive compensation circuit system 130 is configured such that the current supplied to the source region of the first compensation transistor 133 varies depending on the power supply voltage VDD and the charge on the first compensation capacitor 131. For example, when the first compensation capacitor 131 is positively charging, i.e., its first electrode is accumulating negative charge, the current flowing to the first compensation transistor 133 may increase, and / or when the first compensation capacitor 131 is positively discharging, the current flowing to the first compensation transistor 133 may decrease.

[0047] The first compensation transistor 133 is configured to provide a conduction path to each of the second compensation capacitor 132 and the first mirror transistor 146 of the first current mirror 145. The second compensation capacitor 132 is configured to charge / discharge depending on the operating state of the mirror transistor. When the current flowing through the first mirror transistor 146 increases, the second compensation capacitor 132 will charge at a slower rate or begin to charge / discharge at a faster rate because more current will be drawn to the first mirror transistor 146 rather than to the first electrode of the second compensation capacitor 132. When the current flowing through the first mirror transistor 146 decreases, the first electrode of the second compensation capacitor 132 will accumulate more charge or lose charge at a slower rate. The magnitude and direction of the current flowing through the compensation resistor 134 will depend on the state of the second compensation capacitor 132, and therefore on the operating state of the first mirror transistor 146.

[0048] The compensation circuit system 130 is configured to provide discrete capacitors. The compensation circuit system 130 is configured such that the discrete capacitors are effectively connected in series without affecting the DC operating conditions of the regulator 100. The compensation circuit system 130 is configured to compensate for the output poles (wp2) of the regulator's transfer function with the zeros (wz2) of the regulator's transfer function. The compensation circuit system 130 can be configured to provide a variable time constant.

[0049] The first resistor 170 is configured to provide a voltage drop between the power supply voltage VDD and the voltage supplied to the gate region of each of the sensing transistor 141 and the transmission transistor 111.

[0050] Sensing circuitry 140 is configured to regulate the current flowing from the first plate of the first compensation transistor 133 and the second compensation capacitor 132 away from the first current mirror 145. Sensing transistor 141 is configured to control the current flowing from the power supply voltage connection 101 through the first current mirror 145 based on the voltage applied to its gate region. Sensing transistor 141 is configured such that when the voltage applied to its gate region increases, the current flowing through sensing transistor 141 to the first current mirror 145 decreases, and when the voltage applied to its gate region decreases, the current flow increases. Sensing transistor 141 is configured to receive the power supply voltage VDD (e.g., at its source connection) and selectively conduct current based on the voltage in its gate region. Sensing transistor 141 provides a selective conduction path between the power supply voltage connection 101 and the first current mirror 145.

[0051] A first current mirror 145 is configured such that the current flow from the first mirror transistor 146 corresponds to the current flow from the first mirror radio transistor 147. The first mirror transistor 146 may be identical to the first mirror radio transistor 147 (e.g., having the same width-to-length ratio), and the current from each may be exactly the same. The first mirror radio transistor 147 is short-circuited by a diode such that the current from the sensing transistor 141 to the first current mirror 145 flows through the first mirror radio transistor 147 to ground. Then, the corresponding (or identical, if the two transistor systems are identical) current will flow out through the first mirror transistor 146. The current flow through the first mirror transistor 146 is configured to reflect the current from the sensing transistor 141; for example, if the current flowing through the sensing transistor 141 increases, the current flowing through the first mirror transistor 146 will also increase. The first mirror transistor 146 is configured, for example, to draw this current from the first compensation transistor 133, such that when the current flowing through the sensing transistor 141 increases, more current is drawn from the drain region of the first compensation transistor 133 (and optionally from the first electrode of the second compensation capacitor 132, or less current may be delivered from the first compensation transistor 133 to the first electrode).

[0052] The voltage regulator 100 is configured such that the current flow away from the first plate of the first compensation transistor 133 and the second compensation capacitor 132 depends on the voltage applied to the gate region of the sensing transistor 141. The voltage applied to the gate region of the sensing transistor 141 will correspond to the voltage applied to the gate region of the transmission transistor 111 (e.g., it may be the same as the voltage applied to the gate region of the transmission transistor 111). The voltage regulator 100 is configured such that the voltage applied to these gate regions depends on the operating state of the adaptive compensation circuit system 130 and the operating state of the bias transistor 150. Current may flow toward or away from this connection to the adaptive compensation circuit system 130. The magnitude and direction of this current flow will vary depending on the state of the second compensation capacitor 132 (e.g., whether it is charging, charged, or discharging), which may vary depending on the magnitude of the current flow through the first mirror transistor 146.

[0053] The magnitude of the current flowing through the bias transistor 150 will vary depending on the voltage applied to its gate region. The regulator 100 is configured such that the outputs from both the sensing and transmission transistors will vary depending on the voltage applied to the gate region of the bias transistor 150. The voltage applied to the gate region of the bias transistor 150 will depend on the operation of the second OTA transistor 122 (how much current it draws), and this operation of the second OTA transistor 122 will vary depending on the load voltage. Therefore, the regulator 100 is configured to regulate the output of the transmission transistor 111 (and thus regulate the load voltage) based on the load voltage. For example, the regulator 100 is configured such that as the load voltage increases, or begins to increase, this increase causes less current to flow through the transmission transistor 111, and thus causes a decrease in the load voltage (or prevents it from increasing). Similarly, when the load voltage decreases, or begins to decrease, this decrease causes more current to flow through the transmission transistor 111, and thus causes an increase in the load voltage (or prevents it from decreasing).

[0054] Transmission transistor 111 provides a selective conduction path between power supply voltage connection 101 and load voltage output connection 112. The conduction along this path from power supply voltage connection 101 to load voltage output connection 112 will vary depending on the voltage in the gate region of transmission transistor 111 (and therefore depends on the operating state of bias transistor 150 and / or adaptive compensation circuitry 130). When the voltage in the gate region of transmission transistor 111 increases, transmission transistor 111 will draw less current, and when the voltage in the gate region decreases, transmission transistor 111 will draw more current.

[0055] Load coupling port 115 is configured to provide coupling for load 116. In some examples, load 116 may be included as part of a regulator circuit system, in which case load coupling port 115 may effectively include a conductor coupled to the input for load 116. In other examples, load 116 may be a separate component to the regulator circuit system, in which case coupling port 115 may include an electrical coupling element to allow load 116 to be coupled to regulator 100 to receive load voltage from it. Load coupling port 115 is configured to deliver load voltage to load 116. Load voltage output control circuitry 70 is configured to provide the regulated load voltage to load 116. The charge on the second electrode of the third compensation capacitor 113 (and therefore the current flowing to / from the second electrode) will vary depending on the charge provided to the first electrode of the third compensation capacitor 113.

[0056] In the context of this disclosure, it will be understood that the characteristics of regulator 100 can be selected to provide a selected value for the load voltage. For example, transistors, resistors, and / or capacitors of this circuit can be selected to provide relevant operating characteristics that give the load voltage their expected value. The capacitance values ​​for more than one capacitor can be selected based on the desired pole compensation of the capacitors. For example, the capacitance values ​​for each of the first and second compensation capacitors and the third compensation capacitor 113 (and the resistance for the compensation resistor 134) can be selected to provide stability for regulator 100 over the load current range.

[0057] The functionality of the exemplary voltage regulator 100 will now be described with reference to Figure 2.

[0058] Figure 2 shows a block diagram illustrating the functional relationships between the different components of the voltage regulator 100. For each component shown in Figure 2, an arrow originating from (e.g., away from) the component indicates an output. An arrow entering the component indicates an input, for example, indicating that the output of the component leading this arrow can be affected by this input.

[0059] Figure 2 illustrates the adaptive bias circuit system ('ABC' – for example, when provided by the OTA circuit system 120, bias transistor 150, current buffer 160, second current mirror 180 and controlled current source 190 of the regulator 100 of Figure 1), the adaptive compensation circuit system ('ACC' – for example, when provided by the compensation circuit system 130 of the regulator 100 of Figure 1), the load voltage output control circuit system ('LVOCC' – for example, when provided by the output control circuit system 110 and first resistor 170 of the regulator 100 of Figure 1), and the sensing circuit system ('SC' – for example, when provided by the sensing circuit system 140 and first resistor 170 of the regulator 100 of Figure 1).

[0060] Although not shown in Figure 2, a power supply voltage VDD is provided to the components shown in Figure 2 (e.g., when provided by the power supply voltage connector 101 of the regulator 100 of Figure 1). This power supply voltage VDD can be provided to each of ABC, ACC, LVOCC, and SC. The operation of each of these components will depend at least in part on the power supply voltage. Furthermore, it will be understood that the operation of each of these components will also depend on the operation of the other components of the regulator 100.

[0061] The ABC (especially the OTA circuit system 120) also receives the load voltage as input. The output from the OTA circuit system (the current flow through the second OTA transistor 122) will depend on the load voltage it receives, and therefore the operation of the ABC will depend on the load voltage. This operation of the ABC will affect the current flow to / from the first compensation capacitor 131 of the ACC (as indicated by the arrows in Figure 2). Furthermore, the current flow through the second OTA transistor 132 of the ABC will affect the voltage applied to the gate region of the bias transistor 150 of the ABC. The voltage applied to the gate region of the bias transistor 150 will affect the current flow to / from the compensation resistor 134 (as indicated by the arrows in Figure 2). The voltage applied to the gate region of the bias transistor 150 will also affect the operation of the SC and LVOCC (as indicated by the two arrows in Figure 2). This is because the voltage applied to the gate region of the bias transistor 150 will affect the voltage applied to the gate region of the sensing transistor 141 of the SC 140 and the voltage applied to the gate region of the transmission transistor 111 of the LVOCC 110.

[0062] In particular, if the load voltage increases, the second OTA transistor 122 of ABC will draw more current. Less current will be directed toward the first compensation capacitor 131, and the gate voltage for the bias transistor 150 will decrease. In turn, this will reduce the current flow through the bias transistor 150, and thus increase the voltage applied to the gate region of each of the sensing transistor 141 and the transmission transistor 111.

[0063] The operation of SC will affect the operation of ACC. In particular, SC will affect the amount of current flowing away from the first compensation transistor 133 and the second compensation capacitor 132 (as indicated by the arrows shown in Figure 2). When more current flows through the sensing transistor 141 of SC (e.g., in response to a reduction in the gate voltage used by the sensing transistor 141), SC will cause more current to flow away from the first compensation transistor 133 and the second compensation capacitor 132. In turn, this will affect the current flowing through the compensation resistor 134 to / from the second electrode of the second compensation capacitor 132 (and thus also affect the voltage supplied to the gate regions of each of the sensing transistor 141 and the transmission transistor 111). Therefore, the operation of SC will affect the operation of LVOCC (as indicated by the arrows in Figure 2).

[0064] Therefore, the operation of SC will affect the current flow away from the drain region of the first compensation transistor 133. The operation of ABC will affect the current flow to / from the first compensation capacitor 131 and the compensation resistor 134. Based on these inputs to ACC, the charge stored in the two capacitors will vary. These two capacitors act as if connected in series, and therefore the total capacitance associated with ACC will be the capacitance of the two capacitors connected in series. The first compensation transistor 133 acts to provide a variable resistance depending on the operation of the second compensation capacitor 132. The voltage associated with ACC will then affect the voltage applied to the gate regions of each of the sensing transistor 141 and the transmitting transistor 111.

[0065] To further illustrate the functionality of the voltage regulator 100, several examples of its operation will now be described with reference to Figure 1. In the context of this disclosure, it should be understood that the low-dropout voltage regulator 100 is self-regulating. The following operational examples are described as a series of events, but it will be understood that in reality, these events occur simultaneously when the voltage regulator 100 is self-regulating.

[0066] Regulator 100 is constructed to provide a consistent voltage output. Therefore, examples of how regulator 100 responds to increases and decreases in the load voltage output will be described. These examples refer to changes in VDD causing an increase / decrease in the output voltage. It will be understood that there are multiple connections up to the power supply voltage connection 101. Therefore, an increase or decrease in the power supply voltage VDD will simultaneously affect many different components. However, for simplicity, the following description is written in chronological order, as this should help explain how self-regulation occurs. It will also be understood that other causes may exist for increases / decreases in the output voltage, such as those dependent on the load current drawn by the load.

[0067] In the event of an increase in the power supply voltage VDD, the voltage supplied to the source regions of each of the transmission transistor 111 and the sensing transistor 141 will also increase. The voltage supplied to the first resistor 170 will also increase, and the corresponding voltage drop across the first resistor 170 will also increase. Conversely, the increase in the voltage at the source regions of each of the sensing transistor 141 and the transmission transistor 111 will be greater than the increase in the voltage at the respective gate regions of each of the sensing transistor 141 and the transmission transistor 111. Therefore, the gate-source voltage for each of the transmission transistor 111 and the sensing transistor 141 will increase negatively, and the output from each transistor will increase. This will cause an increase in the load voltage, and thus an increase in the gate voltage for the second OTA transistor 122. As a result, the current flowing through the second OTA transistor 122 will increase, causing a voltage drop in the gate region of the bias transistor 150. Then, less current will flow through the bias transistor 150, thus causing the voltage in the gate region of each of the transmission transistor 111 and the sensing transistor 141 to increase relative to their respective source voltage, thereby reducing the load voltage (e.g., returning it to its desired value).

[0068] It will also be understood that during this voltage regulation period, the sensing circuit system 140 (including the first current mirror 145), the second current mirror 180, and the adaptive compensation circuit system 130 can also function to compensate for the operation of the regulator 100. The output from the sensing transistor 141 will correspond to the output from the transmission transistor 111. Thus, the first current mirror 145 will output a larger current, and therefore draw more current away from the drain region of the first compensation transistor 133 and the first electrode of the second compensation capacitor 132. This can cause the second compensation capacitor 132 to discharge, and in turn affect the voltage supplied to the gate regions of the sensing transistor 141 and the transmission transistor 111. In response to a larger VDD, the second compensation transistor 135 and / or the first compensation capacitor 131 can be operated to provide a larger input to the first compensation transistor 133. The operation of the third compensation capacitor 113 can also affect the current flow through the second mirror transistor 182. Conversely, this will also affect the current flow through the second mirror transistor 181, and thus affect the voltage in the gate region of the bias transistor 150.

[0069] When the supply voltage VDD decreases, the solution is the opposite of the above. That is, the load voltage can decrease, which in turn will cause a decrease in the current flowing through the second OTA transistor 122. Therefore, the voltage in the gate region of the bias transistor 150 will be higher, and more current will flow through the bias transistor 150. In turn, this will cause a decrease in the gate voltage of the sensing and transmission transistor relative to its source voltage, and thus an increase in the load voltage.

[0070] The embodiments provide improved low-dropout regulators. In particular, the embodiments provide low-dropout regulators with improved stability (e.g., good phase margin across all operating conditions). This is evident from the poles and zeros used in the regulator. In particular, the output pole (wp2) can be compensated for by the zero (wz2). For example, the equations for wp2 and wz2 can be derived as follows: ,and Here

[0071] From equation wp2 above, gmL varies with the load current, while in equation wz2, gmMPC varies with the load, and all other parameters are constant with the load current in both equations. Therefore, by controlling CC2, And RC, as in the aforementioned regulator 100, the regulator 100 can be stable over the entire load current range. By segmenting the compensation capacitors to achieve this (CC1_1 and CC1_2), the DC operating conditions of the regulator 100 can be unaffected while still providing this increased stability. Providing a current buffer 160 suppresses the presence of a feedforward path, which allows the zero point to transition from a right-half-plane zero to a left-half-plane zero (e.g., to facilitate pole removal). Furthermore, or alternatively, the inclusion of the first compensation transistor 133 facilitates this transition to a left-half-plane zero.

[0072] The additional and / or alternative features for low-dropout regulators will now be described with reference to Figure 3.

[0073] The configuration in Figure 3 is similar to that in Figure 1, and similar reference numerals indicate similar components, which will not be described further. Instead, the following description will focus on the features of the configuration in Figure 3 that differ from those of the regulator 100 in Figure 1.

[0074] Figure 3 shows a voltage regulator 300. In addition to the components described above for the voltage regulator 100 of Figure 1, the voltage regulator 300 of Figure 3 includes a resistor assembly 370, comprising a drain resistor 371, a source resistor 372, and a resistive transistor 373. The voltage regulator 300 in Figure 3 also shows a second current mirror assembly 380 and a load voltage output control circuit system 310, which differ from the voltage regulator 100 of Figure 1. The current mirror assembly 380 includes a first transistor 381, a second transistor 382, ​​a third transistor 383, and a fourth transistor 384. The output control circuit system includes a first output resistor 3171, a second output resistor 3172, a third output resistor 3181, a first output transistor 3182, a current source 3191, and a second output transistor 3192.

[0075] Resistor assembly 370 is configured to replace the first resistor 170 from regulator 100 of FIG. 1. Resistor transistor 373 is coupled to each of power supply voltage connector 301, sensing transistor 341, transmission transistor 311, adaptive compensation circuit system 330, and bias transistor 350. Resistor transistor 373 is a P-channel transistor. The gate region of resistor transistor 373 is coupled to the gate region of sensing transistor 341 and the gate region of transmission transistor 311. The source region of resistor transistor 373 is coupled to power supply voltage connector 301. The drain region of resistor transistor 373 is coupled to compensation resistor 334 (and therefore the second electrode of second compensation capacitor 332) and the drain region of bias transistor 350. Furthermore, the drain region of resistor transistor 373 is also coupled to power supply voltage connector 301. The source region of the resistive transistor 373 is coupled to the power supply voltage connector 301 via the source resistor 372, and the drain region of the resistive transistor 373 is coupled to the power supply voltage connector 301 via the drain resistor 371. The drain and gate regions of the resistive transistor 373 are coupled (to provide a transistor for short-circuiting the diode).

[0076] The gate regions of the transmission transistor 311 and the sensing transistor 341 are both coupled to the power supply voltage input connector 301 via the resistive transistor 373. Specifically, the respective gate regions of the sensing and transmission transistors 341 and 311 are coupled to both the gate and drain regions of the resistive transistor 373, and the source and drain regions of the resistive transistor 373 are coupled to the power supply voltage connector. The drain region of the bias transistor 350 and the compensation resistor 334 are both coupled to both the gate and drain regions of the resistive transistor 373 (and thus coupled to the respective gate regions of the sensing transistor 341 and the transmission transistor 311).

[0077] The second current mirror assembly 380 includes two more transistors than those used in the second current mirror 180 of the regulator 100 in Figure 1. All transistors in the second current mirror assembly 380 are N-channel transistors. The second current mirror assembly 380 is coupled to the current buffer 360, the bias transistor 350, and the third compensation capacitor 313. Specifically, the drain region of the first transistor 381 of the second current mirror assembly 380 is coupled to the drain region of the second transistor 362 of the current buffer 360 and the first electrode of the third compensation capacitor 313. The drain region of the second transistor 382 of the second current mirror assembly 380 is coupled to the drain region of the first transistor 361 of the current buffer 360 and to the gate region of the bias transistor 350. The drain region of the second transistor 382 of the second current mirror assembly 380 may also be coupled to the gate region of the second output transistor 3192 (as shown in Figure 3).

[0078] The gate region of the first transistor 381 of the second current mirror assembly 380 is coupled to the gate region of the second transistor 382 of the second current mirror assembly 380. The source region of the first transistor 381 of the second current mirror assembly 380 is coupled to the drain region of the third transistor 383 of the second current mirror assembly 380. The source region of the second transistor 382 of the second current mirror assembly 380 is coupled to the drain region of the fourth transistor 384 of the second current mirror assembly 380. The gate region of the third transistor 383 of the second current mirror assembly 380 is coupled to the gate region of the fourth transistor 384 of the second current mirror assembly 380. The gate regions of the first and second transistors 381 and 382 of the second current mirror assembly 380 are also coupled to the drain region of the first transistor 381 of the second current mirror assembly 380. The drain region of the first transistor 381 of the second current mirror assembly 380 can also be coupled to the respective gate regions of the third and fourth transistors 383 and 384 of the second current mirror assembly 380 (for example, the gate regions of all four transistors of the second current mirror assembly 380 can be interconnected).

[0079] The load voltage output connector 312 is coupled to the load 316 (via coupling port 315) and the output capacitor 314, which are arranged in parallel to each other. The load voltage output connector 312 is also coupled to other components of the voltage output control circuit system 310. For example, the load voltage output connector is coupled to a first output resistor 3171, and via the first output resistor 3171, to a second output resistor 3172. The load voltage output connector is coupled to a third output resistor 3181, and via the third output resistor 3181, to a first output transistor 3182. The load voltage output connector is also coupled to a current source 3191, and via the current source 3191, to a second output transistor 3192. Each of the first and second output transistors 3182 and 3192 is an N-channel transistor. The load voltage output connector is coupled to the drain region of the first output transistor 3182 via the third resistor 3181. The drain region of the second output transistor 3192 is coupled to the load voltage output connector via the current source 3191, and is also coupled to the gate region of the first output transistor 3182. The source region of each output transistor is coupled to ground.

[0080] Additionally, as can be seen in Figure 3, the load voltage output connector 312 is coupled to the gate region of the second OTA transistor 322. Specifically, a connector is provided from between the first and second output resistors 3171 to the gate region of the second OTA transistor 322. The output control circuitry 310 can be configured to scale the voltage supplied to the second OTA transistor 322, for example by providing a voltage divider, so that the voltage supplied to the second OTA transistor 322 is reduced relative to the load voltage. The amount of scaling (e.g., reduction) of the voltage supplied to the load can be selected to control the maximum variation in the operating conditions of the regulator 300, for example, limiting the maximum variation in the voltage of the gate region of the transmission transistor 311. For example, the values ​​of the first and second output resistors 3171, 3172 can be selected accordingly.

[0081] In the context of this disclosure, it should be understood that the embodiments described herein are examples of low-dropout regulators of this disclosure. However, these examples should not be considered limiting. For example, it will be understood that a particular configuration of the transistors (and their respective channel configurations) need not be considered limiting. For example, different configurations of N / P-channel transistors may be used to provide the desired functionality, and / or different (e.g., non-FET) transistors may be used. Similarly, capacitors are shown with a curve to indicate the stack on the board (e.g., the curve is on the next layer). However, other configurations for these capacitors may be used. In some examples, the sensing circuitry 140 and the feedback it enables may instead be provided by the transmission transistor 111 and the output control circuitry 70. Either way, where the load voltage is used to regulate the second OTA transistor 122, this may instead be an indication of the load voltage, for example, it may be the output from the sensing transistor 141.

[0082] Resistors have been illustrated and discussed in the examples described herein. However, in the context of this disclosure, it should be understood that one or more of these resistors may have an effective resistance of zero. For example, in Figure 3, the first resistor 3171 and the second resistor 3172 may act to scale the voltage supplied to the gate region of the second OTA transistor 322. However, one or more of these resistors may not provide a voltage drop (e.g., control scaling, or provide uniform scaling). Similarly, one or both of the drain resistor 371 and the source resistor 372 may have no resistance.

[0083] As will be understood from the above discussion, the examples shown in the figures are merely illustrative and include features that can be generalized, removed, or replaced as presented herein and in the claims. Referring generally to the figures, it will be understood that the schematic function blocks are used to indicate the functionality of the systems and devices described herein. However, it will be understood that functionality need not be divided in this way and should not be construed as implying any particular hardware structure other than that described below and in the claims. The functionality of one or more elements shown in the figures may be further subdivided and / or distributed throughout the devices disclosed herein. In some examples, the functionality of one or more elements shown in the figures may be integrated into a single functional unit.

[0084] As will be understood by a skilled reader in the context of this disclosure, each of the embodiments described herein can be implemented in many different ways. Any feature of any embodiment of this disclosure can be combined with any of the other embodiments of this disclosure. For example, a method embodiment can be combined with an apparatus embodiment, and features described in reference to the operation of specific elements of the apparatus can be provided in a method that does not use those specific types of apparatus. Furthermore, each feature in each embodiment is intended to be separable from the associated feature it describes, unless explicitly stated that certain other features are essential to its operation. Of course, each of these separable features can be combined with any other feature of the embodiment described, or with any other feature or combination of features of any other embodiment described herein. Moreover, equivalents and modifications not described above can also be employed without departing from the invention.

[0085] Other examples and variations of this disclosure will be readily apparent to a knowledgeable recipient in the context of this disclosure.

[0086] 70: Load voltage output control circuit system 100: Low dropout voltage regulator 101: Power supply voltage connector 110: Load voltage output control circuit system 111: Transmission transistor 112: Load voltage output connector 113: Third compensation capacitor 114: Output capacitor 115: Load Coupling Port 116: Load 120: OTA circuit system 121: First OTA transistor 122: Second OTA transistor 125: Tail-end transistor 130: Adaptive Compensation Circuit System 131: First compensation capacitor 132: Second compensation capacitor 133: First Compensating Transistor 134: Compensating Resistor 135: Second compensating transistor 140: Sensing circuit system 141: Sensing Transistor 145: First Current Mirror 146: First mirror transistor 147: First-class radio crystal 150: Bias transistor 160: Current buffer 161: First Transistor 162: Second transistor 170: First resistor 180: Second current mirror 181: Second mirror transistor 182: Second mirror radio crystal 190: Controlled current source 191: First Transistor 192: Second transistor 300: Voltage Regulator 301: Power supply voltage connector 310: Load voltage output control circuit system 311: Transmission transistor 312: Load voltage output connector 313: Third compensation capacitor 314: Output capacitor 315: Coupling Port 316: Load 322: Second OTA transistor 330: Adaptive Compensation Circuit System 332: Second compensation capacitor 334: Compensating Resistor 341: Sensing Transistor 350: Bias transistor 360: Current Buffer 361: First Transistor 362: Second transistor 370: Resistor assembly 371: Drain resistor 372: Source Resistor 373: Resistive Transistor 380: Second current mirror assembly 381: First Transistor 382: Second transistor 383: Third transistor 384: Fourth Transistor 3171: First output resistor 3172: Second output resistor 3181: Third output resistor 3182: First output transistor 3191: Current source 3192: Second output transistor

Claims

1. A low-dropout regulator, comprising: a power supply voltage connection for receiving a power supply voltage; a load voltage output connection for providing a load voltage to a load; a load voltage output control circuit system including a pass transistor configured to regulate the load voltage based on the voltage at its gate; and an adaptive bias circuit system including: A bias transistor configured to regulate a voltage supplied to the gate of a transmission transistor based on a voltage supplied to the gate of the bias transistor; and an operational transconductance amplifier (OTA) circuit system including a first OTA transistor and a second OTA transistor, wherein the gate of the first OTA transistor is configured to receive a reference voltage, and the gate of the second OTA transistor is configured to receive a voltage indicating the load voltage; and an adaptive compensation circuit system including: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is coupled to a first terminal of the first compensation transistor, and wherein the first electrode of the second compensation capacitor is coupled to both a second terminal and a gate of the first compensation transistor; The first end of the second OTA transistor is coupled to: (i) the power supply voltage connector, (ii) the first electrode of the first compensation capacitor, and (iii) the gate of the bias transistor; and the second electrode of the second compensation capacitor is coupled to the first end of the bias transistor.

2. The low-dropout regulator of claim 1, wherein a first terminal of the transmission transistor is coupled to the power supply voltage connector, and a second terminal of the transmission transistor is coupled to the load voltage output connector.

3. The low-dropout regulator of claim 2 further includes a sensing circuit system, wherein the sensing circuit system includes a sensing transistor, the gate of the sensing transistor is coupled to the gate of the transmission transistor, and is coupled to a first terminal of the power supply voltage connector.

4. The low-dropout regulator of claim 3, wherein the sensing circuit system includes a first current mirror coupled to both the sensing transistor and the adaptive compensation circuit system.

5. The low-dropout regulator of claim 4, wherein the first current mirror includes a first mirror transistor having a first terminal coupled to: (i) a first electrode of the second compensation capacitor, (ii) a gate of the first compensation transistor, and (iii) a second terminal of the first compensation transistor.

6. The low-dropout regulator of claim 5, wherein the first current mirror includes a first mirror radio crystal, and wherein the second terminal of the sensing crystal is coupled to: (i) a first terminal of the first mirror radio crystal, (ii) a gate of the first mirror radio crystal, and (iii) a gate of the first mirror crystal.

7. The low-dropout regulator of claim 1, wherein the adaptive compensation circuit system includes a second compensation transistor, and wherein a first terminal of the first compensation transistor is coupled to the power supply voltage connector via the second compensation transistor.

8. The low-dropout regulator of claim 7, wherein the first terminal of the second compensating transistor is coupled to the power supply voltage connector, and its second terminal and gate are short-circuited and coupled to the second electrode of the first compensating capacitor and the first terminal of the first compensating transistor.

9. The low-dropout regulator of any one of claims 1 to 8, wherein the adaptive compensation circuit system further includes a compensation resistor disposed between the second electrode of the second compensation capacitor and the first terminal of the bias transistor.

10. The low-dropout regulator of claim 1, wherein the gate of the transmission transistor is coupled to the power supply voltage connector via one or more resistors.

11. The low-dropout regulator of claim 10, wherein the first terminal of the bias transistor is coupled to the power supply voltage connector via one or more resistors.

12. The low-dropout regulator of claim 10, wherein the regulator further comprises a resistive transistor, the gate of which is coupled to the gate of the transmission transistor, and a first terminal and a second terminal of the power supply voltage connector, wherein at least one of the first terminal and the second terminal is coupled to the power supply voltage connector via one of the more than one resistor.

13. The low-dropout regulator of claim 12, wherein the gate and second terminal of the resistive transistor are short-circuited.

14. The low-dropout regulator of claim 12 or 13, wherein the first terminal of the bias transistor is coupled to the second terminal of the resistive transistor.

15. The low-dropout regulator of claim 1, wherein the adaptive bias circuit system includes a current buffer, and wherein the gate of the bias transistor is coupled via the current buffer to the power supply voltage connector, the first electrode of the first compensation capacitor, and the first terminal of the second OTA transistor.

16. The low-dropout regulator of claim 15, wherein the current buffer includes a first transistor having a first terminal coupled to: (i) the power supply voltage connector, (ii) the first electrode of the first compensation capacitor, and (iii) the first terminal of the second OTA transistor; and a second terminal coupled to the gate of the bias transistor.

17. The low-dropout regulator of claim 16, wherein the current buffer includes a second transistor having a first terminal coupled to both the power supply voltage connector and the first OTA transistor.

18. The low-dropout regulator of claim 17, wherein the gate of the first transistor of the current buffer is coupled to the gate of the second transistor of the current buffer.

19. The low-dropout regulator of claim 17, wherein the second terminal of the second transistor of the current buffer is coupled to the first electrode of the third compensation capacitor, and wherein the second electrode of the third compensation capacitor is coupled to the load voltage output connector.

20. The low-dropout regulator of claim 15, wherein the load voltage output connection is coupled to: (i) a coupling port for connecting the regulator to a load, and (ii) a first electrode of an output capacitor, for example, wherein a second electrode of the output capacitor is coupled to a reference voltage, such as ground.

21. A low-dropout regulator as claimed in any of claims 15 to 20, wherein the regulator includes a second current mirror, and wherein the second current mirror is coupled to the current buffer and the gate of the bias transistor.

22. The low-dropout regulator of claim 17 or 18, wherein the second terminal of the second transistor of the current buffer is coupled to the first electrode of the third compensation capacitor, wherein the second electrode of the third compensation capacitor is coupled to the load voltage output connector, wherein the regulator includes a second current mirror, wherein the second current mirror is coupled to the gate of the current buffer and the bias transistor, and wherein the second current mirror is also coupled to the first electrode of the third compensation capacitor.

23. The low-dropout regulator of claim 1, wherein the regulator includes a controlled current source configured to couple the power supply voltage connection to a first terminal of the first and second OTA transistors, a first electrode of the first compensation capacitor, and a gate of the bias transistor.

24. The low-dropout regulator of claim 23, wherein the controlled current source comprises: a first transistor having a first terminal coupled to the power supply voltage connector and a second terminal coupled to the first terminal of the first OTA transistor; and a second transistor having a first terminal coupled to the power supply voltage connector, the second terminal of the second transistor being coupled to a first electrode of the compensation capacitor, the first terminal of the second OTA transistor, and the gate of the bias transistor; wherein the gate of the first transistor of the controlled current source is coupled to the gate of the second transistor of the controlled current source.

25. A circuit including a load and a low-dropout regulator, wherein the regulator is coupled to the load and configured to regulate a load voltage supplied to the load; wherein the regulator includes: a voltage input connection for receiving a power supply voltage; a load voltage output circuit system including a transmission transistor having a first terminal, a second terminal, and a gate, wherein the second terminal of the transmission transistor is coupled to the load, and wherein the transmission transistor is configured to regulate the load voltage supplied to the load based on the voltage at its gate; and an adaptive bias circuit system including: A bias transistor configured to regulate a voltage supplied to the gate of a transmission transistor based on a voltage supplied to the gate of the bias transistor; and an operational transconductance amplifier (OTA) circuit system comprising a first OTA transistor and a second OTA transistor, wherein the gate of the first OTA transistor is configured to receive a reference voltage, and the gate of the second OTA transistor is configured to receive a voltage indicating the load voltage; and an adaptive compensation circuit system comprising: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a compensation transistor, wherein the second electrode of the first compensation capacitor is coupled to a first terminal of the compensation transistor, and wherein the first electrode of the second compensation capacitor is coupled to both a second terminal of the compensation transistor and the gate of the compensation transistor; The first terminal of the second OTA transistor is coupled to: (i) the power supply voltage connector, (ii) the first electrode of the first compensation capacitor, and (iii) the gate of the bias transistor; and the second electrode of the second compensation capacitor is coupled to the first terminal of the bias transistor.

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