Current balancing for voltage regulator units in field programmable arrays

Abstract

A semiconductor device has a power rail providing a rail voltage. The power rail is electrically coupled to a plurality of voltage regulators, and each voltage regulator includes: an output interface electrically coupled to the power rail; a first drive path and a second drive path both coupled to the output interface; and a balancing circuit within the regulator. The first drive path and the second drive path are coupled to each other in parallel and operate at an operating frequency during a first phase and a second phase to provide a first path current and a second path current, respectively, to the power rail. The balancing circuit within the regulator senses the first path current and the second path current and controls a first duty cycle of the first phase and / or a second duty cycle of the second phase based on the difference between the first path current and the second path current.

Description

Technical Field

[0001] This application claims priority to U.S. non-provisional patent application No. 17 / 534,345, filed November 23, 2021, entitled “Power Management Integrated Circuit with a Field Programmable Array of Voltage Regulators,” which claims priority to U.S. provisional patent application No. 63 / 143,732, filed January 29, 2021, also entitled “Power Management Integrated Circuit with a Field Programmable Array of Voltage Regulators.” This application also claims priority to U.S. non-provisional patent application No. 17 / 534,362, filed November 23, 2021, entitled "Current Balancing for Voltage Regulator Units in Field Programmable Arrays," which claims priority to U.S. provisional patent application No. 63 / 143,734, filed January 29, 2021, also entitled "Current Balancing for Voltage Regulator Units in Field Programmable Arrays." Each of the foregoing applications is hereby incorporated by reference in its entirety.

[0002] This application relates to Taiwan Patent Application No. 110144255 (Case No. 125533-5005-TW), filed on November 26, 2021, entitled "Power Management Integrated Circuit with a Field Programmable Array of Voltage Regulators", which is incorporated herein by reference in its entirety.

[0003] In summary, this application relates to electronic devices, including but not limited to devices and methods for adaptively driving power rails of electronic systems. Prior Technology

[0004] Electronic devices typically integrate a System-on-a-Chip (SoC) with a Power Management Integrated Circuit (PMIC), communication ports, external memory or storage devices, and other peripheral functional modules on a main logic board. An SoC includes one or more microprocessor or central processing unit (CPU) cores, memory, input / output ports, and auxiliary storage devices in a single package. The PMIC is typically positioned adjacent to the SoC on the main logic board and provides multiple DC power rails to the SoC via conductors formed on the main logic board. For each type of SoC, the PMIC and the conductors leading to the SoC need to be customized, at least based on the microprocessor or CPU core included in that type of SoC. In many cases, customizing the PMIC for each SoC type is not efficient. Furthermore, in some cases, voltage regulators within the same PMIC are unbalanced, degrading PMIC performance. It would be beneficial to provide highly balanced voltage regulators that can be configured to drive different types of SoCs, for example, for use in efficient and high-performance PMIC solutions. Summary of the Invention

[0005] To address the challenges associated with custom-designed PMICs, there is a strong desire to provide semiconductor devices or systems with a general-purpose PMIC that can adaptively support various types of SoCs with different microprocessors or CPU cores. Specifically, the general-purpose PMIC utilizes individual and mutually balanced voltage regulators to achieve high performance.

[0006] The various embodiments of the systems, methods, and apparatuses within the scope of the appended claims each have several aspects, none of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, it will be understood, upon consideration of this disclosure and particularly the section entitled “Detailed Description,” how aspects of the various embodiments can be used to provide a semiconductor device configured to provide multiple power rails to power one or more processor clusters of a System-on-a-Chip (SoC). The semiconductor device includes multiple voltage regulators arranged in a field-programmable array and controlled to output power to the multiple power rails of the SoC based on load information associated with one or more processor clusters coupled to the power rails. In other words, the same semiconductor device can be configured to drive different types of SoCs based on load information of different types of SoCs, thus becoming a general SoC power supply solution.

[0007] In some embodiments, for each power rail, an intra- and / or inter-regulator current balancing mechanism is internally applied to each effective voltage regulator driving the corresponding power rail, such that path currents in different current paths of each effective voltage regulator are balanced, and output currents in different effective voltage regulators driving the corresponding power rail are balanced. These balancing mechanisms are efficiently implemented for each individual voltage regulator (e.g., in a general-purpose PMIC circuit) without involving inputs or control from other different voltage regulators. Furthermore, voltage regulators in a field-programmable array can be electrically decoupled from multiple power rails and become redundant voltage regulators without being completely de-energized (when bypass units are used to disable the feedback path between the output interface and input of the redundant voltage regulator).

[0008] Specifically, in one aspect, an integrated semiconductor device includes a plurality of voltage regulators and a power array controller. The plurality of voltage regulators are arranged in a field-programmable array. The power array controller is coupled to the plurality of voltage regulators and configured to control the plurality of voltage regulators to output power to a plurality of power rails. Each power rail provides a corresponding rail current with a corresponding rail voltage. For each of the plurality of power rails, the power array controller is configured to: determine the corresponding rail current associated with the corresponding power rail; select a subset of voltage regulators based at least on the corresponding rail current; and enable the subset of voltage regulators to generate the corresponding rail voltage and collectively provide the corresponding rail current. In some embodiments, the power array controller includes one or more processors and a memory having instructions stored thereon, which, when executed by the one or more processors, cause the processors to control the plurality of voltage regulators to output power to the plurality of power rails.

[0009] In some embodiments, the power array controller is configured to: determine a control value based at least on the corresponding rail voltage, and enable the subset of voltage regulators to generate the corresponding rail voltage and collectively provide the corresponding rail current according to the determined control value. Furthermore, in some embodiments, enabling the subset of voltage regulators further includes providing the control value to the subset of voltage regulators. The subset of voltage regulators is controlled by the control value to generate the corresponding rail voltage and collectively provide the corresponding rail current. Additionally, in some embodiments, enabling the subset of voltage regulators includes providing an operation enable signal to a selected subset of voltage regulators to generate the corresponding rail voltage and collectively provide the corresponding rail current.

[0010] In some embodiments, the power array controller is configured to determine the corresponding rail current associated with the corresponding power rail based on load information corresponding to the expected or actual load on the corresponding power rail load. Furthermore, in some embodiments, the load information corresponds to processor load information of one or more processor clusters coupled to the corresponding power rail.

[0011] In some embodiments, the integrated semiconductor device further includes one or more direct current (DC) power interfaces. Each DC power interface is configured to receive a different DC supply voltage, and each voltage regulator is coupled to a corresponding subset of the one or more DC power interfaces and configured to be powered by the corresponding DC supply voltage and generate the corresponding rail voltage from the corresponding supply voltage.

[0012] In some embodiments, at a given time, at least one of the plurality of voltage regulators is redundant and is not coupled to any of the plurality of power rails.

[0013] In some embodiments, selecting the subset of voltage regulators for each power rail further includes: uniquely associating each voltage regulator in the subset of voltage regulators with the corresponding power rail at a given time.

[0014] In some embodiments, for each power rail, the corresponding rail current has a maximum rail current IRLM. Each voltage regulator in the subset of voltage regulators is configured to provide a regulator current up to a maximum regulator current IRGM, and the subset of voltage regulators has a first number of voltage regulators corresponding to the ratio of the maximum rail current IRLM to the maximum regulator current IRGM. Furthermore, in some embodiments, a first power rail is configured to reach the corresponding rail voltage within the instantaneous load response time each time the first power rail is activated, and the instantaneous load response time is achieved by the maximum regulator current IRGM. The first number is determined based on the instantaneous load response time. Additionally, a second power rail is configured to reach the corresponding rail voltage within the instantaneous load response time each time the second power rail is activated, and outputs the maximum rail current IRLM during normal operation, the instantaneous load response time being achieved by an instantaneous load current less than the maximum rail current IRLM. In some embodiments, the power array controller is configured to perform the following operations for each power rail: determine the instantaneous rail current of the corresponding power rail; and enable all voltage regulators in the voltage regulator subset to collectively provide the instantaneous rail current of the corresponding power rail. In some embodiments, the power array controller is configured to perform the following operations for each power rail: determine the instantaneous rail current of the corresponding power rail; compare the instantaneous rail current with the maximum regulator current I_RGM; disable one or more voltage regulators in the voltage regulator subset; and enable the remainder of the voltage regulator subset to collectively provide the instantaneous rail current of the corresponding power rail.

[0015] In some embodiments, the plurality of voltage regulators are identical to each other.

[0016] In some embodiments, each of the plurality of voltage regulators corresponds to a corresponding voltage regulator type selected from a plurality of predefined voltage regulator types. For each power rail, the subset of voltage regulators corresponds to a corresponding voltage regulator type, and selecting the subset of voltage regulators includes determining the corresponding voltage regulator type based on at least one performance criterion.

[0017] In some embodiments, for each power rail, each voltage regulator in the subset of voltage regulators further includes: an output interface, one or more drive paths, and a voltage regulator controller. The output interface is coupled to the respective power rail and configured to provide the rail voltage and deliver the respective rail current to the respective power rail. The one or more drive paths are coupled to the output interface and configured to operate at an operating frequency. The voltage regulator controller has an output coupled to the one or more drive paths and an input coupled to the output interface through a feedback path, and is configured to control the one or more drive paths.

[0018] In some embodiments, for each power rail, each voltage regulator in the voltage regulator subset further includes a bypass unit coupled to the one or more drive paths and the voltage regulator controller. The bypass unit is configured to provide a dummy load component. The respective voltage regulator has a standby / redundancy mode in which the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, thereby disabling the respective voltage regulator so that it cannot contribute to the current of the respective rail.

[0019] In some embodiments, for each power rail, each voltage regulator in the subset of voltage regulators is configured to provide a portion of the corresponding rail current, and further includes: an output interface electrically coupled to the corresponding power rail, multiple drive paths, and at least one of an intra-regulator balancing circuit and an inter-regulator balancing circuit. Each drive path is coupled to the output interface and configured to provide a corresponding path current to the corresponding power rail. The intra-regulator balancing circuit is coupled to the multiple drive paths and configured to balance the corresponding path current in the multiple drive paths; and the inter-regulator balancing circuit is coupled to the output interface and configured to balance the portion of the corresponding rail current provided by the corresponding voltage regulator with at least another portion of the corresponding rail current provided by different voltage regulators in the subset of voltage regulators. Additionally, in some embodiments, for each power rail, each voltage regulator in the subset of voltage regulators includes both an intra-regulator balancing circuit and an inter-regulator balancing circuit.

[0020] In another aspect, an integrated semiconductor device includes a power rail and a plurality of voltage regulators electrically coupled to the power rail. The power rail is configured to provide a rail voltage, and the plurality of voltage regulators are configured to collectively provide the rail voltage. Each of the plurality of voltage regulators includes an output interface, a first drive path, a second drive path, and an in-regulator balancing circuit. The output interface is electrically coupled to the power rail. The first drive path is coupled to the output interface and is configured to operate at an operating frequency during a first phase to provide a first path current to the power rail. The second drive path is coupled to the output interface and is configured to operate at the operating frequency during a second phase to provide a second path current to the power rail. The second drive path is electrically coupled in parallel with the first drive path. The in-regulator balancing circuit is coupled to the first drive path and the second drive path and is configured to: sense the first path current and the second path current; and generate a first control signal based on the difference between the first path current and the second path current to control a first duty cycle of the first phase and / or a second duty cycle of the second phase.

[0021] In some embodiments, each of the plurality of voltage regulators further includes a voltage regulator controller having a feedback input coupled to the output interface. The feedback input of the voltage regulator controller is configured to receive the output voltage of the output interface. Each of the plurality of voltage regulators further includes an inter-regulator balancing circuit coupled to the output interface and the voltage regulator controller. The inter-regulator balancing circuit is configured to: sense the output current of the respective voltage regulator; and apply an offset to a control input of the voltage regulator controller, wherein the offset is determined based on the sensed output current of the respective voltage regulator.

[0022] In some embodiments, the balancing circuit within the regulator is configured to: determine that the difference between the first path current and the second path current does not satisfy the path current balance criterion; and, based on determining that the difference between the first path current and the second path current does not satisfy the path current balance criterion, and determining that the first path current is greater than the second path current, to achieve one or both of the following: reducing the first duty cycle of the first phase and increasing the second duty cycle of the second phase until the difference between the first path current and the second path current satisfies the path current balance criterion.

[0023] In some embodiments, each of the plurality of voltage regulators further includes a voltage regulator controller having a feedback input coupled to the output interface, and the feedback input of the voltage regulator controller is configured to receive the output voltage of the output interface. Furthermore, in some embodiments, each of the plurality of voltage regulators further includes an inter-regulator balancing circuit coupled to the output interface and the voltage regulator controller. The inter-regulator balancing circuit is configured to: sense the output current of the respective voltage regulator; and apply an offset to a control input of the voltage regulator controller. The offset is determined based on the sensed output current of the respective voltage regulator. Furthermore, in some embodiments, the voltage regulator controller includes an error amplifier configured to: receive the control input; and apply the offset between the feedback input and a control value defining the rail voltage. In some embodiments, each of the plurality of voltage regulators further includes an inter-regulator balancing circuit coupled to the output interface and the voltage regulator controller. The regulator balancing circuit is configured to: sense one of the first path current and the second path current of the respective voltage regulator; and apply an offset to a control input received by the voltage regulator controller, the offset being based on one of the sensed first path current and the second path current.

[0024] In some embodiments, each of the first and second drive paths further includes: a switching component coupled to an input supply voltage Vin and the output interface; and a driver coupled to the switching component and configured to enable the switching component at the operating frequency during a corresponding phase of the first and second phases, thereby providing a corresponding path current of the first path current and the second path current to the power rail.

[0025] In some embodiments, the first working cycle of the first stage is equal to the second working cycle of the second stage, and the second stage is offset from the first stage.

[0026] In some embodiments, the first control signal is generated based on the difference between the first path current and the second path current to control the second duty cycle of the second phase. Each of the plurality of voltage regulators further includes a third drive path coupled to the output interface and configured to operate at the operating frequency during the third phase to provide a third path current to the power rail, the third drive path being electrically coupled to the first drive path and the second drive path. A balancing circuit within the regulator is coupled to the third drive path and configured to: sense the third path current; and generate a second control signal based on the difference between the first path current and the third path current to control the third duty cycle of the third phase.

[0027] In some embodiments, each of the plurality of voltage regulators further includes a third drive path coupled to the output interface and configured to operate at the operating frequency during a third phase to provide a third path current to the power rail, the third drive path being electrically coupled in parallel with the first drive path and the second drive path. A balancing circuit within the regulator is coupled to the third drive path and configured to: sense the third path current; and generate the first control signal based on the difference between the first path current and the second path current, and based on the difference between the first path current and the third path current, to control the first duty cycle of the first phase.

[0028] In some embodiments, the plurality of voltage regulators and one or more additional voltage regulators are arranged in a field-programmable array, and the plurality of voltage regulators are selected from the field-programmable array based on load information corresponding to the expected or actual load on the power rail to drive the power rail.

[0029] In another aspect, an integrated semiconductor device includes a power rail and a plurality of voltage regulators coupled to the power rail. The power rail is configured to provide a rail voltage, and the plurality of voltage regulators are configured to collectively provide the rail voltage. Each of the plurality of voltage regulators includes an output interface, one or more drive paths, a voltage regulator controller, and a bypass unit. The output interface is coupled to the power rail and configured to provide the rail voltage and deliver up to a predefined regulator current to the power rail. The one or more drive paths are coupled to the output interface and configured to operate at an operating frequency. The voltage regulator controller has an output coupled to the one or more drive paths and an input coupled to the output interface through a feedback path, and is configured to control the one or more drive paths. The bypass unit is coupled to the one or more drive paths and the voltage regulator controller and is configured to provide a dummy load component. Each voltage regulator has a standby / redundancy mode in which the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller.

[0030] Other embodiments and advantages will be apparent to those skilled in the art from the description and drawings in this specification. Simple Explanation of the Diagram

[0031] Figure 1 is a block diagram of an example system module in a typical electronic device according to some embodiments.

[0032] Figure 2 is a block diagram of a power management system according to some embodiments.

[0033] Figure 3 is a cross-sectional view of an integrated semiconductor device according to some embodiments.

[0034] Figure 4A is a field-programmable array of voltage regulators according to some embodiments, and Figure 4B is a basic cluster of voltage regulators in the field-programmable array shown in Figure 4A according to some embodiments.

[0035] Figure 5 is a schematic diagram of a power management system according to some embodiments, the power management system including a field-programmable array of voltage regulators shown in Figure 4.

[0036] Figure 6 is a simplified block diagram of an integrated semiconductor device according to some embodiments, the integrated semiconductor device including multiple voltage regulators for providing one or more power rails to a SoC.

[0037] Figure 7A illustrates a procedure for providing rail current IR at rail voltage VR using a subset of voltage regulators according to some embodiments, and Figure 7B illustrates a procedure for providing rail current IR at rail voltage VR based on one or more redundant voltage regulators according to some embodiments.

[0038] Figure 8A is a block diagram of a voltage regulator used as a basic unit for forming a field-programmable array according to some embodiments.

[0039] Figure 8B is a block diagram of a voltage regulator using current balancing and / or redundancy control according to some embodiments.

[0040] Figure 9 is a circuit diagram of a voltage regulator with multiple drive paths 804 according to some embodiments.

[0041] Figure 10A is a circuit diagram of a voltage regulator having two drive paths balanced by an internal balancing circuit according to some embodiments.

[0042] Figure 10B is a circuit diagram of a voltage regulator having two or more (e.g., three) drive paths balanced by an internal balancing circuit according to some embodiments.

[0043] Figure 10C is a circuit diagram of a voltage regulator that uses a differential amplifier to balance the drive path according to some embodiments.

[0044] Figure 11A is an equivalent circuit diagram of a power rail driven by two voltage regulators in a field-programmable array of voltage regulators, according to some embodiments.

[0045] Figure 11B is an equivalent circuit diagram of a single voltage regulator using a low-pass filter (LPF) for inter-regulator current balancing according to some embodiments.

[0046] Figures 12A and 12B are circuit diagrams of a voltage regulator controlled by an inter-regulator balancing circuit according to some embodiments.

[0047] Figure 13 is a circuit diagram of a voltage regulator in a field-programmable array having an auxiliary loop for controlling redundancy, according to some embodiments.

[0048] Throughout the diagrams, similar diagrammatic symbols refer to the corresponding parts. Implementation

[0049] Reference will now be made in detail to specific embodiments, examples of which are illustrated in the drawings. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternative methods may be used without departing from the scope of the claims, and that the subject matter may be implemented without these specific details. For example, it will be apparent to those skilled in the art that the subject matter presented herein can be implemented on many types of electronic devices with power management capabilities.

[0050] Previously, for each type of SoC, the PMIC and wiring leading to the SoC needed to be customized, at least based on the microprocessor or CPU core included in the SoC of that type. In many cases, customizing the PMIC for each SoC type was inefficient. Furthermore, in some cases, voltage regulators within the same PMIC were unbalanced, degrading the PMIC's performance. In various embodiments of this application, an integrated semiconductor device is configured to provide multiple power rails to power one or more processor clusters of an SoC. The semiconductor device includes multiple voltage regulators arranged in a field-programmable array and controlled to output power to the multiple power rails of the SoC based on load information associated with one or more processor clusters coupled to the power rails. The same integrated semiconductor device can be adapted to power different types of SoCs. Furthermore, in some embodiments, for each power rail, an intra-regulator and / or inter-regulator current balancing mechanism is applied within each effective voltage regulator driving the corresponding power rail, balancing the path currents in different current paths of each effective voltage regulator and balancing the output currents in the different effective voltage regulators driving the corresponding power rail. Through these means, the application provides an efficient and high-performance PMIC solution with a highly balanced voltage regulator that can adaptively drive different types of SOCs.

[0051] Figure 1 is a block diagram of an example system module 100 in a typical electronic device according to some embodiments. The system module 100 in the electronic device includes at least a single-chip system (SoC) 102, a memory module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces (such as a network interface 108), and one or more communication buses 150 for interconnecting these components. In some embodiments, the I / O controller 106 allows the SoC 102 to communicate with I / O devices (e.g., a keyboard, mouse, or touchscreen) via a general serial bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each interface allowing the electronic device to exchange data with external sources (e.g., a server or another electronic device). In some embodiments, the communication bus 150 includes circuitry (sometimes referred to as a chipset) that interconnects the various system components included in the system module 100 and controls communication between the various system components.

[0052] In some embodiments, memory module 104 includes high-speed random access memory, such as DRAM, SRAM, DDR-RAM, or other random access solid-state memory devices. In some embodiments, memory module 104 includes non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some embodiments, the non-volatile memory devices within memory module 104, or alternatively, include non-transitory computer-readable storage media. In some embodiments, memory slots are reserved on system module 100 for accommodating memory module 104. Once inserted into a memory slot, memory module 104 is integrated into system module 100.

[0053] In some embodiments, system module 100 further includes one or more components selected from the following: l Memory controller 110 controls communication between SoC 102 and memory components (including memory module 104) in an electronic device; A solid-state drive (SSD) 112, which uses integrated circuit components to store data in an electronic device, and in many embodiments, is configured based on NAND or NOR memory; The hard disk drive 114 is a conventional data storage device used for storing and retrieving digital information based on a mechanical disk. A power connector 116 includes one or more DC power interfaces, each DC power interface being configured to receive a different DC supply voltage; The power management integrated circuit (PMIC) 118 modulates different DC supply voltages received via a DC power interface into other desired internal supply voltages required by various components or circuits within the electronic device (e.g., the processor core in SoC 102), such as 5V, 3.3V, or 1.8V. A graphics module 120, which generates and feeds an output image to one or more display devices according to the desired image / video format of one or more display devices; and The sound module 122, under the control of a computer program, facilitates the input of audio signals to and output of audio signals from an electronic device.

[0054] It should be noted that the communication bus 150 will also include the interconnection of various system components 110-122 and control of their communication.

[0055] Furthermore, those skilled in the art will recognize that other non-transitory computer-readable storage media can be used, as new data storage technologies have been developed to store information in non-transitory computer-readable storage media within memory module 104 and SSD 112. These new non-transitory computer-readable storage media include, but are not limited to, storage media made of biological materials, nanowires, carbon nanotubes, and individual molecules, although the corresponding data storage technologies are currently under development and have not yet been commercialized.

[0056] In some embodiments, SoC 102 is implemented in a semiconductor package including one or more integrated circuits, and each integrated circuit integrates a subset of the following on a single substrate: one or more microprocessor or CPU cores, memory, input / output ports, and auxiliary storage devices. PMIC 118 is also implemented in a semiconductor package including one or more integrated circuits, each integrated circuit formed on a single substrate. SoC 102 is configured to receive one or more internal supply voltages (also referred to as rail voltages) provided by PMIC 118 via one or more power rails. In some embodiments, both SoC 102 and PMIC 118 are mounted on a main logic board, for example, on two different areas of the main logic board, and are electrically coupled to each other via wires formed in the main logic board. This arrangement introduces parasitic effects and electrical noise that may affect the performance of the SoC, for example, causing voltage drops in the internal supply voltages. Alternatively, according to the various embodiments described below, the semiconductor dies of SoC 102 and PMIC 118 are vertically packaged in an integrated semiconductor device such that they are electrically coupled to each other via electrical connections not formed in the main logic board. This vertical arrangement of the semiconductor dies in SoC 102 and PMIC 118 reduces the length of the electrical connections between SoC 102 and PMIC 118 and avoids performance degradation caused by wiring on the main logic board.

[0057] It should be noted that, in some embodiments, the vertical alignment of the semiconductor dies of SoC 102 and PMIC 118 is facilitated in part by integrating thin-film inductors in the limited space between the dies of SoC 102 and PMIC 118. The thin-film inductor is formed and integrated on the substrate of PMIC 118 and has an inductor height controlled to be less than the height of the limited space, allowing the thin-film inductor to fit within the limited space between the semiconductor dies of SoC 102 and PMIC 118. Because the thin-film inductor is formed on top of the substrate of PMIC 118, it can be directly connected to internal or output nodes of PMIC 118 without using wires from the main logic board to connect the thin-film inductor to the internal or output nodes of PMIC 118.

[0058] In various embodiments of this application, a general-purpose PMIC 118 is configured to drive different types of SoCs 102 in different types of electronic devices 100. Regardless of whether the PMIC 118 and SoC 102 are arranged side-by-side or vertically, the PMIC 118 occupies the same package footprint relative to the main circuit board, while the SoC 102 may have different package footprints based on the electronic modules integrated therein. The PMIC 118 includes multiple voltage regulator units arranged in a field-programmable array. The multiple voltage regulator units are identical to each other or include more than one type of voltage regulator unit. In a particular electronic device, control signals are determined based on the rail voltage and rail current required to power the SoC 102 and other electronic modules (if any) from the power rails. For each of these power rails, a corresponding control signal is used to select a subset of the voltage regulator units in the field-programmable array of the PMIC 118, and the selected voltage regulator units collectively provide rail current to the corresponding power rail at the rail voltage. Therefore, PMIC 118 is reconfigured by these control signals to provide rail voltage and current to the power rails of SoC 102, and each of the multiple configurable voltage regulator units in PMIC 118 is redundant or selected to drive one of the power rails via one of the control signals.

[0059] Figure 2 is a block diagram of a power management system 200 configured to power one or more power rails 206 of a SoC (such as SoC 102) according to some embodiments. The power management system 200 receives one or more input DC supply voltages 202 and digital power control signals 204, and converts the input DC supply voltages 202 into one or more rail voltages, which are output by one or more power rails 206A, 206B through 206N and provided to the SoC 102. The power management system 200 includes a power management interface 208, one or more DC-DC converters 210 (e.g., DC-DC converters 210A, 210B, ..., 210N), and one or more output filters 212 (e.g., output filters 212A, 212B, ..., 212N). The power management interface 208 receives the input DC supply voltages 202 and digital power control signals 204. In some embodiments, the power management interface 208 is controlled by the main power management interface of the central processing unit (e.g., on SoC 102) and configured to receive digital power control signals 204 from SoC 102. A DC-DC converter 210 is coupled to the power management interface 208 and the power rail 206 and is controlled by the digital power control signals 204 to generate one or more rail voltages supplied on the power rail 206 from the input DC supply voltage 202. An output filter 212 is coupled to the DC-DC converter 210 and configured to reduce noise in the power rail 206 supplied to SoC 102 and maintain its stability. In some embodiments, the output filter (e.g., any one of 212A, 212B, ..., 212N) includes one or more corresponding output resistors 214 and one or more output capacitors 216 (e.g., 216A, 216B, ..., 216N). In some embodiments, the output filter (e.g., 212B) includes an inductor 218 and one or more output capacitors (e.g., capacitor 216B).

[0060] In some embodiments, the power management system 200 is implemented on one or more PMIC dies 220 (corresponding to PMIC 118 of FIG. 1), and each PMIC die has a single substrate. In some embodiments, the power management interface 208 and the DC-DC converter 210 are formed on the substrate of a single PMIC die 220, for example, belonging to the same integrated circuit fabricated on the substrate of the PMIC die 220. Conversely, in some embodiments, the power management interface 208 and the DC-DC converter 210 are formed on multiple substrates of multiple PMIC dies 220. In some embodiments, in addition to the power management interface 208 and the DC-DC converter 210, each PMIC die 220 includes multiple thin-film inductors, which are fabricated or mounted on the top surface of the substrate of the PMIC die 220. Optionally, the multiple thin-film inductors include one or more inductors 218 used in the output filter 212. Optionally, the multiple thin-film inductors include one or more inductors 218' used in the DC-DC converter 210. In some embodiments, in addition to interface 208, converter 210 and inductors 218 / 218', PMIC die 220 also integrates a subset of output resistors 214 and capacitors 216 of output filter 212.

[0061] In some embodiments, the power management system 200 includes a field-programmable array of voltage regulator units, an output filter 212, one or more output resistors 214, one or more output capacitors 216, and one or more inductors 218. A digital power control signal 204 is determined, for example, by the SoC 102 based on a target power capability (e.g., rail voltage and rail current) required for the power rail 206. For example, each power rail is configured to power a CPU cluster, cache memory, or functional block of the SoC 102 (which has a corresponding power requirement used by the SoC 102 to define the target power capacity of the respective power rail). According to the control signal 204, the voltage regulator units in the field-programmable array are partitioned and configured to form one or more DC-DC converters 210 (e.g., DC-DC converters 210A, 210B, ..., 210N) to drive the power rail 206 using the target power capability. For each DC-DC converter 210, additional components 212-218 can also be selected and controlled via a corresponding subset of control signals 204 to achieve the desired noise performance for the corresponding power rail 206.

[0062] Figure 3 is a cross-sectional view of an integrated semiconductor device 300 according to some embodiments. The semiconductor device 300 integrates at least one SoC die 302 and at least one PMIC die 220 in a semiconductor package, and includes at least a package substrate 304 having a first surface 304A and a second surface 304B opposite to the first surface 304A. The SoC die 302 is disposed on the first surface 304A of the package substrate 304, and the PMIC die 220 is mechanically coupled to the second surface 304B of the package substrate 304.

[0063] The package substrate 304 also includes a plurality of first via interconnects 306 that pass through the body of the package substrate 304 and are exposed on a first surface 304A and a second surface 304B. The PMIC die 220 is electrically coupled to the SoC die 302 via the plurality of first via interconnects 306 of the package substrate 304. Specifically, the PMIC die 220 includes a plurality of DC connections 308 configured to output a plurality of rail voltages supplied to power rails 206 (FIG. 2). When the PMIC die 220 is mounted on the second surface 304B of the package substrate 304, the DC connections 308 are electrically coupled to the plurality of first via interconnects 306 of the package substrate 304. In some embodiments, the SoC die 302 includes a plurality of power connections 312 configured to receive the plurality of rail voltages. When the SoC die 302 is mounted on the first surface 304A of the package substrate 304, the power connections 312 are electrically coupled to the plurality of first via interconnects 306 of the package substrate 304. Therefore, the PMIC die 220 is configured to provide DC power (i.e., the rail voltage and rail current of the power rail 206) to the SoC die 302 via the DC connection 308 of the PMIC die 220, the power connection 312 of the SoC die 302, and the first via interconnect 306 of the package substrate 304. Furthermore, compared to a system where the PMIC die 220 and SoC die 302 are individually packaged and positioned side-by-side on a main board, the quality of the DC power provided from the PMIC die 220 to the SoC die 302 is significantly improved by using the extremely low impedance DC connection 308.

[0064] In some embodiments, the power management interface 208 on the PMIC die 220 is controlled by the main power management interface of the SoC die 302 and is configured to receive digital power control signals 204 from the SoC die 302. A subset of the first via interconnect 306 is configured to transmit the digital power control signals 204 from the SoC die 302 to the PMIC die 220.

[0065] The SoC die 302 has a first package shape on the packaging substrate 304, and the PMIC 220 has a second package shape on the packaging substrate 304. For the purpose of directly coupling the DC connection 308 of the PMIC die 220 and the power connection 312 of the SoC die 302 using a plurality of first via interconnects 306, the first package shape and the second package shape at least partially overlap. In some cases, the first package shape of the SoC die 302 is larger than the second package shape of the PMIC die 220 and completely surrounds the second package shape of the PMIC die 220. Alternatively, in some cases, the first package shape of the SoC die 302 is offset from the second package shape of the PMIC die 220, but at least partially overlaps with the second package shape of the PMIC die 220. The DC connection 308 of the PMIC die 220, the power connection 312 of the SoC die 302, and the first via interconnects 306 of the packaging substrate 304 are aligned and surrounded in the overlapping area of ​​the first and second package shapes.

[0066] Furthermore, the PMIC die 220 includes a plurality of thin-film inductors 218 corresponding to a plurality of DC connections 308. The plurality of thin-film inductors 218 are positioned adjacent to or facing the second surface 304B of the package substrate 304, for example, on the top surface of the PMIC die 220 facing the second surface 304B of the package substrate 304. In other words, the plurality of thin-film inductors 218 are disposed between the top surface of the PMIC die 220 and the second surface 304B of the package substrate 304. In some embodiments, the PMIC die 220 is mechanically coupled to the package substrate 304, for example, via an adhesive. The height of the plurality of thin-film inductors 218 is less than a predetermined threshold height (e.g., 1 mm, 100 µm) to maintain robustness of the mechanical coupling between the PMIC die 220 and the package substrate 304.

[0067] In some embodiments, the integrated semiconductor device 300 further includes a cap 314 coupled to a first surface 304A of a package substrate 304. The cap 314 is configured to conceal at least a portion of the SoC die 302 and the first surface 304A of the package substrate 304, thereby protecting at least a portion of the SoC die 302 and the first surface 304A. Furthermore, in some embodiments, the cap 314 is made of a conductive material and is configured to be grounded to provide electrostatic shielding for any other circuitry on the SoC die 302 and the first surface 304A when the cap 314 completely covers it, or to provide electrostatic shielding for the portion of the first surface 304 covered by the cap 314 when the cap 314 only partially covers it. In some cases, the cap 314 is made of a thermally conductive material configured to dissipate heat generated by the SoC die 302. In some embodiments, the heat sink 316 or heat sink layer is used to couple the SoC die 302 to the inner surface of the cover 314 so as to uniformly distribute the heat generated by the SoC die 302 from the SoC die 302 to the cover 314.

[0068] In some embodiments, the semiconductor device 300 further includes a socket substrate 318. The socket substrate 318 has a third surface 318A facing a second surface 304B of a package substrate 304. The package substrate 304 is electrically coupled to the socket substrate 318 via a plurality of electrical connectors 320. Specifically, the second surface 304B of the package substrate 304 includes a first region (e.g., a central region) to which the PMIC die 220 is mechanically coupled and a second region (e.g., a peripheral region) where the plurality of electrical connectors 320 are located. In one example, the second region is adjacent to and surrounds the first region. It should be noted that in some cases, the semiconductor device 300 is provided with a socket substrate 318. However, in some cases, the socket substrate 318 is fixed to a circuit board of the electronic device in FIG. 1 and is not part of the integrated semiconductor device 300. Specifically, the semiconductor device 300 is an alternative portion configured to provide the functionality of a combination of the PMIC die 220 and the SoC die 302.

[0069] In some embodiments, the third surface 318A of the receptacle substrate 318 is substantially flat, and the PMIC die 220 is disposed between the second surface 304B of the package substrate 304 and the third surface 318A of the receptacle substrate 318. The height of the plurality of thin-film inductors 218 is less than a predetermined threshold height (e.g., 1 mm, 100 µm) determined by the difference between the length of the electrical connector 320 and the thickness of the PMIC die 220. Alternatively, in some embodiments, the receptacle substrate 318 includes a recessed portion 322 formed on the third surface 318A and configured to receive the PMIC die 220 when it is mechanically and electrically coupled to the second surface 304B of the package substrate 304. The depth of the recessed portion 322 is less than the thickness of the receptacle substrate 318. In some cases, the PMIC die 220 is suspended in the recessed portion 322, i.e., separated from the bottom surface of the recessed portion 322 by an air gap. Alternatively, in some cases, the PMIC die 220 contacts the bottom surface of the recess 322 directly or via an intermediate layer (e.g., an adhesive layer, a heat dissipation layer, or a layer that is both an adhesive layer and a heat dissipation layer).

[0070] In some embodiments not shown in FIG3, the depth of the recess 322 is equal to the thickness of the socket substrate 318, and the recess 322 is an opening or cut-off in the socket substrate 318. When the socket substrate 318 is mounted on a circuit board (e.g., a main logic board), the PMIC die 220 is suspended in the recess 322 (also referred to as an opening or cut-off) and is at least partially surrounded by the package substrate 304, the socket substrate 318, and the circuit board.

[0071] In some embodiments, the power connection 312 of the SoC die 302 is not directly coupled to the first via interconnect 306 of the package substrate 304. Specifically, the first inserter 324 is disposed between the SoC die 302 and the first surface 304A of the package substrate 304. The first interposer 324 also includes a plurality of second via interconnects 326 configured to electrically couple at least the power connection 312 of the SoC die 302 and the first via interconnect 306 of the package substrate 304. Similarly, in some embodiments, the DC connection 308 of the PMIC die 220 is not directly coupled to the first via interconnect 306 of the package substrate 304. Specifically, the second interposer 328 is disposed between the PMIC die 220 and the second surface 304B of the package substrate 304. The second interposer 328 also includes a plurality of third via interconnects configured to electrically couple at least the DC connection 308 of the PMIC die 220 and the first via interconnect 306 of the package substrate 304. Therefore, the power rail 206 of SoC 102 includes at least the power connection 312 of SoC die 302, the first via interconnect 306 of package substrate 304 and the DC connection 308 of PMIC die 220, and in some cases, it also includes the second via interconnect 326 of the first interposer 324 and / or the third via interconnect 332 of the second interposer 328.

[0072] In some embodiments, the semiconductor device 300 further includes one or more discrete electronic modules 330 (e.g., resistors, capacitors, inductors, transistors, and logic chips). The discrete electronic modules 330 may be electrically coupled to the input / output interface circuitry of the SoC die 302 to control input / output coupling for the SoC die 302. Optionally, a subset of the discrete electronic modules 330 (e.g., components 330A) is disposed on a first surface 304A of the package substrate 304. Each component 330A may be contained within or outside a cover 314. Optionally, a subset of the discrete electronic modules 330 (e.g., components 330B) is mechanically coupled to a second surface 304B of the package substrate 304. If a corresponding component 330B has a low profile (e.g., thinner than the length of the electrical connector 320), the component 330B may be adapted to fit in the gap between the second surface 304B of the package substrate 304 and the third surface 318A of the socket substrate 318. Otherwise, if component 330B does not have a low profile (e.g., thicker than the length of electrical connector 320), then the corresponding component 330B can be received by the recessed portion 322 of the socket substrate 318 and configured to be adjacent to the PMIC die 220.

[0073] SoC die 302 and PMIC die 220 are vertically arranged in semiconductor device 300. The power connection 312 of SoC die 302 and the DC connection 308 of PMIC die 220 are aligned and positioned close to each other, thereby reducing parasitic resistance and capacitance coupled to each power rail 206 providing rail voltage to SoC die 302. It should be noted that in some embodiments, multiple PMIC dies 220 may be disposed in recesses 322 of socket substrate 318 and electrically coupled to one or more SoC dies 302 disposed on a first surface 304A of package substrate 304. For example, two PMIC dies 220 are disposed in recesses 322 of socket substrate 318 to jointly power four SoC dies 302. One of the SoC dies 302 selectively corresponds to a microprocessor or CPU core, or a cluster of microprocessors or CPU cores.

[0074] Furthermore, in some embodiments of this application, the PMIC die 220 includes a field-programmable array of voltage regulators that can be configured via control signals to drive different types of SoC dies 302. In some cases, the same PMIC die 220, package substrate 304, and socket substrate 318 are used to support different types of SoC dies 302. The recessed portion 322 formed on the socket substrate 318 has a fixed size to accommodate the same PMIC die 220, and the first via interconnect 306 through the body of the package substrate 304 has a fixed position. Alternatively, in some cases, although the package form factor of the package substrate 304 and the socket substrate 318 varies depending on the type of SoC die, the same PMIC die 220 allows the recessed portion 322 and the first via interconnect 306 of the package substrate 304 to remain unchanged, thereby avoiding the need to customize the PMIC die 220 and the entire package for each individual type of SoC die 302. Therefore, the application of a field-programmable array of voltage regulators in the PMIC die 220 simplifies the assembly process and improves the cost efficiency of the semiconductor device 300.

[0075] Figure 4A is a field-programmable array 400 of voltage regulators 402 according to some embodiments, and Figure 4B is a basic cluster 420 of voltage regulators 402 in the field-programmable array 400 shown in Figure 4A according to some embodiments. The field-programmable array 400 of voltage regulators 402 is used to establish a power management system 200 and is configured to provide one or more power rails 206 to a SoC (such as SoC 102). In the field-programmable array 400, voltage regulators 402 correspond to one or more voltage regulator types and are organized into multiple rows and columns (e.g., 16 columns and 15 rows in Figure 4A). When only one type of voltage regulator is used, the voltage regulators 402 of the field-programmable array 400 are identical to each other (e.g., have the same circuitry but can be configured differently). In some implementations, the field-programmable array 400 includes a single cluster 420 of voltage regulators. In some implementations, the field-programmable array 400 includes multiple basic clusters 420 of voltage regulators, for example, six basic clusters 420 arranged in 2 columns and 3 rows in FIG. 4A. The multiple basic clusters 420 in the field-programmable array 400 may be identical to each other. Alternatively, the multiple basic clusters 420 may be independent of each other, and each basic cluster 420 includes a corresponding subarray of voltage regulators 402, which include a single type of voltage regulator or two or more types of voltage regulators. In some implementations, each basic cluster 420 is formed on different substrates and includes an independent semiconductor wafer. Alternatively, in some embodiments, two or more basic clusters 420 are formed on the same substrate. Regardless of whether the basic clusters 420 of the field-programmable array 400 are formed on a single substrate or multiple substrates, these basic clusters 420 are coupled to each other and configured to collectively implement the power management system 200.

[0076] In some implementations, as shown in FIG2, the power management system 200 includes a power management interface 208 having a power array controller (e.g., power array controller 602 in FIG6). The power array controller is coupled to a field-programmable array 400 of a voltage regulator and is configured to control the field-programmable array 400. In some embodiments, the power array controller further includes multiple circuit modules, such as an analog-to-digital converter (ADC) 404, an analog register 406, an oscillator 408, a static random access memory (SRAM) array 410, a phase-locked loop (PLL) circuit 412, and / or a low-dropout regulator (LDO) 414. The power array controller 602 selectively includes one or more of the following: one or more processors (e.g., a microcontroller 508 (FIG. 5)), non-volatile memory (NVM) 506 (e.g., read-only memory, one-time programmable (OTP) memory), a register 506, and a finite state machine (e.g., 532). In some implementations, each of the multiple circuit modules is positioned between voltage regulators 402 in two adjacent rows of the field-programmable array 400. In some implementations, the memory of the power array controller stores one or more programs with instructions that, when executed by one or more processors, cause the processors to control the voltage regulators 402 in the field-programmable array 400 to output power.

[0077] Multiple voltage regulators 402 are controlled by a power array controller of power management interface 208 to output power to multiple power rails 206. Each power rail 206 needs to provide a corresponding rail current IR with a corresponding rail voltage VR. The power array controller is configured to select a corresponding subset of voltage regulators 402 in the field-programmable array 400 for a given power rail, based at least on the corresponding rail current IR of the given power rail. In some embodiments, the selection of voltage regulators 402 for each power rail 206 is implemented at the package or board level of power management system 200 and may include voltage regulators 402 distributed across different clusters 420 throughout the field-programmable array 400. The voltage regulators selected for a given power rail 206 need not be limited to voltage regulators within a single cluster 420 or a limited number of clusters 420. In one example, a first power rail 206-1 is configured to be powered by ten voltage regulators 402 located on the same cluster 420A. In another example, the second power rail 206-2 is configured to be powered by ten voltage regulators 402 located in two or more different clusters (e.g., 420B, 420C, and 420D) formed on two or more different semiconductor wafers.

[0078] For each of the multiple power rails 206 (e.g., power rails 206-1 or 206-2), voltage regulators 402 in a corresponding subset of those selected for said power rail are controlled to share the corresponding load at the respective power rail in a substantially uniform manner. When enabled to supply power to the respective power rail, each voltage regulator 402 in the corresponding subset is controlled to provide substantially equal portions of the respective rail voltage VR and the respective rail current IR. For example, the first power rail 206-1 provides a first rail voltage VR1 and a first rail current IR1, and each of the ten voltage regulators 402 configured to supply power to the first power rail 206-1 has an output coupled to the first power rail 206-1 and is configured to provide one-tenth of the first rail voltage VR1 and the first rail current IR1 (i.e., 0.1 IR1). In some implementations, the first power rail 206-1 is associated with one or more inter-regulator balancing circuits coupled among the ten voltage regulators 402 to uniformly (or substantially uniformly) balance the load at the respective power rail among the ten regulators 402. Conversely, in some implementations, no inter-regulator balancing circuit is coupled between any two of the ten voltage regulators 402 configured to power the first power rail 206-1. Each voltage regulator 402 is individually and independently controlled, for example, based on its respective output current, to power a corresponding portion of the load, which is balanced with other portions of the load powered by the other voltage regulators 402.

[0079] One or more clusters 420 of voltage regulators are formed on the same substrate as one or more interconnects 416. In some embodiments, pairs of adjacent layers of the one or more interconnects 416 are electrically coupled via electrical contacts and / or vias. Each voltage regulator 402 in the one or more clusters 420 may be electrically coupled to a corresponding power rail 206 via interconnect 416. Each voltage regulator 402 may also be coupled to and controlled by multiple circuit modules of a power array controller via interconnect 416. In some implementations, multiple DC connections 308 are formed and exposed on the top surface of the substrate of the one or more clusters 420 of voltage regulators. The multiple DC connections 308 are electrically coupled to a subset of interconnects 416 and are part of one or more power rails 206 of the SoC die 302. The DC connections 308 are configured to provide one or more rail voltages VR output by the voltage regulator 402 to one or more power rails 206. Specifically, referring to Figures 3 and 4B, the cluster 420 of voltage regulators in the PMIC die 220 is configured to provide DC power (i.e., the rail voltage VR and current IR output by the voltage regulator 402) to the SoC die 302 via the DC connection 308 of the PMIC die 220, the power connection 312 of the SoC die 302, and the first via interconnect 306 of the package substrate 304. In one example, each DC connection 308 of the PMIC die 220 includes conductive bumps (e.g., solder, gold, or copper bumps).

[0080] The field-programmable array 400 of voltage regulators can scale to meet the power requirements (e.g., rail voltage VR, rail current IR) of different types of SoC 302. For example, the field-programmable array 400 includes multiple voltage regulators 402 organized in a cluster. When the field-programmable array 400 is configured to drive a first SoC 302, a first group of voltage regulators 402 is enabled to power a first plurality of power rails 206. When the field-programmable array 400 is configured to drive a second SoC die 302, a second group of voltage regulators 402 is enabled to power a second plurality of power rails 206. The first SoC die 302 is different from the second SoC die 302, and the first plurality of power rails 206 are different from the second plurality of power rails 206. The first group and the second group of voltage regulators 402 are determined based on the power requirements of the power rails 206 of the first SoC die 302 and the second SoC die 302, respectively. The first and second sets of voltage regulators 402 are different from each other, while the same field-programmable array 400 is applied to drive the first SoC die 302 and the second SoC die 302. Therefore, the field-programmable array 400 scales according to the power requirements of the power rails 206 of the first SoC die 302 and the second SoC die 302.

[0081] Figure 5 is a schematic diagram of a power management system 500 according to some embodiments of a field-programmable array 400 including voltage regulators 402 shown in Figure 4. The field-programmable array 400 includes a plurality of voltage regulators 402 configured to be controlled by a plurality of circuit modules. In some implementations, the plurality of circuit modules are arranged between columns of the plurality of voltage regulators 402 on the field-programmable array 400. These circuit modules belong to a power management interface 208. In some implementations, the power management system 500 is controlled by a main power management interface of a central processing unit (e.g., SoC 102) and is configured to receive one or more power control signals 204 from the SoC 102 via the SoC interface 502. The power control signals 204 include information (e.g., configuration information, such as voltage and current requirements) for a plurality of power rails 206 corresponding to the SoC 102, such as rail voltage VR and rail current IR of the power rails 206. SoC 102 stores information for power rail 206 in scratchpad 506. The information for power rail 206 is then retrieved from scratchpad 506, and microcontroller 508 is configured to select a subset of voltage regulators 402 from among a plurality of voltage regulators 402 based on the information for power rail 206 in scratchpad 506 to drive each power rail 206 of the corresponding SoC die 302.

[0082] The power management system 500 also includes one or more of the following: an ADC 404, an analog register 406, an oscillator 408, an SRAM array 410, a PLL circuit 412, and an LDO 414. The oscillator 408 is configured to generate an internal clock signal 510. A clock selection signal 514 is used to determine whether to select the internal clock signal 510 or an external clock signal 512 as the system clock 516. The microcontroller 508 is configured to operate under the control of the system clock 516. The PLL 412 is configured to receive the system clock 516 and generate a multiphase clock 518 using a divider 520 or without using a divider 520. Each voltage regulator 402 includes one or more switch-mode drive paths configured to operate at the frequency of the multiphase clock 518. The frequency of the one or more switch-mode drive paths is equal to or a multiple of the frequency of the system clock 516.

[0083] Furthermore, in some embodiments, an LDO 414 is applied to generate an additional rail voltage 522 from the input DC supply voltage 202; the additional rail voltage 522 differs from the rail voltage 206 provided by the voltage regulator 402. The additional rail voltage 522 is substantially stable under variations in line and load, unaffected by changes in ambient temperature, and stabilizes over time. Although the input DC supply voltage 202 (within a predetermined range) varies, the variation in the additional rail voltage 522 is substantially small, for example, less than a threshold voltage drop. For example, the input DC supply voltage 202 is equal to or below 1.8 V, and even when the input DC supply voltage 202 drops to 1.1 V, the additional rail voltage 522 remains substantially stable at 0.9 V (e.g., with a variation of less than ±50 mV).

[0084] In some embodiments, the power management system 500 further includes a reference generator 524 configured to provide one or more reference power supplies, including an LDO 414, a voltage regulator 402, a fuse 526, and an ADC 404. The ADC 404 includes track-and-hold circuitry and an analog input multiplexer that allows conversion of up to nine different inputs (e.g., one or more reference voltages, input DC supply voltage 202, rail voltage 206, control and data retrieved from register 506).

[0085] In some embodiments, the power management system 500 further includes a thermal shutdown module 528 configured to monitor the temperature of the SoC die 302 coupled to the power management system 500 or the temperature of the power management system 500 itself, and to control (e.g., disable) the output of the rail voltage on the power rail 206 based on the temperature of the SoC die 302 or the power management system 500. In one example, when the temperature of the SoC die 302 exceeds a predefined SoC threshold temperature (e.g., 85°C), the thermal shutdown module 526 controls the power management system 500 to disable the output of the rail voltage VR on the power rail 206, thereby allowing the temperature of the SoC die 302 to drop below the SoC threshold temperature.

[0086] Figure 6 is a simplified block diagram of an integrated semiconductor device 600 according to some embodiments, which includes a plurality of voltage regulators 402 for providing one or more power rails 206 to a SoC 102. The plurality of voltage regulators 402 are arranged in a field-programmable array 400. A power array controller 602 includes a plurality of electronic modules (e.g., one or more of the SoC interface 502, oscillator 408, microcontroller 508, LDO 414, and reference generator 524 in Figure 5) and is coupled to the plurality of voltage regulators 402. The power array controller 602 is configured to control the plurality of voltage regulators 402 to output power to the plurality of power rails 206. Each power rail 206 provides a corresponding rail current IR with a corresponding rail voltage VR. Referring to Figure 6, the field-programmable array 400 of voltage regulators 402 supplies power to four power rails 206-1, 206-2, 206-3, and 206-4, and provides rail currents IR1, IR2, IR3, and IR4 at rail voltages VR1, VR2, VR3, and VR4, respectively. For each of the power rails 206, the power array controller 602 determines the corresponding rail current IR associated with the corresponding power rail 206, selects a subset of voltage regulators 402 based at least on the corresponding rail current IR, and enables the subset of voltage regulators 402 to generate the corresponding rail voltage VR and collectively provide the corresponding rail current IR. Thus, the power array controller 602 and voltage regulators 502 implement a power management system for SOC 102 on one or more PMIC dies 220 (corresponding to PMIC 118 in Figure 1).

[0087] SoC 102 includes multiple electronic components, such as one or more microprocessor or CPU cores 604, memory 606, communication modules 608, timing sources, peripherals (e.g., clocks, counter timers), analog interfaces, input / output ports, and / or auxiliary storage devices. The microprocessors or CPU cores 604 are selectively arranged in clusters. SoC 102 is implemented by one or more integrated circuits (e.g., SoC dies 302) disposed on the same package substrate 304. Each SoC die 302 integrates a subset of the electronic modules of SoC 102 on a corresponding semiconductor substrate. In one example, SoC 102 has a main SoC die including one or more processor cores 604, and accompanying SoC dies including memory 606, analog interfaces, or other components different from the processor cores 604.

[0088] For each power rail 206, the corresponding rail voltage VR is determined by the operation of a corresponding subset of the electronic components of the SOC 102. The power array controller 602 is configured to determine a control value 610 based at least on the corresponding rail voltage VR, and to provide the determined control value 610 to a subset of voltage regulators 402 corresponding to the corresponding power rail 206, thereby enabling the subset of voltage regulators 402 to generate the corresponding rail voltage VR and collectively provide the corresponding rail current IR. Furthermore, in some embodiments, the power array controller 602 provides an operation enable signal 612 to a selected subset of voltage regulators corresponding to each power rail 206 to generate the corresponding rail voltage VR and collectively provide the corresponding rail current IR.

[0089] In some embodiments, the power array controller 602 includes one or more processors and memory having instructions stored thereon that, when executed by the one or more processors, cause the processors to control voltage regulators 402 to output power to a plurality of rails 206. VRU grouping configurations are selectively stored in the memory of the power array controller 602 (e.g., in non-volatile memory 506 (FIG. 5)), the off-chip non-volatile memory (NVM) of the system module 100, or the basic input / output system (BIOS) of the system module 100 to associate control values ​​610 and enable signals 612 with a subset of voltage regulators for each power rail 206. In some cases, the power array controller 602 loads and implements the VRU grouping configuration when the PMIC 220 is powered on.

[0090] Each of the plurality of power rails 206 is configured to power a subset of the electronic modules of the SoC 102, which become the load of the respective power rail 206. For each power rail 206, the power array controller 602 is configured to determine load information 614 corresponding to the expected or actual load on the respective power rail 206, and to determine the corresponding rail current IR associated with the respective power rail based on the load information 614. In some embodiments, the power rails 206 are coupled to a main SoC die having one or more processor cores 604 arranged in clusters, and the load information 614 of the power rails 206 corresponds to processor load information for one or more processor clusters 604 of the main SoC die coupled to the power rails 206. Examples of processor load information include the total number of operations of the type of operation to be performed by the one or more processor clusters 604. Conversely, in some embodiments, one of the power rails 206 is coupled to an accompanying SoC die having memory 606 and is configured to power write and read operations on the memory 606. The load information for the power rail 206 corresponds to the memory load information for memory accesses of the memory 606 accompanying the SoC die. Examples of memory load information include the memory type of the memory 606, the frequency of memory write operations, and the frequency of memory read operations. Therefore, the rail current IR of each power rail 206 is adaptively determined based on the load information 614 of the corresponding power rail 206 (e.g., processor or memory load information).

[0091] Furthermore, in some embodiments, each of the plurality of voltage regulators 402 in the field-programmable array 400 corresponds to a corresponding voltage regulator type selected from a plurality of predefined voltage regulator types. For each power rail 206, the subset of selected voltage regulators 402 corresponds to a corresponding voltage regulator type determined based on at least one performance criterion (e.g., one or more of the following: maximum rail current IRLM, maximum regulator current IRGM, output ripple voltage, power supply rejection ratio, load transient response, output noise, and power efficiency).

[0092] Referring to Figure 6, after selecting a corresponding subset of voltage regulators 402 for each power rail 206, each voltage regulator 402 in the subset is uniquely associated with the corresponding power rail 206 at a specific time. For example, at a first time, power rails 206-1, 206-2, 206-3, and 206-4 are associated with four different sets of voltage regulators 402, as shown in Figure 6. Each voltage regulator 402 in the first row is uniquely associated with power rail 206-1 at the first time, and cannot be associated with any of power rails 206-2, 206-3, and 206-4 at the same first time. However, at a second time, different from the first time, the voltage regulators 402 in the field-programmable array 400 can be reconfigured to power different power rails 206. Each voltage regulator 402 in the first row is uniquely associated with power rail 206-1 at a first time, but can be reconfigured to drive any of power rails 206-2, 206-3, and 206-4 at a second time. More generally, in some embodiments, at least a plurality of voltage regulators 402 in the field-programmable array 400 can be configured to provide power to a selected power rail 206 of the plurality of power rails at any time. Thus, in some embodiments, a subset of voltage regulators 402 is permanently assigned to certain power rails 206, while other subsets are configurable for which power rail 206 they are connected to. In some other embodiments, all voltage regulators 402 in the field-programmable array 400 are configurable for which power rail 206 they are connected to.

[0093] In some cases, one or more voltage regulators 402 (e.g., 402RA-402RD) in the field-programmable array 400 are redundant at a first time. That is, the redundant voltage regulators 402RA-402RD are not coupled to any of the power rails 206 at the first time. At a second time after the first time, each of these redundant voltage regulators 402RA-402RD can be reconfigured to power the corresponding power rail 206. In some embodiments, when a voltage regulator 402 is configured not to power any power rail 206, the voltage regulator 402 is completely de-energized. Instead, in some embodiments, the voltage regulator 402 includes a bypass unit configured to provide a dummy load component. In standby / redundancy mode, the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator 402 (e.g., under the control of the operation enable signal 612), thereby disabling the corresponding voltage regulator 402 from contributing to any rail current IR via the output interface. The following section provides further details about the standby / redundancy mode with reference to Figure 13.

[0094] In some embodiments, the semiconductor device 600 further includes one or more direct current (DC) power interfaces 616. Each DC power interface 616 is configured to receive a different DC supply voltage VIN 202. Each voltage regulator 402 is coupled to a corresponding subset of the one or more DC power interfaces 616 and is configured to be powered by the corresponding DC supply voltage VIN 202 and generate a corresponding rail voltage VR from the corresponding DC supply voltage VIN 202.

[0095] Figure 7A illustrates a procedure 700 according to some embodiments, using a subset of voltage regulators 402 to provide rail current IR at rail voltage VR, and Figure 7B illustrates a procedure 750 according to some embodiments, using one or more redundant voltage regulators 402 to provide rail current IR at rail voltage VR. Rail current IR can vary between 0 and the maximum rail current IRLM. Each voltage regulator in the subset of voltage regulators 402 is configured to provide a regulator current up to the maximum regulator current IRGM. The subset of voltage regulators 402 has a first number of voltage regulators corresponding to the ratio of the maximum rail current IRLM to the maximum regulator current IRGM. For example, in Figure 6, the first power rail 206-1 is required to output the maximum rail current IRLM, and each voltage regulator 402 can provide a corresponding regulator current up to the maximum regulator current IRGM. Based on the maximum rail current IRLM (e.g., 0.6 A) and the maximum regulator current IRGM (e.g., 80 mA), eight voltage regulators are required to provide rail current IR up to the maximum rail current IRLM for the power rail 206-1.

[0096] In some embodiments, a maximum rail current IRLM is applied during the activation of power rail 206 to achieve rail voltage VR within the instantaneous load response time, and power rail 206 subsequently operates with an operating current less than the maximum rail current IRLM. Power rail 206 is configured to achieve rail voltage VR within the instantaneous load response time each time power rail 206 is activated. Sufficient power can be supplied to the power rail to achieve rail voltage VR within the instantaneous load response time by providing a maximum regulator current IRGM and a maximum rail current IRLM during activation, and therefore, the first number of voltage regulators is determined in part based on the instantaneous load response time required for the activation of power rail 206. However, in some embodiments, when the voltage on the corresponding power rail 206 is ramped up when the power rail is activated, the current supplied by the power management system 500 is significantly less than the maximum power rail current for said power rail to reduce system stress, avoid overshoot, etc.

[0097] During operation of power rail 206 (sometimes referred to herein as normal operation, as opposed to enable), the operating current IR supplying power to SoC 102 varies and does not exceed the maximum rail current I RLM. Conversely, in some embodiments, the maximum rail current I RLM is reached at least occasionally during normal operation of power rail 206 when the rail current IR is used to supply power to SoC 102. The operating current varies between 0 and the maximum rail current I RLM. During normal operation, as opposed to enable of power rail 206, a first number of voltage regulators is determined based on the operating current of power rail 206 rather than the instantaneous load response time of power rail 206 each time enable is achieved. The instantaneous load response time of power rail 206 can be achieved through an instantaneous rail current less than the maximum rail current I RLM.

[0098] Referring to Figure 7A, power rail 206 has an instantaneous rail current IR at a given time, regardless of whether the given time corresponds to the activation or normal operation of power rail 206. In some embodiments, power array controller 602 generates a control value 610 and an operation enable signal 612 to enable all voltage regulators in a subset of voltage regulators 402 to collectively provide the instantaneous rail current IR of power rail 206. In other words, the subset of voltage regulators 402 does not operate in standby / redundancy mode because the instantaneous rail IR varies between 0 and the maximum rail current IRLM. For example, the first power rail 206-1 (Figure 6) outputs an instantaneous rail current IR equal to 0.5 IRLM at one time, and all eight voltage regulators configured to provide the maximum rail current IRLM are enabled when controlled by power array controller 602 to collectively provide only 0.5 IRLM. Therefore, in this example, only a portion of the power capacity of each voltage regulator 402 is utilized. In some cases, the rail voltage VR associated with the instantaneous rail current IR differs from the rail voltage VR associated with the maximum rail current IRLM by a first rail voltage error. The power array controller 602 and / or voltage regulator 402 are configured to keep (e.g., limit or control) the first rail voltage error within the rail drift tolerance VRT.

[0099] Furthermore, in some embodiments, a subset of voltage regulators 402 is controlled to contribute substantially equally to the instantaneous rail current IR. For example, each voltage regulator 402 provides a corresponding portion of the instantaneous rail current IR, and said portion varies by less than 5% (or 10%, 20%, or other predefined limits) among voltage regulators 402 configured to provide power to the same power rail 206. Each voltage regulator 402 may include inter-regulator balancing circuitry to balance the portion of the corresponding rail current IR provided by the corresponding voltage regulator 402 with at least another portion of the corresponding rail current IR provided by different voltage regulators 402 within the subset of voltage regulators 402. In some implementations, the inter-regulator balancing circuitry (e.g., 826 in FIG. 8B) is located internally to each voltage regulator 402 and uses the portion of the corresponding rail current IR provided by the corresponding voltage regulator 402 as negative feedback to control said portion of the corresponding rail current IR internally and independently of other voltage regulators configured to provide power to the same power rail 206.

[0100] Referring to Figure 7B, in some embodiments, one or more voltage regulators 402 in a subset of voltage regulators 402 are deactivated and operate in standby / redundancy mode (e.g., under the control of operation enable signal 612), while the remainder of the subset of voltage regulators 402 are activated to collectively provide the instantaneous rail current IR of the corresponding power rail. One or more voltage regulators 402 have a second number of voltage regulators 402, and the second number is determined based on a comparison (e.g., ratio) between the instantaneous rail current IR and the maximum regulator current IRGM, or equivalently based on a comparison (e.g., ratio) between the instantaneous rail current IR and the maximum rail current IRLM. For example, a subset of voltage regulators 402 has 8 voltage regulators, and the second number is equal to a value between 1 and 8. If the instantaneous rail current IR is within a first range (e.g., (0, ...), ... I RLM]), enabling the first voltage regulator 402A to provide the instantaneous rail current IR. If the instantaneous rail current IR increases to more than at the corresponding time. I RLM, I RLM, I RLM, I RLM, I RLM, I RLM and If IRLM is activated, then voltage regulators 402B, 402C, 402D, 402E, 402F, 402G, and 402H are activated at those corresponding times (e.g., gradually or continuously) to provide instantaneous rail current IR within the corresponding rail current range. Furthermore, in some embodiments, when a second number of voltage regulators 402 operate in standby / redundancy mode, the remainder of a subset of voltage regulators 402 are controlled to contribute substantially equally to the instantaneous rail current IR; for example, each activated voltage regulator 402 provides a corresponding portion of the instantaneous rail current IR that varies less than 5% (or 10%, 20%, or other predefined limits) among voltage regulators 402 associated with the same power rail 206.

[0101] In some cases, when one or more voltage regulators 402 operate in standby / redundant mode, the rail voltage VR associated with the instantaneous rail current IR differs from the rail voltage VR associated with the maximum rail current IRLM by a second rail voltage error. This second rail voltage error (e.g., controlled by the power array controller 602 and / or voltage regulator 402) is controlled to keep (e.g., limit or control) the second rail voltage error within the rail drift tolerance VRT. When the same rail current IR is provided using at least one redundant regulator (FIG. 7B) or without using a redundant regulator (FIG. 7A), the second rail voltage error is smaller than the first rail voltage error, and the involvement of the redundant regulator 402 provides higher accuracy for the rail voltage VR with more complex regulator control.

[0102] In some embodiments, each voltage regulator 402 in the field-programmable array 400, FIG. 8A is a block diagram of a voltage regulator 402 as one of the voltage regulators in the field-programmable array 400 according to some embodiments. In the field-programmable array 400, a power rail 206 is electrically coupled to a plurality of voltage regulators 402, which are configured to collectively provide a corresponding rail voltage VR to the power rail. Each voltage regulator 402 includes an output interface 802, one or more drive paths 804, and a voltage regulator controller 806. The output interface 802 is electrically coupled to the power rail 206 to output the rail voltage VR. One or more drive paths 804 are coupled in parallel between the voltage regulator controller 806 and the output interface 802, and each drive path 804 is configured to operate at an operating frequency during its respective phase to provide a corresponding path current IP to the power rail 206. The corresponding path current IP becomes part of the rail current IR injected into the power rail 206. The voltage regulator controller 806 is configured to receive a control value 610 and an operation enable signal 612 from the power array controller 602, and to generate a path control signal 808 to control one or more drive paths 804.

[0103] Voltage regulator 402 includes a feedback path 822 that couples output interface 802 to voltage regulator controller 806. That is, voltage regulator controller 806 has a feedback input 840 configured to receive the output voltage of output interface 802. Voltage regulator controller 806 is configured to dynamically adjust path control signal 808 based on the output voltage of output interface 802 and generate a rail voltage VR defined by control value 610. Specifically, in some embodiments, path control signal 808 defines a duty cycle that voltage regulator controller 806 dynamically adjusts based on a comparison of the output voltage of output interface 802 with the rail voltage VR defined by control value 610.

[0104] Voltage regulator 402 includes a buck converter, i.e., a DC-DC switch-mode converter, which operates based on integrated switches. Each drive path 804 includes a switching component 810 and a pulse width modulation (PWM) driver 812. The PWM driver 812 is coupled between voltage regulator controller 806 and the switching component 810. The PWM driver 812 receives a clock signal 814 (e.g., a multiphase clock 518) and a path control signal 808 to control the switching component 810. Specifically, the path control signal 808 defines a duty cycle, and the clock signal 814 has a frequency equal to the operating frequency of one or more drive paths 804. The PWM driver 812 is configured to modify the clock signal 814 using the path control signal 808 to generate a switching signal 816. The switching component 810 is controlled by the switching signal 816 to turn on and off at the operating frequency according to the duty cycle. Switching component 810 is also coupled to DC power interface 616 and configured to be powered by a corresponding DC supply voltage Vin, which is thus output to switching output 818 of switching component 810 according to the duty cycle and at the operating frequency. Switching output 818 of switching component 810 is further regulated (e.g., filtered) by passive load component 820 (e.g., series inductor) to generate rail voltage VR. Rail voltage is output to power rail 206 via output interface 802. In some implementations, rail voltage VR is substantially constant (e.g., with an output ripple voltage less than the ripple tolerance) and has an average amplitude equal to the product of DC supply voltage Vin, duty cycle, and conversion efficiency of switching component 810.

[0105] Figure 8B is a block diagram of a voltage regulator 402 using current balancing and / or redundancy control according to some embodiments. In some embodiments, the voltage regulator 402 further includes one or more of the following: an intra-regulator balancing circuit 824, an inter-regulator balancing circuit 826, and a bypass unit 828. The intra-regulator balancing circuit 824, the inter-regulator balancing circuit 826, and the bypass unit 828 are located inside the voltage regulator 402. In some embodiments, each individual voltage regulator 402 may independently disable current output, internally balance current, and / or balance its contribution to the rail current IR with other voltage regulators driving the same power rail 206. Specifically, in some embodiments, when the voltage regulator 402 includes multiple drive paths 804, the intra-regulator balancing circuit 824 is coupled between the passive load component 820 of the drive path 804 and at least one of the PWM drivers of the PWM drivers 812 of the drive path 804. The regulator's internal balancing circuit 824 is configured to monitor the drive path 804 (e.g., monitor the current transmitted through the switching assembly 810 and the passive load assembly 820) and control at least one of the PWM drivers in the PWM drivers 812 to adjust at least one duty cycle of the drive path 804 and dynamically balance the corresponding path current of the drive path 804.

[0106] In some embodiments, voltage regulator 402 includes one or more drive paths 804, and inter-regulator balancing circuitry 826 is coupled from passive load assembly 820 and output interface 802 to voltage regulator controller 806. For each voltage regulator 402, inter-regulator balancing circuitry 826 is configured to balance a portion of the corresponding rail current IR provided by the corresponding voltage regulator 402 with at least another portion of the corresponding rail current IR provided by different voltage regulators 402 selected from a subset of voltage regulators 402 to power the same power rail 206 (e.g., based on a portion of the corresponding rail current IR provided by the corresponding voltage regulator itself). Specifically, in some embodiments, inter-regulator balancing circuitry 826 is configured to monitor a portion of the corresponding rail current IR and control path control signal 808 based on said portion of the corresponding rail current IR itself. For each voltage regulator 402, a portion of the corresponding rail current IR transmitted through switching assembly 810 and passive load assembly 820 is monitored by inter-regulator balancing circuitry 826. In some cases, if a portion of the corresponding rail current provided by the corresponding voltage regulator is relatively large, the control path control signal 808 reduces the duty cycle of the drive path 804 (of the corresponding voltage regulator) to suppress said portion of the corresponding rail current IR; if a portion of the corresponding rail current provided by the corresponding voltage regulator is relatively small, the control path control signal 808 increases the duty cycle of the drive path 804 to increase said portion of the corresponding rail current IR.

[0107] Conversely, in some embodiments shown here, the inter-regulator balancing circuit 826 of the first voltage regulator 402 is also coupled to the passive load assembly 820 and the output interface 802 of the second voltage regulator 402, which is different from the first voltage regulator 402, and supplies power to the same power rail 206 in conjunction with the first voltage regulator 402. The inter-regulator balancing circuit 826 is configured to balance a portion of the rail current IR provided by the first voltage regulator 402 with a portion of the rail current IR provided by the second voltage regulator 402 based on a comparison of the portions of the rail current IR provided by the first and second voltage regulators.

[0108] Bypass unit 828 is used to enable standby / redundancy mode, in which voltage regulator 402 is deactivated to contribute to the rail current IR of the corresponding power rail. Standby / redundancy mode is selectively applied when voltage regulator 402 (e.g., 402E in FIG. 6) is applied to drive power rail 206, or when voltage regulator 402 (e.g., 402RA-402RD in FIG. 6) is not applied to drive any power rail 206. Bypass unit 828 is coupled to one or more drive paths 804 and voltage regulator controller 806 and is configured to provide dummy load components (e.g., including passive RC filters) in place of the load coupled to power rail 206. In standby / redundancy mode, bypass unit 828 is enabled to bypass the feedback path 822 from the output interface 802 to the input of voltage regulator controller 806, thereby deactivating the corresponding voltage regulator 402 from contributing to the corresponding rail current IR. In the example shown in Figure 8B, switch 830A is open and inserted into feedback path 822, and switch 830B is open and inserted into the interconnect carrying the switch signal 816 in each drive path 804. In some implementations, each of switches 830A and 830B includes a multiplexer and is controlled by an operation enable signal 612 received by voltage regulator 402. Bypass unit 828 is coupled between switches 830A and 830B in each drive path 804 and is configured to intercept switch signal 816 and decouple voltage regulator controller 806 from power rail 206 and feedback path 822. Thus, bypass unit 828 enables auxiliary path 832 to bypass feedback path 822 in standby / redundancy mode. An example implementation of bypass unit 828 is shown in Figure 13 described below.

[0109] Figure 9 is a circuit diagram of a voltage regulator 402 having multiple drive paths 804 according to some embodiments. A voltage regulator controller 806 is coupled to each of the drive paths 804A-804N and provides a path control signal 808 to each drive path. A feedback path 822 connects the output interface 802 of the drive paths 804A-804N to a feedback input 840 of the voltage regulator controller 806. In some embodiments, the voltage regulator controller 806 includes a digital-to-analog converter (DAC) 902, an error amplifier 904, and amplifier feedback circuitry, and is configured to implement pulse width modulation for the drive paths 804A-804N. The DAC 902 applies a control value 610 to generate a reference voltage 906 received at the input of the error amplifier 904. The amplifier feedback circuitry and the feedback path 822 dynamically control the rail voltage VR output at the output interface 802 to match the reference voltage 906. Specifically, path control signal 808 is generated by voltage regulator controller 806 to control the duty cycle of drive paths 804A-804N to match rail voltage VR and reference voltage 906. In some cases, power array controller 602 also provides operation enable signal 612 to each voltage regulator 402 to enable the generation of a corresponding rail voltage VR and a corresponding rail current IR. Operation enable signal 612 is selectively applied to control (e.g., enable and disable) error amplifier 904 and / or DAC 902.

[0110] Each drive path in drive paths 804A-804N further includes a passive load component 820, a PWM driver 812, and a switching component 810 coupled to the output interface 802. The PWM driver 812 is configured to receive a clock signal 814 having an operating frequency and modulate the clock signal 814 to provide a phased switching signal 816. The power switching component 810 is coupled between the PWM driver 812 and the passive load component 820 and is configured to couple the passive load component 820 to one or more DC supply voltages VIN under the control of the switching signal 816. In some embodiments, the switching component 810 includes a first transistor 810A and a second transistor 810B controlled by the switching signal 816 to couple the passive load component 820 to the DC supply voltage VIN and ground, respectively.

[0111] Figure 10A is a circuit diagram of a voltage regulator 402 according to some embodiments, having two drive paths 804A and 804B balanced by an internal balancing circuit 824. The voltage regulator 402 is one of a plurality of voltage regulators 402 electrically coupled to a power rail 206 and configured to collectively provide a rail voltage VR to the power rail 206. The voltage regulator 402 includes a first drive path 804A, coupled to an output interface 802 and configured to operate at an operating frequency during a first phase to provide a first path current IP1 to the power rail 206. A second drive path 804 is coupled to the output interface 802 and configured to operate at an operating frequency during a second phase to provide a second path current IP2 to the power rail 206. The second drive path 804B is electrically coupled in parallel with the first drive path 804A. In some cases, the first and second phases are identical and have the same duty cycle. In other cases, the first and second phases are different from each other. The first working cycle of the first stage is equal to the second working cycle of the second stage, but offset from it. The first working cycle of the first stage partially overlaps with or completely offsets the second working cycle of the second stage.

[0112] The regulator's internal balancing circuit 824 is coupled to the first drive path 804A and the second drive path 804B, and is configured to sense the first path current IP1 and the second path current IP2, and generate a control signal 1002 based on the difference between the first path current IP1 and the second path current IP2 to control a first duty cycle of a first stage, a second duty cycle of a second stage, or both. For example, if the regulator's internal balancing circuit 824 determines that the first path current IP1 is greater than the second path current IP2, it controls the PWM driver 812A of the first drive path 804A to reduce the first duty cycle to decrease the first path current IP1, or controls the PWM driver 812B of the second drive path 804B to increase the second duty cycle to increase the second path current IP2. In some embodiments, the regulator's internal balancing circuit 824 is always enabled (e.g., by the balancing controller 1004) to dynamically balance the path currents IP1 and IP2 between the two drive paths 804A and 804B. In some embodiments, the regulator's internal balancing circuit 824 is enabled to periodically or in response to instructions received from the SoC 102 to balance the path currents IP1 and IP2 between the two drive paths 804A and 804B.

[0113] In some embodiments, the balancing circuit 824 within the regulator determines that the difference between the first path current IP1 and the second path current IP2 does not satisfy a path current balance criterion. In one example, the path current balance criterion requires that the absolute value of the difference does not exceed a current threshold (e.g., 0.1 mA) or a percentage threshold (e.g., 5%). Based on the determination that the difference between the first path current and the second path current does not satisfy the path current balance criterion and the determination that the first path current is greater than the second path current, the voltage regulator 402 implements one or both of the following: reducing the first duty cycle of the first stage and increasing the second duty cycle of the second stage until the difference between the first path current and the second path current satisfies the path current balance criterion. Alternatively, in some cases, the path current balance criterion requires that the first path current IP1 and the second path current IP2 be equal (i.e., their difference is zero), and whenever the path currents IP1 and IP2 are not equal, the voltage regulator 402 adjusts the first stage of drive path 804A and / or the second stage of drive path 804B.

[0114] The difference between the first path current IP1 and the second path current IP2 is caused by various factors, including mismatches in the PWM driver 812, switching assembly 810, or passive load assembly 820 of the corresponding drive path 804. The internal balancing circuit 824 within the regulator enables the internal analog current balancing loop within each voltage regulator 402 to correct for mismatches in the first drive path 804A and the second drive path 804B without requiring digital signal processing or additional input / output signals. In one example, the analog current balancing loop enabled by the internal regulator balancing circuit 824 includes an integral loop.

[0115] Figure 10B is a circuit diagram of a voltage regulator 402 according to some embodiments, having two or more (e.g., three) drive paths 804 balanced by an in-regulator balancing circuit 824. Similar to drive paths 804A and 804B, at least a third drive path 804C is coupled to the output interface 802 and configured to operate at the operating frequencies of drive paths 804A and 804B during a third phase to provide a third path current IP3 to the power rail 206 in conjunction with the first drive path 804A and the second drive path 804B. The third drive path 804C is electrically coupled in parallel with the first drive path 804A and the second drive path 804B. In some embodiments, the control signal 1002 includes a first control signal 1002A generated based on the difference between the first path current IP1 and the second path current IP2 to control a second operating cycle of the second phase. The regulator's internal balancing circuit 824 is coupled to the third drive path 804C and configured to sense the third path current IP3 and generate a second control signal 1002B based on the difference between the first path current IP1 and the third path current IP3 to control the third operating cycle of the third stage. Through these means, the first path current IP1 is used as a reference, and each of the other drive paths 804 is adjusted so that the corresponding path current matches the first path current IP1.

[0116] Alternatively, in some embodiments, the balance circuit 824 within the regulator is coupled to the third drive path 804C and configured to sense the third path current IP3, and to generate a control signal 1002 based on the difference between the first path current IP1 and the second path current IP2, and based on the difference between the second path current IP2 and the third path current IP3, to control the first duty cycle of the first phase. The first path current IP1 can be adjusted to be between the second path current IP2 and the third path current IP3 to reduce the variation between path currents IP1 and IP3. In some cases, the minimum difference corresponding to the first pair of drive paths 804 is identified among the differences between any pair of drive paths 804A-804C, and the duty cycle of the remaining portion of drive paths 804A-804C is adjusted to a value between the duty cycles of the drive paths in the first pair. Thus, only one duty cycle of the three drive paths 804A-804C is adjusted to enhance the balance between path currents IP1, IP2, and IP3.

[0117] Figure 10C is a circuit diagram of a voltage regulator 402 that uses a differential amplifier 1006 to balance drive paths 804 according to some embodiments. The balancing circuit 824 within the regulator includes one or more differential amplifiers 1006. Each differential amplifier 1006 is coupled to two drive paths in drive path 804. Specifically, the switching outputs 818A and 818B of drive paths 804A and 804B are filtered through low-pass filters 1008A and 1008B coupled to the differential inputs of amplifiers 1006 to remove high-frequency noise from the switching outputs 818A and 818B. The differential amplifier 1006 generates a control signal 1002 based on the switching outputs 818A and 818B to control a first duty cycle of a first stage, a second duty cycle of a second stage, or both. The control signal 1002 is selectively a single-ended signal or a differential signal. Therefore, if enabled, the differential amplifier 1006 adjusts the first stage of drive path 804A and / or the second stage of drive path 804B whenever the path currents IP1 and IP2 are unbalanced.

[0118] Figure 11A is an equivalent circuit diagram 1100 of a power rail 206 driven by two voltage regulators 402 in a field-programmable array 400 of voltage regulators according to some embodiments. For inter-regulator current balancing, each voltage regulator 402 is simplified and corresponds to a voltage source 1110 according to a voltage source model. The power rail 206 powered by these voltage regulators 402 is configured to power a subset of the SoC 102. For each voltage regulator 402, an output interface 802 is physically located within the package outline of the corresponding voltage regulator 402 and connected to the power rail 206 via a first interconnect 1102 having a resistor Rline1 that selectively includes the parasitic resistance of the first interconnect 1102. In some cases, the first interconnects 1102 of the voltage regulators 402 are merged at a regulator header 1104 (e.g., DC connection 308 in Figure 4B) to form the power rail 206. In some cases, the first interconnects 1102 of three or more voltage regulators 402 are merged at more than one regulator connector 1104 to form a power rail 206. Optionally, more than one regulator connector 1104 is used with additional interconnects connecting more than one regulator connector 1104. Optionally, the common regulator connector 1104 is determined by adjusting the equivalent resistance of the first interconnects 1102 of the voltage regulators 402 supplying power to the power rail 206. The power rail 206 is routed from regulator connector 1104 using a distributed resistance Rline2, which optionally includes the parasitic resistance of the power rail 206. Each voltage regulator 402 has an output impedance Ro1106.

[0119] In some embodiments, the mismatch between the two voltage regulators 402 corresponds to an internal error in one or more of the voltage regulators 402, for example, an internal error caused by a reference voltage error of the DAC 902 and / or an offset voltage of the error amplifier 904 of the voltage regulator controller 806. The resistance Rline1 of the first interconnect 1102 is negligible. The distributed resistance Rline2 of the power rail 206 does not affect the mismatch between the two voltage regulators 402. In some embodiments, the output current of each voltage regulator 402 is sensed and used to control the offset input of the error amplifier 904, thereby canceling the offset voltage of the error amplifier 904. In some implementations, a modulator 1108 is integrated into each voltage regulator 402 to compensate for the internal error of the respective voltage regulator 402. For example, the modulator 1108 is implemented as the inter-regulator balancing circuit 826 in FIG. 8B, FIG. 12A, or FIG. 12B.

[0120] In some embodiments, modulator 1108 includes a low-pass filter (LPF) 1112. Figure 11B is an equivalent circuit diagram 1150 of a single voltage regulator 402 using LPF 1112 for inter-regulator current balancing according to some embodiments. The voltage drop across the output impedance Ro1106 of voltage regulator 402 corresponds to the output current of voltage regulator 402, i.e., a portion of the rail current IR contributed by voltage regulator 402. The voltage drop is extracted, filtered through LPF 1112 to reduce high-frequency noise, and applied to voltage regulator controller 806 (e.g., error amplifier 904) with a scaling factor (e.g., 1). LPF 1112 enables negative feedback to cancel and compensate for internal errors of voltage regulator 402. The current balancing configuration is implemented internally to voltage regulator 402 without requiring any input or control from other voltage regulators 402 driving the same power rail 206 or power array controller 602.

[0121] Figures 12A and 12B are circuit diagrams of a voltage regulator 402 controlled by an inter-regulator balancing circuit 826 according to some embodiments. The inter-regulator balancing circuit 826 is coupled to the output interface 802 and the voltage regulator controller 806, and is configured to sense the output current of the corresponding voltage regulator 402 and apply an offset 1202 to the control input of the voltage regulator controller 806. The offset 1202 is determined based on the sensed output current of the voltage regulator 402. In some embodiments, the voltage regulator controller 806 includes an error amplifier 904 configured to receive the control input and apply the offset 1202 between the feedback input 840 and a control value defining the rail voltage of the power rail 206 powered by the voltage regulator 402.

[0122] Referring to FIG12A, in some embodiments, an inter-regulator balancing circuit 826 is coupled to the output inductor 1204 of the passive load assembly 820, which is coupled at the output interface 802. The inter-regulator balancing circuit 826 is configured to sense the output current of the voltage regulator 402 based on the voltage drop across the output inductor 1204. Alternatively, in some embodiments, an output resistor 1206 having a much smaller resistance (e.g., less than the threshold resistance) is coupled in series at the output interface 802. The inter-regulator balancing circuit 826 is coupled to the output interface 802 via the output resistor 1204 and senses the output current of the voltage regulator 402 from the voltage drop across the output resistor 1204. Therefore, the inter-regulator balancing circuit 826 is configured to sense the output current of the voltage regulator 402 and apply an offset 1202 to the control input received by the voltage regulator controller 806. Offset 1202 is determined directly based on the output current of voltage regulator 402 (specifically based on the voltage drop across output inductor 1204 or output resistor 1206).

[0123] Referring to FIG12B, in some embodiments, the voltage regulator 402 includes multiple drive paths 804 having path currents selectively balanced with each other. In some embodiments, an inter-regulator balancing circuit 826 is coupled to a path inductor 1208 of a passive load component 820 in one of the drive paths 804. The inter-regulator balancing circuit 826 is configured to sense one of the multiple path currents IP of the voltage regulator 402 based on the voltage drop across the path inductor 1208. Alternatively, in some embodiments, a path resistor 1210 having a much smaller resistance (e.g., less than a threshold resistance) is coupled in series in one of the drive paths 804. The inter-regulator balancing circuit 826 is coupled to the path resistor 1210 and indirectly senses and determines the output current of the voltage regulator 402 from the voltage drop across the path resistor 1210. In other words, the inter-regulator balancing circuit 826 is configured to sense one of the multiple path currents IP of the voltage regulator 402 and apply an offset 1202 to the control input received by the voltage regulator controller 806. The offset 1202 is determined based on the sensed path current among the multiple path currents IP (specifically, based on the voltage drop across the path inductor 1208 or the path resistor 1210).

[0124] In some embodiments, the inter-regulator balancing circuit 826 includes two LPFs, each coupled to one of the following: output inductor 1204, output resistor 1206, path inductor 1208, and path resistor 1210. Offset 1202 is determined based on the DC and low-frequency portions of the output current of the voltage regulator 402.

[0125] In some embodiments, the voltage regulator 402 includes an intra-regulator balancing circuit 824 (not shown in FIG. 12B) configured to balance path currents IP1 and IP2, and an inter-regulator balancing circuit 826 configured to control the output current of the voltage regulator 402 (i.e., the corresponding portion of the rail current IR supplied to the power rail 206 associated with the voltage regulator 402). In some embodiments, the voltage regulator 402 includes only one of the intra-regulator balancing circuit 824 and the inter-regulator balancing circuit 826.

[0126] Figure 13 is a circuit diagram of a voltage regulator 402 of a field-programmable array 400 having a voltage regulator with an auxiliary loop 1302 for controlling redundancy, according to some embodiments. As explained above, the voltage regulator 402 has a standby / redundancy mode, wherein the voltage regulator 402 (e.g., 402RA-402RD) is not enabled to power any power rail 206, or wherein the voltage regulator 402 (e.g., 402H in Figure 7B) is used to drive the power rail 206 but is temporarily deactivated from contributing to the corresponding rail current IR of the power rail 206. In some embodiments, regardless of whether the voltage regulator 402 is coupled to any power rail 206, the voltage regulator 402 includes an output interface 802, one or more drive paths 804, a voltage regulator controller 806, and a bypass unit 828. The voltage regulator controller 806 has an output coupled to one or more drive paths 804 and a feedback input 840 coupled to the output interface 802 through a feedback path 822. Bypass unit 828 is coupled to one or more drive paths 804 and voltage regulator controller 806 and is configured to provide dummy load component 1304. In standby / redundancy mode, when bypass unit 828 is enabled, auxiliary loop 1302 bypasses the feedback path 822 from output interface 802 to the input of voltage regulator controller 806 and drives dummy load component 1304 using one or more switching components 1306. Therefore, auxiliary loop 1302 includes bypass unit 828 and is enabled in standby / redundancy mode to replace feedback path 822 to disable voltage regulator 402 from contributing to the corresponding rail current IR of power rail 206.

[0127] In standby / redundancy mode, bypass unit 828 is enabled to bypass the switching assembly 810 and passive load assembly 820 of each drive path 804. Each drive path 804 also includes a multiplexer or switch 830B coupled to the PWM driver 812, the switching assembly 810, and the bypass unit 828. The multiplexer or switch 830B is configured to select the bypass unit 828 and deselect the switching assembly 810, and electrically couple the PWM driver 812 to the bypass unit 828 in standby / redundancy mode. Voltage regulator 402 also includes a multiplexer or switch 830A coupled between the feedback input 840 of voltage regulator controller 806 and the output interface 802. The multiplexer or switch 830A is configured to operate simultaneously with the multiplexer or switch 830B of each drive path 804 to select the bypass unit and deselect the output interface 802 for the input of voltage regulator controller 806. In some embodiments, the operation enable signal 612 is used to simultaneously control multiplexer or switch 830A, multiplexer or switch 830B, and dummy load component 1304 to enable standby / redundancy mode. Through these means, in standby / redundancy mode, the switching component 810 and passive load component 820 of each drive path 804 are disabled, while the voltage regulator controller 806 and the PWM driver 812 of each drive path 804 operate together with the dummy load component 1304 and the switching component 1306.

[0128] In summary, when the voltage regulator 402 is in standby / redundancy mode, the auxiliary loop 1302 is used to decouple the output interface 802 without completely shutting down the voltage regulator 402. The voltage regulator controller 806 and the PWM driver 812 of the drive path 804 are operable, allowing the voltage regulator 402 to wake up quickly upon recovery from standby / redundancy mode and maintain the desired instantaneous response time. Furthermore, the switching component 810 of the drive path 804 is decoupled and disabled, and the dummy load component 1304 and the switching component 1306 are designed to consume less power than the switching component 810 and the load component 820 of the drive path 804. This efficiently saves power consumption of the voltage regulator 402 in standby / redundancy mode. Conversely, when the auxiliary loop 1302 is not used to enable the standby / redundancy mode of the voltage regulator 402, the voltage regulator controller 806 and the PWM driver 812 of the drive path 804 are disabled to enable the standby / redundancy mode. Voltage regulator 402 is completely off in standby / redundant mode and must be reactivated each time it resumes from standby / redundant mode to contribute to the corresponding rail current IR of the power rail 206 that needs to be powered by voltage regulator 402. The reactivation procedure when voltage regulator 402 resumes from standby / redundant mode is typically slow and impairs its transient response time.

[0129] The terminology used in the various implementations described herein is for the purpose of describing a particular implementation only and is not intended to be limiting. As used in the various implementations described herein and in the descriptions of the appended claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will also be understood that the term “and / or,” as used herein, is intended to include any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “includes,” “including,” “comprises,” and / or “comprising,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, it will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0130] As used herein, the term “if” is selectively interpreted to mean “when,” “at,” “in response to a decision,” “in response to detection,” or “according to a decision,” depending on the context. Similarly, the phrases “if a decision” or “if [the condition or event] is detected” are selectively interpreted to mean “when a decision is made,” “in response to a decision,” “when [the condition or event] is detected,” “in response to the detection of [the condition or event],” or “according to a decision that [the condition or event] is detected,” depending on the context.

[0131] The above description has been provided with reference to specific implementations. However, the illustrative discussion above is not intended to be exhaustive or limited to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. These implementations were chosen and described in order to best explain the disclosed principles and their practical applications, thereby enabling others to best utilize the contents of this disclosure and various implementations with various modifications suitable for the specific intended use.

[0132] 100: System Module 102: System-on-a-Chip (SoC) 104: Memory Module 106: Input / Output (I / O) Controller 108: Network Interface 110: Memory controller 112: Solid State Drive (SSD) 114: Hard Disk Drive 116: Power connector 118: Power Management Integrated Circuit (PMIC) 120: Graphics Module 122: Sound Module 150: Communication Bus 200: Power Management System 202: Input DC power supply voltage 204: Digital power control signal 206: Power Rail 206-1: First power rail 206-2: Second power rail 206-3: Power Rail 206-4: Power Rail 206A: Power Rail 206B: Power Rail 206N: Power rail 208: Power Management Interface 210A: DC-DC Converter 210B: DC-DC Converter 210N: DC-DC converter 212A: Output Filter 212B: Output Filter 212N: Output Filter 214: Output resistor 216A: Capacitor 216B: Capacitor 216N: Capacitor 218: Inductor 218': Inductor 220: PMIC grains 300: Integrated Semiconductor Equipment 302: SoC die 304: Packaging substrate 304A: First surface 304B: Second Surface 306: First through-hole interconnect 308: DC Connection 312: Power Connection 314: Capping 316: Radiator 318: Socket baseboard 318A: Third Surface 320: Electrical connector 322: Depressed portion 324: First Intermediary Layer 326: Second through-hole interconnect 328: Second Intermediary Layer 330A: Component 330B: Component 332: Third through-hole interconnect 400: Field Programmable Array 402: Voltage Regulator 402E: Voltage Regulator 402RA: Voltage Regulator 402RB: Voltage Regulator 402RC: Voltage Regulator 402RD: Voltage Regulator 404: Analog-to-Digital Converter (ADC) 406: Analog Register 408: Oscillator 410: Static Random Access Memory (SRAM) Array 412: Phase-locked loop (PLL) circuit 414: Low Dropout Voltage Regulator (LDO) 416: Interconnection 420: Cluster 420A:Cluster 420B: Cluster 420C: Cluster 420D: Cluster 500: Power Management System 502: SoC Interface 506: Temporary Register 508: Microcontroller 510: Internal clock signal 512: External clock signal 514: Clock Selection Signal 516: System Clock 518: Multiphase Clock 520: Frequency divider 522: Additional rail voltage 524: Reference Generator 526: Fuse 528: Thermal shutdown module 532: Finite State Machine 600: Integrated Semiconductor Equipment 602: Power Array Controller 604: Processor Cluster 606: Memory 608: Communication Module 610: Control value 612: Operation Enable Signal 614: Load Information 616: DC Power Interface 700: Program 750: Program 802: Output Interface 804: Driver Path 804A: Driver Path 804B: Driver Path 804C: Driver Path 804N: Drive path 806: Voltage Regulator Controller 808: Path control signal 810: Switching assembly 810A: First Transistor 810B: Second Transistor 812: PWM driver 814: Clock signal 816: Switch signal 818: Switch Output 818A: Switch Output 818B: Switch Output 820: Passive Load Component 822: Feedback Path 824: Balance circuit inside the regulator 826: Balance circuit between regulators 828: Bypass Unit 830A: Switch 830B: Switch 832: Auxiliary Path 840: Feedback Input 902: Analog Converter (DAC) 904: Error Amplifier 906: Reference Voltage 1002: Control signal 1002A: First control signal 1002B: Second control signal 1004: Balance Controller 1006: Differential Amplifier 1008A: Low-pass filter 1008B: Low-pass filter 1100: Equivalent Circuit Diagram 1102: First Interconnect 1104: Regulator Connector 1106: Output impedance 1108: Modulator 1110: Voltage source 1112: Low-pass filter (LPF) 1150: Equivalent Circuit Diagram 1202: Offset 1204: Output Inductor 1206: Output resistor 1208: Path Inductor 1210: Path resistor 1302: Auxiliary circuit 1304: Virtual Load Balancing Component 1306: Switch assembly

Claims

1. An integrated semiconductor device, comprising: A plurality of voltage regulators electrically coupled to a power rail and configured to provide a rail voltage via the power rail, each of the plurality of voltage regulators further comprising: an output interface electrically coupled to the power rail; a first drive path coupled to the output interface and configured to operate at an operating frequency during a first phase to provide a first path current to the power rail; a second drive path coupled to the output interface and configured to operate at the operating frequency during a second phase to provide a second path current to the power rail, wherein the second drive path is electrically coupled in parallel with the first drive path; and an internal balancing circuit coupled to the first drive path and the second drive path, the internal balancing circuit being configured to: sense the first path current and the second path current, and generate a first control signal based on the difference between the first path current and the second path current to control a first duty cycle of the first phase and / or a second duty cycle of the second phase; A voltage regulator controller having an output coupled to the first drive path and the second drive path and an input coupled to the output interface through a feedback path, and configured to control the one or more drive paths; and a bypass unit coupled to the first drive path, the second drive path, and the voltage regulator controller, and configured to provide a virtual load component, wherein the respective voltage regulator has a standby / redundancy mode in which the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller.

2. The integrated semiconductor device according to claim 1, wherein, The regulator's internal balancing circuit is configured to: determine that the difference between the first path current and the second path current does not satisfy the path current balance criterion; and, based on the determination that the difference between the first path current and the second path current does not satisfy the path current balance criterion and the determination that the first path current is greater than the second path current, to achieve one or both of the following: reduce the first operating cycle of the first stage and increase the second operating cycle of the second stage until the difference between the first path current and the second path current satisfies the path current balance criterion.

3. The integrated semiconductor device according to claim 1, wherein each of the plurality of voltage regulators further comprises: A voltage regulator controller having a feedback input coupled to the output interface, the feedback input of the voltage regulator controller being configured to receive the output voltage of the output interface.

4. The integrated semiconductor device according to claim 3, wherein each of the plurality of voltage regulators further comprises: An inter-regulator balancing circuit coupled to the output interface and the voltage regulator controller is configured to sense the output current of the respective voltage regulator and apply an offset to the control input of the voltage regulator controller, wherein the offset is determined based on the sensed output current of the respective voltage regulator.

5. The integrated semiconductor device according to claim 4, wherein, The voltage regulator controller includes an error amplifier configured to receive the control input and apply the offset between the feedback input and a control value that defines the rail voltage.

6. The integrated semiconductor device according to claim 3, wherein each of the plurality of voltage regulators further comprises: An inter-regulator balancing circuit coupled to the output interface and the voltage regulator controller is configured to: sense one of the first path current and the second path current of the respective voltage regulator, and apply an offset to a control input received by the voltage regulator controller, the offset being based on one of the sensed first path current and the second path current.

7. The integrated semiconductor device according to any one of claims 1 to 6, wherein, Each of the first and second drive paths further includes: a switching component coupled to the input supply voltage Vin and the output interface; and a driver coupled to the switching component and configured to enable the switching component at the operating frequency during a corresponding phase of the first and second phases, thereby providing a corresponding path current of the first path current and the second path current to the power rail.

8. The integrated semiconductor device according to any one of claims 1 to 6, wherein, The first working cycle of the first stage is equal to the second working cycle of the second stage, and the second stage is offset from the first stage.

9. The integrated semiconductor device according to any one of claims 1 to 6, wherein: The control signal includes a first control signal generated based on the difference between the first path current and the second path current to control the second duty cycle of the second phase; each of the plurality of voltage regulators further includes a third drive path coupled to the output interface and configured to operate at the operating frequency during the third phase to provide a third path current to the power rail, the third drive path being electrically coupled in parallel with the first drive path and the second drive path; and a balancing circuit within the regulator is coupled to the third drive path and configured to sense the third path current and generate a second control signal based on the difference between the first path current and the third path current to control the third duty cycle of the third phase.

10. The integrated semiconductor device according to any one of claims 1 to 6, wherein: Each of the plurality of voltage regulators further includes a third drive path coupled to the output interface and configured to operate at the operating frequency during the third phase to provide a third path current to the power rail, the third drive path being electrically coupled in parallel with the first drive path and the second drive path; and an internal balancing circuit coupled to the third drive path and configured to sense the third path current and generate the first control signal based on the difference between the first path current and the second path current and based on the difference between the first path current and the third path current to control the first duty cycle of the first phase.

11. The integrated semiconductor device according to claim 1, wherein, Each of the first and second drive paths further includes: a passive load component coupled to the output interface; a driver configured to: receive a clock signal having an operating frequency and modulate the clock signal to provide a phased switching signal; and a power switch component coupled to the driver and the passive load component, the power switch component being configured to couple the passive load component to one or more DC supply voltages under the control of the switching signal.

12. The integrated semiconductor device according to claim 11, wherein, In the standby / redundancy mode, the bypass unit is enabled to bypass the power switch assembly and the passive load assembly of each drive path, and each drive path in the first drive path and the second drive path further includes: a multiplexer coupled to the driver, the power switch assembly and the bypass unit, wherein the multiplexer is configured to select the bypass unit and deselect the power switch assembly and electrically couple the driver to the bypass unit in the standby / redundancy mode.

13. The integrated semiconductor device according to any one of claims 1 to 6, further comprising: The power rail is configured to provide the rail voltage.

14. An electronic system comprising: Power rails, which are configured to provide rail voltage; And integrated semiconductor devices as described in claim 1.

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