Photoresist development with organic vapor

Abstract

The development of resists can be used, for example, to form patterned masks against a high-resolution patterned background. Development can be performed using organic vapors (e.g., carboxylic acids). In some embodiments, the organic vapor is trifluoroacetic acid. In some embodiments, the organic vapor is hexafluoroacetate. Metal-containing resist films (e.g., EUV-sensitive organometallic oxides) can be deposited on semiconductor substrates using dry or wet deposition techniques. The metal-containing resist films on the semiconductor substrates can be developed using organic vapors, or residues of metal-containing resist material formed on the surface of the process chamber can be removed using organic vapors.

Description

Technical Field

[0001] This invention relates to photoresist development using organic vapors. Prior Technology

[0002] The fabrication of semiconductor devices (such as integrated circuits) involves a multi-step process involving photolithography. Generally, this process includes depositing material on a wafer and patterning the material using photolithography techniques to form structural features of the semiconductor device (such as transistors and circuits). Typical photolithography processes known in the art include the following steps: preparing a substrate; coating photoresist, for example by spin coating; exposing the photoresist to a desired pattern, making the exposed areas of the photoresist more soluble or less soluble in a developing solution; developing the photoresist by removing the exposed or unexposed areas using a developing solution; and subsequent processing to establish features on the photoresist-removed substrate area, such as through etching or material deposition.

[0003] The development of semiconductor design has created and is driven by the need to form smaller features on semiconductor substrate materials. This technological advancement is characterized by Moore's Law, which states that the transistor density in densely integrated circuits doubles every two years. More precisely, advances in chip design and manufacturing have enabled modern microprocessors to contain billions of transistors and other circuit features on a single chip. These individual features on such chips can be approximately 22 nanometers (nm) or smaller, and in some cases less than 10 nm.

[0004] One challenge in fabricating devices with such small features is the ability to reliably and repeatedly form photolithography masks with sufficient resolution. Currently, photolithography processes typically use 193 nm ultraviolet (UV) light to expose the photoresist. The fact that the wavelength of the light is significantly larger than the desired size of the feature to be formed on the semiconductor substrate presents inherent problems. Achieving feature sizes smaller than the light wavelength requires sophisticated resolution enhancement techniques, such as multiple patterning. Therefore, there is significant interest and research progress in developing photolithography techniques using shorter wavelengths of light (e.g., extreme ultraviolet radiation (EUV)) with wavelengths of 10 nm to 15 nm (e.g., 13.5 nm).

[0005] However, EUV photolithography can present challenges, including low power output and light loss during patterning. Conventional organic chemical amplifying resists (CARs), similar to those used in 193 nm UV photolithography, have potential drawbacks when used in EUV photolithography, particularly due to their low absorption coefficients in the EUV region and the diffusion of photoactivated chemicals leading to blurring or line edge roughness. Furthermore, to provide the etch resistance required for patterning the underlying device layer, small features patterned in conventional CAR materials can result in high aspect ratios that risk pattern collapse. Therefore, improved EUV photoresist materials with properties such as reduced thickness, higher absorbance, and greater etch resistance are still needed.

[0006] The background description provided herein is for the purpose of outlining the technical context. The inventors’ work (within the scope described in the prior art paragraphs) and descriptions that may not have been otherwise considered prior art at the time of application are not expressly or impliedly acknowledged as prior art to this technology. Summary of the Invention

[0007] This article provides a method for developing a photopatterned metal-containing resist. The method includes providing a photopatterned metal-containing resist on the surface of a semiconductor substrate in a process chamber, and dry developing the photopatterned metal-containing resist, which selectively removes a portion of the photopatterned metal-containing resist by exposing it to a developing chemical substance containing organic vapors to form a resist mask.

[0008] In some embodiments, the organic vapor comprises a carboxylic acid. In some embodiments, the organic vapor comprises trifluoroacetic acid. In some embodiments, the organic vapor comprises trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chloro-difluoro-acetic acid, thioacetic acid, or mercaptoacetic acid. In some embodiments, the organic vapor comprises hexafluoroacetyl acetone. In some embodiments, the developing chemical comprises a gaseous mixture of a halogenated carboxylic acid and a hydrogen halide. In some embodiments, dry development of a photopatterning metal-containing resist comprises reacting the organic vapor with the photopatterning metal-containing resist at a temperature below about 200°C to form a volatile compound. In some embodiments, dry development of a photopatterning metal-containing resist comprises exposure to at least the organic vapor during a plasma-free thermal process. In some embodiments, the photopatterning metal-containing resist is a photopatterning metal-containing EUV resist, wherein the photopatterning metal-containing EUV resist is an organometallic oxide or contains an organometallic film. In some embodiments, dry development of optically patterned metal resists includes using the developing chemical to selectively remove the unexposed EUV portions of the optically patterned metal resists relative to the EUV-exposed portions, thereby forming a resist mask.

[0009] This document also provides a method for removing residues from one or more surfaces of a process chamber. The method includes depositing a metal resist material on the surface of a semiconductor substrate in the process chamber, wherein a portion of the metal resist material forms residues on one or more surfaces of the process chamber, and introducing a dry etchant containing organic vapor into the process chamber, wherein the dry etchant at least partially removes the residues on the one or more surfaces of the process chamber.

[0010] In some embodiments, the organic vapor comprises a carboxylic acid. In some embodiments, the organic vapor comprises trifluoroacetic acid. In some embodiments, the organic vapor comprises trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chloro-difluoro-acetic acid, thioacetic acid, or mercaptoacetic acid. In some embodiments, the organic vapor comprises hexafluoroacetyl acetone. In some embodiments, the dry etchant comprises a gaseous mixture of a halogenated carboxylic acid and a hydrogen halide. In some embodiments, at least partial removal of the residue comprises reacting the organic vapor with a metal-containing resist material at a temperature below about 200°C to form a volatile compound. In some embodiments, at least partial removal of the residue comprises exposure to at least the organic vapor during plasmaless heat treatment. In some embodiments, the metal-containing resist material is an organometallic oxide or an organometallic film. In some embodiments, the method further includes rinsing the process chamber after the introduction of the dry etchant to remove residual dry etchant from the process chamber, and conditioning the one or more surfaces of the process chamber by forming a protective coating containing a metal resist material on the one or more surfaces of the process chamber. Simple Explanation of the Diagram

[0011] Figure 1 presents a flowchart of an example method for depositing and developing photoresist according to some embodiments.

[0012] Figure 2 presents a flowchart of an example method for dry development of a metal resist according to some embodiments.

[0013] Figures 3A-3C show cross-sectional schematic diagrams of various processing stages of dry development according to some embodiments.

[0014] Figure 4A shows a cross-sectional schematic diagram of dry development without the application of inert gas plasma according to some embodiments.

[0015] Figure 4B shows a schematic cross-sectional view of dry development using circulating inert gas plasma for slag removal according to some embodiments.

[0016] Figure 5 presents a flowchart of an example method for dry chamber cleaning according to some implementations.

[0017] Figures 6A-6D show cross-sectional schematic diagrams of various processing stages of dry chamber cleaning according to some embodiments.

[0018] Figure 7 illustrates a schematic diagram of an exemplary process station according to some embodiments, which is suitable for performing dry development, cleaning, reprocessing, descaling and smoothing operations.

[0019] Figure 8 illustrates an exemplary multi-station processing tool suitable for performing many of the dry development, cleaning, reprocessing, descaling, and smoothing operations described herein.

[0020] Figure 9 shows a schematic cross-sectional view of an exemplary inductively coupled plasma device for implementing some of the embodiments and operations described herein.

[0021] Figure 10 illustrates a semiconductor process cluster tool architecture with a vacuum-integrated deposition and patterning module (connected to a vacuum transfer module), suitable for implementing the processes described herein.

[0022] Figure 11A shows a cross-sectional schematic diagram of an example of a dry deposition apparatus according to some embodiments.

[0023] Figure 11B shows a detailed side and plan view of a portion of the top plate, substrate, and edge ring of a dry deposition apparatus according to some embodiments. Implementation

[0024] This invention generally relates to the field of semiconductor processing. In a particular embodiment, the invention pertains to processes and apparatuses for developing photoresists (such as EUV-sensitive metal- and / or metal oxide-containing photoresists) using organic vapors (e.g., organic acids) to form patterned masks, for example, against a background of EUV patterning or patterning at other wavelengths. Although the following discussion may focus on EUV photoresists, it will be apparent that the photoresists discussed herein are also applicable to radiation at other wavelengths, and that the techniques and apparatus discussed herein are not limited to EUV photoresist manufacturing.

[0025] Detailed reference is made to specific embodiments of the present invention herein. Examples of specific embodiments are shown in the accompanying drawings. Although the invention will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to these specific embodiments. Rather, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention. In the following description, numerous specific details are set forth to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known process operations are not described in detail so as not to unnecessarily obscure the invention. [introduce]

[0026] Thin film patterning in semiconductor processing is often an important step in semiconductor manufacturing. Patterning involves photolithography. In conventional photolithography, such as 193 nm photolithography, the pattern is printed by emitting photons from a photon source onto a mask and printing the pattern onto a photosensitive photoresist, thereby inducing a chemical reaction in the photoresist. After development, some portions of the photoresist are removed to form the pattern.

[0027] Advanced technology nodes (as defined in the International Semiconductor Technology Roadmap) include nodes of 22 nm, 16 nm, or beyond. For example, in the 16 nm node, the width of a typical via or line in a damascene structure is typically no greater than about 30 nm. The miniaturization of features on advanced semiconductor integrated circuits (ICs) and other devices is driving lithography to improve resolution.

[0028] Extreme ultraviolet (EUV) lithography extends lithography techniques by moving to imaging source wavelengths smaller than those achievable with conventional optical lithography methods. EUV sources with wavelengths of approximately 10–20 nm or 11–14 nm (e.g., 13.5 nm) can be used in leading-edge lithography tools, also known as scanners. EUV radiation is strongly absorbed in a wide range of solid and fluid materials, including quartz and water vapor, and therefore can be operated in a vacuum.

[0029] EUV lithography utilizes EUV resists, which are patterned to form a mask for etching the underlying layer. The EUV resist is a polymer-based chemically amplified resist (CAR) produced via a liquid-based spin coating technique. These EUV resists may include any EUV-sensitive film or material described herein. An alternative to CAR is a directly photo-patternable metal oxide film, for example, available from Inpria (Corvallis, Oregon) and described, for example, in U.S. Patent Publications Nos. US 2017 / 0102612, US 2016 / 021660, and US 2016 / 0116839, which, by reference and herein, at least disclose photo-patternable metal oxide films. These films can be produced via spin coating or dry vapor deposition. Metal oxide films can be directly patterned in a vacuum environment via EUV exposure (i.e., without the use of separate photoresist), providing a patterning resolution of less than 30 nm. This is described, for example, in U.S. Patent No. 9,996,004, published June 12, 2018, entitled "EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS," and / or in International Application No. PCT / US19 / 31618, filed May 9, 2019, entitled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," the disclosures of which (at least regarding the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks) are incorporated herein by reference. Generally, patterning involves exposing an EUV resist to EUV radiation to form a light pattern in the resist, followed by development according to the light pattern to remove a portion of the resist to form a mask.

[0030] It should also be understood that although this invention relates to lithography patterning techniques and materials, exemplified by EUV lithography, it can also be applied to other next-generation lithography technologies. Besides EUV, including the currently used and developed standard 13.5 nm EUV wavelength, the radiation sources most relevant to such lithography are DUV (deep UV), which generally refers to excimer laser sources using 248 nm or 193 nm, X-rays (which in turn include EUV at lower energy levels within the X-ray range), and electron beams (which can cover a wider energy range). Specific methods may depend on the specific materials and applications used in the semiconductor substrate and the final semiconductor device. Therefore, the methods described in this application are merely examples of methods and materials that can be used in this technology.

[0031] Directly photomable patternable EUV resists can be composed of or contain metals and / or metal oxides. Metals / metal oxides are promising due to their ability to enhance EUV photon absorption and generate secondary electrons, and / or exhibit greater etch selectivity relative to the underlying film stack and device layers. To date, these resists have been developed using wet (solvent) methods, which require moving the wafer to a development track where it is exposed to a developing solvent, followed by drying and baking. Wet development not only limits productivity but also leads to line collapse due to surface tension effects and / or delamination.

[0032] Dry development techniques have been proposed to overcome these problems by eliminating substrate delamination and interfacial cracking. Dry development can improve the performance of narrower linewidths (e.g., preventing line collapse caused by surface tension and delamination that occurs in wet development) and may increase throughput (e.g., by eliminating the need for a wet developer). Other advantages may include eliminating the use of organic solvent developers, reducing sensitivity to substrate adhesion, and removing solubility-based limitations. Dry development also provides greater adjustability and allows for further critical dimension (CD) control and residue removal.

[0033] Dry development presents its own challenges, including the etching selectivity between unexposed and EUV-exposed resist materials. Compared to wet development, it may result in a higher dose-to-size requirement for effective resist exposure. Suboptimal selectivity may also lead to rounded PR corners due to lower contrast at feature edges, which could increase line CD variation in subsequent transfer etching steps. Dry removal containing metal inhibitors

[0034] According to various embodiments of the present invention, photopatterning of metal-containing photoresist systems is achieved by exposure to vapors of organic acids or other gaseous precursors. An EUV-sensitive metal-containing or metal oxide film (e.g., organotin oxide) is disposed on a semiconductor substrate. The EUV-sensitive metal-containing or metal oxide film system is directly patterned by EUV exposure in a vacuum environment. The pattern is then developed using developing chemicals to form a resist mask. In some embodiments, the developing chemicals are dry developing chemicals. In some embodiments, the dry developing chemicals include organic vapors, such as trifluoroacetic acid. These dry developing techniques can be performed while allowing organic vapors to flow into processes currently utilizing mild plasma (high voltage, low power) or non-plasma thermal processes. Additionally or alternatively, the present invention provides dry chamber cleaning of EUV resist materials or metal-containing resist materials from the inner surface of the process chamber by exposure to organic acids or other gaseous precursors. In some embodiments, the organic vapor is trifluoroacetic acid. Dry cleaning can be a non-plasma thermal cleaning operation. Dry chamber cleaning can be performed in any process chamber used for deposition, beveled edge and / or backside cleaning, baking, developing or etching operations.

[0035] Many embodiments of the present invention may include combining all dry operations through vapor deposition, EUV lithography patterning, and dry development. Many other embodiments include combinations of wet and dry processing operations, such as spin-coating EUV photoresist (a wet process) combined with the dry development or other wet or dry processes described herein. Many post-deposition (or post-coating) processes are also described, such as bevel and backside cleaning, chamber cleaning, descaling, smoothing, curing to modify and enhance film properties, and photoresist rework.

[0036] Figure 1 presents a flowchart of an example method for depositing and developing photoresist according to some embodiments. The operation of process 100 may be performed in different sequences and / or with different, fewer, or additional operations. The state of process 100 can be described with reference to Figures 2, 3A-3C, 4A-4B, 5, and 6A-6D. One or more operations of process 100 may be performed using the apparatus described in any of Figures 7-11B. In some embodiments, the operation of process 100 may be performed at least in part based on software stored in one or more non-transitory computer-readable media. In some embodiments, dry chamber cleaning may be performed after deposition, backside and bevel edge cleaning, post-coating baking, post-exposure baking, or dry development.

[0037] In block 102 of process 100, a layer of photoresist is deposited. This can be a dry deposition process, such as vapor deposition, or a wet deposition process, such as spin coating.

[0038] The photoresist may be a metal-containing EUV photoresist. EUV-sensitive metal-containing or metal oxide films can be deposited on a semiconductor substrate using any suitable technique, including wet (e.g., spin coating) or dry (e.g., CVD) deposition techniques. For example, the process has been validated for EUV photoresist compositions based on organotin oxides, suitable for commercially available spin-coated formulations (e.g., available from Inpria, Corvallis, Oregon) and formulations coated using dry vacuum deposition techniques, as further described below.

[0039] Semiconductor substrates can include any material configuration suitable for photolithography, particularly for the fabrication of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer on which features (“underlying features”) have been formed, having an irregular surface morphology. As mentioned herein, “surface” refers to the surface on which the film of the present invention will be deposited or exposed to EUV during processing. Underlying features may include areas where material has been removed (e.g., by etching) or where material has been added (e.g., by deposition) prior to the methods of the present invention. Such prior processing may include the methods of the present invention or other processing methods in an iterative process, thereby forming two or more layers of features on the substrate.

[0040] EUV-sensitive films can be deposited on semiconductor substrates and can be used as resists in subsequent EUV lithography and processing. These EUV-sensitive films include materials that change upon EUV exposure, such as losing bulky side-group substituents bonded to metal atoms in low-density M-OH-rich materials, thereby crosslinking them into metal oxide materials with denser MOM bonds. EUV patterning creates regions of film with physical or chemical changes relative to unexposed areas. These properties can be utilized in subsequent processing, such as dissolving unexposed or exposed areas, or selectively depositing material on exposed or unexposed areas. In some embodiments, the unexposed film has a more hydrophobic surface than the exposed film under the conditions for such subsequent processing. For example, material removal can be achieved by utilizing differences in the film's chemical composition, density, and crosslinking. Removal can be achieved through wet or dry processing, as further described below.

[0041] In many embodiments, the thin film is an organometallic material (e.g., an organotin material containing tin oxide) or other metal oxide material / parts. Organometallic compounds can be prepared by a gas-phase reaction of an organometallic precursor with a reactant. In many embodiments, the organometallic compound is formed by mixing a specific combination of an organometallic precursor having bulky alkyl or fluoroalkyl groups with a reactant and polymerizing the mixture in the gas phase to produce a low-density, EUV-sensitive material deposited on a semiconductor substrate. [, , ]

[0042] In many embodiments, the organometallic precursor comprises at least one alkyl group on each metal atom, the metal atom may remain after the gas-phase reaction, and other ligands or ions coordinated to the metal atom may be replaced by the reactants. Organometallic precursors include those having the following formula: M aR bL c (Formula I)

[0043] Wherein: M is an element having a highly patterned radiation absorption cross section; R is an alkyl group, such as CnH2n+1, preferably where n = 1–6; L is a ligand, ion, or other part reactive with the relative reactant; a ≥ 1; b ≥ 1; and c ≥ 1. In many embodiments, M has an atomic absorption cross section equal to or greater than 1 x 107 cm2 / mol. M may be selected, for example, from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, M is tin. R may be fluorinated, for example having the formula CnFxH(2n+1). In many embodiments, R has at least one β-hydrogen or β-fluorine. For example, R may be selected from the group consisting of methyl, ethyl, isopropyl, n-propyl, tert-butyl, isobutyl, n-butyl, sec-butyl, n-pentyl, isopentyl, tert-pentyl, sec-pentyl, and mixtures thereof. L can be any part that can be easily substituted by the relative reactant to produce the M-OH moiety, such as the moiety selected from the group consisting of amines (e.g., dialkylamine, monoalkylamine), alkoxy, carboxyl, halogens and mixtures thereof.

[0044] The organometallic precursor can be any of a variety of candidate organometallic precursors. For example, when M is tin, such precursors include tert-butyltris(dimethylamino)tin, isobutyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, isopropyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and similar alkyl(tris)(tert-butoxy)tin compounds, such as tert-butyltris(tert-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0045] The relative reactant has the ability to substitute the reactive moiety, ligand, or ion (e.g., L in Formula 1 above) to connect at least two metal atoms via chemical bonding. The relative reactant may include water, peroxides (e.g., hydrogen peroxide), di- or poly-hydroxy alcohols, fluorinated di- or poly-hydroxy alcohols, fluorinated glycols, and other sources of the hydroxyl moiety. In many embodiments, the relative reactant reacts with the organometallic precursor by forming oxygen bridges between adjacent metal atoms. Other possible relative reactants include hydrogen sulfide and hydrogen disulfide, which can crosslink metal atoms via sulfur bridges.

[0046] In addition to organometallic precursors and reactants, the thin film may also include optional materials to modify the film's chemical or physical properties, such as modifying its sensitivity to EUV or enhancing its etch resistance. These optional materials can be introduced, for example, through doping during vapor phase formation prior to deposition onto the substrate, after film deposition, or both. In some embodiments, a mild distal H₂ plasma can be introduced to, for example, replace some Sn-L bonds with Sn-H, which can enhance the resist's reactivity under EUV.

[0047] In many embodiments, EUV patternable films are fabricated and deposited on semiconductor substrates using vapor deposition equipment and processes known in the art. In these processes, polymerized organometallic materials are formed in the vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALDs with CVD components, such as discontinuous ALD processes where the metal precursor and the relative reactants are separated in time or space.

[0048] Generally, the method involves mixing an organometallic precursor vapor stream with a relative reactant vapor stream to form a polymerized organometallic material, and depositing the organometallic material onto the surface of a semiconductor substrate. In some embodiments, more than one organometallic precursor is included in the vapor stream. In some embodiments, more than one relative reactant is included in the vapor stream. As will be understood by those skilled in the art, the mixing and deposition aspects of the process can be performed simultaneously in a substantially continuous process.

[0049] In an exemplary continuous CVD process, two or more gas streams (in separate inlet paths) of an organometallic precursor and a source of a reactant are introduced into the deposition chamber of a CVD apparatus, where they mix and react in the gas phase to form aggregated polymeric materials (e.g., through metal-oxygen-metal bonding). The gas streams can be introduced, for example, using separate inlet ports or dual-chamber spray heads. The apparatus is configured to mix the organometallic precursor and the reactant streams in the chamber, thereby allowing the organometallic precursor and the reactant to react to form polymerized organometallic materials. Without limiting the mechanism, function, or practicality of this technology, it is believed that the products from these gas-phase reactions become larger in molecular weight due to the crosslinking of metal atoms through the reactants, and subsequently condense or deposit on a semiconductor substrate. In many embodiments, the steric barrier of bulky alkyl groups prevents the formation of a densely packed network and produces a smooth, amorphous, low-density film.

[0050] CVD processes are typically performed under reduced pressure, for example, from 10 millitors to 10 torr. In some embodiments, the process is performed at 0.5 to 2 torr. In some embodiments, the temperature of the semiconductor substrate is at or below the temperature of the reaction stream. For example, the semiconductor substrate temperature can be from 0°C to 250°C, or from ambient temperature (e.g., 23°C) to 150°C. In many processes, the deposition of polymerized organometallic materials on the substrate occurs at a rate inversely proportional to the surface temperature.

[0051] In some embodiments, EUV patternable films are fabricated and deposited on semiconductor substrates using wet deposition equipment and processes known in the art. For example, organometallic materials are formed on the surface of semiconductor substrates by spin coating.

[0052] The thickness of the EUV patternable film formed on the surface of a semiconductor substrate can vary depending on surface characteristics, the materials used, and processing conditions. In many embodiments, the film thickness can range from 0.5 nm to approximately 100 nm, and can be sufficient to absorb most of the EUV light under EUV patterning conditions. EUV patternable films may be able to accommodate absorption equal to or greater than 30%, resulting in significantly fewer useful EUV photons directed towards the bottom of the EUV patternable film. Higher EUV absorption leads to higher crosslinking and density near the top of the EUV-exposed film compared to the bottom. Although insufficient crosslinking may lead to the resist being more easily peeled or collapsed during wet development, a risk not present in dry development, all-dry lithography methods can promote more efficient EUV photon utilization through less opaque resist films. While effective EUV photon utilization can occur in EUV patternable films with higher total absorption, it will be understood that in some instances, the EUV patternable film may be less than approximately 30%. In comparison, most other resistive films have a maximum total absorption of less than 30% (e.g., 10% or less, or 5% or less), allowing sufficient exposure of the resist material at the bottom of the resistive film. In some embodiments, the film thickness is 10 nm to 40 nm or 10 nm to 20 nm. Without limiting the mechanism, function, or practicality of the invention, the process of the present invention has fewer limitations on the surface adhesion properties of the substrate, and therefore can be applied to a variety of substrates. Furthermore, as discussed above, the deposited film can closely conform to surface features, thereby providing the advantage of forming a mask on a substrate (e.g., a substrate with underlying features) without "filling" or otherwise planarizing such features.

[0053] In addition to depositing a thin film containing metal EUV resist on the semiconductor substrate in block 102 of process 100, some metal EUV resist material may form as residues on the inner surfaces of the process chamber. The inner surfaces may include the chamber walls, bottom plate, and top plate of the process chamber. Other inner surfaces may include spray heads, nozzles, and substrate support surfaces. The metal EUV resist material may be formed due to dry deposition processes (such as CVD or ALD processes). The thickness of the metal EUV resist material residue may increase over time due to additional processing (e.g., deposition) operations performed in the process chamber. The residue is prone to peeling, degranulation, or stripping from the inner surfaces of the process chamber, thereby causing contamination in downstream processes.

[0054] Dry chamber cleaning is performed after depositing a metal-containing EUV resist film in block 102 of process 100 at block 150. This allows deposition and dry cleaning to be performed in the same process chamber. However, it will be understood that in some embodiments, dry chamber cleaning may be performed in a process chamber different from the deposition operation. In fact, dry chamber cleaning may be performed after edge and / or backside cleaning, baking, developing, or etching operations, as residues may also form inside the chamber in which any of these operations were performed, which may be the same as or different from the deposition chamber.

[0055] The removed dry-deposited EUV resist material is generally composed of Sn, O, and C, but the same cleaning method can be extended to films with other metal oxide resists and materials. Furthermore, this method can be used for film stripping and photoresist reprocessing.

[0056] In block 104, an optional cleaning process is performed to clean the back side and / or beveled edges of the semiconductor substrate. Back side and / or beveled edge cleaning can non-selectively etch the EUV resist film to equally remove films with varying degrees of oxidation or cross-linking on the back side and beveled edges of the substrate. During the application of EUV patternable films via wet or dry deposition processes, some unintended resist material may deposit on the beveled edges and / or back side of the substrate. This unintended deposition can cause unwanted particles to subsequently migrate to the top surface of the semiconductor substrate, becoming particle defects. Furthermore, this beveled edge and back side deposition can cause downstream processing problems, including contamination of patterning (scanner) and developing tools. Conventionally, the removal of this beveled edge and back side deposition is performed using wet cleaning techniques. For spin-coated photoresist materials, this process is called Edge Bead Removal (EBR) and is performed by guiding solvent flows from above and below the beveled edges as the substrate rotates. The same process can be applied to resists based on soluble organotin oxides deposited through vapor deposition technology.

[0057] Cleaning of the beveled edges and / or back side of the substrate can also be a dry cleaning process. In some embodiments, the dry cleaning process involves vapors and / or plasmas containing one or more of the following gases: HBr, HCl, BCl3, SOCl2, Cl2, BBr3, H2, O2, PCl3, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, the dry cleaning process may use the same chemicals as those used in the dry development process described herein. For example, cleaning of the beveled edges and / or back side may use organic acids, such as trifluoroacetic acid or other organic vapors. For cleaning of the beveled edges and / or back side, the vapors and / or plasmas must be confined to specific areas of the substrate to ensure that only the back side and beveled edges are removed, without any film degradation on the front side of the substrate.

[0058] Process conditions can be optimized for beveled edge and / or backside cleaning. In some implementations, higher temperatures, higher pressures, and / or higher reactant flow rates may result in increased etching rates. Suitable process conditions for dry beveled edge and backside cleaning may be: reactant flow rates of 100–10000 sccm (e.g., 500 sccm HCl, HBr, HI, or H2 with Cl2 or Br2, BCl3 or H2, or other halogen-containing compounds), temperatures of 20–140˚C (e.g., 80˚C), pressures of 20–1000 mTorr (e.g., 100 mTorr) or 50–765 Torr (e.g., 760 Torr), plasma power of 0–500 W at high frequencies (e.g., 13.56 MHz), and durations of approximately 10 to 20 seconds, depending on the photoresist film and its composition and properties. Bevel and / or backside cleaning can be accomplished using Coronus® tools available from Lam Research Corporation in Fremont, California, but a wider range of process conditions may be used depending on the reactor’s capacity.

[0059] Edge and / or backside cleaning can alternatively extend to complete photoresist removal or photoresist "rework," in which the coated EUV photoresist is removed and the semiconductor substrate is ready for photoresist recoating, for example, when the original photoresist is damaged or defective. Photoresist rework should be performed without damaging the underlying semiconductor substrate; therefore, oxygen-based etching should be avoided. Instead, organic vapor chemicals or variations of halogen-containing chemicals as described herein can be used. It will be understood that photoresist rework operations can be applied at any stage during process 100. Therefore, photoresist rework operations can be performed after deposition, after edge and / or backside cleaning, after PAB treatment, after EUV exposure, after PEB treatment, after development, or after hard baking. In some embodiments, photoresist rework can be performed to non-selectively remove exposed and unexposed areas of the photoresist, but selectively on the underlying substrate.

[0060] In some embodiments, the photoresist reprocessing involves vapors and / or plasmas containing one or more of the following gases: HBr, HCl, HI, BCl3, Cl2, BBr3, H2, PCl3, CH4, methanol, ammonia, formic acid, NF3, and HF. In some embodiments, the photoresist reprocessing may use the same chemicals as those used in the dry development process described herein. For example, organic acids, such as trifluoroacetic acid or other organic vapors, may be used in the photoresist reprocessing.

[0061] Process conditions can be optimized for photoresist reprocessing. In some implementations, higher temperatures, higher pressures, and / or higher reactant flow rates may result in increased etching rates. Suitable process conditions for photoresist reprocessing may be: reactant flow rates of 100–500 sccm (e.g., 500 sccm HCl, HBr, HI, BCl3, or H2 with Cl2 or Br2), temperatures of 20–140˚C (e.g., 80˚C), pressures of 20–1000 mTorr (e.g., 30 mTorr) or 50–765 Torr (e.g., 760 Torr), plasma power of 0–800 W (e.g., 200 W) at high frequencies (e.g., 13.56 MHz), wafer bias of 0–200 Vb (higher biases can be used for harder substrate materials), and a duration of approximately 20 seconds to 3 minutes, sufficient to completely remove the EUV photoresist, depending on the photoresist film and its composition and properties. It should be understood that while these conditions apply to some processing reactors, such as the Kiyo etching tools available from Lam Research Corporation in Fremont, California, a wider range of process conditions may be used depending on the capabilities of the processing reactor.

[0062] In block 150 of process 100, a dry chamber cleaning operation can be performed after cleaning the beveled edge and / or back side of block 104 in process 100. This allows beveled edge and / or back side cleaning and dry chamber cleaning to be performed in the same process chamber. However, it will be understood that in some embodiments, dry chamber cleaning can be performed in a process chamber different from the beveled edge and / or back side cleaning.

[0063] In block 106 of process 100, an optional post-coating bake (PAB) is performed after deposition of the metal-containing EUV resist film and before EUV exposure. The PAB process may involve a combination of heat treatment, chemical exposure, and / or moisture to enhance the EUV sensitivity of the metal-containing EUV resist film and reduce the EUV dose required to develop patterns within the metal-containing EUV resist film. The PAB process temperature can be adjusted and optimized to enhance the sensitivity of the metal-containing EUV resist film. For example, the process temperature may be between about 90°C and about 200°C, or between about 150°C and about 190°C. In some embodiments, the PAB process may be performed at a pressure between atmospheric pressure and vacuum, and the process duration may be about 1 to 15 minutes, for example, about 2 minutes. In some embodiments, the PAB process may be performed at a temperature between about 100°C and 230°C for about 1 to 2 minutes.

[0064] In block 150 of process 100, a dry chamber cleaning operation can be performed after the PAB treatment of block 106 in process 100. This allows baking and dry chamber cleaning to be performed in the same process chamber. However, it will be understood that in some embodiments, dry chamber cleaning can be performed in a process chamber different from the PAB treatment.

[0065] In block 108 of process 100, a metal-containing EUV resist film is exposed to EUV radiation to form a pattern. Generally, EUV exposure causes changes in chemical composition and cross-linking in the metal-containing EUV resist film, thereby producing etch-selective contrast that can be used for subsequent development.

[0066] Metal-containing EUV resistive films can then be patterned by exposing regions of the film to EUV light, typically under relatively high vacuum. EUV apparatuses and imaging methods used herein include those known in the art. In particular, as discussed above, the exposed regions of the film are established through EUV patterning, resulting in altered physical or chemical properties relative to the unexposed regions. For example, in the exposed regions, metal-carbon bond breaking may occur, such as through β-hydrogen elimination, leaving reactive and accessible metal hydride functional groups that can be transformed into hydroxides and cross-linked metal oxide moieties via metal-oxygen bridges during a subsequent post-exposure baking (PEB) step. This process can be used to establish a chemical contrast for development, acting as a negative resist. Generally, a greater number of β-Hs in alkyl groups results in a more sensitive film. This can also be interpreted as weaker Sn-C bonds with more branches. After exposure, the metal-containing EUV resistive film can be baked to induce additional cross-linking of the metal oxide film. The differences in properties between exposed and unexposed areas can be utilized in subsequent processing, such as dissolving the unexposed areas or depositing material on the exposed areas. For example, a dry method can be used to develop a pattern to form a mask containing metal oxides.

[0067] In particular, in many embodiments, hydrocarbon-terminated tin oxide present on the surface is converted into hydrogen-terminated tin oxide in the exposed areas of the imaging layer, especially when exposed using EUV in a vacuum. However, removing the exposed imaging layer from the vacuum and introducing it into the air, or controlling the introduction of oxygen, ozone, H₂O₂, or water, will cause the surface Sn-H to oxidize to Sn-OH. The difference in properties between the exposed and unexposed areas can be utilized in subsequent processing, for example, by reacting the irradiated area, the unexposed area, or both with one or more reagents to selectively add material to the imaging layer or remove material from the imaging layer itself.

[0068] Without limiting the mechanism, function, or practicality of this technology, EUV exposure (e.g., at doses from 10 mJ / cm² to 100 mJ / cm²) leads to the breaking of Sn-C bonds, resulting in the loss of alkyl substituents, reducing steric hindrance, and causing low-density films to collapse. Furthermore, reactive metal-H bonds generated in the β-hydrogen elimination reaction can react with adjacent active groups (e.g., hydroxyl groups) in the film, leading to further crosslinking and densification, and establishing a chemical contrast between exposed and unexposed regions.

[0069] After the metal-containing EUV resist film is exposed to EUV light, a photo-patterned metal-containing EUV resist is provided. The photo-patterned metal-containing EUV resist includes both EUV-exposed and unexposed areas.

[0070] In block 110 of process 100, optional post-exposure baking (PEB) is performed to further increase the contrast of etch selectivity of the photopatterned metallized EUV resist. The photopatterned metallized EUV resist can be heat-treated in the presence of various chemicals to promote crosslinking of the EUV-exposed areas, or simply baked on a hot plate in ambient air, for example, between 100°C and 250°C for 1 to 5 minutes (e.g., 190°C for 2 minutes).

[0071] In many implementations, the baking strategy involves careful control of the baking environment, the introduction of reactive gases, and / or careful control of the ramp rate of the baking temperature. Examples of useful reactive gases include, for example, air, H₂O, H₂O₂ vapor, CO₂, CO, O₂, O₃, CH₄, CH₃OH, N₂, H₂, NH₃, N₂O, NO, alcohols, acetone, formic acid, Ar, He, or mixtures thereof. The PEB treatment is designed to (1) drive the complete evaporation of organic debris generated during EUV exposure and (2) oxidize any Sn-H, Sn-Sn, or Sn radicals generated during EUV exposure into metal hydroxides, and (3) promote cross-linking between adjacent Sn-OH groups to form a denser cross-linked SnO₂ network. The baking temperature is carefully selected to achieve optimal EUV lithography performance. Too low a PEB temperature will result in insufficient cross-linking, thus leading to lower chemical contrast in development at a given dose. Excessively high PEB temperatures can also have adverse effects, including severe oxidation and film shrinkage in unexposed areas (in this example, areas removed by developing the patterned film to form a mask), and undesirable interdiffusion at the interface between the photopatterned metal EUV resist and the substrate. Both of these can lead to reduced chemical contrast and increased defect density due to insoluble residues. PEB processing temperatures can be between about 100°C and about 300°C, between about 170°C and about 290°C, or between about 200°C and about 240°C. In some embodiments, the PEB processing can be performed under pressures between atmospheric pressure and vacuum, and the processing duration is about 1 to 15 minutes, for example, about 2 minutes. In some embodiments, the PEB heat treatment can be repeated to further increase etch selectivity.

[0072] In block 150 of process 100, a dry chamber cleaning operation can be performed after the PEB treatment in block 110 of process 100. This allows baking and dry chamber cleaning to be performed in the same process chamber. However, it will be understood that in some embodiments, dry chamber cleaning can be performed in a process chamber different from the PEB treatment.

[0073] In block 112 of process 100, a photo-patterned metal-containing EUV resist is developed to form a resist mask. In many embodiments, exposed areas (positive type) or unexposed areas (negative type) may be removed. In some embodiments, development may include selective deposition on the exposed or unexposed areas of the photo-patterned metal-containing EUV resist, followed by an etching operation. In some embodiments, development may be performed by exposure to one or more organic vapors (e.g., trifluoroacetic acid). In some embodiments, development may be performed without triggering plasma. Alternatively, development may be performed using one or more organic vapor (e.g., trifluoroacetic acid) streams activated in a remote plasma source or activated by exposure to remote UV radiation. The photoresist used for development may include elements selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. This element may have a high patterned radiation absorption cross section. In some embodiments, this element may have a high EUV absorption cross section. In some embodiments, the metal-containing EUV resist may have a total absorption greater than 30%. In a fully dry lithography process, this provides more efficient utilization of EUV photons, thereby enabling the development of thicker, less EUV-resistant resists.

[0074] Examples of development processes involve EUV-sensitive photoresist films (e.g., 10-30 nm thick, such as 20 nm) containing organotin oxides, which are subjected to EUV exposure dose and post-exposure baking, followed by development. The photoresist film may be deposited, for example, based on the vapor-phase reaction of an organotin precursor (e.g., isopropyl(tris)(dimethylamino)tin) with water vapor, or it may be a spin-coated film containing tin clusters in an organic matrix.

[0075] In block 150 of process 100, dry chamber cleaning can be performed after dry development in block 112 of process 100. This allows dry development and dry chamber cleaning to be performed in the same process chamber. However, it will be understood that in some embodiments, dry chamber cleaning can be performed in a process chamber different from that used for dry development. Furthermore, it will be understood that dry chamber cleaning can be performed in a process chamber that is the same as or different from that used for etching. The etching operation can be used to etch the substrate underside of a semiconductor substrate.

[0076] In block 114 of process 100, the semiconductor substrate may be hard-baked as appropriate. During hard baking, the semiconductor substrate is subjected to elevated temperatures. For example, the semiconductor substrate may be subjected to elevated temperatures equal to or greater than about 50°C, between about 100°C and about 300°C, or between about 170°C and about 290°C. Hard baking can remove residual solvents or etching gases from the developing process.

[0077] Figure 2 presents a flowchart of an example method for dry developing a metal resist according to some embodiments. The operation of process 200 may be performed in different sequences and / or with different, fewer, or additional operations. The state of process 200 can be described with reference to Figures 3A-3C and 4A-4B. One or more operations of process 200 may be performed using the apparatus described in any of Figures 7-11B. In some embodiments, the operation of process 200 may be implemented at least in part based on software stored in one or more non-transitory computer-readable media.

[0078] In block 202 of process 200, a photo-patterned metal-containing resist is provided to the surface of a semiconductor substrate in the process chamber. The metal-containing resist can be deposited on the surface of the semiconductor substrate. The metal-containing resist can be exposed to UV radiation (e.g., EUV radiation) using a scanner or EUV lithography tool to form the photo-patterned metal-containing resist. In some embodiments, the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist. For example, the photo-patterned metal-containing EUV resist is an organometallic oxide or an organometallic film. The semiconductor substrate may be provided in the process chamber after processing in a scanner and / or PEB processing chamber.

[0079] In block 204 of process 200, dry development is performed on photopatterned metal-containing resists. This selectively removes a portion of the resist by exposure to a developing chemical containing organic vapors to form a resist mask. Dry development of photopatterned metal-containing resists involves using developing chemicals to selectively remove the EUV-unexposed portions of the resist relative to the EUV-exposed portions to form a resist mask. Typically, wet developing chemicals are used for development. Wet development using solvents produces undesirable waste streams. Wet development generally involves moisture and / or oxygen, which is more likely to lead to residue formation. Wet development is limited by solubility and cluster size, while dry development is not limited by solubility and cluster size. Wet development is more prone to pattern collapse and delamination problems that are avoided by dry development. The development in this invention uses dry developing chemicals instead of wet developing chemicals in the gas phase.

[0080] Developing using dry developing chemicals typically involves halogen vapors, such as boron trichloride (BCl3) vapor, hydrogen (H2) mixed with chlorine (Cl2) or bromine (Br2), or hydrogen halide vapors, such as hydrogen bromide (HBr), hydrogen chloride (HCl), or hydrogen fluoride (HF). However, these vapors may leave residues or contaminants after development. Residues may include residual etching byproducts adsorbed on the semiconductor substrate surface or even on the chamber walls. For example, halogen vapors can react with moisture or oxygen to form persistent etching byproducts that are difficult to remove. In some instances, residual etching byproducts include sticky and difficult-to-remove bromides. Accumulation of residual etching byproducts can cause process drift, leading to hazardous precautions in the process chamber. Furthermore, residues adsorbed on the semiconductor substrate may detach from the substrate and contaminate downstream processing tools. In some cases, residues may include clusters of high metal concentrations or metal oxides that can contaminate downstream processing tools. Furthermore, since residual etching byproducts are difficult to remove and do not readily volatilize, a separate plasma step or a separate chamber with plasma capability may be required. Otherwise, performing high-temperature fluctuations to volatilize the residues is generally undesirable for the semiconductor substrate and process chamber.

[0081] The developing chemical substance of this invention is an organic vapor. The organic vapor can be an organic acid. In some embodiments, the organic acid includes a carboxylic acid. In some embodiments, the organic acid includes trifluoroacetic acid (CF3COOH). The organic vapor can be halogenated or at least fluorinated. In some embodiments, the organic vapor includes hexafluoroacetone (CF3COCH2COCF3). In some embodiments, the organic vapor includes trifluoroacetic anhydride ((CF3CO)2O), acetic anhydride ((CH3CO)2O), trichloroacetic acid (CCl3COOH), monofluoroacetic acid (CFH2COOH), difluoroacetic acid (CF2HCOOH), mixed halogenated acetic acids (e.g., chloro-difluoro-acetic acid), sulfur-containing analogs of acetic acid, thioacetic acid (CH3COSH), or mercaptoacetic acid (HSCH2CO2H). In some embodiments, the developing chemical substance includes a gaseous mixture of carboxylic acid and hydrogen halides. For example, the developing chemical substance includes a mixture of acetic acid or formic acid and hydrogen chloride or hydrogen bromide. In some embodiments, organic vapors may flow in with or without an inert / carrier gas (e.g., helium (He), neon (Ne), argon (Ar), xenon (Xe), and nitrogen (N2)).

[0082] Organic vapors can react with metal-containing inhibitors to form etching byproducts that are more volatile than those formed by halogen vapors. For example, etching byproducts of tin bromide can have boiling points equal to or greater than about 200°C. However, etching byproducts of tin fluoroacetate can have boiling points below about 200°C. For instance, hexatin(II)-di-µ-oxy-octakis-µ-trifluoroacetate (1F) is volatile at 191°C and 1 Torr, while tin(IV) tetrakis(trifluoroacetate) (2F) is volatile at 84°C and 1 Torr. Both 1F and 2F offer high thermal stability and volatility. Etching byproducts formed by the reaction of organic vapors with metal-containing inhibitors can exhibit excellent volatility. In particular, the etching byproducts formed by the reaction of trifluoroacetic acid with EUV-unexposed organometallic resists can exhibit excellent volatility. Without any theoretical limitations, other fluorinated derivatives of trifluoroacetic acid or organic acids can increase the volatility of etching byproducts exhibiting their electron-withdrawing effect. These other fluorinated derivatives of trifluoroacetic acid or organic acids can be strong organic acids.

[0083] The organic vapor of this invention can be a strong organic acid. As used herein, a strong organic acid can have a pKa value equal to or less than about 3.8. The strength of the organic acid can be increased by halogenation. In some embodiments, the strength of the organic acid can be significantly increased by fluorination. For example, while formic acid or acetic acid can etch metal-containing resist materials, such as organometallic resist materials, trifluoroacetic acid can etch such metal-containing resist materials more effectively. Although metal-containing resist materials can be selectively removed by plasma-assisted weaker organic acids (e.g., acetic acid), stronger organic acids can selectively remove metal-containing resist materials without plasma assistance. Accordingly, in this invention, dry development of metal-containing resists can be performed without plasma assistance. However, as described below, plasma can be used in desorption, slagging, or smoothing operations after dry development, depending on the situation. In the case of evaporation of etching byproducts of the organic vapor, such plasma-based desorption, slagging, or smoothing operations are unnecessary.

[0084] The organic vapors of this invention enable dry development in plasma-free thermal processes. This means that dry development can be performed in process chambers without plasma capability. In some embodiments, dry development can be performed without subsequent plasma-based descaling or smoothing operations. By eliminating plasma exposure, plasma damage to the semiconductor substrate is avoided, and costs can be significantly reduced and yields increased. Furthermore, the inner surface of the process chamber can be made of a material that does not require resistance to plasma or halogen vapors (e.g., hydrogen halides). The surfaces of the chamber walls, top plate, and chamber components (e.g., spray nozzles) may be susceptible to corrosion in the presence of moisture and halogen vapors. Therefore, the inner surface of the process chamber is typically made of a material that is stable in plasma, halogen vapors, and water vapor. However, for the dry development chemicals of this invention (e.g., trifluoroacetic acid), the inner surface of the process chamber of this invention may be made of a material that does not necessarily meet the above requirements. In some embodiments, the chamber walls of the process chamber may include alumina, anodized aluminum, or plastic.

[0085] Productivity can be significantly improved by applying plasma-free thermal methods because multiple wafers can be batch-developed simultaneously in a low-cost thermal vacuum chamber / furnace. However, in some implementations, the thermal dry development process may be followed by exposure to plasma. Subsequent exposure to plasma may occur during desorption, deslagging, smoothing, or other processing operations.

[0086] Dry development with metal resists can be combined with other dry processing operations, such as dry deposition with metal resists (e.g., CVD). In some embodiments, semiconductor substrate processing can combine all dry steps, including film formation via vapor deposition, EUV lithography patterning, and dry development. Baking, edge and / or backside cleaning, and chamber cleaning can also be dry operations. These processing operations avoid the material and production costs associated with wet processing operations (e.g., wet development). Furthermore, dry processing offers greater adjustability and increases critical size (CD) control and potential residue removal. Generally, wet processing involves moisture and / or oxygen, which is more likely to lead to residue formation. Wet development is limited by solubility and cluster size, while dry development is not. Wet development is more prone to pattern collapse and delamination problems that are avoided by dry development. Furthermore, employing a fully dry processing operation facilitates integration within interconnected vacuum processing chambers without exposure to ambient air or trace contaminants contained therein. For example, the PEB heat treatment during which further crosslinking of the exposed areas occurs can be performed in the same chamber as development, although it will be understood that the PEB heat treatment can be performed in a separate chamber.

[0087] In some embodiments, dry development can be performed by using heat treatment and allowing organic vapors (such as trifluoroacetic acid) to flow in. For example, dry development can be performed in a heat treatment chamber. In some embodiments, organic vapors (such as trifluoroacetic acid) can rapidly remove the unexposed portions of the photopatterned metal resist relative to the exposed portions of the photopatterned metal resist, leaving a pattern of the exposed film that can be transferred to the underside of the semiconductor substrate through an etching process.

[0088] In some embodiments, the semiconductor substrate may be exposed to dry developing chemicals, such as strong organic acids, in a heat treatment chamber (e.g., a furnace). The heat treatment chamber may include pipelines for delivering organic vapors to the developing chemicals within the heat treatment chamber. In some embodiments, the heat treatment chamber may include one or more heating elements for temperature control, such as heating elements coupled to heating assemblies facing the semiconductor substrate in the process chamber for substrate temperature control. In some embodiments, the one or more heating elements may be one or more LEDs. The one or more heaters may heat the semiconductor substrate to elevated temperatures during dry developing to promote the volatilization of etching byproducts.

[0089] In a hot dry developing process, a photo-patterning metal resist is exposed to developing chemicals, which optimizes etch selectivity between exposed and unexposed areas. Generally, lower temperatures increase the contrast of etch selectivity, while higher temperatures decrease it. Higher temperatures also increase the volatilization of etching byproducts, limiting residue formation on the semiconductor substrate. In some embodiments, the temperature may be less than about 200°C, between about 20°C and about 190°C, between about 40°C and about 120°C, or between about 50°C and about 100°C. The photo-patterning metal resist reacts with organic vapors at temperatures below about 200°C to form volatile compounds.

[0090] The chamber pressure is adjustable, which can affect the etch selectivity between exposed and unexposed areas during thermal dry development. In some embodiments, the chamber pressure can be relatively low and accompanied by undilution, wherein the chamber pressure can be between about 0.1 mTorr and about 1000 mTorr, between about 0.2 mTorr and about 300 mTorr, or between about 0.5 mTorr and about 100 mTorr. In some embodiments, the chamber pressure can be between about 20 mTorr and about 2000 mTorr, or between about 20 mTorr and about 1000 mTorr, for example, about 300 mTorr. In some embodiments, the chamber pressure can be relatively high and have a high flow rate accompanied by dilution, wherein the chamber pressure can be between about 100 Torr and about 765 Torr or between about 200 Torr and about 760 Torr.

[0091] The gas flow rate of the dry developing chemicals can be adjusted, whereby the gas flow rate can affect the etching selectivity between exposed and unexposed areas during thermal dry developing. In some embodiments, the gas flow rate can be between about 0.5 SLM and about 30 SLM, between about 1 SLM and about 20 SLM, or between about 2 SLM and about 15 SLM. The gas flow rate can include the total flow rate of the flowing gases, including organic vapors and carrier gases such as nitrogen, argon, etc. The organic vapor flow rate can be only a portion of the total flow rate, where the organic vapor flow rate can be between about 0.01 SLM and about 1 SLM. In examples with high flow rates, the organic vapor flow rate can be between about 1 SLM and about 10 SLM.

[0092] The exposure duration can be adjusted during the hot dry developing process. The exposure duration can depend on the amount of resist to be removed, the developing chemicals, the amount of crosslinking in the resist, the composition and properties of the resist, and other factors. In some embodiments, the exposure duration can be between about 5 seconds and about 5 minutes, between about 10 seconds and about 3 minutes, or between about 10 seconds and about 1 minute.

[0093] In some embodiments, the photopatterned metal-containing resist is developed using a plasma-free thermal method. In alternative embodiments, the photopatterned metal-containing resist is developed in a plasma development process. The photopatterned metal-containing resist is exposed to developing chemicals, including radicals / ions of one or more gases. These one or more gases may include organic vapors, such as trifluoroacetic acid. The process chamber for processing the semiconductor substrate for dry development may be a plasma generation chamber or a plasma generation chamber coupled to a process chamber remotely. The plasma generation chamber may be an inductively coupled plasma (ICP) reactor, a transformer-coupled plasma (TCP) reactor, or a capacitively coupled plasma (CCP) reactor employing equipment and techniques known in the art. An electromagnetic field is applied to the one or more gases to generate plasma in the plasma generation chamber. Ions and / or radicals from the distal plasma may interact with the photopatterned metal-containing resist. These plasma ions and / or radicals may include ions and / or radicals of organic acids (e.g., trifluoroacetic acid). In some embodiments, a vacuum line is coupled to the process chamber for pressure control, while a developer chemical line may be coupled to the plasma generation chamber to deliver one or more gases into the plasma generation chamber. The process chamber may include one or more heaters for temperature control, such as heaters coupled to a heating assembly facing the substrate for substrate temperature control. In some embodiments, the development of the photopatterning metal resist is exposed to conditions optimized to produce a mild plasma with high voltage and low power characteristics. In some embodiments, the RF power level may be adjusted, wherein the RF power may be equal to or less than about 1000 W, equal to or less than about 800 W, or equal to or less than about 500 W.

[0094] In addition to or as an alternative to plasma activation, the activation of one or more gases in a dry development process can be performed by photoactivation. In some embodiments, photoactivation can be achieved by exposure to ultraviolet (UV) radiation. For example, the process chamber may include a lamp, such as a UV lamp configured to generate UV radiation. Exposing one or more gases to UV radiation can generate free radicals of those gases, which can be used for photopatterning of dry development containing metal resists. The exposure of the one or more gases to UV radiation can be performed without exposing the photopatterning metal resists to UV radiation. In other words, the photopatterning of the metal resists is out of sight of the UV lamp.

[0095] It will be understood that the aforementioned thermal development, plasma development, and photoactivated development methods can be combined. These development methods can be applied simultaneously or sequentially. One or more development methods can be applied during the inflow of dry developing chemicals into the gas phase. Development can produce positive or negative forms, wherein the dry developing chemicals selectively remove unexposed or exposed material, leaving exposed or unexposed material as a mask.

[0096] As described above, the etch selectivity during dry development can be adjusted by controlling process conditions such as temperature, pressure, gas flow rate, gas composition, and plasma power, as well as other adjustable process conditions. Adjusting the etch selectivity in a single step or multiple steps achieves the desired patterning characteristics. In some embodiments, the etch selectivity during dry development is adjusted throughout one or more steps to influence the resist profile. More specifically, the amount of taper or concavity in the resist profile can be controlled by applying dry development chemicals with different etch selectivities in one or more steps. Descaling, photoresist reprocessing, curing, smoothing, and cleaning operations can also be adjusted based on the adjustable etch selectivity.

[0097] Figures 3A-3C show cross-sectional schematic diagrams of various processing stages of dry development according to some embodiments. The examples shown in Figures 3A-3C illustrate negative dry development. As shown in Figure 3A, wafer 300 includes a substrate 302 and a substrate layer 304 to be etched. In some embodiments, substrate layer 304 includes an ashingable hard mask, such as spin-coated carbon (SoC) or other materials, such as silicon, silicon oxide, silicon nitride, silicon carbide, etc. In some embodiments, substrate layer 304 may be a stack of layers disposed on substrate 302. Wafer 300 further includes a photopatterned metallized EUV resist film 306. For example, photopatterned metallized EUV resist film 306 may be an organometallic layer disposed on substrate layer 304 to be etched. Photopatterned metallized EUV resist film 306 may have a thickness between about 5 nm and about 50 nm or between about 10 nm and about 30 nm. Following photopatterning in an EUV scanner and / or the PEB treatment as described above, a photopatterned metallized EUV resist film 306 can be provided to the process chamber. The photopatterned metallized EUV resist film 306 includes unexposed EUV regions 306a and EUV-exposed regions 306b. As shown in FIG3B, the unexposed EUV regions 306a of the photopatterned metallized EUV resist film 306 can be removed during a dry development process by exposure to a stream of dry development chemicals without triggering plasma. Dry development chemicals may include organic vapors, such as organic acids. Organic acids may include halogenated or fluorinated carboxylic acids. Examples of organic acids include, but are not limited to, trifluoroacetic acid, hexafluoroacetate, trichloroacetic acid, monofluoroacetic acid, and difluoroacetic acid. Other examples of organic acids include mixed halogenated acetic acids, such as chloro-difluoro-acetic acid, sulfur-containing analogs of acetic acid, thioacetic acid, and mercaptoacetic acid. A resist mask 308 is formed after development by removing the unexposed EUV regions 306a. Subsequently, the substrate layer 304 to be etched can be etched using a resist mask 308 to provide the structure shown in FIG3C.

[0098] Organometallic oxide films can possess tetrahedral coordination structures. The exposed regions exhibit a higher degree of Sn-O-Sn crosslinking, resulting in higher density and lower / slower reactivity to halocarboxylic acids. The unexposed regions exhibit lower density due to the presence of bulky alkyl substituents (which hinder access pathways and Sn-OH moiety condensation). In the unexposed regions, acids (e.g., trifluoroacetic acid) more readily protonate the more "basic" and accessible oxygen lone pairs (characteristic of more tetrahedral organotin oxide hydroxides). This can generate volatile byproducts of trifluoroacetate, which are then removed from the unexposed regions. Without any theoretical constraints, trifluoroacetic acid can selectively protonate oxygen lone pairs to form volatile byproducts. When the alkyl group is isopropyl, at a typical EUV patterning dose, at least two out of every three isopropyl substituents are removed, causing the exposed area after the PEB step to condense into a higher density SnO2-like material. Due to its more hexagonal tin structure, it exhibits lower reactivity with trifluoroacetic acid. In this structure, oxygen atoms are less accessible, resulting in a slower reaction with trifluoroacetic acid.

[0099] In some cases, residues or slag may remain after development. These residues may be due to slower etching components in less homogeneous EUV photoresist formulations (including those applied via spin coating). Such residues can contain high metal concentrations, which may pose a problem during subsequent pattern transfer.

[0100] Additionally or alternatively, roughness may form on the sidewalls of the etched features in the developed pattern after development. Some of this can be attributed to the stochastics of light or a non-optimal Gaussian distribution, resulting in partially or fully exposed material in areas where the resist should remain unexposed, or vice versa.

[0101] In some embodiments, dry development can be performed via a descaling / smoothing operation. In some embodiments, the descaling and smoothing operation can be an inert gas plasma desorption operation. For example, the inert gas plasma desorption operation can be a helium plasma desorption operation. The inert gas plasma desorption operation can be performed after dry development or in a cycle with dry development.

[0102] Figure 4A shows a schematic cross-sectional view of dry development without the application of an inert gas plasma, according to some embodiments. The photopatterned metal-containing EUV resist film includes exposed and unexposed areas. As shown in Figure 4A, particles or clusters of metal oxides (e.g., SnOx) may occupy the unexposed areas. As dry development proceeds, these metal oxide clusters become more concentrated. These metal oxide clusters are generally difficult to remove. Development may selectively remove organic materials. After removing the unexposed areas, the metal oxide clusters may remain on the substrate surface as residue. Metal oxide clusters remaining on the sidewalls of the exposed areas may cause roughness.

[0103] Figure 4B shows a cross-sectional schematic diagram of dry development using a circulating inert gas plasma for descaling according to some embodiments. The first stage involves dry development to remove a significant portion of the unexposed areas of the patterned metal-containing EUV resist film. Dry development chemicals may include, for example, organic acids and / or hydrogen halides. "A significant portion" can mean at least 70% by volume, more than 80% by volume, or more than 90% by volume of the unexposed area. Clusters of metal oxides concentrate on the surface of the remaining unexposed areas of the EUV resist film. The second stage involves applying an inert gas plasma (such as helium plasma) with low power and high ion energy for a short duration. The helium plasma removes the clusters of metal oxides. Furthermore, the helium plasma removes the clusters from the sidewalls and smooths the sidewalls. Helium plasma treatment can also be used to assist in hardening or curing the patterned EUV resist film to form a denser metal oxide-like hard mask. After the helium plasma treatment, a less selective dry etching step can be used to remove any residue remaining in the unexposed areas of the EUV resist film.

[0104] In some embodiments, dry development may be cycled with helium plasma treatment one or more times until the unexposed areas of the EUV resist film are removed. Helium plasma descaling / smoothing may be cycled with dry development, as described above, to enhance the effect. In this manner, most of the organic components of the pattern, such as the unexposed areas, are removed by dry development, followed by a brief helium plasma operation to remove some concentrated metals on the surface, facilitating access to the remaining underlying organic material, which can then be removed in subsequent dry development operations / cycles. Another cycle of helium plasma can be used to remove any remaining metals, leaving a clean and smooth feature surface. Cycles may continue until all, or substantially all, residues and roughness remain are removed, leaving a clean and smooth feature surface.

[0105] The process conditions used for slagging and smoothing operations can be controlled during or after development. In some embodiments, the reactant flow rate can be between about 50 sccm and about 1000 sccm, or between about 100 sccm and about 500 sccm, for example, about 500 sccm of He. In some embodiments, the temperature can be between about -60°C and about 120°C, between about -20°C and about 60°C, or between about 20°C and about 40°C, for example, about 20°C. In some embodiments, the chamber pressure can be between about 1 mTorr and about 300 mTorr, between about 5 mTorr and about 100 mTorr, or between about 5 mTorr and about 20 mTorr, for example, about 10 mTorr. The plasma power can be relatively low and accompanied by high ion energy. In some embodiments, the plasma power may be between about 50 W and about 1000 W, between about 100 W and about 500 W, or between about 100 W and about 300 W, for example, about 300 W. In some embodiments, the wafer bias voltage is between about 10 V and about 500 V, or between about 50 V and about 300 V, for example, about 200 V. The plasma can be generated using a high RF frequency. In some embodiments, the RF frequency is 13.56 MHz. The duration of exposure to the inert gas plasma may be relatively short to avoid excessive exposure to UV radiation during plasma exposure. In some embodiments, the exposure duration is between about 0.5 seconds and about 5 seconds, between about 1 second and about 3 seconds, for example, about 2 seconds.

[0106] Inert gas plasma treatment for descaling and cleaning unexposed resist residues has the added benefit of curing the exposure resist, thus enhancing its hard masking function in subsequent operations such as etching the underlying substrate. This resist curing is achieved by exposing the EUV exposure resist to UV radiation generated by the inert gas plasma, which can continue after descaling / smoothing is complete and under off-bias conditions. If descaling / smoothing is not required or not performed, inert gas plasma curing can be performed instead.

[0107] Not only can the organic vapors of this invention be used in dry developing processes, but the organic vapors of trifluoroacetic acid can also be used in dry chamber cleaning or other processing operations for the dry removal of metal resists.

[0108] Figure 5 presents a flowchart of an example method for dry chamber cleaning according to some embodiments. Dry chamber cleaning may be performed after deposition, bevel and / or backside cleaning, baking, development, or etching. In some embodiments, dry chamber cleaning may be performed after the deposition of resist material and in the same process chamber as the deposited resist material. The operation of process 500 may be performed in different sequences and / or with different, fewer, or additional operations. The state of process 500 can be described with reference to Figures 6A-6D. One or more operations of process 500 may be performed using the apparatus described in any of Figures 7-11B. In some embodiments, the operation of process 500 may be implemented at least in part based on software stored in one or more non-transitory computer-readable media.

[0109] In block 502 of process 500, a metal resist material is deposited on the surface of a semiconductor substrate in a process chamber, wherein a portion of the metal resist material forms residues on one or more surfaces of the process chamber. The composition and deposition of such metal resist materials can be described, for example, in International Patent Application No. PCT / US2019 / 31618 filed May 9, 2019, which is incorporated herein by reference to disclose methods and materials applicable to the present invention. The methods include generating polymerized organometallic materials in the vapor phase and depositing them onto a semiconductor substrate. In some embodiments, the metal resist material is an EUV resist material containing a metal oxide. For example, the elements in the metal resist material are selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, the metal resist material includes organometallic oxides, such as organotin oxides.

[0110] In some embodiments, the process chamber in which the semiconductor substrate is provided may be a dry deposition chamber. In other embodiments, the process chamber in which the semiconductor substrate is provided may be a beveled edge and / or backside cleaning chamber, a PAB processing chamber, a PEB processing chamber, a developing chamber, or an etching chamber. Any of the aforementioned chambers may accumulate metal resist-containing material on their inner surfaces over time. As more and more semiconductor substrates are processed in the process chamber, unintended metal resist-containing material may grow as residues on the inner surfaces. Periodic cleaning is required to remove unintended deposits of metal resist-containing material. Cleaning may be performed "in situ," wherein dry chamber cleaning is performed in the same process chamber in which the unintended metal resist-containing material was formed.

[0111] Residues may form on one or more surfaces of the process chamber, wherein the one or more surfaces may include one or more of the chamber walls, top plate, bottom plate, spray head surface, nozzle surface, and substrate support surface. In some embodiments, the residues may be formed due to a dry deposition process (e.g., CVD or ALD process). The thickness of the residues on the one or more surfaces may increase over time due to additional processing (e.g., deposition) operations performed in the process chamber. In some embodiments, the average thickness of the residues is equal to or greater than about 2 nm, equal to or greater than about 3 nm, equal to or greater than about 5 nm, or equal to or greater than about 10 nm. Metal resist materials are prone to peeling, degranulation, or stripping from the one or more surfaces, thereby contaminating subsequent semiconductor substrates during processing.

[0112] Figure 6A shows a schematic cross-sectional view of a metal-containing EUV inhibitor material 602 formed on the chamber wall 604 of a process chamber. The metal-containing EUV inhibitor material 602 may include particles or clusters of metal oxide 606. The particles or clusters of metal oxide 606 may be difficult to remove. In some embodiments, the metal-containing EUV inhibitor material 602 is formed by a vapor deposition method (e.g., CVD or ALD). Over time, the metal-containing EUV inhibitor material 602 may accumulate thickness on the chamber wall 604 of the process chamber. The metal-containing EUV inhibitor material 602 may be an organotin oxide. The particles or clusters of metal oxide 606 may include tin oxide.

[0113] Returning to Figure 5, in block 504 of process 500, a dry etchant containing organic vapor is introduced into the process chamber, wherein the dry etchant at least partially removes residues on one or more surfaces of the process chamber. In some embodiments, the organic vapor is an organic acid. The organic acid may be a strong organic acid with pKa equal to or less than about 3.8. In some embodiments, the organic acid includes carboxylic acids. In some embodiments, the organic acid includes trifluoroacetic acid. The organic vapor may be halogenated or at least fluorinated. In some embodiments, the organic vapor includes hexafluoroacetic acid. In some embodiments, the organic vapor includes trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, mixed haloacetic acids (e.g., chloro-difluoro-acetic acid), sulfur-containing analogs of acetic acid, thioacetic acid, or mercaptoacetic acid. In some embodiments, the dry etchant includes a gaseous mixture of carboxylic acid and hydrogen halide. For example, the dry etchant includes a mixture of acetic acid or formic acid and hydrogen chloride or hydrogen bromide. In some embodiments, organic vapors may flow in with or without an inert / carrier gas (e.g., helium, neon, argon, xenon, and nitrogen).

[0114] In some embodiments, at least partial removal of the residue includes reacting the organic vapor with the metal-containing inhibitor material at a temperature below about 200°C to form a volatile compound. In some embodiments, at least partial removal includes substantially removing the residue, wherein "substantially removing" means removing the residue sufficiently such that at least some of the one or more surfaces are exposed after removal.

[0115] In some embodiments, the process chamber may be prepared to have desired conditions for dry chamber cleaning before the introduction of the dry etchant. Preparation of the process chamber may achieve certain pressure conditions, the content of loose particles or film impurities, moisture content, temperature conditions, or protection of surfaces or components (e.g., substrate supports) within the process chamber from the dry etchant. In some embodiments, preparing the process chamber may include flushing and / or pumping the process chamber to remove unwanted particles. Flushing gas may flow into the process chamber to facilitate the removal of unwanted particles. Flushing away metal-organic precursors can be used to avoid unwanted byproducts and ensure adequate removal of metal-organic precursors before dry chamber cleaning.

[0116] In some embodiments, the chamber walls and other components may be heated to release unreacted precursors. Heat may additionally or alternatively promote the removal of moisture from the process chamber. Without being limited by any theory, the presence of moisture slows the reaction between the dry etchant used to remove the metal resist and the metal resist material. Furthermore, the elevated temperature in the process chamber promotes a higher etching rate for removing the metal resist material. One or more heaters in the process chamber may heat the one or more surfaces to an elevated temperature. In some embodiments, the elevated temperature may be between about 20°C and about 180°C, between about 40°C and about 160°C, or between about 80°C and about 140°C.

[0117] In some embodiments, preparing the process chamber may include providing a blank substrate onto a substrate support within the process chamber. Thus, a semiconductor substrate on which a metal resist material is deposited can be removed from the process chamber prior to dry chamber cleaning. In this way, the semiconductor substrate is not exposed to the dry etchant when residues of the metal resist material are removed from one or more surfaces of the process chamber. The blank substrate may be provided onto the substrate support during dry chamber cleaning to protect the substrate support (e.g., an electrostatic chuck) from exposure to the dry etchant. Alternatively, the substrate support may be protected by providing a protective cap over it during dry chamber cleaning.

[0118] Dry etchant can be introduced through a spray nozzle overcoupled to the process chamber or through a separate chamber inlet. The dry etchant flows into the process chamber to react with residues of metal resist materials and form volatile products. Without any theoretical limitations, organometallic oxide resist materials can have tetrahedral coordination structures, and organic vapors (e.g., trifluoroacetic acid) can protonate oxygen lone pairs to form volatile byproducts. After the formation of volatile byproducts, the process chamber can be pumped and flushed to remove them. Furthermore, the process chamber can be pumped and flushed to remove residual dry etchant. Such residual dry etchant may cause undesirable etching of the semiconductor substrate in subsequent processes.

[0119] Dry chamber cleaning can be optimized to achieve low etch selectivity or high etch rate of resist material deposited in the process chamber. This allows for rapid and efficient removal of unwanted resist material. In some embodiments, higher temperatures and / or higher pressures may result in lower etch selectivity and increased etch rates with the dry etchant. For example, resist material can be removed at etch rates up to 1 nm / s. During exposure to the dry etchant, residues of metal-containing resist material on one or more surfaces may be subjected to elevated temperatures. These elevated temperatures may be between about 20°C and about 180°C, between about 40°C and about 160°C, or between about 80°C and about 140°C. In some embodiments, residues of metal-containing resist material react with organic vapors at temperatures below about 200°C to form volatile compounds. Pressures within the process chamber may be high during exposure to the dry etchant. In some embodiments, the chamber pressure is between about 0.01 Torr and 765 Torr, between about 0.1 Torr and 100 Torr, or between about 0.1 Torr and about 6 Torr. In some embodiments, the chamber pressure cycles between high and low pressure during exposure to the dry etchant. The organic vapor flow rate can also be adjusted to control etching selectivity. In some embodiments, the organic vapor flow rate is between about 0.05 SLM and about 10 SLM, or between about 0.1 SLM and about 5 SLM.

[0120] As discussed above regarding dry etching, dry chamber cleaning is performed using organic vapors (e.g., organic acids) rather than halogen vapors. Halogen vapors (e.g., hydrogen halide vapors) tend to leave residual etching byproducts after removing metal resist materials. However, organic vapors (e.g., trifluoroacetic acid) form more volatile etching byproducts that are easier to remove from the process chamber. Organic vapors (e.g., trifluoroacetic acid) can be used for dry chamber cleaning in plasma-free thermal processes. In other words, residues containing metal resist materials are removed without triggering plasma. Residual carbon, contaminants, or other residual materials may or may not be removed by exposure to plasma. In some embodiments, one or more surfaces may be exposed to oxidizing gases, such as oxygen (O₂), ozone (O₃), carbon dioxide (CO₂), or carbon monoxide (CO), after the introduction of the dry etchant.

[0121] Because the deposited film (unexposed or uncrosslinked) can be thermally cleaned without the use of plasma, the method described herein can also be used to clean downstream and upstream components of tools outside the process chamber (e.g., exhaust lines from the process chamber to the vacuum pump). More generally, this dry cleaning method can be used to clean other contaminated parts and components with a similar metallic composition (which produces volatile byproducts with organic vapors).

[0122] In some embodiments, the inner surface of the process chamber may be compatible with the organic vapors of the present invention. Instead of making the inner surface of the process chamber resistant to plasma and halogen vapors (e.g., hydrogen halides), the inner surface may comprise any material resistant only to the organic vapors of the present invention. In some embodiments, the chamber walls of the process chamber may comprise alumina, anodized aluminum, or plastic.

[0123] In some embodiments, the process chamber may include chamber component temperature control coupled to one or more surfaces (e.g., chamber walls) to control temperature. In some embodiments, the process chamber may include air inlets other than the spray head for delivering dry etchant. The air inlets may be located in areas of the process chamber with higher concentrations of metal resist materials. The air inlets may be located in areas of the process chamber where dry etchant is unlikely to be delivered via the spray head. In some embodiments, the air inlets may be located below the substrate support, within the walls of the process chamber, and / or near the exhaust point of the process chamber. Multiple air inlets may be used to deliver dry etchant into the process chamber. This ensures dry cleaning of the entire process chamber. In many embodiments, the dry etchant is delivered into the process chamber through one or more air inlets separate from the spray head, and the deposited gas can be delivered into the process chamber through the spray head. In some embodiments, the spray head may supply individual gases by keeping the gas largely isolated within the spray head. The spray head may include multiple gas chamber volumes. Multiple drain lines can be used to ensure that gases downstream of the process chamber are separated. Switches can be operablely coupled to multiple drain lines to isolate dry etching chemicals from deposited gases / precursors.

[0124] To protect the spray head, a pressure differential can be used to prevent dry etchant from entering the spray head (e.g., backflow). In some embodiments, the dry etchant can clean the inner surface of the spray head by flowing it through it. However, residual organic vapors or moisture may remain in the channels of the spray head. In some embodiments, the spray head may be made of a transparent material and can be heated by a suitable light source. For example, a radiation source tuned to an appropriate wavelength (e.g., IR or blue wavelength) can directly heat the residual organic vapors and / or moisture to remove them. Alternatively, residual organic vapors and / or moisture can be removed by gas flushing.

[0125] Figure 6B shows a schematic cross-sectional view of the chamber wall 604 after the dry etchant has removed the metal-containing EUV resist material 602 from the chamber wall 604. The dry etchant may include organic vapors, such as organic acids, which may include trifluoroacetic acid. The chamber wall 604 may be heated to high temperatures to promote low etch selectivity. The process chamber may be increased to high pressure to promote low etch selectivity. The removal of the metal-containing EUV resist material 602 can be performed without the use of plasma. After exposure to the dry etchant, residual particles or clusters of metal oxide 606 may remain on the chamber wall 604. In addition, residual dry etchant 608 may remain in the process chamber.

[0126] Referring back to Figure 5, in block 506 of process 500, the process chamber may be flushed as needed to remove residual dry etchant from the process chamber. The flushing operation may involve either introducing flushing gas into the process chamber or a combination of introducing flushing gas and pumping the process chamber to the desired chamber pressure. The flushing gas may be an inert gas and / or a reactive gas. The reactive gas may react with the residual dry etchant to promote removal. The reactive gas may be, for example, a tin-based precursor, such as an organotin precursor. The inert gas may be argon, helium, xenon, or nitrogen. The chamber pressure may be between approximately 0.1 Torr and approximately 6 Torr.

[0127] In some embodiments, the rinsing operation can be performed at a high temperature. The high temperature facilitates the removal of organic vapors from the process chamber. In one example, one or more heaters coupled to one or more surfaces of the process chamber can heat the process chamber to a high temperature. In another example, one or more IR sources or LEDs can be mounted in the process chamber to heat the process chamber to a high temperature. The high temperature can be between about 20°C and about 180°C, or between about 80°C and about 140°C.

[0128] In some embodiments, direct or remote plasma-based treatments can be used to accelerate the removal of residual dry etchant, which may have coated the inner surfaces of the process chamber after dry chamber cleaning. In other embodiments, non-plasma treatments can be used to accelerate the removal of residual dry etchant. Oxidizing gases may be introduced to oxidize the residual dry etchant. Therefore, non-plasma treatments may include delivering ozone and / or oxygen streams.

[0129] Figure 6C shows a schematic cross-sectional view of the chamber wall 604 after the removal of residual dry etchant 608 from the process chamber. Pumping / flushing operations can be performed to remove the residual dry etchant 608 from the process chamber. In some embodiments, the chamber wall 604 or other components of the process chamber can be heated to facilitate the release of the residual dry etchant 608. In some embodiments, direct or remote plasma-based treatments can be applied to remove the residual dry etchant 608, wherein such plasma-based treatments may include fluorine-based plasma processes, oxygen-based plasma processes, or combinations thereof. In some other embodiments, non-plasma treatments can be applied to remove the residual dry etchant 608. Particles or clusters of metal oxide 606 may remain on the chamber wall 604.

[0130] Returning to Figure 5, in block 508 of process 500, one or more surfaces of the process chamber can be adjusted as needed by forming a protective coating containing a metal resist material on one or more surfaces of the process chamber. The average thickness of the protective coating may be less than the average thickness of the metal resist material residue. In some embodiments, the average thickness of the protective coating is equal to or greater than about 1 nm, equal to or greater than about 2 nm, equal to or greater than about 3 nm, or between about 1 nm and about 5 nm. Alternatively, one or more surfaces can be adjusted as needed by forming a protective coating made of a material different from the metal resist material. Such protective coatings may be variants of organotin oxides. After exposure to a dry etchant, one or more surfaces remain exposed. Exposed surfaces in the process chamber may be vulnerable to attack, particularly halogen-based substances. Adjustment operations can provide protection for one or more surfaces. Furthermore, adjustment operations can cover residual metal oxide particles or clusters attached to one or more surfaces. In this way, metal oxide particles or clusters are less likely to contaminate the wafer during subsequent processing.

[0131] Conditioning one or more surfaces of the process chamber can be performed using vapor-phase deposition techniques (e.g., CVD or ALD). Organometallic materials are generated in the vapor phase and deposited onto one or more surfaces of the process chamber. The organometallic materials can be deposited, for example, based on the vapor-phase reaction of an organotin precursor (e.g., isopropyl(tris)(dimethylamino)tin) with water vapor. The water vapor flow rate can be relatively low. During conditioning, the substrate support can be protected or covered by a blank wafer or other protective coating. A protective coating can be formed on the chamber walls, bottom plate, top plate, or chamber components, such as inlets, spray nozzles, and outlet lines. After depositing the protective coating containing a metal resist material, a pumping / rinsing operation can be performed to remove excess precursors and / or reactants. Conditioning one or more surfaces of the process chamber can trap residual metal oxide particles and limit particulate contamination.

[0132] Figure 6D shows a schematic cross-sectional view of a metal resist material 610 formed on the chamber wall 604 of a process chamber. The metal resist material 610 can be redeposited during conditioning to protect the chamber wall 604 during processing and trap metal oxide 606 particles or clusters to prevent wafer contamination. This can also be referred to as chamber seasoning. The metal resist material 610 is formed by vapor deposition (e.g., CVD or ALD). In some embodiments, the metal resist material 610 may be an organotin oxide. By conditioning / tuning the chamber wall 604 and other inner surfaces of the process chamber, undesirable first wafer effects can be mitigated when restarting the deposition operation on the semiconductor substrate.

[0133] Although this invention frequently refers to the removal of exposed and / or developed EUV-sensitive films, the removal process can be extended to EUV films with similar compositions (e.g., other MO xR y-based films), such as other films containing metal oxides, where the metal can form volatile byproducts with organic vapors, including unexposed EUV blocking films. In some embodiments, films other than EUV blockers can be removed by this method, such as hard masks, UV blockers, or films with similar compositions for other applications; in this respect, the removal process is related to the chemical composition of the film rather than its function. [equipment]

[0134] The apparatus of this invention is configured for dry removal of EUV resist. The apparatus can be configured to perform dry development or dry chamber cleaning. The apparatus can be configured for other processing operations, such as deposition, bevel and backside cleaning, post-coating baking, EUV scanning, post-exposure baking, photoresist reprocessing, descaling, smoothing, curing, and other operations. In some embodiments, the apparatus is configured to perform all dry operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus may include a single wafer chamber or multiple stations within the same process chamber. Because there are multiple stations within the same process chamber, various processing operations (such as those described herein) can be performed at different stations within the same process chamber. In one example, PEB heat treatment can be performed in one station and developed in another.

[0135] An apparatus configured for dry removal of EUV resist includes a process chamber with a substrate support. The apparatus may include a dry etching line coupled to the process chamber for delivering etching gas. In some embodiments, the etching gas includes an organic vapor, such as trifluoroacetic acid. The apparatus may include one or more heaters for temperature control. These heaters may be provided in the process chamber and / or the substrate support. In some embodiments, multiple inlets may be located within the process chamber to direct the etching gas to areas near which unintended EUV resist tends to form. The apparatus may further include one or more sensors for sensing particle counts, wafer counts, thickness counts, or other parameters for triggering dry chamber cleaning and / or the endpoint of dry chamber cleaning.

[0136] In some embodiments, the process chamber is made of an inexpensive material (e.g., plastic). In other embodiments, the process chamber is made of metal (e.g., anodized aluminum) or ceramic (e.g., alumina).

[0137] Figure 7 illustrates a schematic diagram of an exemplary process station according to some embodiments, suitable for performing dry development, cleaning, reprocessing, descaling, and smoothing operations. Multiple process stations 700 may be contained within a common low-pressure process tool environment. For example, Figure 8 illustrates an embodiment of a multi-station processing tool 800, such as the VECTOR® processing tool available from Lam Research Corporation in Fremont, California. In some embodiments, one or more hardware parameters of the process station 800 (including those discussed in detail below) may be programmed by one or more computer controllers 850.

[0138] Process stations can be configured as modules within a cluster of tools. Figure 10 illustrates a semiconductor process cluster tool architecture with vacuum-integrated deposition and patterning modules suitable for implementing the embodiments described herein. Such cluster process tool architectures may include resist deposition, resist exposure (EUV scanner), resist development, and etching modules, as described above and further with reference to Figures 9 and 10 below.

[0139] In some embodiments, certain processing functions can be performed continuously in the same module, such as dry development and etching or dry deposition and dry chamber cleaning. Furthermore, embodiments of the present invention are directed to methods and apparatus for: receiving a wafer (including an EUV resist film layer disposed on the layer to be etched or a stack of layers) into a dry development / etching chamber after photopatterning in an EUV scanner; performing dry development on the photopatterned EUV resist film layer; and subsequently etching the underlying layer using the patterned EUV resist as a mask, as described herein.

[0140] Referring back to Figure 7, process station 700 is in fluid communication with reactant delivery system 701 to deliver process gases to distribution spray heads 706. Reactant delivery system 701 optionally includes mixing container 704 for mixing and / or regulating process gases for delivery to spray heads 706. One or more mixing container inlet valves 720 control the introduction of process gases into mixing container 704. Under plasma exposure, plasma can also be delivered to spray heads 706, or it can be generated in process station 700. As described above, in at least some embodiments, non-plasma thermal exposure is advantageous.

[0141] Figure 7 includes an optional vaporization point 703 for vaporizing liquid reactants to be supplied to mixing vessel 704. In some embodiments, a liquid flow controller (LFC) may be provided upstream of vaporization point 703 to control the mass flow rate of the liquid for vaporization and delivery to process station 700. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted to respond to feedback control signals provided by a proportional-integral-derivative (PID) controller electrically connected to the MFM.

[0142] The spray head 706 distributes process gases to the substrate 712. In the embodiment shown in FIG. 7, the substrate 712 is located below the spray head 706 and is shown resting on the base 708. The spray head 706 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gases to the substrate 712.

[0143] In some embodiments, the base 708 may be raised or lowered to expose the substrate 712 in the volume 707 between the substrate 712 and the spray head 706. It will be appreciated that in some embodiments, the base height may be adjusted in a programmed manner via a suitable computer controller 750. In some embodiments, the spray head 706 may have multiple air chamber volumes with multiple temperature controls.

[0144] In some embodiments, the base 708 may be temperature-controlled via the heater 710. In some embodiments, during the non-plasma thermal exposure of the photopatterning resist to organic vapor developing chemicals (e.g., trifluoroacetic acid), the base 708 may be heated to above 0°C and up to 300°C or higher, for example, 40 to 160°C, such as about 80 to 140°C, as described in the disclosed embodiments. In some embodiments, the heater 710 of the base 708 may include a plurality of independently controllable temperature control zones.

[0145] Furthermore, in some embodiments, pressure control of process station 700 can be provided via butterfly valve 718. As shown in the embodiment of FIG7, butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 700 can also be adjusted by changing the flow rate of one or more gases introduced into process station 700.

[0146] In some embodiments, the position of the spray head 706 can be adjusted relative to the base 708 to change the volume 707 between the substrate 712 and the spray head 706. Furthermore, it will be understood that the vertical position of the base 708 and / or the spray head 706 can be varied within the scope of the invention by any suitable mechanism. In some embodiments, the base 708 may include a rotation axis for rotating the orientation of the substrate 712. It will be understood that in some embodiments, one or more of these exemplary adjustments can be performed in a programmed manner by one or more suitable computer controllers.

[0147] In plasma-usable applications (e.g., deslagging or smoothing operations), the spray head 706 and base 708 are electrically communicated with the radio frequency (RF) power supply 714 and matching network 716 to power the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the following: process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 714 and matching network 716 can operate at any suitable power to form a plasma with the desired free radical species composition. Examples of suitable power are up to about 500 W.

[0148] In some embodiments, instructions for controller 750 may be provided via input / output control (IOC) sequence instructions. In one example, instructions for setting conditions for a process stage may be included in the corresponding formulation stage of the process formulation. In some embodiments, process formulation stages may be sequentially arranged such that all instructions for a process stage are executed simultaneously with that process stage. In some embodiments, instructions for setting one or more reactor parameters may be included in the formulation stage. For example, the formulation stage may include instructions for setting the flow rate of a dry developing chemical reaction gas (e.g., trifluoroacetic acid) and time delay instructions for the formulation stage. In some embodiments, controller 750 may include any of the features described below with respect to system controller 850 of FIG8.

[0149] As described above, one or more process stations may be included in a multi-station processing tool. Figure 8 shows a schematic diagram of an embodiment of a multi-station processing tool 800 having an inbound loading chamber 802 and an outbound loading chamber 804 (one or both of which may include a remote plasma source). A robot 806 operating at atmospheric pressure is configured to move a wafer from a pod loaded through a transfer pod 808 to the inbound loading chamber 802 via an atmospheric port 810. The wafer is placed on a base 812 in the inbound loading chamber 802 by the robot 806, the atmospheric port 810 is closed, and the loading chamber is pumped. In the case where the inbound loading chamber 802 includes a remote plasma source, the wafer may be exposed to remote plasma processing before being introduced into the processing chamber 814 to process the substrate surface in the loading chamber. Furthermore, the wafer may also be heated in the inbound loading chamber 802, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 816 to the processing chamber 814 is opened, and another robot (not shown) places the wafer onto the base of the first station in the reactor (shown in the reactor) for processing. Although the embodiment shown in Figure 8 includes a loading chamber, it will be understood that in some embodiments, the wafer may be provided directly into the process station.

[0150] The illustrated processing chamber 814 includes four process stations, numbered 1 to 4 in the embodiment shown in FIG. 8. Each station has a heating base (shown as 818 in station 1) and a gas line inlet. It will be appreciated that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, the process station may switch between dry developing and etching process modules. Additionally or alternatively, in some embodiments, processing chamber 814 may include one or more pairs of matched dry developing and etching process stations. Although the illustrated processing chamber 814 includes four stations, it will be understood that the processing chamber according to the invention may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0151] Figure 8 illustrates an embodiment of a wafer handling system 890 for transferring wafers within a processing chamber 814. In some embodiments, the wafer handling system 890 can transfer wafers between multiple process stations and / or between process stations and loading chambers. It will be appreciated that any suitable wafer handling system can be employed. Non-limiting examples include wafer conveyors and wafer handling robots. Figure 8 also illustrates an embodiment of a system controller 850 for controlling process conditions and the hardware status of process tools 800. The system controller 850 may include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0152] In some implementations, system controller 850 controls all activities of process tool 800. System controller 850 executes system control software 858 stored in mass storage device 854, loaded into memory device 856, and executed on processor 852. Alternatively, control logic can be hard-coded into controller 850. Application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays or FPGAs) and the like can be used for these purposes. In the following discussion, regardless of whether "software" or "coding" is used, functionally equivalent hard-coded logic can be used in this situation. System control software 858 may include parameters for controlling timing, gas mixing, gas flow rate, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power level, RF power level, substrate base, chuck and / or die position, and other parameters for specific processes executed by process tool 800. System control software 858 can be configured in any suitable manner. For example, numerous process tool component subroutines or control objects can be written to control the operation of the process tool components used to implement various process tool processes. The system control software 858 can be coded in any suitable computer-readable programming language.

[0153] In some embodiments, system control software 858 may include input / output control (IOC) sequence instructions for controlling the aforementioned parameters. In some embodiments, other computer software and / or programs stored on a mass storage device 854 and / or memory device 856 associated with system controller 850 may be used. Examples of programs or program fragments used for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0154] The substrate positioning program may include program code for a process tool component, which is used to load the substrate onto the base 818 and control the spacing between the substrate and other components of the process tool 800.

[0155] The process gas control program may include codes for controlling the composition and flow rate of organic vapors (e.g., trifluoroacetic acid as described herein), and optionally for stabilizing the pressure in one or more process chambers prior to deposition. The pressure control program may include codes for controlling the pressure in the process station by regulating, for example, throttle valves in the process station's exhaust system or the gas flow rate entering the process station.

[0156] The heater control program may include coding to control the current flowing to the heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat-conducting gas (e.g., helium) to the substrate.

[0157] The plasma control program may include coding for setting the RF power level applied to process electrodes in one or more process stations, according to embodiments herein.

[0158] The pressure control program may include coding for maintaining the pressure within the reaction chamber, according to the embodiments herein.

[0159] In some implementations, a user interface may be associated with the system controller 850. The user interface may include a display screen, a graphical software display of device and / or process conditions, and user input devices (such as pointing devices, keyboards, touch screens, microphones, etc.).

[0160] In some implementations, the parameters adjusted by the system controller 850 may be related to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), etc. These parameters may be provided to the user in the form of a recipe (which can be input via a user interface).

[0161] Through the analog and / or digital input connectors of the system controller 850, signals for monitoring the process can be obtained from various process tool sensors. Signals for controlling the process can be output on the analog and / or digital output connectors of the process tool 800. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (e.g., pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain process conditions.

[0162] The system controller 850 provides programming instructions for implementing the deposition process described above. These programming instructions can control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. These instructions can control these parameters to operate the development, cleaning, and / or etching processes according to the various embodiments described herein.

[0163] System controller 850 will typically include one or more memory devices and one or more processors configured to execute the instructions such that the device will perform the method according to the disclosed embodiments. Machine-readable media (containing instructions for controlling process operations according to the disclosed embodiments) may be coupled to system controller 850.

[0164] In some embodiments, the system controller 850 is part of a system, which may be part of one of the examples described above. Such systems may include semiconductor processing equipment comprising a processing tool or multiple tools, a chamber or multiple chambers, a processing platform or multiple platforms, and / or specific processing components (wafer pedestals, airflow systems, etc.). Such systems may be combined with electronic equipment to control the operation of semiconductor wafers or substrates before, during, and after processing. Such electronic equipment may refer to a "controller" that controls various components or subcomponents of the system or multiple systems. Depending on the processing conditions and / or system type, the system controller 850 may be programmable to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (such as heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, and wafer transfer (entry and exit to tools and other transfer tools connected or coupled to a specific system, and / or loading chambers).

[0165] Broadly speaking, system controller 850 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, initiating cleaning operations, initiating endpoint measurements, and the like. Integrated circuits may include: a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller executing program instructions (e.g., software). Program instructions may be instructions transmitted to system controller 850 in the form of various individual settings (or program files), which define operating parameters for implementing a specific process (on a semiconductor wafer, or for a semiconductor wafer, or for a system). In some implementations, the operating parameters may be part of a formulation defined by a process engineer to achieve one or more processing steps during the manufacturing process of one or more of the following: layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer grains.

[0166] In some embodiments, the system controller 850 may be part of a computer, or coupled to a computer that is integrated with, coupled to, or connected to the system via other networks, or a combination thereof. For example, the system controller 850 may be in all or part of a cloud-based or factory mainframe computer system that allows remote access to wafer processing. The computer enables the system to remotely access and monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, check trends or performance metrics from multiple manufacturing operations, change parameters for the current process, set processing steps after the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network, which may include a local area network or the Internet. The remote computer may include a user interface capable of parameter and / or setting input or programming, which can then be transmitted from the remote computer to the system. In some examples, system controller 850 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool with which system controller 850 is coupled or controlled. Therefore, as described above, system controller 850 may be distributed, for example, by comprising one or more separate controllers networked together and operating toward a common purpose (e.g., the processes and control described herein). An example of a distributed controller for this purpose is one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), both combined to control the process on the chamber.

[0167] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, rotary cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, EUV lithography chambers (scanners) or modules, developing chambers or modules, and any other semiconductor processing systems that may be associated with or used in the manufacture and / or processing of semiconductor wafers.

[0168] As described above, depending on the process steps or plural steps to be performed with recourse to the tool, the system controller 850 may communicate with one or more of the following in the semiconductor manufacturing plant: other tool circuits or modules, other tool members, cluster tools, other tool interfaces, adjacent tools, adjacent tools, tools distributed throughout the plant, a master computer, another controller, or tools used in a material transport to and from the ports used in the material transport / carriage port.

[0169] An inductively coupled plasma (ICP) reactor, which in certain embodiments may be applicable to etching operations suitable for implementing certain embodiments, is now described. Despite the ICP reactors described herein, in some embodiments it should be understood that capacitively coupled plasma reactors can also be used.

[0170] 9 schematically illustrates a cross-sectional view of an inductively coupled plasma equipment 900 suitable for implementing certain embodiments or embodiments such as dry development, cleaning, and / or etching, exemplified by a Kiyo® reactor produced by Lam Research Corporation, Ferrimon Collin, California. In other embodiments, other tools or tool types having the function of performing the dry developing, cleaning, and / or etching processes described herein may be used for implementation.

[0171] The inductively coupled plasma apparatus 900 includes an entire process chamber structurally defined by chamber walls 901 and windows 911. Chamber walls 901 may be made of stainless steel, aluminum, or plastic. Windows 911 may be made of quartz or other dielectric materials. An optional internal plasma grid 950 divides the entire process chamber into an upper sub-chamber 902 and a lower sub-chamber 903. In most embodiments, the plasma grid 950 can be removed, thus utilizing the chamber space formed by sub-chambers 902 and 903. A chuck 917 is located within the lower sub-chamber 903 near its bottom inner surface. The chuck 917 is configured to receive and hold a semiconductor wafer 919 on which etching and deposition processes are performed. The chuck 917 may be an electrostatic chuck for supporting the wafer 919 (when present). In some embodiments, an edge ring (not shown) surrounds the chuck 917 and has an upper surface that is substantially flat with the top surface of the wafer 919 (when present above the chuck 917). The chuck 917 also includes electrostatic electrodes for adsorbing and desorbing the wafer 919. For this purpose, a filter and a DC (DV) clamping power supply (not shown) may be provided. Other control systems for lifting the wafer 919 away from the chuck 917 may also be provided. The chuck 917 may be charged using an RF power supply 923. The RF power supply 923 is connected to a matching circuit 921 via a connection 927. The matching circuit 921 is connected to the chuck 917 via a connection 925. In this way, the RF power supply 923 is connected to the chuck 917. In many embodiments, depending on the process performed according to the disclosed embodiments, the bias power of the electrostatic chuck may be set to approximately 50 V or may be set to a different bias power. For example, the bias power can be between about 20 V and about 100 V, or between about 30 V and about 150 V.

[0172] The element for generating plasma includes a coil 933 located above window 911. In some embodiments, the disclosed embodiments do not use a coil. The coil 933 is made of a conductive material and includes at least one full turn. The example coil 933 shown in FIG9 includes three turns. The cross-section of the coil 933 is shown in symbols, with the coil having an "X" extending into the page and the coil having a "●" extending out of the page. The element for generating plasma also includes an RF power supply 941 configured to supply RF power to the coil 933. Generally, the RF power supply 941 is connected to a matching circuit 939 via connection 945. The matching circuit 939 is connected to the coil 933 via connection 943. In this way, the RF power supply 941 is connected to the coil 933. An optional Faraday shield 949 is located between the coil 933 and window 911. The Faraday shield 949 may be spaced apart relative to the coil 933. In some embodiments, the Faraday shield 949 is positioned directly above window 911. In some embodiments, the Faraday shield 949 is located between the window 911 and the suction cup 917. In some embodiments, the Faraday shield 949 is not spaced apart from the coil 963. For example, the Faraday shield 949 may be directly below the window 911 without gaps. The coil 933, the Faraday shield 949, and the window 911 are each configured to be substantially parallel to each other. The Faraday shield 949 prevents the deposition of metal or other species on the window 911 of the process chamber 924.

[0173] Process gases can flow into the process chamber through one or more main gas inlets 960 located in the upper secondary chamber 902 and / or through one or more side gas inlets 970. Similarly, although not explicitly shown, similar gas inlets can be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump (e.g., a first- or second-order mechanical dry and / or turbomolecular pump) 940 can be used to extract process gases from the process chamber 924 and maintain pressure within the process chamber 924. For example, during a flushing operation, the vacuum pump can be used to evacuate the lower secondary chamber 903. Valve-controlled conduits can be used to fluidly connect the vacuum pump to the process chamber 924 to selectively control the application of the vacuum environment provided by the vacuum pump. This can be accomplished using a closed-loop controlled flow-limiting device during plasma processing, such as a throttle valve (not shown) or a pendulum (not shown). Similarly, a vacuum pump and valve-controlled fluid connection can also be used for the capacitively coupled plasma processing chamber.

[0174] During operation of the apparatus 900, one or more process gases may be supplied through airflow inlets 960 and / or 970. In some embodiments, process gases may be supplied only through the main airflow inlet 960 or only through the side airflow inlet 970. In some examples, the airflow inlets shown in the figure may be replaced by more complex airflow inlets (e.g., one or more spray heads). The Faraday shield 949 and / or optional grille 950 may include internal channels and orifices that allow process gases to be delivered to the process chamber 924. One or both of the Faraday shield 949 and optional grille 950 may serve as spray heads for the delivery of process gases. In some embodiments, a liquid vaporization and delivery system may be located upstream of the process chamber 924, so that once the liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber 924 through airflow inlets 960 and / or 970.

[0175] Radio frequency (RF) power is supplied from RF power source 941 to coil 933, causing RF current to flow through coil 933. The RF current flowing through coil 933 generates an electromagnetic field around coil 933. The electromagnetic field induces a current in the upper secondary chamber 902. Numerous generated ions and free radicals physically and chemically interact with wafer 919, etching the feature areas of wafer 919 and selectively depositing layers on wafer 919.

[0176] If a plasma grid 950 is used, and there are both an upper sub-chamber 902 and a lower sub-chamber 903, the induced current acts on the gas present in the upper sub-chamber 902 to generate an electron-ion plasma in the upper sub-chamber 902. The optional internal plasma grid 950 limits the number of thermionic electrons in the lower sub-chamber 903. In some embodiments, the device 900 is designed and operated such that the plasma present in the lower sub-chamber 903 is an ion-ion plasma.

[0177] Both the upper electron-ion plasma and the lower ion-ion plasma can contain both positive and negative ions, but the ion-ion plasma will have a greater ratio of negative to positive ions. Volatile etching and / or deposition byproducts can be removed from the lower sub-chamber 903 through port 922. The chuck 917 disclosed herein can operate at elevated temperatures between approximately 10°C and approximately 250°C. The temperature will depend on the process operation and specific formulation.

[0178] When the device 900 is installed in a cleanroom or manufacturing facility, it can be coupled to the facility (not shown). The facility includes piping for providing process gases, vacuum, temperature control, and environmental particle control. When installed in the target manufacturing facility, these facilities are coupled to the device 900. Additionally, the device 900 can be coupled to a transfer chamber, which allows robots to use typical automation to transfer semiconductor wafers in and out of the device 900.

[0179] In some embodiments, system controller 930 (which may include one or more physical or logic controllers) controls some or all of the operation of process chamber 924. System controller 930 may include one or more memory devices and one or more processors. In some embodiments, device 900 includes a switching system for controlling flow rate and duration when performing the disclosed embodiments. In some embodiments, device 900 may have a switching time of up to about 500 ms or up to about 750 ms. The switching time may depend on flow chemistry, selected formulation, reactor structure, and other factors.

[0180] In some embodiments, the system controller 930 is part of a system, which may be part of one of the examples described above. Such systems may include semiconductor processing equipment comprising a processing tool or multiple tools, a chamber or multiple chambers, a processing platform or multiple platforms, and / or specific processing components (wafer pedestals, airflow systems, etc.). Such systems may be combined with electronic equipment to control the operation of semiconductor wafers or substrates before, during, and after processing. Such electronic equipment may be integrated into the system controller 930, which can control various components or sub-components of the system or multiple systems. Depending on the processing conditions and / or system type, the system controller may be programmable to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, and wafer transfer (entry and exit to tools and other transfer tools connected or coupled to a specific system, and / or loading chambers).

[0181] Broadly speaking, the system controller 930 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, initiating cleaning operations, initiating endpoint measurements, and the like. Integrated circuits may include: a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). Program instructions may be instructions transmitted to the controller in the form of various individual settings (or program files) that define operating parameters for implementing a specific process (on a semiconductor wafer, or for a semiconductor wafer, or for a system). In some implementations, the operating parameters may be part of a formulation defined by a process engineer to achieve one or more processing steps during the manufacturing process of one or more of the following: layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer grains.

[0182] In some embodiments, the system controller 930 may be part of a computer, or coupled to a computer that is integrated with, coupled to, or networked with the system, or a combination thereof. For example, the controller may be located in all or part of a cloud-based or factory mainframe computer system that allows remote access to wafer processing. The computer enables the system to remotely access and monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, check trends or performance metrics from multiple manufacturing operations, change parameters for the current process, set processing steps after the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network, which may include a local area network or the Internet. The remote computer may include a user interface capable of parameter and / or setting input or programming, which can then be transmitted from the remote computer to the system. In some examples, the system controller 930 receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that parameters can be specific to the type of process to be performed and the type of tool with which the controller is coupled or controlled. Therefore, as described above, the system controller 930 can be distributed, for example, by comprising one or more separate controllers that are networked together and operate toward a common purpose (e.g., the process and control described herein). An example of a distributed controller for this purpose is one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), both combined to control the process on the chamber.

[0183] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, rotary cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, track chambers or modules, EUV lithography chambers (scanners) or modules, dry developing chambers or modules, and any other semiconductor processing systems that may be associated with or used in the manufacture and / or processing of semiconductor wafers.

[0184] As described above, depending on the process steps or plural steps to be performed with recourse to the tool, the controller may communicate with one or more of the following in a semiconductor manufacturing plant: other tool circuits or modules, other tool members, cluster tools, other tool interfaces, adjacent tools, adjacent tools, tools distributed throughout the plant, a master computer, another controller, or a tool used in a material conveying, and the tool port used in or to which the container is loaded to and from.

[0185] EUVL patterning can be performed using any suitable tool commonly referred to as a scanner, such as the TWINSCAN NXE:3300B® platform supplied by ASML (Veldhoven, The Netherlands). The EUVL patterning tool can be a separate apparatus for the substrate to move in and out for deposition and etching described herein. Alternatively, as described below, the EUVL patterning tool may be a module on a larger multi-member tool. Figure 10 plots a tool architecture for a semiconductor process cluster with vacuum integrated deposition, EUV patterning and dry development / etch modules (joined with vacuum transfer modules), which are applicable to implementing the processes described herein. Despite the fact that the process can be performed without such vacuum integration equipment, such equipment may be advantageous in some embodiments.

[0186] Figure 10 plots a tool architecture for a semiconductor process cluster with vacuum-integrated deposition and patterning modules (which are interfacing with vacuum transfer modules), which are applicable to implementing the processes described herein. The arrangement of transfer modules used to "transfer" wafers between multiple storage facilities and processing modules may be referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum integrated according to the requirements of the specific process. Other modules (e.g. for etching) can also be included in the cluster.

[0187] The vacuum transfer module (VTM) 1038 is connected to four processing modules 1020a-1020d (which can be separately optimized to perform numerous manufacturing processes). For example, treatment modules 1020a-1020d may be implemented to perform deposition, evaporation, ELD, dry development, cleaning, etching, stripping, and / or other semiconductor processes. For example, module 1020a may be an ALD reactor, which may be operated to perform thermal atomic layer deposition as described herein in a non-electric plasma, for example, a Vector tool available from Lam Research Corporation, Ferrimon Collin, California. Additionally, module 1020b may be a PECVD tool, such as Lam Vector®. It should be understood that the diagram is not necessarily drawn to scale.

[0188] Gas chambers 1042 and 1046 (also referred to as loading chambers or transfer modules) are connected to VTM 1038 and patterning module 1040. For example, as described above, a suitable patterning module could be the TWINSCAN NXE:3300B® platform supplied by ASML (Felderhofen, Netherlands). This tooling architecture allows workpieces (e.g., semiconductor substrates or wafers) to be transferred under vacuum so as not to react before exposure. Considering the strong light absorption of incident photons by ambient gases (such as H₂O, O₂, etc.) and the need for a significant reduction in pressure for EUVL, the integration of the deposition module with the lithography tooling is encouraged.

[0189] As described above, this integrated architecture is merely one possible implementation of the tools used to carry out the process. These processes can also be implemented using standalone EUVL scanners and deposition reactors (e.g., Lam Vector tools), either independently or integrated with other tools (e.g., etching, stripping, etc.) in a cluster architecture (e.g., Lam Kiyo or Gamma tools) as modules, as shown in Figure 10, but without an integrated patterned module.

[0190] Gas chamber 1042 can be an "output" loading chamber, referring to the transfer of the substrate from VTM 1038 for deposition module 1020a to patterning module 1040, while gas chamber 1046 can be an "in" loading chamber, referring to the transfer of the substrate from patterning module 1040 back to VTM 1038. The in loading chamber 1046 can also provide an interface to the outside of the tool for substrate entry and exit. Each process module has a facet that bonds the module to VTM 1038. For example, deposition process module 1020a has facet 1036. Within each facet, sensors (e.g., sensors 1-18 shown) are used to detect the passage of wafer 1026 as it moves between corresponding stations. Patterning module 1040 and gas chambers 1042 and 1046 can similarly accommodate additional facets and sensors (not shown).

[0191] A primary VTM robot 1022 transfers wafers 1026 between modules (including gas chambers 1042 and 1046). In one embodiment, robot 1022 has one arm, while in another embodiment, robot 1022 has two arms, each arm having an end effector 1024 to pick up wafers (such as wafer 1026) for transfer. A front-end robot 1044 is used to transfer wafers 1026 from the output gas chamber 1042 to the patterning module 1040 and from the patterning module 1040 into the gas chamber 1046. The front-end robot 1044 can also transfer wafers 1026 between the entry loading chamber and the outside of the tool for substrate entry and removal. Because the entry gas chamber module 1046 has the ability to match environments between atmospheric and vacuum, wafers 1026 can move between two pressure environments without damage.

[0192] It should be noted that EUVL tools typically operate at higher vacuum levels than deposition tools. In this case, it is desirable to increase the vacuum environment of the substrate during the transfer from deposition to the EUV tool to allow the substrate to be degassed before entering the patterning tool. The output gas chamber 1042 provides this function by maintaining the transferred wafer at a lower pressure (not exceeding the pressure in the patterning module 1040) for a period of time and venting any exhaust gases, ensuring that the optics of the patterning tool 1040 are not contaminated by exhaust gases from the substrate. A suitable output gas chamber pressure does not exceed 1E-8 Torr.

[0193] In some embodiments, system controller 1050 (which may include one or more physical or logical controllers) controls some or all of the operations of cluster tools and / or their separate modules. It should be noted that the controller may be local to the cluster architecture, located outside the cluster architecture in the manufacturing layer, or remotely connected to the cluster architecture via a network. System controller 1050 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor control boards, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored on memory devices associated with the controller, or may be provided via a network. In some embodiments, the system controller executes system control software.

[0194] System control software may include instructions for controlling the application and / or timing of any state of operation of tools or modules. System control software can be configured in any suitable manner. For example, it may be written into various process tool component subroutines or control objects to control the operation of process tool components required to implement various process tool processes. System control software may be coded in any suitable computer-readable programming language. In some embodiments, system control software includes input / output control (IOC) sequencing instructions for controlling the aforementioned parameters. For example, each stage of a semiconductor manufacturing process may include one or more instructions executed by a system controller. For example, instructions for setting process conditions for condensation, deposition, evaporation, patterning, and / or etching stages may be included in the corresponding formulation stage.

[0195] In many embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus may include a processing chamber for patterning, deposition, and etching, and a controller including instructions for forming the negative pattern mask. The instructions may include encoding for patterning features in a chemically amplified (CAR) resist on a semiconductor substrate by exposing the surface of a substrate to EUV exposure in the processing chamber, dry developing the photo-patterning resist, and using the patterning resist as a mask to etch an underlayer or stack.

[0196] It should be noted that the computer controlling wafer movement can be located locally within the cluster architecture, or external to the cluster architecture in the manufacturing layer, or remotely connected to the cluster architecture via a network. The controller described above with respect to any of Figures 7, 8, or 9 can be implemented using the tool shown in Figure 10.

[0197] Figure 11A illustrates an example of a deposition chamber for vapor deposition of a metal resist material according to some embodiments. As can be seen, apparatus 1100 is illustrated as having a process chamber 1102, which includes a cover 1108. The process chamber 1102 may include a wafer transfer channel 1104 extending through one of the walls of the process chamber 1102, sized to allow a substrate 1122 to pass through and enter the interior of the process chamber 1102, wherein the substrate 1122 may be placed on a wafer support 1124. The wafer transfer channel 1104 may have a gate valve 1106 or a similar door mechanism operable to seal or open the wafer transfer channel 1104, thereby allowing the environment within the process chamber 1102 to be isolated from the environment on the other side of the gate valve 1106. For example, the process chamber 1102 may be supplied with the substrate 1122 by a wafer handling robot located in an adjacent transfer chamber. These transfer chambers may, for example, have a plurality of process chambers 1102 arranged around their periphery, each of which is connected to the transfer chamber via a corresponding gate valve 1106.

[0198] The wafer support 1124 may include, for example, an electrostatic chuck (ESC) 1126, which can be used to provide a wafer support surface for supporting the substrate 1122. The ESC 1126 may include, for example, a base plate 1134, which is coupled to a top plate 1128 placed on the base plate 1134. The top plate 1128 may be made of, for example, a ceramic material and may have several other components embedded therein. In the illustrated example, the top plate 1128 has two separate electrical systems embedded therein. One such system is an electrostatic clamping electrode system, which may have one or more clamping electrodes 1132 that can be used to generate a charge within the substrate 1122, thereby causing the substrate 1122 to be pulled against the wafer support surface of the top plate 1128. In the embodiment of FIG11A, two clamping electrodes 1132 are provided to provide a bipolar electrostatic clamping system, but some embodiments may use only a single clamping electrode 1132 to provide a unipolar electrostatic clamping system.

[0199] Another system is a thermal control system, which can be used to control the temperature of the substrate 1122 during processing conditions. In Figure 11A, the thermal control system is a multi-zone thermal control system, characterized by four annular resistance heater traces 1130a, 1130b, 1130c, and 1130d, which are concentric with each other and located below the clamping electrode 1132. In some embodiments, the central resistance heater trace 1130a may fill a generally circular area, and each resistance heater trace 1130a / b / c / d may follow a generally serpentine or other tortuous path within the corresponding annular area. Each resistance heater trace 1130a / b / c / d may be individually controlled to provide various radial heating profiles in the top plate 1128; in some examples, such a four-zone heating system may, for example, be controlled to maintain a temperature uniformity of ±0.5°C on the substrate 1122. Although the device 1100 of Figure 11A is characterized by a four-zone heating system in ESC 1126, other embodiments may use single-zone or multi-zone heating systems with more or fewer than four zones.

[0200] In some embodiments of the temperature control mechanism discussed above, a heat pump can be used instead of the resistance heating trace. For example, in some embodiments, the resistance heater trace can be replaced or enhanced by Peltier junctions or other similar devices that can be controlled to "pump" heat from one side to the other. Such mechanisms can be used, for example, to draw heat from the top plate 1128 (and thus the substrate 1122) and direct it to the bottom plate 1134 and the heat exchange channel 1136, thus allowing the substrate 1122 to be cooled more quickly and efficiently (if necessary).

[0201] ESC 1126 may also include, for example, a base plate 1134, which can provide structural support to the underside of the top plate 1128 and also function as a heat dissipation system. For example, the base plate 1134 may include one or more heat exchange channels 1136 distributed throughout the base plate 1134, such as following a serpentine, circular, or spiral pattern around the center of the base plate 1134. A heat exchange medium (e.g., water or an inert fluorinated liquid) can circulate through the heat exchange channels 1136 during use. The flow rate and temperature of the heat exchange medium can be externally controlled to induce specific heating or cooling behavior within the base plate 1134.

[0202] ESC 1126 may be supported, for example, by a wafer support housing 1142 connected to and supported by a wafer support pillar 1144. The wafer support pillar 1144 may, for example, have wiring channels 1148 and other through-holes for routing cables, fluid conduits, and other equipment to the underside of the base plate 1134 and / or the top plate 1128. For example, although not shown in FIG. 11A, cables for providing electrical power to the resistance heater traces 1130a / b / c / d may be routed through the wiring channels 1148, as may cables for providing electrical power to the clamping electrodes 1132. Other cables (e.g., cables for temperature sensors) may also be routed through the wiring channels 1148 to locations inside the wafer support 1124. In embodiments with a temperature-controlled base plate 1134, conduits for conveying heat exchange media in and out of the base plate 1134 may also be routed through the wiring channels 1148. To avoid excessive confusion, these cables and conduits are not shown in Figure 11A, but it is understood that they will still be present.

[0203] The apparatus 1100 of Figure 11A also includes a wafer support z-actuator 1146 that provides movable support for the wafer support pillar 1144. The wafer support z-actuator 1146 can be actuated to move the wafer support pillar 1144 and the wafer support member 1124 supported thereon vertically upward or downward within the reaction space 1120 of the process chamber 1102, for example, by several inches. In this way, the gap distance X between the substrate 1122 and the underside of the spray head 1110 can be adjusted according to various process conditions.

[0204] In some embodiments, the wafer support 1124 may also include one or more edge rings, which can be used to control and / or fine-tune various process conditions. In FIG11A, an upper edge ring 1138 is provided, located on, for example, lower edge rings 1140a and 1140b, which are in turn supported by a wafer support housing 1142 and a third lower edge ring 1140c. The upper edge ring 1138 can generally be subjected to the same processing environment as the substrate 1122, while the lower edge rings 1140a / b / c can generally be isolated from the processing environment. Due to the increased exposure of the upper edge ring 1138, it may have a limited lifespan and may require more frequent replacement or cleaning compared to the lower edge rings 1140a / b / c.

[0205] The apparatus 1100 may also include a system for removing process gases from the process chamber 1102 during and after processing. For example, the process chamber 1102 may include an annular gas chamber 1156 surrounding the wafer support pillar 1144. The annular gas chamber 1156 may also be fluidly connected to a vacuum pre-line 1152, which may be connected to a vacuum pump, for example, located below a bottom plate beneath the apparatus 1100. A regulating valve 1154 may be provided between the vacuum pre-line 1152 and the process chamber 1102 and actuated to control the flow into the vacuum pre-line 1152. In some embodiments, a baffle 1150, such as an annular plate or other structure, may be provided to distribute the flow into the annular gas chamber 1156 more evenly around the periphery of the wafer support pillar 1144, reducing the likelihood of flow inhomogeneity in the reactants flowing through the substrate 1122.

[0206] The spray head 1110 shown is a dual-chamber spray head 1110, comprising a first chamber 1112 (which is supplied with process gas through a first inlet 1116) and a second chamber 1114 (which is supplied with process gas through a second inlet 1118). Generally, two chambers can be used to keep the precursor and the corresponding reactant separated before the release of the precursor and the corresponding reactant. In some embodiments, the spray head 1110 may have more than two chambers. In some instances, a single chamber is used to deliver the precursor to the reaction space 1120 of the process chamber 1102. Each chamber may have a corresponding set of gas distribution ports that fluidly connect the corresponding chamber to the reaction space 1120 through a panel of the spray head 1110 (the panel being the portion of the spray head 1110 inserted between the lowermost chamber and the reaction space 1120).

[0207] The first inlet 1116 and the second inlet 1118 of the spray head 1110 can be supplied with treatment gas through a gas supply system, which can be configured to provide one or more precursors and / or reactants, as discussed herein. The illustrated device 1100 is configured to provide multiple precursors and multiple reactants. For example, a first valve manifold 1168a can be configured to provide a precursor to the first inlet 1116, while a second valve manifold 1168b can be configured to provide other precursors or other reactants to the second inlet 1118.

[0208] The first valve manifold 1168a may be configured to provide one or more precursors to the first inlet 1116, while the second valve manifold 1168b may be configured to provide other precursors or other reactants to the second inlet 1118. In this example, the first valve manifold 1168a includes, for example, a plurality of valves A1-A5. Valve A2 may be, for example, a three-way valve having one port fluidly connected to the first vaporizer 1172a, another port fluidly connected to the bypass line 1170a, and a third port fluidly connected to a port on another three-way valve A3. Similarly, valve A4 may be another three-way valve having one port fluidly connected to the second vaporizer 1172b, another port fluidly connected to the bypass line 1170a, and a third port fluidly connected to a port on another three-way valve A5. One of the other ports on valve A5 may be fluidly connected to the first inlet 1116, while the remaining ports on valve A5 may be fluidly connected to one of the remaining ports on valve A3. The remaining ports on valve A3 may also be fluidly connected to valve A1, which may be fluidly inserted between valve A3 and a flushing gas source 1174 (e.g., nitrogen, argon, or other suitable inert gas (relative to the precursor and / or the reactant)). In some embodiments, only the first valve manifold is used.

[0209] For the purposes of this invention, the term "fluid connection" is used with respect to volumes, chambers, orifices, etc., that can be interconnected to form a fluid connection, similar to the term "electrical connection" used with respect to components connected together to form an electrical connection. The term "fluid insertion" (if used) can be used to refer to a component, volume, chamber, or orifice that is fluidly connected to at least two other components, volumes, chambers, or orifices, such that fluid flowing from one of these other components, volumes, chambers, or orifices to the other will first flow through the "fluid insertion" component before reaching the other. For example, if a pump is fluidly inserted between a container and an outlet, fluid flowing from the container to the outlet will first flow through the pump before reaching the outlet.

[0210] The first valve manifold 1168a may be controllable, for example, to allow vapor from one or both of vaporizers 1172a and 1172b to flow into the process chamber 1102 or through the first bypass line 1170a and into the vacuum pre-line 1152. The first valve manifold 1168a may also be controllable to allow purging gas to flow from the purging gas source 1174 into the first inlet 1116.

[0211] For example, to allow steam to flow from the first vaporizer 1172a into the reaction space 1120, valve A2 can be actuated to allow steam to flow from the first vaporizer 1172a into the first bypass line 1170a. This flow rate can be maintained for a sufficient time to allow the steam flow rate to reach steady-state flow conditions. After sufficient time (or after the flow meter (if used) indicates a stable flow rate), valves A2, A3, and A5 can be actuated to direct the steam flow from the first vaporizer 1172a to the first inlet. Valves A4 and A5 can perform similar operations to deliver steam from the second vaporizer 1172b to the first inlet 1116. In some instances, it may be desirable to purge one of the steams from the first gas chamber 1112 by actuating valves A1, A3, and A5 to allow purge gas from the purge gas source 1174 into the first inlet 1116. In some additional embodiments, it may be desirable to simultaneously allow vapor from either vaporizer 1172a or 1172b to flow into the first inlet 1116 along with gas from the flushing gas. These embodiments can be used to dilute the concentration of reactants contained in these vapors.

[0212] It will be understood that the second valve manifold 1168b can be controlled in a similar manner, for example, by controlling valves B1-B5 to supply vapor from vaporizers 1172c and 1172d to the second inlet 11318 or to the second bypass line 1170b. It will also be understood that different manifold arrangements can be used, including a single integral manifold including valves for controlling the flow of precursors, reactants, or other reactants to the first inlet 1116 and the second inlet 1118.

[0213] As previously mentioned, some devices 1100 may be characterized by a smaller number of vapor sources, such as only two vaporizers 1172, wherein the valve manifold 1168 may be modified to have a smaller number of valves, such as only valves A1-A3.

[0214] As discussed above, equipment used for dry deposition of films (e.g., equipment 1100) can be configured to maintain a specific temperature profile within the process chamber 1102. In particular, such equipment 1100 can be configured to maintain the substrate 1122 at a lower temperature, for example, at least 25°C to 50°C lower than most equipment of equipment 1100 that directly contacts the precursors and / or reactants. Additionally, the equipment temperature of equipment 1100 that directly contacts the precursors and / or reactants can be maintained at a sufficiently high level to prevent vaporized reactants from condensing on the equipment surface. Simultaneously, the temperature of the substrate 1122 can be controlled to a level that promotes the condensation or at least deposition of reactants on the substrate 1122.

[0215] To provide such temperature control, various heating systems may be included in the device 1100. For example, the process chamber 1102 may have a container for receiving a box heater 1158, for example, a process chamber 1102 having a generally cylindrical internal volume but a square or rectangular external shape, with vertical holes for receiving the box heater 1158 drilled in the four corners of the chamber 1102 housing. In some embodiments, the spray head 1110 may be covered by a heater blanket 1160, which can be used to apply heat to the exposed upper surface of the spray head 1110 to maintain the spray head temperature elevated. Heating the various gas lines used to conduct vaporized reactants from the vaporizer 1172 to the spray head 1110 may also be advantageous. For example, resistance heating strips may be wrapped around these gas lines and used to heat them to elevated temperatures. As shown in FIG11A, all gas lines through which precursors and / or relative reactants may flow are shown as being heated, including bypass line 1170. The only exception is the gas line from valve manifold 1168 to the first inlet 1116 and the second inlet 1118, which may be short and may be indirectly heated by the spray head 1110. Of course, these gas lines can even be actively heated (if desired). In some embodiments, a heater may be provided near the gate valve 1106 to provide heat to the gate valve.

[0216] The various operating systems of device 1100 can be controlled by controller 1184, which may include one or more processors 1186 and one or more memory devices 1188, operatively connected to each other and communicatively connected to various systems and subsystems of device 1100 to provide control functions to those systems. For example, controller 1184 may be configured to control valves A1-A5 and B1-B5, various heaters 1158, 1160, carburetor 1172, regulator valve 1154, gate valve 1106, wafer support actuator, etc.

[0217] Another feature that the device 1100 may include is shown in FIG11B, which depicts a close-up side sectional and plan view of a portion of the substrate 1122, top plate 118, and upper edge ring 1138 of FIG11A. As can be seen, in some embodiments, the substrate 1122 may be raised above most of the top plate 1128 by a plurality of small platforms 1176, which may be shallow bosses that protrude a short distance from the nominal upper surface of the top plate 1128 to provide a back-side gap 1178 between the underside of the substrate 1122 and most of the top plate 118. A circumferential wall feature 1177 may be provided around the periphery of the top plate 1128. The circumferential wall feature 1177 may extend around the entire periphery of the top plate 1128 and have the same height on its surface as the platform 1176. During processing operations, a generally inert gas (e.g., helium) may flow into the back-side gap 1178 through one or more gas ports 1182. The gas can then flow radially outward before encountering the circumferential wall feature 1177, which then restricts this radial outward flow and confines the higher pressure region of the gas to between the substrate 1122 and the top plate 1128. The inert gas leaking out of the circumferential wall 1177 may eventually flow out through the radial gap 1180 between a portion of the outer edge of the substrate 1122 and the upper edge ring 1138. This gas can protect the underside of the substrate 1122 from adverse effects of the processing operation by preventing the gas released from the spray head 1110 from reaching the underside of the substrate 1122. Simultaneously, the gas released into the back gap 1178 region can also increase the thermal coupling between the substrate 1122 and the top plate 1128, thus allowing the top plate 1128 to more effectively heat or cool the substrate 1122. Because the circumferential wall provides higher pressure, the gas in the back gap 1178 region can also be at a higher density than the gas in the rest of the chamber, thus providing more effective thermal coupling between the substrate 1122 and the top plate 1128.

[0218] The controller 1184 can be configured, for example, by executing computer-executable instructions, to cause the device 1100 to perform a number of operations consistent with the disclosure provided above.

[0219] Once the metal resist film has been deposited on the substrate 1122, the substrate 1122 can be transferred, as described above, to one or more subsequent process chambers or tools for additional operations (e.g., any of those described herein). Further deposition apparatus is described in International Patent Application No. PCT / US2020 / 038968, filed June 22, 2020, entitled "APPARATUS FOR PHOTORESIST DRY DEPOSITION," the entire contents of which are incorporated herein by reference. [in conclusion]

[0220] Methods and apparatus for dry development of metal and / or metal oxide photoresists are disclosed to form patterned masks, for example, against an EUV patterned background.

[0221] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and many modifications or changes will be suggested to those skilled in the art in light of this. Although many details have been omitted for clarity, many design alternatives may be implemented. Therefore, these examples should be considered illustrative rather than restrictive, and the invention is not limited to the details given herein, but can be modified within the scope of the invention.

[0222] 100: Method 102: Square 104: Square 106: Square 108: Square 110: Square 112: Square 114: Square 150: Square 200: Process 202: Square 204: Square 300: Wafer 302:Substrate 304: Substrate layer 306: Patterned metal-containing EUV resist film 306a: Areas not exposed to EUV 306b: EUV exposure area 308: Resistant Mask 500: Process 502: Square 504: Square 506: Square 508: Square 602: Metal-containing EUV inhibitor material 604: Chamber wall 606: Metal Oxide 608: Dry Etching Agent 610: Metallic EUV inhibitor materials 700: Process Station 701: Reactant Delivery System 703: Vaporization point 704: Mixing Container 706: Sprayer Head 707: Volume 708: Base 710: Heater 712:Substrate 714: Radio Frequency (RF) Power Supply 716: Matching network 718: Butterfly Valve 720: Mixing container inlet valve 800: Multi-station processing tools, process stations, process tools 802: Loading Room at Station 804: Departure Loading Room 806: Robot 808: Teleport Box 810: Large air port 812: Base 814: Processing Chamber 816: Chamber transfer port 818: Base 850: Computer controller, system controller 852: Processor 854: High-capacity storage device 856: Memory device 858: System Control Software 890: Wafer Handling System 900: Inductively Coupled Plasma Equipment 901: Chamber wall 902: Upper secondary chamber 903: Lower secondary chamber 911: Window 917: Suction Cup 919: Semiconductor Wafer 921: Matching Circuit 922: Port 923: Radio Frequency (RF) Power Supply 924: Process Chamber 925: Connection 927: Connection 930: System Controller 933: Coil 939: Matching Circuit 940: Vacuum pump 941: Radio Frequency (RF) Power Supply 943: Connection 945: Connection 949: Faraday Shield 950: Plasma Grid 960: Main airflow inlet 970: Side airflow inlet 1020a: Processing Module 1020b: Processing Module 1020c: Processing Module 1020d: Processing Module 1022: Vacuum Transfer Module (VTM) Robot 1024: End effector 1026: Wafer 1036: End face 1038: Vacuum Transfer Module (VTM) 1040: Patterned Module 1042: Air Chamber 1044: Front-end robot 1046: Air Chamber 1050: System Controller 1100: Equipment 1102: Process Chamber 1104: Wafer Transfer Channel 1106: Gate valve 1108: Cover 1110: Sprayer Head 1112: First air chamber 1114: Second air chamber 1116: First Entrance 1118: Second Entrance 1120: Reaction space 1122:Substrate 1124: Wafer support 1126: Electrostatic Chuck 1128: Top Slab 1130a: Resistance heater trace 1130b: Resistance heater trace 1130c: Resistance heater trace 1130d: Resistance heater trace 1132: Clamping Electrode 1134: Base Plate 1136: Heat exchange channel 1138: Upper edge ring 1140a: Lower edge ring 1140b: Lower edge ring 1140c: Lower edge ring 1142: Wafer support shell 1144: Circular support column 1146: Wafer Support Z-Actuator 1148: Winding Channel 1150: baffle 1152: Vacuum foreline 1154: Control valve 1156: Annular chamber 1158: Box-type heater 1160: Heating Blanket 1168a: First valve manifold 1168b: Second valve manifold 1170a: First bypass pipeline 1170b: Second bypass pipeline 1172a: First vaporizer 1172b: Second vaporizer 1172c: Carburetor 1172d: Carburetor 1174: Flushing gas source 1176: Countertop 1177: Circumferential wall feature 1178: Dorsal gap 1180: Radial clearance 1182: Gas Port 1184: Controller 1186: Processor 1188: Memory Device A1: Valve A2: Valve A3: Valve A4: Valve A5: Valve B1: Control valve B2: Control valve B3: Control valve B4: Control Valve

Claims

1. A method for developing a resist, comprising: providing a photo-patterned metal-containing resist on a surface of a semiconductor substrate in a process chamber; and dry developing the photo-patterned metal-containing resist, wherein a portion of the photo-patterned metal-containing resist is selectively removed by exposure to a developing chemical substance comprising an organic vapor to form a resist mask.

2. The method as described in claim 1, wherein the organic vapor comprises a carboxylic acid.

3. The method as described in claim 2, wherein the organic vapor comprises trifluoroacetic acid.

4. The method as described in claim 1, wherein the organic vapor comprises trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chloro-difluoro-acetic acid, thioacetic acid, or mercaptoacetic acid.

5. The method as described in claim 1, wherein the organic vapor comprises hexafluoroacetyl ketone.

6. The method as described in any one of claims 1-5, wherein the developing chemical substance comprises a gaseous mixture of a halocarboxylic acid and a hydrogen halide.

7. The method as described in any one of claims 1-5, wherein dry development of the photopatterned metal-containing resist comprises reacting the organic vapor with the photopatterned metal-containing resist at a temperature below about 200°C to form a volatile compound.

8. The method as described in any one of claims 1-5, wherein dry development of the optically patterned metal resist includes exposure to at least the organic vapor during a plasma-free thermal process.

9. The method as described in any one of claims 1-5, wherein the photopatterning metal resist is a photopatterning metal EUV resist, wherein the photopatterning metal EUV resist is an organometallic oxide or a film containing an organometallic film.

10. The method of any one of claims 1-5, wherein dry development of the optically patterned metal resist comprises using the development chemical to selectively remove the unexposed portion of the optically patterned metal resist relative to the EUV-exposed portion to form the resist mask.

11. A method for removing residues from a process chamber, comprising: depositing a metal resist material on a surface of a semiconductor substrate in a process chamber, wherein a portion of the metal resist material forms residues on one or more surfaces of the process chamber; and introducing a dry etchant comprising an organic vapor into the process chamber, wherein the dry etchant at least partially removes the residues on the one or more surfaces of the process chamber.

12. The method as described in claim 11, wherein the organic vapor comprises a carboxylic acid.

13. The method as described in claim 12, wherein the organic vapor comprises trifluoroacetic acid.

14. The method as claimed in claim 11, wherein the organic vapor comprises trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chloro-difluoro-acetic acid, thioacetic acid, or mercaptoacetic acid.

15. The method as described in claim 11, wherein the organic vapor comprises hexafluoroacetone.

16. The method as described in any one of claims 11-15, wherein the dry etchant comprises a gaseous mixture of a halocarboxylic acid and a hydrogen halide.

17. The method as described in any one of claims 11-15, wherein at least partial removal of the residue comprises reacting the organic vapor with the metal-containing inhibitor material at a temperature below about 200°C to form a volatile compound.

18. The method as described in any one of claims 11-15, wherein at least partial removal of the residue includes exposure to at least the organic vapor during a plasmaless thermal process.

19. The method as described in any one of claims 11-15, wherein the metal-containing inhibitor material is an organometallic oxide or a film containing an organometallic material.

20. The method of any one of claims 11-15, further comprising: rinsing the process chamber after the introduction of the dry etchant to remove residual dry etchant from the process chamber; and conditioning the one or more surfaces of the process chamber by forming a protective coating of one of the metal resist materials on the one or more surfaces of the process chamber.

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