Semiconductor device and manufacturing method of semiconductor device

Abstract

A semiconductor device may include: a gate structure comprising alternating layers of insulating layers and a control gate; a channel layer penetrating the gate structure; a floating gate located between the control gate and the channel layer; a first barrier pattern located between the control gate and the floating gate; and a second barrier pattern located between the first barrier pattern and the control gate and between the control gate and the insulating layer, the second barrier pattern comprising a material having a dielectric constant higher than that of the first barrier pattern.

Description

[Technical Field]

[0001] This disclosure generally relates to an electronic device, and more specifically to a semiconductor device and a method of manufacturing a semiconductor device. [Previous Technology]

[0002] The integration level of a semiconductor device is primarily determined by the area occupied by a single memory cell. As the integration level of semiconductor devices where memory cells are formed in a single layer on a substrate reaches its limit, a three-dimensional semiconductor device has recently been proposed, in which memory cells are stacked on a substrate. Various structures and manufacturing methods have been developed to improve the operational reliability of three-dimensional semiconductor devices. [Summary of the Invention]

[0003] According to one aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a gate structure including alternating layers of insulating layers and a control gate; a channel layer penetrating the gate structure; a floating gate located between the control gate and the channel layer; a first blocking pattern located between the control gate and the floating gate; and a second blocking pattern located between the first blocking pattern and the control gate and between the control gate and the insulating layer, the second blocking pattern comprising a material having a dielectric constant higher than that of the first blocking pattern.

[0004] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a gate structure including alternating layers of insulating layers and a control gate; a channel layer penetrating the gate structure; a floating gate located between the control gate and the channel layer; a first blocking pattern located between the control gate and the floating gate; and a second blocking pattern located between the first blocking pattern and the floating gate and between the floating gate and the insulating layer, the second blocking pattern comprising a material with a dielectric constant lower than that of the first blocking pattern.

[0005] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising the steps of: forming a stacked structure comprising alternating layers of first and second material layers; forming a first opening penetrating the stacked structure; forming a second opening between the second material layers; forming a first barrier pattern by oxidizing the first material layer exposed through the second opening; forming floating gates in the second openings respectively; forming a channel layer in the first opening; forming a third opening by removing the first material layer; forming a second barrier pattern in the third opening, the second barrier pattern comprising a material having a dielectric constant higher than that of the first barrier pattern; and forming control gates surrounded by the second barrier pattern in the third openings respectively.

[0006] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising the steps of: forming a stacked structure comprising alternating layers of a first material layer and a second material layer; forming a first opening penetrating the stacked structure; forming a second opening by etching the first material layer; forming a first barrier pattern in each of the second openings; forming a second barrier pattern in both the first and second openings, the second barrier pattern comprising a material having a dielectric constant lower than that of the first barrier pattern; forming floating gates surrounded by the second barrier patterns in each of the second openings; and forming a channel layer in the first opening.

Implementation Method

[0019] The specific structural or functional descriptions disclosed herein are merely for the purpose of illustrating embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments illustrated herein.

[0020] An embodiment provides a semiconductor device with a stable structure and improved characteristics, and provides a method for manufacturing the semiconductor device.

[0021] Figures 1A and 1B are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0022] Referring to FIG1A, the semiconductor device may include a gate structure GST, a channel layer 16, a memory pattern 14, and a barrier layer 13. The semiconductor device may further include a tunneling insulating layer 15, a core 17, or a combination thereof.

[0023] The gate structure GST may include alternating layers of conductive layers 11 and insulating layers 12. The conductive layers 11 may be gate electrodes for memory cells, select transistors, etc. In one embodiment, the conductive layer 11 may be a control gate. Each conductive layer 11 may include a conductive pattern 11A and a barrier pattern 11B. The barrier pattern 11B may be located between the barrier layer 13 and the conductive pattern 11A, respectively. Each barrier pattern 11B may have a C-shaped cross-section. The barrier pattern 11B may include a metal nitride. The conductive pattern 11A may include a conductive material, such as polysilicon, tungsten, molybdenum, or other metals. The insulating layer 12 may be used to insulate the stacked conductive layers 11 from each other. The insulating layer 12 may include an insulating material, such as an oxide, nitride, or an air gap.

[0024] The channel layer 16 can penetrate the gate structure GST. The channel layer 16 can extend in the stacking direction of the conductive layer 11 and the insulating layer 12. The channel layer 16 can be a region in which channels such as memory cells and selection transistors are formed. The channel layer 16 can include a semiconductor material. In embodiments, the channel layer 16 can include silicon, germanium, nanostructures, etc.

[0025] The tunneling insulating layer 15 may be formed as a sidewall surrounding the channel layer 16. In an embodiment, the tunneling insulating layer 15 may include pure oxide. A core 17 may be formed in the channel layer 16. The core 17 may have a single-layer or multi-layer structure. The core 17 may include an insulating material, such as an oxide, nitride, or air gap. Alternatively, the core 17 may include a conductive material and may be an electrode layer, a vertical bit line, etc.

[0026] A semiconductor device may have a form in which the core 17 is omitted or even the center of the channel layer 16 is filled.

[0027] The memory pattern 14 can be located between the conductive layer 11 and the channel layer 16. The memory pattern 14 may include a floating gate, a charge trapping material, polysilicon, a nitride, a variable resistance material, a phase change material, or a combination thereof. The memory pattern 14 can be located between the insulating layers 12. Each memory pattern 14 can contact the upper insulating layer 12 and the lower insulating layer 12. Each memory pattern 14 can have a first height H1, and each conductive layer 11 can have a second height H2. The first height H1 can be substantially equal to or different from the second height H2. In an embodiment, the first height H1 can be higher than the second height H2.

[0028] The barrier layer 13 may include a first barrier pattern 13A, a second barrier pattern 13B or a third barrier pattern 13C, or any combination thereof.

[0029] The first barrier pattern 13A may be located between the conductive layer 11 and the memory pattern 14. The first barrier pattern 13A may include oxide. Each first barrier pattern 13A may have a height H1 that is substantially the same as that of each memory pattern 14. Each first barrier pattern 13A may have a first thickness T1, and the first thickness T1 may be 1 to 10 nanometers.

[0030] The second barrier pattern 13B may be located between the first barrier pattern 13A and the conductive layer 11, and between the conductive layer 11 and the insulating layer 12. The second barrier pattern 13B may extend to the sidewall of the insulating layer 12. The second barrier pattern 13B may surround the conductive layer 11, and the barrier pattern 11B may be located between the second barrier pattern 13B and the conductive pattern 11A, respectively. The second barrier pattern 13B may have a second thickness T2, and the second thickness T2 may be 1 to 10 nanometers.

[0031] The second barrier pattern 13B may include a material with a dielectric constant higher than that of the first barrier pattern 13A. The second barrier pattern 13B may include a high-k material. In embodiments, the second barrier pattern 13B may include silicon nitride (Si3N4), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4), or hafnium silicate (HfSiO4), or any combination thereof. In embodiments, the second barrier pattern 13B may include hafnium silicate (HfSiOx), and the dielectric constant of the second barrier pattern 13B can be adjusted by adjusting the silicon concentration of the hafnium silicate (HfSiOx). The dielectric constant of the second barrier pattern 13B with a relatively high silicon content may be lower than that of the second barrier pattern 13B with a relatively low silicon content. Therefore, the dielectric constant of the second barrier pattern 13B can be adjusted by utilizing the silicon content, thereby allowing for adjustment of the gate coupling ratio.

[0032] The third blocking pattern 13C may be located between the first blocking pattern 13A and the memory pattern 14. Each third blocking pattern 13C may have a height H1 that is substantially the same as that of each memory pattern 14. Each third blocking pattern 13C may have a height H1 that is substantially the same as that of each first blocking pattern 13A. Each third blocking pattern 13C may have a third thickness T3, and the third thickness T3 may be 1 to 10 nanometers.

[0033] The third barrier pattern 13C may include a material with a dielectric constant higher than that of the first barrier pattern 13A. The third barrier pattern 13C may include a high-k dielectric material. In embodiments, the third barrier pattern 13C may include silicon nitride (Si3N4), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4), or hafnium silicate (HfSiO4), or any combination thereof. In embodiments, the third barrier pattern 13C may include hafnium silicate (HfSiOx), and the dielectric constant of the third barrier pattern 13C can be adjusted by adjusting the silicon concentration of the hafnium silicate (HfSiOx). Therefore, the gate coupling ratio can be adjusted.

[0034] The third barrier pattern 13C may include a material substantially the same as the material of the second barrier pattern 13B, or may include a material different from the material of the second barrier pattern 13B. In an embodiment, the second barrier pattern 13B and the third barrier pattern 13C may include hafnium silicate (HfSiOx), and the concentrations of silicon included in the second barrier pattern 13B and the concentrations of silicon included in the third barrier pattern 13C may be substantially equal or different from each other.

[0035] Referring to FIG. 1B, the semiconductor device may further include a metal pattern 18. The metal pattern 18 may be located between the barrier layer 13 and the memory pattern 14. In an embodiment, the metal pattern 18 may be located between the first barrier pattern 13A and the memory pattern 14, or between the third barrier pattern 13C and the memory pattern 14. The metal pattern 18 may have a height H1 substantially the same as the first barrier pattern 13A, the third barrier pattern 13C, or the memory pattern 14. In an embodiment, each metal pattern 18 may have a fourth thickness T4, and the fourth thickness T4 may be from 1 to 100 angstroms.

[0036] The metal pattern 18 may include a metal with a relatively high work function. A metal with a high work function may have a high Fermi energy and can increase the inelastic scattering rate of electrons. Therefore, electrons tunneling from the memory pattern 14 toward the barrier layer 13 are trapped in the metal pattern 18. Although the barrier layer 13 comprises a high-k dielectric material, it can prevent or minimize the increase in leakage current. In embodiments, the metal pattern 18 may include a pure metal, a metal nitride, or a metal silicate. The metal pattern 18 may include titanium (Ti), platinum (Pt), tin (Sn), ruthenium (Ru), or titanium nitride (TiN), or any combination thereof. The metal pattern 18 may include nanostructures such as nanodots, nanoclusters, or nanofilms.

[0037] According to the above structure, since the barrier layer 13 includes a high-k dielectric material, the gate coupling ratio can be improved. Furthermore, the concentration of silicon in the hafnium silicate (HfSiOx) can be adjusted to regulate the gate coupling ratio. Since the barrier layer 13 is not interposed between the memory pattern 14 and the insulating layer 12, the height of the gate structure GST can be reduced, and the integration density of the semiconductor device can be improved. Since the metal pattern 18 is located between the barrier layer 13 and the memory pattern 14, leakage current can be reduced.

[0038] Figures 2A to 2C are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Descriptions of portions overlapping with the above-described portions will be omitted below.

[0039] Referring to FIG2A, the semiconductor device may include a gate structure GST, a channel layer 26, a memory pattern 24, and a barrier layer 23. The semiconductor device may further include a tunneling insulating layer 25, a core 27, or a combination thereof.

[0040] The gate stack structure GST may include alternating layers of conductive layers 21 and insulating layers 22. The conductive layer 21 may be a control gate. Each conductive layer 21 may include a conductive pattern 21A and a barrier pattern 21B. The barrier pattern 21B may be located between the conductive pattern 21A and a third barrier pattern 23C, and between the conductive pattern 21A and the insulating layer 22. A channel layer 26 may penetrate the gate structure GST. A tunneling insulating layer 25 may be formed as a sidewall surrounding the channel layer 26. A core 27 may be formed in the channel layer 26.

[0041] The memory pattern 24 can be located between the conductive layer 21 and the channel layer 26. In an embodiment, the memory pattern 24 may include a floating gate, a charge trapping material, polysilicon, a nitride, a variable resistance material, a phase change material, or a combination thereof. The memory pattern 24 can be located between the insulating layers 22. Each memory pattern 24 can be surrounded by a barrier layer 23. Each memory pattern 24 can have a first height H1, and each conductive layer 21 can have a second height H2. The first height H1 can be substantially equal to or different from the second height H2. In an embodiment, the second height H2 can be higher than the first height H1.

[0042] The barrier layer 23 may include a first barrier pattern 23A, a second barrier pattern 23B, a third barrier pattern 23C, or a combination thereof. The first barrier pattern 23A may be located between the conductive layer 21 and the memory pattern 24. Each first barrier pattern 23A may have a height H2 that is substantially the same as that of each conductive layer 21. The first barrier pattern 23A may include hafnium silicate (HfSiOx). When the first barrier pattern 23A includes hafnium silicate (HfSiOx), the dielectric constant of the first barrier pattern 23A can be adjusted by adjusting the silicon concentration of the hafnium silicate (HfSiOx). Therefore, the gate coupling ratio can be adjusted.

[0043] The second barrier pattern 23B may be located between the first barrier pattern 23A and the memory pattern 24, and between the memory pattern 24 and the insulating layer 22. The second barrier pattern 23B may extend to the sidewall of the insulating layer 22. The second barrier pattern 23B may surround the memory pattern 24. The second barrier pattern 23B may include a material with a dielectric constant lower than that of the first barrier pattern 23A. In an embodiment, the second barrier pattern 23B may include an oxide.

[0044] The third barrier pattern 23C may be located between the first barrier pattern 23A and the conductive layer 21. Each third barrier pattern 23C may have a height H2 substantially the same as each conductive layer 21. Each third barrier pattern 23C may have a height H2 substantially the same as each first barrier pattern 23A. The third barrier pattern 23C may include a material with a dielectric constant lower than that of the first barrier pattern 23A. In an embodiment, the third barrier pattern 23C may include an oxide.

[0045] Referring to FIG. 2B, each conductive layer 21 may include a conductive pattern 21A and may not include a barrier pattern. Each conductive pattern 21A may have a second height H2, and each memory pattern 24 may have a first height H1. The first height H1 and the second height H2 may be substantially equal or different from each other. The second height H2 may be higher than the first height H1.

[0046] Referring to FIG. 2C, the semiconductor device may further include a metal pattern 28. The metal pattern 28 may be located between the barrier layer 23 and the memory pattern 24. In an embodiment, the metal pattern 28 may be located between the first barrier pattern 23A and the memory pattern 24, or between the third barrier pattern 23C and the memory pattern 24. The height of the metal pattern 28 may be lower than the height of the first barrier pattern 23A or the third barrier pattern 23C. The metal pattern 28 may have a height substantially the same as the memory pattern 24. Since the metal pattern 28 is located between the barrier layer 23 and the memory pattern 24, leakage current can be reduced.

[0047] According to the above structure, since the barrier layer 23 includes a high-k dielectric material, the gate coupling ratio can be improved. Furthermore, the gate coupling ratio can be adjusted by changing the concentration of silicon included in hafnium silicate (HfSiOx). The barrier layer 23 may not be inserted between the conductive layer 21 and the insulating layer 22. Therefore, the height of the gate stack structure GST can be reduced, and the integration of the semiconductor device can be improved. Since the metal pattern 28 is located between the barrier layer 23 and the memory pattern 24, leakage current can be reduced.

[0048] Figures 3A to 3K are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Descriptions of portions overlapping with the above will be omitted below.

[0049] Referring to FIG. 3A, a stacked structure ST is formed. The stacked structure ST may include alternating layers of a first material layer 31 and a second material layer 32. The first material layer 31 may include a material having high etch selectivity relative to the second material layer 32. In an embodiment, the first material layer 31 may include a sacrificial material (such as a nitride), and the second material layer 32 may include an insulating material (such as an oxide).

[0050] Subsequently, a first opening OP1 can be formed, which penetrates the stacked structure ST. The first opening OP1 can be a plane with a circular shape, an elliptical shape, a polygonal shape, etc. In an embodiment, a plurality of first openings OP1 arranged in a first direction and a second direction intersecting the first direction can be formed.

[0051] Referring to FIG. 3B, a second opening OP2 is formed between the second material layers 32. The second opening OP2 can be used to ensure space for forming memory cells. The second opening OP2 can be formed by selectively etching the first material layer 31. The second opening OP2 can be connected to the first opening OP1.

[0052] Referring to FIG. 3C, a first barrier pattern 33A is formed on a first material layer 31 exposed via the second opening OP2. The first barrier pattern 33A can be formed by oxidizing the first material layer 31 exposed via the second opening OP2. The first barrier patterns 33A can be located in the second opening OP2 respectively and isolated from each other. The first barrier pattern 33A may include oxide. The thickness 33A_T of each first barrier pattern 33A can be 1 to 10 nanometers.

[0053] Referring to FIG. 3D, a third barrier layer 33C is formed. The third barrier layer 33C may be formed in the first opening OP1 and the second opening OP2. The third barrier layer 33C may be formed along the surfaces of the second material layer 32 exposed via the first opening OP1 and the second opening OP2 and along the surface of the first barrier pattern 33A. The third barrier layer 33C may include a material with a dielectric constant higher than that of the first barrier pattern 33A. In an embodiment, the third barrier layer 33C may include hafnium silicate (HfSiOx). The thickness 33C_T of the third barrier layer 33C may be 1 to 10 nanometers.

[0054] Referring to FIG. 3E, a sacrificial layer 62 is formed in the second opening OP2. In an embodiment, the sacrificial layer 62 can be formed by forming a sacrificial material layer in the first opening OP1 and the second opening OP2, and then etching the portion of the sacrificial material layer formed in the first opening OP1. The third barrier layer 33C can be partially exposed by the sacrificial layer 62. The portion of the third barrier layer 33C formed in the second opening OP2 can be covered by the sacrificial layer 62, and the portion of the third barrier layer 33C formed in the first opening OP1 can be exposed. The sacrificial layer 62 may include a material with high etch selectivity relative to the second material layer 32 and the third barrier layer 33C. In an embodiment, the sacrificial layer 62 may include polycrystalline silicon, tungsten, etc.

[0055] Referring to FIG. 3F, a third barrier pattern 33CA is formed. The third barrier pattern 33CA can be formed by selectively etching the third barrier layer 33C. The portion of the third barrier layer 33C exposed by the sacrificial layer 62 can be etched, and the portion located between the first barrier pattern 33A and the sacrificial layer 62 can be retained. Therefore, a trench G can be formed between the sacrificial layer 62 and the second material layer 32.

[0056] Referring to FIG. 3G, the sacrificial layer 62 is removed. The second opening OP2 can be reopened by selectively etching the sacrificial layer 62. The second material layer 32 and the third blocking pattern 33CA can be exposed by the second opening OP2.

[0057] Referring to FIG. 3H, memory patterns 34 are formed in the second opening OP2 respectively. The memory patterns 34 can be isolated from each other by a second material layer 32. In an embodiment, the memory patterns 34 can be formed by forming a memory layer in the first opening OP1 and the second opening OP2, and then etching the portion of the memory layer formed in the first opening OP1. Each memory pattern 34 can have a surface exposed through the first opening OP1, and the surface of the memory pattern 34 includes a trench G1. The trench G1 may be formed during the deposition of the memory layer along the inner surfaces of the first opening OP1 and the second opening OP2.

[0058] The memory pattern 34 may include a floating gate, a charge trapping material, polycrystalline silicon, a nitride, a variable resistance material, a phase change material, or a combination thereof. In an embodiment, the memory pattern 34 may be a floating gate. The memory pattern 34 can be formed by forming a floating gate layer in the first opening OP1 and the second opening OP2, and then etching the floating gate layer. The shape of the floating gate can be controlled by performing wet etching and oxidation on the floating gate layer.

[0059] Referring to FIG. 3I, a tunneling insulating layer 35 is formed in the first opening OP1. When each memory pattern 34 includes a trench G1 on its surface, the tunneling insulating layer 35 can be filled in the trench G1. Subsequently, a channel layer 36 is formed in the tunneling insulating layer 35. The channel layer 36 can completely fill or partially fill the first opening OP1. Subsequently, a core 37 can be formed in the channel layer 36.

[0060] Referring to FIG. 3J, the third opening OP3 can be formed by removing the first material 31. In an embodiment, the third opening OP3 can be formed by forming a slit (not shown) that penetrates the stacked structure ST, and then selectively etching the first material layer 31. The first blocking pattern 33A can be exposed via the third opening OP3.

[0061] Referring to FIG. 3K, a second barrier pattern 33B is formed. In an embodiment, the second barrier pattern 33B may be formed along the inner surfaces of the first opening OP1 and the third opening OP3. The second barrier pattern 33B may be formed on the surface of the second material layer 32 and on the surface of the first barrier pattern 33A. The second barrier pattern 33B may include a material with a dielectric constant higher than that of the first barrier pattern 33A. In an embodiment, the second barrier pattern 33B may include hafnium silicate (HfSiOx). Therefore, a barrier layer may be formed comprising the first barrier pattern 33A, the second barrier pattern 33B, and the third barrier pattern 33CA.

[0062] Subsequently, a third material layer 61 can be formed in the third opening OP3. In an embodiment, the third material layer 61 can be formed by forming the third material layer in the first opening OP1 and the third opening OP3, and then etching the portion of the third material layer formed in the first opening OP1. The third material layers 61 can be isolated from each other. In an embodiment, the third material layer 61 can be a control gate. The third material layer 61 can be surrounded by a second barrier pattern 33B. The height of each third material layer 61 can be lower than the height of each memory pattern 34. Therefore, a gate structure GST can be formed in which the third material layer 61 and the second material layer 32 are alternately stacked.

[0063] Each third material layer 61 may include a conductive pattern 61A and a barrier pattern 61B. In an embodiment, after the barrier layer and the conductive layer are formed in the first opening OP1 and the third opening OP3, the portion of the barrier layer formed in the first opening OP1 and the portion of the conductive layer formed in the first opening OP1 may be etched. Therefore, the conductive pattern 61A and the barrier pattern 61B respectively surrounding the conductive pattern 61A can be formed.

[0064] According to the above manufacturing method, a barrier layer 33 comprising a high-k dielectric constant material is formed. Therefore, the gate coupling ratio can be improved. Furthermore, the barrier layer 33 is formed so that it is not inserted between the memory pattern 34 and the second material layer 32. Therefore, the length of the floating gate can be increased, and the programming / erasing window can be increased. In addition, the height of the gate structure GST can be reduced, and the integration of the semiconductor device can be improved.

[0065] Figures 4A to 4F are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, descriptions of portions overlapping with the above will be omitted.

[0066] Referring to FIG. 4A, a stacked structure ST is formed. The stacked structure ST may include alternating layers of a first material layer 41 and a second material layer 42. The first material layer 41 may include a material with high etch selectivity relative to the second material layer 42. Subsequently, a first opening OP1 may be formed, penetrating the stacked structure ST. Subsequently, a second opening OP2 may be formed by etching the first material layer 41. Subsequently, a first barrier pattern 43A may be formed by oxidizing the first material layer 41 exposed via the second opening OP2. Subsequently, a third barrier pattern 43C may be formed in the second opening OP2. In an embodiment, the third barrier pattern 43C may be formed by forming a third barrier layer in the first opening OP1 and the second opening OP2, and then etching the third barrier layer using a sacrificial layer. The third barrier pattern 43C may include a material with a dielectric constant higher than that of the first barrier pattern 43A. In an embodiment, the third barrier pattern 43C may include hafnium silicate (HfSiOx).

[0067] Referring to Figures 4B to 4E, a metal pattern 48A is formed in the second opening OP2. In an embodiment, the metal pattern 48A can be formed by selectively depositing metal on the surface of the third barrier pattern 43C exposed via the second opening OP2. In an embodiment, the metal pattern 48A can be formed via an etching process using a sacrificial layer 72. The process using the sacrificial layer 72 will be described below.

[0068] First, referring to FIG. 4B, a metal layer 48 is formed. The metal layer 48 may be formed in the first opening OP1 and the second opening OP2. The metal layer 48 may be formed along the surface of the second material layer 42 exposed via the first opening OP1 and the second opening OP2 and the surface of the third barrier pattern 43C. The metal layer 48 may include pure metal or include metal nitrides. The metal layer 48 may include titanium nitride (TiN), titanium (Ti), platinum (Pt) or ruthenium (Ru), or any combination thereof. The metal layer 48 may include nanostructures, such as nanodots, nanoclusters, or nanofilms.

[0069] Referring to FIG4C, a sacrificial layer 72 is formed in the second opening OP2. The sacrificial layer 72 may include a material with high etch selectivity relative to the second material layer 42 and the metal layer 48. In an embodiment, the sacrificial layer 72 may include polycrystalline silicon, silicon oxide (SiO2), silicon nitride (SixNy), etc.

[0070] Referring to FIG. 4D, a metal pattern 48A is formed. The metal pattern 48A can be formed by selectively etching the metal layer 48. The portion of the metal layer 48 exposed by the sacrificial layer 72 can be etched, and the portion located between the third blocking pattern 43C and the sacrificial layer 72 can be retained. Therefore, a trench G can be formed between the sacrificial layer 72 and the second material layer 42.

[0071] Referring to FIG4E, the sacrificial layer 72 is removed. The second opening OP2 can be reopened by selectively etching the sacrificial layer 72. The second material layer 42 and the metal pattern 48A can be exposed through the second opening OP2.

[0072] Referring to FIG4F, a memory pattern 44 can be formed in the second opening OP2. Subsequently, a tunneling insulation layer 45, a channel layer 46 and a core 47 can be formed in the first opening OP1, or some of the tunneling insulation layer 45, the channel layer 46 and the core 47 can be formed.

[0073] Subsequently, the first material layer 41 can be removed, and a second barrier pattern 43B can be formed. The second barrier pattern 43B may include a material with a dielectric constant higher than that of the first barrier pattern 43A. In an embodiment, the second barrier pattern 43B may include hafnium silicate (HfSiOx). Therefore, a barrier layer 43 can be formed, which includes the first barrier pattern 43A, the second barrier pattern 43B, and the third barrier pattern 43C. Subsequently, a third material layer 71 can be formed in the third opening OP3 (see FIG. 3J). Each third material layer 71 may include a conductive pattern 71A and a barrier pattern 71B.

[0074] According to the manufacturing method described above, the metal pattern 48A is formed between the memory pattern 44 and the barrier layer 43. Therefore, leakage current can be reduced.

[0075] Figures 5A to 5G are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, descriptions of portions overlapping with the above-described parts will be omitted.

[0076] Referring to FIG. 5A, a stacked structure ST is formed. The stacked structure ST may include alternating layers of a first material layer 51 and a second material layer 52. The first material layer 51 may include a material having high etch selectivity relative to the second material layer 52. In one embodiment, the first material layer 51 may include a sacrificial material (such as a nitride), and the second material layer 52 may include an insulating material (such as an oxide). In another embodiment, the first material layer 51 may include a conductive material such as polysilicon, tungsten, or molybdenum, and the second material layer 52 may include an insulating material such as an oxide.

[0077] Subsequently, a first opening OP1 can be formed, which penetrates the stacked structure ST. Then, a second opening OP2 can be formed by etching the first material layer 51. Subsequently, a third barrier pattern 53C can be formed in the second opening OP2. In an embodiment, the third barrier pattern 53C can be formed by oxidizing the first material layer 51 exposed through the second opening OP2. The third barrier pattern 53C may include an oxide.

[0078] Referring to Figures 5B to 5E, a first blocking pattern 53AB can be formed in the second opening OP2. In an embodiment, the first blocking pattern 53AB can be formed on the surface of the third blocking pattern 53C exposed through the second opening OP2.

[0079] First, referring to FIG. 5B, a first barrier layer 53A is formed in the first opening OP1 and the second opening OP2. The first barrier layer 53A may be formed along the surface of the second material layer 52 exposed via the first opening OP1 and the second opening OP2 and the surface of the third barrier pattern 53C. The first barrier layer 53A may include a material with a dielectric constant higher than that of the third barrier pattern 53C. In an embodiment, the first barrier layer 53A may include hafnium silicate (HfSiOx).

[0080] Referring to FIG. 5C, sacrificial layers 82 are formed in the second opening OP2. The sacrificial layer 82 may include a material with high etch selectivity relative to the second material layer 52 and the first barrier layer 53A. In an embodiment, the sacrificial layer 82 may include polycrystalline silicon, tungsten, etc.

[0081] Referring to FIG. 5D, a first barrier pattern 53AB is formed. The first barrier pattern 53AB can be formed by selectively etching the first barrier layer 53A. The portion of the first barrier layer 53A exposed by the sacrificial layer 82 can be etched, and the portion located between the third barrier pattern 53C and the sacrificial layer 82 can be retained. Therefore, a trench G can be formed between the sacrificial layer 82 and the second material layer 52.

[0082] Referring to FIG5E, the sacrificial layer 82 is removed. The second opening OP2 can be reopened by selectively etching the sacrificial layer 82. The second material layer 52 and the first blocking pattern 53A can be exposed by the second opening OP2.

[0083] Referring to FIG. 5F, a second barrier pattern 53B is formed. The second barrier pattern 53B may be formed along the inner surfaces of the first opening OP1 and the second opening OP2. The second barrier insulating layer 53B may include a material with a dielectric constant lower than that of the first barrier pattern 53AB. In an embodiment, the second barrier pattern 53B may include an oxide. Therefore, a barrier layer 53 may be formed, which includes the first barrier pattern 53AB, the second barrier pattern 53B, and the third barrier pattern 53C.

[0084] Subsequently, memory patterns 54 can be formed in the second opening OP2. Memory patterns 54 can be surrounded by a second blocking pattern 53B. Memory patterns 54 may include floating gates, charge trapping materials, polycrystalline silicon, nitrides, variable resistance materials, phase change materials, or combinations thereof. Subsequently, tunneling insulating layers 55, channel layers 56, and cores 57 can be formed in the first opening OP1, or some of the tunneling insulating layers 55, channel layers 56, and cores 57 can be formed in the first opening OP1.

[0085] The metal pattern can be formed before the memory pattern 54 is formed. In an embodiment, the metal pattern can be formed by a selective deposition process or an etching process using a sacrificial layer.

[0086] Referring to FIG. 5G, the first material layer 51 may be replaced by a third material layer 81. In one embodiment, when the first material layer 51 comprises a sacrificial material and the second material layer 52 comprises an insulating material, the first material layer 51 may be replaced by a conductive layer. Each third material layer 81 may include a conductive pattern 81A and a barrier pattern 81B. In another embodiment, when the first material layer 51 comprises a conductive material and the second material layer 52 comprises an insulating material, the first material layer 51 may be siliconized.

[0087] According to the above manufacturing method, a barrier layer 53 comprising a high-k dielectric constant material is formed. Therefore, the gate coupling ratio can be improved. In addition, the barrier layer 53 is formed not to be inserted between the third material layer 81 and the second material layer 52. Therefore, the height of the gate structure GST can be reduced, and the integration of the semiconductor device can be improved.

[0088] Figure 6 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0089] Referring to FIG6, the memory system 1000 may include: a memory device 1200 configured to store data; and a controller 1100 configured to communicate between the memory device 1200 and the host 2000.

[0090] The host 2000 may be a device or system for storing data in or retrieving data from the memory system 1000. The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. These requests may include programming requests for programming operations, read requests for read operations, erase requests for erase operations, etc. The host 2000 can communicate with the memory system 1000 via various interfaces, such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0091] The host 2000 may include at least one of a computer, a portable digital device, a tablet computer, a digital camera, a digital audio player, a television, a wireless communication device, and a cellular phone, but the embodiments disclosed herein are not limited thereto.

[0092] The controller 1100 can control the overall operation of the memory system 1000. The controller 1100 can control the memory device 1200 according to the request of the host 2000. The controller 1100 can control the memory device 1200 to perform programming operations, read operations, erase operations, etc., according to the request of the host 2000. Alternatively, the controller 1100 can perform background operations, etc., without any request from the host 2000, to improve the performance of the memory system 1000.

[0093] The controller 1100 can transmit control signals and data signals to the memory device 1200 to control the operation of the memory device 1200. The control signals and data signals can be transmitted to the memory device 1200 through different input / output lines. Data signals may include commands, addresses, or data. Control signals can be used to distinguish the time periods during which data signals are input.

[0094] The memory device 1200 can perform programming operations, read operations, erase operations, etc., under the control of the controller 1100. The memory device 1200 can be implemented as a volatile memory device in which the data stored is lost when the power supply is interrupted; or as a non-volatile memory device in which the data stored is retained even when the power supply is interrupted. The memory device 1200 can be a semiconductor device having the structure described above with reference to FIGS. 1A to 2C. The memory device 1200 can be a semiconductor device manufactured by the manufacturing method described above with reference to FIGS. 3A to 3K, 4A to 4F, or 5A to 5G. In an embodiment, the semiconductor device may include: a gate structure comprising alternating layers of insulating layers and a control gate; a channel layer penetrating the gate structure; a floating gate located between the control gate and the channel layer; a first barrier pattern located between the control gate and the floating gate; and a second barrier pattern located between the first barrier pattern and the control gate and between the control gate and the insulating layer, the second barrier pattern comprising a material having a dielectric constant higher than that of the first barrier pattern.

[0095] Figure 7 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0096] Referring to Figure 7, the memory system 30000 can be implemented as a cellular phone, smartphone, tablet computer, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100, which is capable of controlling the operation of the memory device 2200.

[0097] The controller 2100 can control the data access operations of the memory device 2200 under the control of the processor 3100, such as programming operations, erasing operations, and reading operations.

[0098] Data programmed in memory device 2200 can be output via display 3200 under the control of controller 2100.

[0099] The radio transceiver 3300 can transmit / receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and transmit the processed signals to the controller 2100 or the display 3200. The controller 2100 can transmit the signals processed by the processor 3100 to the memory device 2200. In addition, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 is a device that can input control signals for controlling the operation of the processor 3100 or input data processed by the processor 3100, and can be implemented as a pointing device, such as a touchpad or computer mouse, button or keyboard. The processor 3100 can control the operation of the display 3200, so that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output via the display 3200.

[0100] In some embodiments, the controller 2100 that controls the operation of the memory device 2200 may be implemented as part of the processor 3100 or as a separate chip from the processor 3100.

[0101] Figure 8 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0102] Referring to Figure 8, the memory system 40000 can be implemented as a personal computer (PC), tablet computer, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0103] The memory system 40000 may include a memory device 2200 and a controller 2100, the controller 2100 being able to control the data processing operations of the memory device 2200.

[0104] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on the data input via the input device 4200. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, button or keyboard.

[0105] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. In some embodiments, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a separate chip from the processor 4100.

[0106] Figure 9 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0107] Referring to Figure 9, the memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile terminal with a digital camera attached, a smartphone with a digital camera attached, or a tablet computer with a digital camera attached.

[0108] The memory system 50000 may include a memory device 2200 and a controller 2100, the controller 2100 being able to control data processing operations of the memory device 2200, such as programming operations, erasing operations or reading operations.

[0109] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals, and the converted digital signals can be transmitted to the processor 5100 or the controller 2100. Under the control of the processor 5100, the converted digital signals can be output via the display 5300 or stored in the memory device 2200 via the controller 2100. Furthermore, under the control of the processor 5100 or the controller 2100, the data stored in the memory device 2200 can be output via the display 5300.

[0110] In some embodiments, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 5100 or as a separate chip from the processor 5100.

[0111] FIG10 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0112] Referring to Figure 10, the memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0113] The controller 2100 can control the data exchange between the memory device 2200 and the card interface 7100. In some embodiments, the card interface 7100 may be a secure digital card (SD) interface or a multimedia card (MMC) interface, but this disclosure is not limited thereto.

[0114] The card interface 7100 can facilitate data exchange between the host 60000 and the controller 2100 according to the protocol of the host 60000. In some embodiments, the card interface 7100 can support the Universal Serial Bus (USB) protocol and the IC-USB protocol. The card interface 7100 can refer to hardware, software embedded in hardware, or signal transmission schemes that can support the protocols used by the host 60000.

[0115] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (e.g., PC, tablet, digital camera, digital audio player, cellular phone, console video game hardware or digital set-top box), the host interface 6200 can communicate with the memory device 2200 through the card interface 7100 and the controller 2100 under the control of the microprocessor 6100.

[0116] According to this disclosure, the memory cells are three-dimensionally stacked, thereby improving the integration of the semiconductor device. Furthermore, the semiconductor device can have a stable structure and improved reliability.

[0117] Exemplary embodiments of this disclosure have been described in the figures and description. Although specific terminology has been used herein, those terms are merely for the purpose of explaining the embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0118] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the meaning generally understood by one of ordinary skill in the art to which this disclosure pertains. Terms with dictionary definitions shall be understood to have meanings consistent with the context of the relevant art. Unless explicitly defined in this application, terms should not be interpreted in an ideal or overly formal manner. <Cross-reference to related applications>

[0119] This application claims priority to Korean Patent Application No. 10-2021-0033529, filed on March 15, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. [Simplified Explanation of the Diagram]

[0007] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0008] In the figures, dimensions may be enlarged for clarity. It is understood that when an element is referred to as being between two elements, it may be the only element between the two elements, or there may be one or more intermediate elements. Similar reference numerals refer to similar elements throughout all the figures.

[0009] [Figures 1A and 1B] are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] [Figures 2A to 2C] are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] [Figures 3A to 3K] are figures illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] [Figures 4A to 4F] are figures illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] [Figures 5A to 5G] are figures illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] [Figure 6] is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0015] [Figure 7] is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0016] [Figure 8] is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0017] [Figure 9] is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0018] [Figure 10] is a diagram illustrating a memory system according to an embodiment of the present disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of insulating layers and a control gate; A channel layer that penetrates the gate structure; A floating gate, wherein the floating gate is located between the control gate and the channel layer; A first blocking pattern is located between the control gate and the floating gate; A second blocking pattern is located between the first blocking pattern and the control gate and between the control gate and the insulating layer. The second blocking pattern comprises a material with a dielectric constant higher than that of the first blocking pattern. And a third blocking pattern, which is located between the first blocking pattern and the floating gate, and the third blocking pattern comprises a material with a dielectric constant higher than that of the first blocking pattern.

2. The semiconductor device according to claim 1, wherein, The third barrier pattern includes hafnium silicate (HfSiOx).

3. The semiconductor device according to claim 1, wherein, The first blocking pattern includes oxides.

4. The semiconductor device according to claim 1, wherein, The second barrier pattern includes hafnium silicate (HfSiOx).

5. The semiconductor device according to claim 1, wherein, The thickness of each of the floating gates is greater than the thickness of each of the control gates.

6. The semiconductor device according to claim 1, wherein, The floating gate electrode is in contact with the insulating layer.

7. The semiconductor device according to claim 1, the semiconductor device further comprising a metal pattern located between the first blocking pattern and the floating gate.

8. The semiconductor device according to claim 7, wherein, The metal pattern includes metal, metal nitride, or nanostructure.

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