Integrated circuit with sacrificial memory cells and method of operation thereof

Abstract

An integrated circuit includes a main memory array having cells switchable between a first state and a second state. The circuit also includes sacrificial memory cells, each manufactured to switch between the first and second states and associated with at least one column of the main array. A controller is configured to detect a write operation to one column of the main array, apply stress to one of the sacrificial cells associated with that column, and detect failure of one of the associated sacrificial cells. The sacrificial cells are manufactured to have lower write cycle endurance than the cells of the main array or to withstand greater stress. Failure of one column of the main array is predicted, at least in part, based on the detected failure of one of the associated sacrificial cells.

Description

[Technical Field]

[0001] This invention relates to providing a mechanism for predicting computer memory failure using on-chip sacrificial memory cells in various devices and apparatuses. [Previous Technology]

[0002] Cells in computer memory devices can fail after undergoing a large number of write cycles. The expected number of cycles a cell can withstand is called its expected cycle durability. Cycle durability depends on both manufacturing and operating factors. Although mechanisms exist for detecting errors caused by cell failure after an error occurs (such as error correction codes), these mechanisms cannot predict failure and cannot prevent data loss. [Summary of the Invention]

[0003] An integrated circuit comprising: a non-volatile memory (NVM) array including a plurality of columns, each column including a plurality of NVM cells, each NVM cell being switchable between a first state and a second state in response to a write operation; a plurality of sacrificial NVM cells, etc., manufactured to be switchable between the first state and the second state, each sacrificial NVM cell being associated with at least one column of the NVM array; and a controller configured to: detect a write operation in one column of the NVM array; apply stress to one sacrificial NVM cell associated with the column based on the write operation; and detect a failure of the associated sacrificial NVM cell.

Implementation Method

[0005] The various devices and apparatuses described herein provide mechanisms for predicting computer memory failures using on-chip sacrificial memory cells.

[0006] While this disclosure allows for many different forms of embodiments, specific embodiments are shown in the drawings and will be detailed herein. It should be understood that the embodiments shown and described herein should be considered as examples providing the principles of this disclosure, and are not intended to limit this disclosure to the specific embodiments shown and described. In the following description, similar element symbols are used to describe the same, similar, or corresponding parts in several views of the drawings. For simplicity and clarity, element symbols may be repeated between drawings to indicate corresponding or similar elements.

[0007] Computer memory has many characteristics, including operating voltage, power consumption, cycle endurance, retention time, expandability, and cost. For example, some applications are designed to use low operating voltages (one volt or less) and have low power consumption, while others require high cycle endurance (10¹⁵ cycles or more). Furthermore, non-volatile memory should also have long data retention times (e.g., more than ten years).

[0008] Computer memory is often implemented as a memory array in an integrated circuit. The memory array can be configured as a number of columns, each column including multiple memory cells. Each memory cell can switch between a first state and a second state in response to a write operation, wherein the first state represents the logic value "1" and the second state represents the logic value "0".

[0009] Cycle durability refers to the expected number of switching or state-changing cycles that a memory cell can execute before it can no longer switch between states. In other words, cycle durability refers to the expected number of switching cycles that a memory cell can execute before it can no longer switch between states.

[0010] According to certain embodiments of this disclosure, the integrated circuit containing the memory array also includes a failure prediction circuit system. The failure prediction circuit system includes sacrificial memory cells, which are manufactured like cells of the main array and are switchable between a first state and a second state. Each sacrificial memory cell is associated with at least one column of the memory array. The failure prediction circuit system also includes a controller configured to detect write operations to one column of the memory array. Based on the detected write operations, the controller switches the sacrificial memory cells associated with that column between the first state and the second state. The controller is also configured to detect failures of the associated sacrificial memory cells that are switchable between the first state and the second state. The detected failures of the associated sacrificial memory cells predict failures of at least one column of the memory array.

[0011] The failure detection circuitry is configured such that a sacrificial memory cell may fail before its associated cell in the main memory array. This can be achieved by manufacturing a less durable sacrificial memory cell, or by applying more stress to the sacrificial memory cell than to its associated cell in the main memory array. The increased stress can be applied, for example, by using a higher level of switching voltage or current, applying voltage or current for a longer duration, or switching cells more frequently.

[0012] The failure detection circuit system can be used with various types of memory. The cells of the main memory array and the sacrificial memory cells are of the same type. However, the manufacturing differences between the cells of the main memory array and the sacrificial memory cells may depend on the memory type design.

[0013] Some memories (such as static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), and flash memory) store information in the presence or absence of charge or the state of logic gates. Other memories (such as phase change memory (PCM), resistive random access memory (RRAM), and correlated electron random access memory (CeRAM)) store information in high or low resistance states. Other memories store information in magnetic field polarization, including older technologies (such as core memory) and memories using newer technologies (such as magnetoresistive random access memory (MRAM), including spin-transfer torque MRAM (STT-MRAM)). There is some overlap in the technology because the resistance system of an MRAM cell depends on the magnetization direction determination resistor.

[0014] Figure 1 is an illustration of a single memory cell 100. The cell includes a switching layer 104 located between a bottom electrode 106 and a top electrode 108. The switching layer 104 can switch between a first state (such as a high-resistance state) and a second state (such as a low-resistance state). Generally, the state is switched by applying a write voltage across the switching layer. The state of the cell can be read by measuring the resistance of the cell. This can be accomplished, for example, by applying a read voltage across the cell. A low-resistance state (LRS) can correspond to a logic value of 1, and a high-resistance state (HRS) can correspond to a logic value of 0, or vice versa. Therefore, the memory cell 100 stores one bit of information.

[0015] PCMs typically use chalcogenide materials (usually Ge2-Sb2-Te5, GST) in the switching layer 102, and rely on the resistance difference between the crystalline and amorphous phases for efficient data storage. In the crystalline phase, the cell is in a low resistance state (LRS) or ON state, while in the amorphous phase, the cell is in a high resistance state (HRS) or OFF state. The SET operation generates LRS and corresponds to storing the logic value "1", while the RESET operation generates HRS and corresponds to storing the logic value "0" in the device. For the SET operation, the PCM is heated to above its crystallization temperature when a voltage pulse is applied, while for the RESET operation, a larger current is passed through the cell and then suddenly cut off, causing the material to melt and then quench to achieve an amorphous state.

[0016] In the RRAM, the switching layer 102 is composed of insulating layers sandwiched between the top electrode 104 and the bottom electrode 106. The RRAM depends on the formation and breakage of conductive wires in the insulator between the two electrodes, corresponding to the LRS and HRS respectively.

[0017] In CeRAM, the switching layer 102 utilizes a quantum phase transition (called the Mott transition) present in carbon-doped transition metal oxide (TMO) materials. This transition produces a large resistance change due to the voltage or current-induced shift in the occupancy of the electron orbitals surrounding each metal ion.

[0018] In MRAM, the switching layer 102 can use a magnetic tunnel junction (MTJ) as a storage element.

[0019] Figure 2 shows a more detailed representation of the example MRAM cell 200. The MRAM cell 200 includes a switching layer 202 coupled to a top electrode 204 and a bottom electrode 206. The switching layer 202 includes a magnetically pinned ferromagnetic layer 208 in which the magnetic field polarization is in a fixed direction; and a magnetically free ferromagnetic layer 210 in which the magnetic field polarization can be switched between a direction parallel to (referred to as the "P" state) the polarization direction of the pinned ferromagnetic layer 208 and an antiparallel direction (referred to as the "AP" state) the polarization direction of the pinned ferromagnetic layer 208. For example, the ferromagnetic layer may be a material such as MgO or Al2O3.

[0020] The tunneling oxide layer 212 is a thin dielectric layer that supports quantum mechanical tunneling of spin-polarized electrons through the layer. The tunneling oxide layer 212, the pinned ferromagnetic layer 208, and the free layer 210 together form a magnetic tunneling junction (MTJ). The relative magnetization orientation of the two ferromagnetic layers separated by the dielectric layer determines the resistance of the MTJ structure. The MRAM cell is designed to have two stable magnetic states, corresponding to high and low resistance values, and to retain those values ​​without any applied power. The cell is read by sensing the resistance to determine whether the state is high or low, while writing is performed by the magnetic field generated by the current flowing in the bit lines and word lines. The antiferromagnetic layer 214 prevents disturbances in the magnetization orientation of the pinned ferromagnetic layer 208.

[0021] Applying an external electromagnetic field can change the magnetization direction of the free ferromagnetic layer 210. When the pinned layer and the free layer have the same magnetization direction, the MTJ system is in parallel or LRS. When the magnetization directions of the two ferromagnetic layers are antiparallel, the MTJ system is in HRS.

[0022] The operating characteristics of the MRAM cell 200 depend at least on the stack cross-sectional size d and the thickness t of the tunneling oxide layer 212.

[0023] In the design of memory devices, conflicts often exist between different desired characteristics. For example, switching pulses are applied to switch between high-resistance and low-resistance states or between magnetic polarizations. Shorter pulses allow for faster switching, but require higher voltage or current levels. Better data retention requires higher switching threshold levels, which again require higher voltage or current levels. This conflicts with the cycle life of the memory, as cycle life is affected by the level and duration of the switching pulse. Increasing the switching pulse level for faster and / or longer data retention increases the probability of cell failure.

[0024] The following disclosure is described with reference to embodiments of an MRAM device. However, the disclosure is not limited thereto and can be used in other types of memory devices, such as PCRAM, FeRAM, CeRAM, RRAM, and other types of non-volatile memory (NVM) or volatile memory (VM). For example, a memory cell may be a non-volatile memory cell (NVM cell), a main memory array may be a non-volatile memory array (NVM array), and a sacrificial memory cell may be a non-volatile sacrificial memory cell (NVM sacrificial cell).

[0025] Figure 3 is a graph showing the relationship between memory cell storage temperature and memory cell cycle durability for STT-MRAM memory cells. Storage temperature is the maximum temperature (°C) at which the cell can store information for up to ten years. Durability is the number of switching cycles. The graph shows that temperature adversely affects durability. This makes it difficult to predict the durability of the memory device because the temperature at which the memory device will be exposed is unknown.

[0026] Cyclic durability depends on the stresses the unit is subjected to (such as the amplitude and duration of the pulses that excite the unit) and the unit's ability to withstand such stresses. Apart from the unit structure, the ratio of defective units to operational units depends on the amplitude and duration of the voltage / current. This parameter can be evaluated from design parameters.

[0027] One embodiment of this disclosure uses sacrificial memory cells located close to the memory blocks of the memory array. Since the sacrificial memory cells and the main memory array are manufactured in the same integrated circuit (chip), they are exposed to the same process and temperature variations. However, the sacrificial memory cells are engineered and stressed so that they will fail before the cells in the associated region of the main memory array.

[0028] Figure 4 is an illustration of an integrated circuit 400 including sacrificial memory cells according to an embodiment of the present disclosure. The integrated circuit 400 includes a main memory array 402 and associated peripheral circuitry. Memory cells in the main memory array 402 can switch between a first state and a second state in response to a write operation. The peripheral circuitry includes column circuitry 404 (e.g., word lines coupled to columns of the memory array) and row circuitry 406 (e.g., bit lines coupled to rows of the memory array). According to one embodiment of the present disclosure, the integrated circuit 400 also includes a failure prediction circuitry system. The failure prediction circuitry system includes a sacrificial memory cell 408, associated peripheral circuitry 410, and a controller 412. The sacrificial memory cell 408 can also switch between a first state and a second state and has the same or similar structure as the cells in the main memory array.

[0029] For example, the peripheral circuitry 410 for the sacrifice memory unit 408 may be included in the peripheral circuitry (404 and 406) or provided as a separate module. This implementation manufactures a highly integrated memory device, or allows the sacrifice unit and associated peripheral circuitry to be provided as separate intellectual property (IP) blocks.

[0030] In one embodiment, the sacrificial memory cell 408 is engineered such that it will fail before the cells in the main memory array. That is, the sacrificial memory cell 408 is manufactured to have lower write cycle endurance. For example, for MRAM cells, the magnetic tunneling junction (MTJ) can be fabricated with a thinner oxide layer, or the MTJ stack can be fabricated with a smaller cross-sectional area or cross-sectional size (such as a smaller diameter for cylindrical stacks). A smaller cross-sectional area or cross-sectional size increases the current density in the cell, causing the cell to be subjected to more stress in each switching cycle.

[0031] Multiple types of sacrificial cells can be associated with the same column, having different failure probabilities. For example, a Type 1 sacrificial cell may be manufactured to fail before a Type 2 cell. The failure of a Type 2 sacrificial cell predicts the failure of the associated primary cell earlier than the failure predicted by a Type 1 cell, and may trigger different mitigation responses. The controller 412 is configured to apply stress to the sacrificial memory cells during operation, such that they will fail before cells in the associated region of the primary memory array. The controller detects write operations to the primary memory array 402 and switches one or more sacrificial memory cells between a first state and a second state based on the detected write operations. The sacrificial memory cell 408 may be associated with a designated sub-block (e.g., region 414) of the primary memory array. The controller monitors access to the sub-block and determines when the associated sacrificial memory cell should be switched. For example, when the sacrificial memory cell is manufactured to be less durable than the primary memory, the sacrificial memory cell may be switched each time a write is made to the sub-block. When sacrificial memory cells are manufactured to have the same durability as main memory, they can be switched more frequently than sub-blocks. Depending on the technology of the sacrificial memory cells, a low-current reset operation can be used before the next stress operation occurs. This could be the case for STT-RAM, for example.

[0032] The sacrificial cell may be stressed more frequently than the cells of the main array. For example, the cell may be stressed each time it is written to the associated main cell, as well as at selected additional times (e.g., during idle periods).

[0033] The sacrificial cell can be stressed at a higher level than the main array cells. This can be accomplished by applying a higher voltage. The higher voltage can be generated by various means, such as reducing the resistance of associated selector devices, bit lines, or source lines. For example, bit lines and / or source lines can have increased width, increased thickness, or multiple layers. In a further embodiment, a selector with a lower threshold voltage can be used to reduce its on-resistance, further increasing the voltage applied to the sacrificial cell.

[0034] The stress level applied to the sacrificial unit may be gradually increased during the life of the memory device.

[0035] The controller reads the sacrificed memory cell after it has been switched to detect a failure or other defect. Specifically, a failure is detected when the sacrificed memory cell is no longer switchable between a first state and a second state (logic values ​​0 and 1). This contrasts with techniques used to check operating conditions, in which, for example, a test cell is used to set the data storage voltage for static random access memory (SRAM). In these techniques, the test cell itself does not fail and remains switchable.

[0036] The failure of a sacrificial memory cell, which can switch between a first state and a second state, indicates that the main memory array may become close to failure. Based on the failure of one or more sacrificial memory cells, the controller predicts the failure of at least one sub-block of the main memory array and takes appropriate action. For example, the controller may generate an interrupt signal, copy data from the sub-block to another location in response to the predicted failure, or mark the sub-block as faulty.

[0037] Figure 5 is a graph showing the relationship between the resistance of a memory cell and stress time. Resistance is shown in ohms (Ω), while stress time is shown in arbitrary units. An example response depicted as solid line 502 in the graph shows that the resistance drops rapidly after a certain stress, indicating that the cell has failed and is no longer functional. More generally, the responses of different cells will differ. For example, line 504 shows the response of a cell with higher initial resistance, and line 506 shows the response of a cell with lower initial resistance. This indicates that cells with lower resistance (such as cells with a thinner oxide layer) are likely to fail earlier than cells with higher resistance. In one embodiment, the failure prediction circuitry is configured to apply stress to the sacrificial memory cell for a longer time than is required. In a further embodiment, the sacrificial memory cell is switched more frequently than the associated sub-blocks of the main memory array.

[0038] Figure 6 is a graph showing the proportion of failed cells in the memory array over time for different voltage levels. The ratio of failed cells to all cells is expressed as F. The time to cell failure is shown in seconds. Figures 602, 603, 606, and 608 show the failure ratio over time for voltages of 1.81V, 1.75V, 1.69V, and 1.63V, respectively. It can be seen that cells fail earlier at higher voltages. In one embodiment, the sacrificial memory cell is driven with a voltage or current higher than that of the cells in the main memory array. The amount of overdriving can be determined, causing cell durability to deteriorate to a specified amount. In this way, the sacrificial memory cell may fail before cells in the associated sub-block of the main memory. Therefore, the failure of the sacrificial memory cell can be used to predict the failure of the associated main memory cell.

[0039] In a further embodiment, the sacrificial memory cell is manufactured such that it is equally likely to fail before the cells in the associated sub-blocks of the main memory array, even when subjected to the same stress.

[0040] Figure 7 is a graph showing the relationship between the oxide layer thickness and the breakdown voltage in a magnetoresistive memory cell. The figure shows the breakdown voltage as a function of oxide layer thickness for cells in a parallel (P) or antiparallel (AP) state with positive and negative bias voltages. Figure 7 indicates that cells with a thinner oxide layer break down at a lower voltage than cells with a thicker oxide layer. In one embodiment of this disclosure, the sacrificial memory cell is manufactured to have a thinner oxide layer than the cells in the main memory array. As a result, the sacrificial cell may fail before the cells in the main memory array.

[0041] In a further embodiment, the switching element of the sacrificial memory cell is manufactured to have a smaller cross-sectional area (e.g., smaller diameter or smaller cross-sectional size) than that of the cells in the main memory array. This increases the current density of the sacrificial memory cell compared to that in the main memory cell. Furthermore, this makes it possible for the sacrificial memory cell to be unswitchable before cells in associated sub-blocks of the main memory array.

[0042] Manufacturing processes can lead to significant variations between devices. For example, the thickness of the oxide can vary. In one embodiment of this disclosure, the controller of the failure prediction circuit system includes a lookup table that stores trimmed values ​​to indicate the desired operating point for sacrificing memory cells.

[0043] Although Figure 4 depicts columns of sacrificial memory cells adjacent to the main memory array, sacrificial memory cells can be placed around the entire memory block. In one embodiment, the controller of the failure prediction circuitry determines which sacrificial memory cells are associated with which sub-blocks of the main memory array. In this way, the failure prediction circuitry can warn / replace specific memory sub-blocks instead of causing the entire array to fail. More accurate predictions can be achieved by using more sacrificial memory cells and smaller sub-blocks. For example, when using very large sub-blocks (e.g., 1 Mbit), the associated sacrificial memory cells cannot distinguish between 10 writes to individual cells in the sub-block or 107 writes to a single cell in the sub-block. Accordingly, smaller sub-blocks can be used. In one embodiment, a sacrificial memory cell is used for each line of the array—it can be, for example, 64, 128, 256, or 512 bits. In a further embodiment, a sub-block can be used for several lines of the array.

[0044] It should be noted that smaller sub-blocks enable more accurate predictions. For example, with only one sacrifice per 1Mb sub-block, if each cell is written 10 times, the sacrificed memory cell will record 107 cycles of stress—the same as if a single cell in the sub-block were stressed 107 times. A good calibration procedure, along with appropriate finesse, will overcome this problem.

[0045] In magnetic tunneling junctions (MTJs), the most common failure mechanism is the failure to restore parallelism. However, cells using other technologies, such as RRAM cells, can suffer from multiple failure sources.

[0046] In one embodiment shown in FIG8, different state changes are tracked. The memory device 800 is similar to that shown in FIG4, except that for each sub-block 414, the transition from LRS to HRS (e.g., P2AP in MRAM) is tracked by a first sacrificial cell, and the transition from HRS to LRS (e.g., AP2P in MRAM) is tracked by separate second sacrificial memory cells. Assuming that HRS ("AP" in MRAM or "R-off" in RRAM) represents a logic value of 0, and LRS ("P" in MRAM or "R-on" in RRAM) represents a logic value of 1, if the data written to the sub-block contains at least one bit with a value of 0, stress is applied to the first cell, and if the data written to the sub-block contains at least one bit with a value of 1, stress is applied to the second cell. The first sacrificial memory cell is denoted as cell 802, and the second sacrificial memory cell is denoted as cell 804. These cells can be manufactured at various other locations relative to the main memory array 402.

[0047] Figure 9 is a flowchart of a method 900 for predicting cell failure in a memory device according to an embodiment of the present disclosure. After the start block 902, a write operation to a column of a memory array to an integrated circuit is detected at block 904. The column includes multiple memory cells. The write operation switches one or more cells in the column between a first state and a second state. Some cells may switch from 0 to 1, and some from 1 to 0. Other cells may remain unchanged or be rewritten with the same value. Based on the detected write operation, one or more sacrificial memory cells associated with the column are stressed at block 906. This may be accomplished, for example, by switching between the first state and the second state. At block 908, the sacrificial memory cells associated with the column are tested to see if they are functioning correctly. This may be accomplished, for example, by reading the cell to verify that the attempted switching has occurred. In resistive memory, applying stress may involve attempting to switch the sacrificial cell from low resistance to high resistance. If the measured cell resistance remains low, a failure is detected. This indicator unit will fail under sufficiently high voltage and current. If one or more sacrifice memory units can no longer switch between the first and second states, the corresponding column(s) of the main memory array will also become ineffective.

[0048] This method enables intelligent solutions to increase the system's lifespan. For example, if "1" is written more often than "0" and the first (P2AP) sacrificed memory cell detects a possible failure in the medium future, the data encoding can be reversed to make "0" written more often, thereby extending the system's lifespan.

[0049] FIG10 is an illustration of a column 1000 of memory cells in an integrated circuit memory device including sacrificial memory cells according to an embodiment of the present disclosure. Column 1000 includes a word line (WL) 1002, which is established to select the column for accessing the sacrificial memory cells and cells of the main array. Generally, a column may include one or more sacrificial cells and a plurality of main cells. In the figure, the sacrificial memory cells are coupled between a bit line (BL) 1004 and a sense line (SL) 1006, while the first memory cells of the main array are coupled between a bit line 1008 and a sense line 1010, and the second memory cells of the main array are coupled between a bit line 1012 and a sense line 1014. When the word line 1002 and the bit line 1004 are established, a transistor 1016 allows a voltage to be applied across the resistive element 1018 of the sacrificial cell. Similarly, when word line 1002 and bit lines 1008 and 1012 are established, transistors 1020 and 1022 allow voltages to be applied to the resistive elements 1024 and 1026 across the main array cells, respectively. The resulting currents on sensing lines 1006, 1010, and 1014 can be measured to determine whether the corresponding cell is in a high-resistance or low-resistance state. In this way, the sacrificial cell can be stressed at least as frequently as any cell in the same column of the array.

[0050] Excessive stress on the sacrificial memory cell can lead to a "false positive", in which the controller issues a "durability alarm" that is not related to the durability status of the memory block.

[0051] To reduce the occurrence of "false positives", the controller, which interfaces with the peripheral circuit system, can utilize any available information about the memory block write operation. For example, in the case of using a "read-before-write" scheme that only writes the changed bits, if one or more bits in the associated sub-block are changed, stress will only be applied to the sacrificial memory cell.

[0052] Similarly, if a circuit system is used to terminate the write operation once the switching operation is detected to be complete, the termination information can be used to control the duration of the stress signal to the sacrificial memory cell.

[0053] FIG11 is an illustration of an integrated circuit memory device 1100 according to an embodiment of the present disclosure. Device 1100 includes a main memory array 402 and associated peripheral circuitry. The peripheral circuitry includes column circuitry 404 (e.g., word lines coupled to columns of the memory array) and row circuitry 406 (e.g., bit lines coupled to rows of the memory array). Sacrificial memory cells are provided for failure prediction. Sacrificial memory cells are accessed and stressed by peripheral circuitry 404 and 410. Each column of sacrificial memory cells is associated with a sub-region of the main memory array 402. For example, sacrificial memory cells 1102, 1104, and 1106 are associated with memory sub-region 1108. Other sacrificial cells are associated with sub-region 1110, and there are still additional cells associated with sub-region 1112. In one embodiment, sacrificial cells with different failure characteristics are associated with each sub-region. For example, these cells can be manufactured with different durability levels, allowing one type of cell to fail more quickly. If a sacrificial memory failure occurs, different actions can be taken depending on the cell type, with a more aggressive action taken when a more durable cell fails.

[0054] FIG12 is an illustration of an integrated circuit memory device 1200 according to an embodiment of the present disclosure. In this embodiment, the memory array 1202 includes both main memory units and sacrificial memory units 1204. Furthermore, peripheral circuit systems 1206 and 1208 include circuit systems for both the main memory units and the sacrificial units. The controller 1212 may also be integrated with the peripheral circuit systems.

[0055] Figure 13 is an illustration of an integrated circuit memory device 1300 including sacrificial memory cells according to an embodiment of the present disclosure. In this embodiment, the main memory array 1302 and the sacrificial memory cells 1304 are manufactured as separate modules. The main memory array 1302 is accessed via peripheral circuit systems 1306 and 1308, while the sacrificial memory cells 1304 are accessed via peripheral circuit systems 1310 and 1312. A controller 1314 controls when and how stress is applied to the sacrificial memory cells 1304 and monitors for cell failure. Therefore, the failure prediction circuitry can be highly integrated with the main memory array or provided as a stand-alone module close to the main memory array.

[0056] The above-described failure prediction system discloses the ability to predict durability failures in the main memory array by positioning sacrificial memory cells close to block memory cells. The sacrificial memory cells are manufactured and / or stressed so that they fail (in operation) before the cells in the main memory array.

[0057] The failure prediction system is subjected to the same program and temperature changes as the main memory array, thereby achieving more accurate prediction of durability failure.

[0058] The failure prediction system can be integrated with the peripheral circuitry of the main memory array to enable the use of more detailed write information to control the stress applied to the sacrificial memory cells.

[0059] The failure prediction system disclosed herein can be used in different types of memory, including volatile and non-volatile memory, capacitive memory, and resistive memory.

[0060] In one embodiment, the sacrificial memory cell is manufactured such that its equivalent is expected to fail before the cells in the main memory array (given the same stress). For most types of memory, the relationship between cell manufacturing parameters and durability is known. Specifically, it is generally known how variations in certain parameters (such as layer thickness or cross-sectional area) will affect durability. This information can be used to determine the manufacturing parameter values ​​used for the sacrificial memory cell.

[0061] In cases where temperature conditions impose hard limitations on the operation of the sacrificial memory cell, an external temperature sensor can calibrate the excessive stress applied to the sacrificial memory cell.

[0062] As previously mentioned, the control of the sacrifice memory unit can be externally programmed to change the adjustment value of the sacrifice unit operation point determined based on corner angle, etc.

[0063] Due to manufacturing variations, sacrificed memory cells and main memory cells may have different durability levels. In one embodiment, a group of sacrificed memory cells is used to monitor a memory array or a sub-block of the array. Durability failure is predicted from the performance of the group rather than from the failure of a single sacrificed memory cell.

[0064] Monitoring information from the sacrifice memory cell can be used for other purposes (such as wear leveling).

[0065] In this document, the relevant terms (such as first and second, top and bottom, and the like) are used only to distinguish one entity or action from another, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms "comprise / comprising," "include / including," "has / having," or any other variations thereof are intended to cover non-exclusive inclusion, such that a program, method, article, or apparatus that includes a list of elements includes not only those elements, but may also include other elements not expressly listed or not inherent to such program, method, article, or apparatus. The phrase "comprises…a" preceding an element does not, without further limitation, exclude the presence of additional identical elements in the program, method, article, or apparatus that includes that element.

[0066] Throughout this document, references to "one embodiment," "certain embodiments," "an embodiment," "(multiple) implementation(s)," "(multiple) aspects(s)," or similar terms mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, the appearance of such phrases or references to the same embodiments throughout this specification necessarily implies that all such embodiments are included. Furthermore, in one or more embodiments, specific features, structures, or characteristics can be combined in any suitable manner without limitation.

[0067] As used herein, the term "or" is intended to be interpreted as including or referring to any one or any combination thereof. Therefore, "A, B, or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C". An exception to this definition will only occur when the combination of elements, functions, steps, or actions is inherently mutually exclusive in some respect.

[0068] As used herein, the term “configured to” when applied to a component means: (i) that the component can be designed or configured to perform a specified function; or (ii) that the component has the required structure to enable it to be reconfigured or adapted to perform that function.

[0069] Numerous details have been mentioned to provide an understanding of the embodiments described herein. These embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have not been described in detail to avoid obscuring the embodiments. This disclosure is not intended to limit the scope of the embodiments described herein.

[0070] Those skilled in the art will understand that this disclosure has been described by example. This disclosure may be implemented using hardware component equivalents (such as special purpose hardware and / or dedicated processors) that are equivalent to the disclosure described and claimed. Similarly, dedicated processors and / or dedicated hardwired logic may be used to constitute alternative equivalent embodiments of this disclosure.

[0071] The dedicated or reconfigurable hardware components used to implement the disclosed mechanism can be described, for example, by instructions in a hardware description language (HDL) (such as VHDL, Verilog, or RTL (Register Transfer Language)) or by a wiring lookup table of components and connections. Instructions can be at the functional level, the logical level, or a combination thereof. Instructions or wiring lookup tables can be input into an automated design or manufacturing process (sometimes called high-order synthesis), which interprets the instructions and generates digital hardware that implements the stated function or logic based on the interpreted instructions.

[0072] HDL instructions or wiring diagrams may be stored on non-transitory computer-readable media (such as electrically erasable programmable read-only memory (EEPROM); non-volatile memory (NVM); mass storage devices (such as hard disk drives, floppy disk drives, optical disk drives); optical storage elements, magnetic storage elements, magneto-optical storage elements, flash memory, core memory, and / or other equivalent storage technologies without departing from this disclosure. Such alternative storage devices shall be considered equivalent.

[0073] The various embodiments described herein are implemented using dedicated hardware, configurable hardware, or a programmed processor that executes programmed instructions, which are broadly described in flowchart form and can be stored on any suitable electronic storage medium or transmitted via any suitable electronic communication medium. Combinations of these elements may be used. Those skilled in the art will understand that the above-described procedures and mechanisms can be implemented in any number of variations without departing from this disclosure. For example, the order of certain operations performed may often be changed, additional operations may be added, or operations may be deleted without departing from this disclosure. Such variations are contemplated and considered equivalent.

[0074] The various representative embodiments detailed herein have been presented by way of example rather than limitation. Those skilled in the art will understand that various changes can be made to the form and details of the said embodiments to arrive at equivalent embodiments that are still within the scope of the appended claims. [Simplified Explanation of the Diagram]

[0004] Visual representations are provided accompanying drawings to more fully describe various representative embodiments and to enable those skilled in the art to better understand the disclosed representative embodiments and their inherent advantages. In these drawings, similar element symbols identify corresponding or similar elements. [Figure 1] is an illustration of a memory cell. [Figure 2] is an illustration of a magnetoresistive memory cell. [Figure 3] is a graph showing the relationship between memory cell storage temperature and memory cell cycle durability. [Figure 4] is an illustration of an integrated circuit memory device including sacrificial memory cells according to an embodiment of the present disclosure. [Figure 5] is a graph showing the relationship between memory cell resistance and storage and stress time. [Figure 6] is a graph showing the proportion of failed cells in a memory array over time for different voltage levels. [Figure 7] is a graph showing the relationship between oxide layer thickness and breakdown voltage in a magnetoresistive memory cell. [Figure 8] is an illustration of an integrated circuit memory device including sacrificial memory cells according to an embodiment of the present disclosure. [Figure 9] is a flowchart of a method for predicting cell failure in a memory device according to an embodiment of the present disclosure. [Figure 10] is an illustration of a series of integrated circuit memory devices including sacrificial memory cells according to an embodiment of the present disclosure. [Figure 11] is an illustration of an integrated circuit memory device including sacrificial memory cells of different properties according to an embodiment of the present disclosure. [Figure 12] is an illustration of an integrated circuit memory device according to an embodiment of the present disclosure, in which a memory array includes sacrificial memory cells. [Figure 13] is an illustration of an integrated circuit memory device including sacrificial memory cells according to an embodiment of the present disclosure.

Claims

1. An integrated circuit comprising: a non-volatile memory (NVM) array including a plurality of columns, each column including a plurality of NVM cells, each NVM cell being switchable between a first state and a second state in response to a write operation; a plurality of sacrificial NVM cells, etc., manufactured to be switchable between the first state and the second state, each sacrificial NVM cell being associated with at least one column of the NVM array; and a controller configured to: detect a write operation in one column of the NVM array; in response to detecting the write operation, apply stress to one of the sacrificial NVM cells associated with the column, including applying a switching pulse to the sacrificial NVM cell, the switching pulse being configured to switch the sacrificial NVM cell between the first state and the second state; and in response to the switching pulse, detect a failure of the associated sacrificial NVM cell to switch between the first state and the second state, wherein the failure indicates a cycle endurance of the column of the array.

2. The integrated circuit of claim 1, wherein the switching pulse is configured to: switch a first sacrificial NVM cell associated with the column from the first state to the second state in response to a write operation that switches an NVM cell in the column from the first state to the second state; and switch a second sacrificial NVM cell associated with the column from the second state to the first state in response to a write operation that switches an NVM cell in the column from the second state to the first state.

3. The integrated circuit of claim 1, wherein the failure of at least one column of the NVM array is predicted at least in part based on the detected failure of one of the associated sacrificial NVM cells.

4. The integrated circuit of claim 1, wherein the NVM cells of the plurality of sacrificial NVM cells are manufactured to have a write cycle endurance lower than that of the NVM cells of the NVM array, wherein the different cells of the plurality of sacrificial NVM cells have been manufactured to have similar or different write cycle endurance levels.

5. As in request item 4, the integrated circuit, wherein: Each of the sacrificial NVM cells and the cells of the NVM array includes a stack having a cross-sectional dimension and including an oxide layer; and each cell of the plurality of sacrificial NVM cells has an oxide layer that is thinner or a cross-sectional dimension that is smaller than that of the cells of the NVM array.

6. The integrated circuit of claim 1, wherein the controller is configured to stress the associated sacrifice NVM cell more frequently than to detect the write operation.

7. The integrated circuit of claim 1, wherein the plurality of sacrificial NVM cells include a switching circuit system configured to provide a switching pulse to the sacrificial NVM cells, the switching pulse having a higher level or longer duration than all switching pulses applied during a write operation to one of the NVM arrays.

8. An integrated circuit as claimed in claim 1, wherein a sacrificed NVM cell is located in the near region of at least one column of cells of the associated NVM array in the integrated circuit, and is integrated with the NVM array or manufactured as a separate module.

9. The integrated circuit of claim 1, wherein each column of the NVM array contains one or more word groups, each NVM cell in a column of the NVM array represents a bit of a word group, and at least one sacrificed NVM cell is associated with a word group or a column of the NVM array.

10. The integrated circuit of claim 1, wherein the NVM array comprises a plurality of sub-regions, and wherein each sub-region of the NVM array is associated with a plurality of sacrificial NVM cells.

11. The integrated circuit of claim 1, wherein the plurality of sacrificial NVM cells and the NVM array include magnetoresistive random access memory (MRAM), phase-change memory (PCM), resistive random access memory (RRAM), or correlated electronic random access memory (CeRAM).

12. The integrated circuit of claim 1, further comprising: a peripheral circuitry system coupled to and configured to perform write operations thereon, wherein the controller is integrated with the peripheral circuitry system.

13. A method of operating an integrated circuit having one or more sacrificial NVM cells, comprising: detecting a write operation to one column of an NVM array of the integrated circuit, the column including a plurality of NVM cells, and the write operation switching one or more cells of the column between the first state and the second state; in response to detecting the write operation, applying a first switching pulse to one or more sacrificial NVM cells of the integrated circuit associated with the column, the one or more sacrificial NVM cells being configured to switch between the first state and the second state; and in response to the first switching pulse, detecting a failure of one of the sacrificial NVM cells to switch between the first state and the second state.

14. The method of claim 13, further comprising: predicting the failure of the column based at least in part on the detected failure of one or more sacrifice NVM units.

15. The method of request item 14 further includes: signaling the column for predicted failure.

16. The method of claim 14, further comprising: relocating data from the column to another column of the NVM array in response to a predicted failure of the column.

17. As in request item 13, wherein: Switching an NVM cell between the first state and the second state includes applying a second switching pulse to the NVM cell, the first switching pulse having a higher level or a longer duration than the second switching pulse.

18. The method of claim 13, wherein the one or more sacrificial NVM cells of the integrated circuit that switch between the first state and the second state are executed more frequently than the write operation is detected.

19. The method of claim 13, further comprising: assigning at least one column of the NVM array to each of the sacrificed NVM cells.

20. The method of claim 19, wherein the assignment is performed automatically based on a detected operating condition of the integrated circuit.

21. The method of claim 13, further comprising configuring the first switching pulse to: switch a first sacrificial NVM cell among the one or more NVM cells from the first state to the second state in response to a write operation that switches an NVM cell of the NVM array from the first state to the second state; and switch a second sacrificial NVM cell among the one or more NVM cells from the second state to the first state in response to a write operation that switches an NVM cell of the NVM array from the second state to the first state.

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