Nested interposer with through-silicon via bridge die

Abstract

An electronic package includes an interposer having an interposer substrate, a cavity extending into but not through the interposer substrate, a via-via (TIV) in the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component within the cavity, wherein the nested component includes a component pad coupled to the component via. A core via is located beneath the nested component and extends from the nested component through the interposer substrate. A die is coupled to the interposer pad via a first interconnect and to the component pad via a second interconnect.

Description

Technical Field

[0001] The specific features disclosed herein relate to electronic packaging, and more particularly to multi-chip package architectures having one or more chips attached to an interposer and one or more components embedded in cavities within the interposer. Prior Technology

[0002] The need for increased performance and reduced form factor is driving packaging architectures toward multi-chip integration. Multi-chip integration allows chips manufactured at different process nodes to be implemented in a single electronic package. However, current multi-chip architectures result in a large form factor, making them unsuitable for certain use cases or not what end users want. Summary of the Invention

[0003] This description relates to nested interposers with silicon via bridge wafers and methods for forming such electronic packages, depending on various specific configurations. In the following description, various aspects of the exemplary embodiments will be described using terminology commonly used by those skilled in the art to convey their substantial work to others skilled in the art. However, those skilled in the art will understand that this disclosure may be implemented only in some of the described aspects. For purposes of explanation, specific numbers, materials, and structures are listed to provide a thorough understanding of the exemplary embodiments. However, those skilled in the art will understand that this disclosure may not need to be implemented with specific details. In other instances, well-known features have been omitted or simplified so as not to obscure the exemplary embodiments.

[0004] The various tasks will be described sequentially as multiple discrete tasks in a manner most conducive to understanding this disclosure; however, the order of description should not be interpreted as implying that these tasks necessarily depend on a specific order. In particular, these tasks need not be performed in the order they are presented.

[0005] As noted above, current packaging solutions are beginning to utilize multi-chip architectures. However, including multiple chips in a single package is not without its problems. Besides the large coverage area of ​​existing multi-chip architectures, such systems also suffer from poor yield and reliability. In particular, when using conventional packaging substrates, it is difficult to control the interconnection between chips due to warping and other alignment issues. Accordingly, specific examples disclosed herein include electronic packages that utilize nested interposers with through-silicon via (TSV) Si bridge chips for chip-to-chip placement with fine bump pitch.

[0006] To provide context, nested interposers may include interposers with one or more cavities. Nested components may be positioned within the cavities. One or more wafers may be interconnected with the interposer and the nested components. In some embodiments, the interconnects include intermediate pads positioned between the pads of the nested components and the wafers, and between the pads of the interposer and the wafers. In some embodiments, the intermediate pads are connected to the interposer pads and the nested component pads via vias. In other embodiments, the intermediate pads are directly connected to the interposer pads and the nested component pads. The intermediate pads (and vias in some embodiments) provide misalignment correction for misalignment between the interposer and the nested components. Accordingly, the embodiments allow for high yield and reliability, even when using fine-pitch interconnects (e.g., when the nested component is a bridge between two wafers).

[0007] Referring now to Figure 1A, a cross-sectional view of an electronic package 100 according to a specific configuration is shown. In this configuration, the electronic package 100 may include an interposer 130 and a nested component 140. The nested component 140 is positioned within a cavity 135 passing through the interposer 130. The nested component 140 is called "nested" because the component 140 is placed within the cavity 135. That is, the nested component 140 is partially surrounded by the interposer 130. In the exemplary configuration, a single cavity 135 is shown within the interposer 130. However, it should be understood that any number of cavities 135 can be used, depending on the device. Examples of multiple cavities 135 are provided in more detail below. In the exemplary configuration, a single nested component 140 is shown within a cavity 135. However, it should be understood that any number of nested components 140 can be positioned within a single cavity 135. The following provides a more detailed example of multiple nested components 140 in a single cavity 135.

[0008] In some embodiments, the interposer 130 may be any suitable substrate material. For example, the interposer 130 may be or include a substrate, including glass, ceramic, semiconductor materials (such as high or low resistivity silicon, III-V semiconductors, or the like), or organic substrates (high density interconnect (HDI) substrates, embedded trace substrates (ETS), high density package (HDP) substrates, molded substrates, or the like). In some embodiments, the interposer 130 is a passive device. That is, the interposer 130 may only include passive components (such as traces, vias, etc.). For example, the interposer 130 may include a via 134 that provides a connection between a pad 133 below the interposer 130 and a pad 136 above the interposer 130. In other embodiments, the interposer 130 may be an active interposer. That is, the interposer 130 may include active devices (such as transistors, etc.).

[0009] In a specific embodiment, the nested component 140 may be an active or passive component. For example, an active nested component 140 may include logic devices, analog / radio frequency (RF) devices, input / output (I / O) circuitry, memory devices, voltage regulators, sensors, or the like. A passive nested component 140 may include high-density multi-chip interconnect bridge chips, capacitors, inductors, resistors, thermoelectric coolers, high-speed connectors, or the like. In an exemplary embodiment, the nested component 140 includes an active surface 141. Although referred to as an "active" surface 141, it should be understood that an active surface 141 may include entirely passive features. In a specific embodiment, the nested component 140 may include a through component via (TCV) 144. The TCV 144 may electrically couple the active surface 141 to a pad 143 on the back side of the nested component 140.

[0010] In some embodiments, the intermediate layer 130 and the nested member 140 may be embedded by the mold layer 132. The mold layer 132 may fill the remaining portion of the cavity 135. That is, a portion of the mold layer 132 may be positioned between the sidewall of the nested member 140 and the sidewall of the intermediate layer 130. In some embodiments, the mold layer 132 may cover the top surface of the nested member 140 and the top surface of the intermediate layer 130.

[0011] In a specific embodiment, the pads 133 of the interposer 130 and the pads 143 of the nested component 140 may be contacted by bumps 137, which are positioned in openings through the solder resist 195 surrounding the pads 133 and 143. In a specific embodiment, the bump 137 may be referred to as a "package side bump" (PSB). The PSB may interface with a package substrate (not shown).

[0012] In a specific embodiment, the electronic package 100 may further include one or more wafers 120 embedded in a mold layer 122. In a specific embodiment, the active surface 121 of the wafer 120 may be electrically coupled to an interposer 130 and a nested member 140. For example, interconnect 181 provides an electrical connection between the wafer 120 and the interposer 130, and interconnect 182 provides an electrical connection between the wafer 120 and the nested member 140. In a specific embodiment, interconnect 181 may have a pitch different from that of interconnect 182. For example, interconnect 182 may have a smaller pitch than interconnect 181. In an exemplary embodiment, the nested member 140 is a bridge providing an electrical connection between two wafers 120.

[0013] Referring now to Figure 1B, a magnified portion 180 of an electronic package 100 according to a specific configuration is shown. Portion 180 more clearly illustrates the architecture of interconnects 181 and 182. As shown, interconnects 181 and 182 are substantially similar to each other, except that the width of interconnect 182 is smaller than the width of interconnect 181. In a specific configuration, the interconnects include an intermediate pad 184. The intermediate pad 184 may be positioned above the top surface of the die layer 132. Bumps 183 (e.g., solder bumps) may be positioned above the intermediate pad 184. Bumps 183 may be electrically coupled to the die pad 123 of the die 120.

[0014] In a specific configuration, the intermediate liner 184 may be electrically coupled to the intermediate liner 136 or the component liner 146 via the through-hole 191. The through-hole 191 may extend through a portion of the mold layer 132. In the exemplary configuration, the through-hole 191 is exemplified as having a substantially vertical sidewall profile. This configuration may be provided when the through-hole opening is defined by lithography. However, it should be understood that the configuration may also include the through-hole 191 having a tapered sidewall profile. This configuration is typically formed when the through-hole opening is formed by a laser drilling process.

[0015] Interconnects 181 and 182 are provided using intermediate pads 184 and vias 191, which improves alignment with wafer 120. In particular, since nested components 140 are placed within cavities 135 of the interposer 130, there may be some degree of misalignment between the interposer pads 136 and component pads 146. However, since vias 191 are likely formed by a single lithography operation, they will align with each other. Similarly, intermediate pads 184 are likely fabricated using a single lithography process to align intermediate pads 184 with each other. In Figure 1B, the interposer 130, nested components 140, and wafer 120 are shown perfectly aligned, and the benefits of the alignment correction capability of interconnects 181 and 182 are not readily apparent.

[0016] Referring now to Figure 1C, a cross-sectional view of portion 180 according to a specific pattern is shown, which more clearly illustrates the benefits of the alignment correction feature. As shown in Figure 1C, the nested member 140 is offset from the center of the cavity 135. Accordingly, the member gasket 146 is misaligned relative to the intermediate gasket 136. However, the through holes 191 are all aligned relative to each other, and the intermediate gaskets 184 are all aligned relative to each other. For example, the centerline of the through hole 191 above the member gasket 146 is not aligned with the centerline of the member gasket 146. The misalignment can be corrected as long as the through hole 191 falls on some surface of the member gasket 146 (and not also on the adjacent member gasket 146). In Figure 1C, the centerline of the through hole 191 above the intermediate gasket 136 is shown to be substantially aligned with the centerline of the intermediate gasket 136. However, it should be understood that the through hole 191 may be displaced relative to the intermediate gasket 136 in some specific patterns.

[0017] Figure 1C shows the misalignment in the X direction. That is, through-hole 191 may provide misalignment correction in the XY plane. However, it should be understood that through-hole 191 may also provide Z height correction. For example, if the thickness of the interposer 130 and the nested member 140 is not uniform, through-holes of different heights can be used to provide a uniform Z height for subsequent connections.

[0018] Referring now to Figure 2A, a cross-sectional view of an electronic package 200 according to an additional specific embodiment is shown. In this embodiment, the electronic package 200 may be substantially similar to the electronic package 100 described above, except that the interconnects 281 and 282 are modified. For example, the electronic package 200 may include an interposer 230 having a cavity 235 and a nested member 240 within the cavity 235. The interposer 230 and the nested member 240 may be embedded in a mold layer 232. The active surface 221 of the die 220 may be connected to the interposer 230 and the nested member 240 via interconnects 281 and 282. The die 220 may be embedded in the mold layer 222. In this embodiment, the interposer 230 may include a via 234 providing connection to a pad 233 and a bump 237; and the nested member 240 may include a via 244 connecting the active surface 241 to the pad 243 and the bump 237. Solder resist 295 may be positioned around pads 233 and 243.

[0019] Referring now to Figure 2B, an enlarged cross-sectional view of region 280 of Figure 2A is shown according to a specific configuration, which more clearly illustrates interconnects 281 and 282. As shown, interconnects 281 and 282 are substantially similar to each other, except that the width of interconnect 282 is smaller than the width of interconnect 281. In this specific configuration, the interconnect includes an intermediate pad 284. The intermediate pad 284 may be positioned above the top surface of the die layer 232. Bumps 283 (e.g., solder bumps) may be positioned above the intermediate pad 284. Bumps 283 may be electrically coupled to the die pad 223 of the die 220.

[0020] In specific configurations, the intermediate gasket 284 may be directly connected to the intermediate gasket 236 or the component gasket 246. Instead of using through holes (as shown in Figures 1A-1C), the intermediate gasket 236 and the component gasket 246 instead have a thickness T extending through the mold layer 232. Accordingly, the intermediate gasket 236 and the component gasket 246 provide the same functionality as the through hole 191 in Figures 1A-1C.

[0021] The use of intermediate pads 284 provides interconnects 281 and 282, which improves the alignment of the wafer 220. In particular, since the nested component 240 is placed within the cavity 235 of the interposer 230, there may be some degree of misalignment between the interposer pads 236 and the component pads 246. However, since the intermediate pads 284 are likely formed from a single lithography operation, they will align with each other. In Figure 2B, the interposer 230, nested component 240, and wafer 220 are shown perfectly aligned, and the benefits of the alignment correction capability of interconnects 281 and 282 are not very clear.

[0022] Referring now to Figure 2C, a cross-sectional view of region 280 according to a specific pattern is shown, which more clearly illustrates the benefits of the alignment correction feature. As shown in Figure 2C, the nested member 240 is offset from the center of the cavity 235. Accordingly, the member pad 246 is misaligned relative to the intermediate pad 236. However, the intermediate pads 284 are aligned relative to each other. For example, the centerline of the intermediate pad 284 above the member pad 246 is not aligned with the centerline of the member pad 246. The misalignment can be corrected as long as the intermediate pad 284 falls on a surface of the member pad 246 (and not also on the adjacent member pad 246). In Figure 2C, the centerline of the intermediate pad 284 above the intermediate pad 236 is shown to be substantially aligned with the centerline of the intermediate pad 236. However, it should be understood that the intermediate pad 284 may be displaced relative to the intermediate pad 236 in some specific patterns.

[0023] Figure 2C shows the misalignment in the X direction. That is, the intermediate pad 284 may provide misalignment correction in the XY plane. However, it should be understood that the thick intermediate pad 236 and component pad 246 may also provide Z height correction. The use of the intermediate pad 236 and component pad 246 to provide Z height correction will be described in more detail below.

[0024] On the other hand, the need for miniaturization of form factors and increased integration layers for high performance is driving complex packaging practices in the semiconductor industry. Die dicing achieves miniaturization and high performance with the yield problems seen in other methods, but requires fine die-to-die interconnects. Embedded multi-die interconnect bridges (EMIBs) represent a breakthrough, enabling lower-cost and simpler 2.5D packaging with extremely high-density interconnects between heterogeneous chips on a single package. Instead of expensive silicon interposers with TSVs (Through Silicon Vias), small silicon bridge chips are embedded in the package, allowing for extremely high-density die-to-die connections only where needed. Standard flip-chip assemblies are used for robust power delivery and to connect high-speed signals directly from the chip to the package substrate.

[0025] For future generations of chip dicing, several bridges are needed to connect chips with bump pitches much finer than those currently provided by EMIB (e.g., 25 micrometers or lower). However, the EMIB approach can suffer from high cumulative bump thickness variation (BTV); and as the number of bridges to be embedded increases, the cost and yield of embedding may worsen. Alternative architectures, such as patching, have been proposed. One patching approach could involve replacing standard bridge chips without TSV connections with EMIB-T (EMIB with TSV connections) or active functional chips. Fine chip-to-chip interconnects can be achieved through this embedded chip for chip placement. Due to assembly considerations of attaching the patch to the substrate (mid-level interconnect, MLI), patching can be simplified to eliminate the need for multiple redistribution layer (RDL) routing or fan-out layers. While mass remelting is not feasible, the significant planarization issues caused by stacked warpage can result in extremely narrow thermal compression bonding (TCB) attachment windows. Using glass to fabricate nested interposer packages can lead to a significant reduction in warpage, but this architecture may not be suitable for often thinner EMIB-T or active chips, and the warpage advantage from nesting diminishes as the interposer thickness decreases. To realize the full potential of the nested interposer architecture, according to one or more specific embodiments disclosed herein, the EMIB-T or active chip is nested while simultaneously maintaining the warpage benefits from having a thick interposer for MLI attachment to the substrate.

[0026] The specific configuration described herein can be implemented to fabricate a nested interposer architecture capable of accommodating thin EMIB-T or active chips for fine-pitch die-to-die (D2D) interconnects. Nesting in this case is achieved using cavities of the desired thickness, within which the EMIB-T or active chips are placed. TSV connections between the embedded chips in the cavities and the substrate can be achieved through metallized vias formed beneath the cavities. Other top-chip connections to the substrate can be operated through vias in non-cavity regions of the interposer.

[0027] To provide further context, several approaches are being investigated to enable wafer placement, but none offer or provide a robust warp mitigation solution for the reliable MLI attachment required to fabricate the final package. The aforementioned nested interposer packaging can provide significant warp reduction and enables mass remelting at the desired fan-out pitch. Mechanical data gathered from simulating the nested glass interposer architecture reveals that the glass thickness required for low warp is likely around 350 micrometers. However, the through-cavity architecture may not be compliant for embedding EMIB-T or active wafers. Incidentally, equipment and process improvements may only result in limited improvements to the patch attachment window, while changes to the material formulation used to reduce patch warp may have undesirable effects or, in some cases, be impossible. While the nested interposer significantly improves warp and enables mass remelting attachment processes, the glass thickness and through-cavity architecture may not be suitable for embedding EMIB-T or active wafers.

[0028] According to one or more specific embodiments disclosed herein, a nested interposer architecture has cavities of desired thickness in which EMIB-T or active chips are placed. TSV connections of the chips embedded in the cavities to the substrate are accomplished via metallized vias formed beneath the cavities. Other top chip connections to the substrate can be operated via vias in non-cavity regions of the interposer. It is possible to implement an appendage with this architecture that not only provides the desired low warpage for robust MLI attachments but also accommodates active or EMIB-T chips.

[0029] To provide further context, modular chip interconnects, or chip dicing, are becoming an increasingly important requirement in the packaging industry because they enable heterogeneous chip integration, miniaturization of form factors, high efficiency, and improved yield. Various approaches to modular chip interconnects have been proposed; however, each approach has its own drawbacks. The specific implementations described herein may offer a low-cost, mature, and high-yield approach to overcome these problems and can be adopted by a wide variety of applications requiring high-density chip-to-chip interconnects.

[0030] The process can be implemented to produce packages in high-volume manufacturing (HVM) glass panel processing lines, for example, to produce nested interposers with EMIB-T or active wafers for fine wafer-to-wafer (D2D) layup. As an exemplary process, the cross-sectional views illustrated in Figures 3A-3K represent various operations of a method for fabricating nested interposers with silicon via bridge wafers according to the specific configuration disclosed herein.

[0031] Referring to Figure 3A, the glass substrate or panel 300 is selected or fabricated to have the desired final interposer thickness. It should be understood that the glass substrate or panel 300 may be a panel layer, a sub-panel layer, a wafer layer, etc. The glass substrate or panel 300 is drilled to provide a patterned glass substrate 300A with an opening 302 therein, as shown in Figure 3B.

[0032] Referring to Figure 3C, the opening 302 of Figure 3B is plated to form a via 334, which may be called a through interposer via (TIV) or through glass via (TGV). The cavity 304 and opening 306 are then drilled into a patterned glass substrate 300A to form a secondary patterned glass substrate 300B. The component 340 is then placed into the cavity 304, as shown in Figure 3D. In one embodiment, the component 340 is an EMIB-T (Silicon Through-Video Bridge Chip) or an active chip. In one embodiment, the component 340 is coupled through the component via 344 to a back die pad 343A and bump 343B covered in a back dielectric 341 (e.g., a die bonding film, DBF). The front side of the component may include a front die pad 308 and a front pillar 309.

[0033] Referring to Figure 3E, dielectric layer 310 is disposed above the exposed surface. In one embodiment, dielectric layer 310 embeds glass substrate 300B and nested member 340. For example, dielectric layer 310 may fill cavity 304, thus partially filling the space between the sidewall of nested member 340 and the sidewall of glass substrate 300B. Although referred to as a "dielectric layer," it should be understood that dielectric layer 310 may be any material suitable for the packaging application or formed by any material deposition process suitable for the packaging application. For example, dielectric layer 310 may be formed by molding, lamination, deposition, or the like. The back dielectric 341 of member 340 is then etched through opening 306 to form opening 311 of bump 343B of the exposed portion, as shown in Figure 3F. In one embodiment, dielectric layer 310 protects front bump 309 during etching to form opening 311.

[0034] Referring to Figure 3G, the dielectric layer 310 is then thinned to form a thinned dielectric layer 310A, which exposes the top of the front bump 309 of the member 340. An opening 312 is then formed in the thinned dielectric layer 310A to expose the via 334, as shown in Figure 3H.

[0035] Referring to Figure 3I, plating and / or semi-additive processing are then performed to form intermediate pads 336, component pads 346, and traces 347 on the front side. Semi-additive processing can also be performed to form a core via 314 under the component 340, and back intermediate pads 333A and 333B on the back side. The back intermediate pad 333B is coupled to the core via 314. Then, a two-sided solder resist lamination is performed to form a front solder resist layer 316A and a back solder resist layer 316B, as shown in Figure 3J.

[0036] Referring again to Figure 3J, the interposer 389 includes a front solder resist layer 316A, which covers the interposer pad 336 and the component pad 346. Vias 391A and 391B are formed in the front solder resist layer 316A and coupled to the interposer pad 336 and the component pad 346, respectively. An intermediate pad 384 is then formed on the front solder resist layer 316A and coupled to the vias 391A and 391B. A bump 383 is formed on the intermediate pad 384. A die pad 323 is formed on the intermediate pad 384. The interposer 389 also includes a back solder resist layer 316B, which covers the back pads 333A and 333B. Vias 318A and 318B are formed in the back solder resist layer 316B and coupled to the back pads 333A and 333B, respectively. Intermediate pad 319A is then formed on the back solder resist layer 316B and coupled to vias 318A and 318B. Bump 319B is formed on intermediate pad 319A. Package substrate pad 319C is formed on intermediate pad 319A.

[0037] Referring to Figure 3K, wafers 393A and 393B are coupled to the interposer layer 389 of Figure 3J to form a multi-wafer structure 399. Wafers 393A and 393B may include bumps 395A and 395B for coupling to the wafer pads 323 of the interposer layer 389. Bump 395A is above and may be coupled to the via interposer substrate, while bump 395B is above and may be coupled to component 340. The multi-wafer structure 399 may also include an underfill 394 and / or a die-on-wafer mold 397, as shown.

[0038] Based on the specific configuration disclosed herein, referring again to Figures 3A-3K, for simplicity, the formation of a single interposer layer is shown. However, multiple interposers may be formed on the panel. The process can begin with panel-layer glass of desired thickness and coefficient of thermal expansion (CTE, e.g., a low CTE of approximately 3.4 or less). First, core vias (e.g., vias that directly connect top wafers to the substrate) are created using a crack-free laser-based drilling process. The drill pitch and diameter can be selected depending on the desired application. Seed layers are formed on the surface and sidewalls of the drilled holes using sputtering or electroless plating. The glass vias (TGVs) are subsequently filled with copper using an electroplating process. Polishing is then performed to remove excess copper from the glass surface, making the vias flush with the glass surface. Cavities of desired thickness are then drilled, which will eventually house the EMIB-T or active wafer, followed by drilling vias to connect the embedded wafers to the substrate. The EMIB-T or active wafer is then placed in the cavity and encapsulated on top with a dielectric material. The dielectric material can be a conventional cumulative dielectric material, such as Ajinomoto cumulative film (ABF). A plasma etching process can then be used to remove portions of the wafer bonding film and expose the TSV pads on the back side of the wafer. The front side is then polished / ground to expose the embedded wafer pillars. Core vias are then drilled, and a semi-additive process (SAP) is used to fill and form pads and traces on the front side. The resulting layer can serve as a reset or routing layer for High Bandwidth Memory (HBM) / Fully Integrated Voltage Regulator (FIVR) integration. Subsequently, the back vias connecting the embedded wafer TSV pads are metallized, followed by pad formation. Solder resist layers are then laminated onto the front and back sides. First-level interconnect (FLI) bumps are then formed using a standard process, and core vias are opened using photolithography. Vias for fine wafer-to-wafer connections are formed using ultraviolet (UV) laser followed by a photolithography-based plating process (e.g., tin plating). Alternatively, a photolithography via process can be used to generate FLI bumps. MLI formation is also performed. Solder resist openings are created by exposure and development to generate via openings. Copper fill plating can then be performed followed by photolithography-based Sn bump formation. A microsphere bumping process can also be performed to generate MLI bumps. In the case of multiple interposers, the interposers can then be isolated into cells and sent for top die attachment assembly, which is often performed at the cell level. In a specific configuration, the glass in the interposers provides excellent coplanarity and tight alignment accuracy to ensure fine die-to-die (D2D) bonding. Top die assembly can be performed using thermocompression bonding (TCB) to attach the top die to the nested interposers. Underfill formation, upper die formation, and subsequent grinding to expose the back side of the wafer can then be performed, followed by metallization of the back side of the wafer.

[0039] It should be understood that this describes a glass-based nesting; however, any material can be used (e.g., silicon, ceramics, etc., which provide rigidity). The cavity houses the active chip or EMIB with TSV connections, and metallized vias in the interposer connect these TSV connections to the substrate. The presence of this cavity will be uniquely visible in the final product. This connection can be used to power the embedded chip or for any other desired functionality. Specific configurations can be implemented to achieve finer D2D placement and robust MLI attachment of the chip in various interconnect architectures. This can be achieved using a nested interposer architecture that can accommodate thin EMIB-Ts or active chips for fine bump pitch D2D interconnects. Specific configurations can be implemented by nesting EMIB-Ts or active chips in cavities of desired thickness. The TSV connections of the embedded chip in the cavity to the substrate can be achieved through metallized vias fabricated under / below the cavity. This connection can be used to power the embedded chip or for any other desired functionality. Additional top-chip connections to the substrate can be operated via vias in non-cavity regions of the interposer. In one specific configuration, nested interposers provide low warpage, and MLI attachment to the substrate can be accomplished using a relatively inexpensive mass remelting process. It should be understood that this type of heterogeneous chip integration or chip placement / stitching can be implemented to extend Moore's Law.

[0040] On the other hand, referring now to FIG4A, a plan view of an electronic package 400 according to an exemplary embodiment is shown. In this embodiment, the electronic package 400 includes an interposer 430 having a plurality of cavities 435A~E. In this embodiment, a plurality of nested members 440 are positioned within the cavities 435. It should be understood that for ease of demonstration, the cavities 435 are shown as extending entirely through the interposer 430; however, in at least some embodiments, the cavities 435 extend only partially through, rather than entirely through, the interposer 430. In some embodiments, at least one cavity 435 includes a plurality of nested members 440. For example, two nested members 440 are positioned within cavity 435B. In this embodiment, the cavity 435 may be entirely within the coverage area of ​​a wafer 420 (indicated by the dashed line), within the coverage area of ​​more than one wafer 420, and / or partially within the coverage area of ​​a single wafer 420. For example, cavities 435 A and 435 B are entirely within the coverage area of ​​wafer 420 A, cavity 435 C is within the coverage area of ​​wafers 420 A and 420 B, cavity 435 E is within the coverage area of ​​wafers 420 A and 420 C, and cavity 435 D is partially within the coverage area of ​​wafer 420 B.

[0041] Referring now to Figure 4B, a cross-sectional schematic diagram along line B-B' is shown of the electronic package 400 of Figure 4A according to a specific configuration. In the illustrated configuration, the shown interposer 430 has nested members 440 within cavities 435 A, 435 C, and 435 D. The interposer 430 and the nested members 440 may be electrically coupled to wafers 420 A and 420 B via interconnects including an intermediate pad 484. The intermediate pad 484 is schematically shown for simplicity between wafers 420 A and 420 B and the interposer 430 and the nested members 440. However, it should be understood that the intermediate pad 484 may substantially be a portion of the interconnects 181 and 182 described above with respect to Figures 1A-1C or the interconnects 281 and 282 described above with respect to Figures 2A-2C. In the configuration, the bottom surfaces of the interposer 430 and the nested members 440 may be electrically coupled to package-side bumps 437.

[0042] Referring now to Figure 4C, a cross-sectional schematic diagram along line C-C' of the electronic package 400 of Figure 4A is shown according to a specific configuration. In the illustrated configuration, the shown interposer 430 has nested members 440 within cavities 435B and 435E. The interposer 430 and the nested members 440 may be electrically coupled to wafers 420A and 420B via interconnects including an intermediate pad 484. The intermediate pad 484 is schematically shown for simplicity between wafers 420A and 420B and the interposer 430 and the nested members 440. However, it should be understood that the intermediate pad 484 may substantially be a portion of the interconnects 181 and 182 described above with respect to Figures 1A-1C or the interconnects 281 and 282 described above with respect to Figures 2A-2C. In the configuration, the bottom surfaces of the interposer 430 and the nested members 440 may be electrically coupled to package-side bumps 437.

[0043] On the other hand, referring now to FIG5, a plan view of an electronic package 500 according to an exemplary embodiment is shown. In this embodiment, the electronic package 500 may include a plurality of interposers 530 A to D. Each interposer 530 may have any shape. For example, the interposers 530 are exemplified as straight lines. The interposers 530 may be configured such that the sidewalls of the interposers 530 define cavities 535. In this embodiment, one or more nested members 540 may be positioned within the cavities 535. In this embodiment, one or more wafers 520 (indicated by dashed lines) may be disposed above the interposers 530 and the nested members 540. Each wafer 520 may extend above one or more interposers 530.

[0044] In any given scenario, each intermediary layer 530 may be substantially similar to one another. For example, each intermediary layer 530 may be either a passive intermediary layer 530 or an active intermediary layer 530. In other scenarios, intermediary layers 530 may not all be the same. For example, one or more intermediary layers 530 may be active intermediary layers 530, and one or more intermediary layers 530 may be passive intermediary layers.

[0045] In a specific embodiment, a nested interposer is attached to the substrate (MLI attachment). The nested interposer, having an EMIB-T / active wafer assembled with a top wafer composite, is then attached to the substrate. The nested interposer provides low warpage, and the attachment can be accomplished using an inexpensive mass remelting process. The resulting assembly can be attached to a board. For example, the cross-sectional view illustrated in Figure 6 represents the formation of an electronic system according to a specific embodiment of this disclosure, which includes a nested interposer with silicon via bridge wafers.

[0046] Referring to Figure 6, the electronic assembly 600 is fabricated, for example, by using solder balls 604 on bumps or pads 615 of the package substrate 602 to couple the assembly 399 (e.g., as described above with respect to Figure 3K) to the package substrate 602. The package substrate 602 is coupled to, for example, a board 606 of a printed circuit board (PCB) by using solder balls 608 on bumps or pads 617 of the package substrate 602. In one specific embodiment, the package substrate 602 includes a chip side 614, a board side 616, and a core or direct routing layer 612. In some specific embodiments, the assembly 399 is directly coupled to the board 606. That is, the package substrate 602 may be selectively omitted.

[0047] Figure 7 illustrates a computing device 700 according to one embodiment of the present disclosure. The computing device 700 houses a board 702. The board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some embodiments, at least one communication chip 706 is also physically and electrically coupled to the board 702. In a further embodiment, the communication chip 706 is part of the processor 704.

[0048] These other components include, but are not limited to, volatile memory such as random access memory (DRAM), non-volatile memory such as read-only memory (ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, mass storage device (e.g., hard disk drive, compact disk, digital versatile disk, DVD, etc.).

[0049] The communication chip 706 is capable of wireless communication to transfer data between the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which may communicate data using modulated electromagnetic radiation through non-physical media. This term does not imply that the associated device is free of any wires, although in some specific cases they may be. The communication chip 706 may implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols indicating 3G, 4G, 5G, and beyond. The computing device 700 may include multiple communication chips 706. For example, the first communication chip 706 may be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth; and the second communication chip 706 may be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0050] The processor 704 of the computing device 700 includes an integrated circuit chip packaged within the processor 704. In some embodiments of this disclosure, the integrated circuit chip of the processor may be packaged in an electronic system, which, depending on the specific configuration described herein, includes a multi-chip package having an interposer and nested components coupled to one or more chips via interconnects. The term "processor" may refer to any device or part of a device that processes electronic data from a register and / or memory to convert the electronic data into other electronic data that may be stored in the register and / or memory.

[0051] The communication chip 706 also includes an integrated circuit chip packaged within the communication chip 706. According to another embodiment of this disclosure, the integrated circuit chip of the communication chip 706 may be packaged in an electronic system 700, which, depending on the specific configuration described herein, includes a multi-chip package having an interposer and nested components coupled to one or more chips via interconnects.

[0052] The above description of the embodiments illustrated in this disclosure (including those described in the abstract) is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Although specific embodiments and examples of this disclosure are described herein for illustrative purposes, various equivalent modifications may be made within the scope of this disclosure, as will be recognized by those skilled in the art.

[0053] In light of the foregoing details, these modifications may be made to this disclosure. The terminology used in the following claims should not be construed as limiting this disclosure to the specific embodiments disclosed in the specification and claims. Rather, the scope of this disclosure is to be determined entirely by the following claims, which are to be interpreted in accordance with established doctrines of claim interpretation.

[0054] Exemplary Specific Example 1: An electronic package includes an interposer having an interposer substrate, a cavity extending into but not through the interposer substrate, a via-channel via (TIV) in the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component within the cavity, wherein the nested component includes a component pad coupled to the component via. A core via is located beneath the nested component and extends from the nested component through the interposer substrate. A die is coupled to the interposer pad via a first interconnect and to the component pad via a second interconnect.

[0055] Exemplary Specific State 2: Electronic package of Exemplary Specific State 1, wherein the first interconnect and the second interconnect each include an intermediate pad and a bump above the intermediate pad.

[0056] Exemplary Specific Form 3: An electronic package of Exemplary Specific Form 1 or 2, which further includes a dielectric layer above and around the interposer and nested components.

[0057] Exemplary Specific State 4: Electronic package of Exemplary Specific State 3, wherein the intermediate pad is above the surface of the dielectric layer.

[0058] Exemplary Specific State 5: An electronic package of Exemplary Specific State 4, wherein an intermediate pad for a first interconnect is coupled to an intermediate pad via a first via through a portion of the dielectric layer, and wherein an intermediate pad for a second interconnect is coupled to a component pad via a second via through a portion of the dielectric layer.

[0059] Exemplary Specific Form 6: Electronic package of Exemplary Specific Form 4, wherein the intermediate pad of the first interconnect is directly connected to the intermediate pad, and wherein the intermediate pad of the second interconnect is directly connected to the component pad.

[0060] Exemplary Specific Form 7: An electronic package of Exemplary Specific Forms 1, 2, 3, 4, 5 or 6, wherein the center line of the first interconnect is offset from the center line of the intermediate pad, and wherein the center line of the second interconnect is offset from the center line of the component pad.

[0061] Exemplary Specific State 8: Electronic package of Exemplary Specific State 1, 2, 3, 4, 5, 6 or 7, wherein the first part of the cavity is within the coverage area of ​​the wafer, and wherein the second part of the cavity is outside the coverage area of ​​the wafer.

[0062] Exemplary Specific State 9: Electronic package of Exemplary Specific State 1, 2, 3, 4, 5, 6, 7 or 8, wherein the nested component is the active component.

[0063] Exemplary Specific 10: An electronic package of Exemplary Specific 1, 2, 3, 4, 5, 6, 7, 8 or 9, further comprising a second chip, wherein the second chip is coupled to a nested component by a third interconnect comprising an intermediate pad and a bump above the intermediate pad.

[0064] Exemplary Specific State 11: Electronic package of Exemplary Specific State 10, wherein nested components electrically couple a first wafer to a second wafer.

[0065] Exemplary Specific State 12: Electronic package of Exemplary Specific State 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein the active surface of the nested component faces the wafer.

[0066] Exemplary Specific State 13: Electronic package of Exemplary Specific State 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the intermediate substrate includes glass, ceramic, silicon, silicon carbide, alumina or organic material.

[0067] Exemplary Specific Example 14: An electronic system comprising a board and an interposer electrically coupled to the board. The interposer includes: a cavity extending into but not through the interposer substrate; a nested member within the cavity; an intermediate via (TIV) in the interposer substrate; and a core via beneath the nested member, the core via extending from the nested member through the interposer substrate. A first wafer is electrically coupled to the interposer and the nested member via a plurality of first interconnects. A second wafer is electrically coupled to the interposer and the nested member via a plurality of second interconnects.

[0068] Exemplary Specific State 15: An electronic system of Exemplary Specific State 14, wherein nested components electrically couple a first wafer to a second wafer.

[0069] Exemplary Specific Example 16: An electronic system of Exemplary Specific Example 14 or 15, further comprising a packaging substrate, wherein the packaging substrate is electrically coupled to a board, and wherein an interlayer is electrically coupled to the packaging substrate.

[0070] Exemplary Specific Example 17: An electronic package includes an interposer having a glass substrate, a cavity extending into but not through the glass substrate, a through-glass via (TGV) in the glass substrate, and an interposer pad electrically coupled to the TGV. The electronic package includes a silicon bridge wafer in the cavity, wherein the silicon bridge wafer includes a silicon bridge wafer pad coupled to the silicon TGV. A core via is located beneath the silicon bridge wafer and extends from the silicon bridge wafer through the glass substrate. The wafer is coupled to the interposer pad via a first interconnect and to the silicon bridge wafer pad via a second interconnect.

[0071] Exemplary Specific Pattern 18: An electronic package of Exemplary Specific Pattern 17, wherein the first interconnect and the second interconnect each include an intermediate pad and a bump above the intermediate pad.

[0072] Exemplary Specific Pattern 19: An electronic package of Exemplary Specific Pattern 18 or 19, which further includes a dielectric layer above and around the interposer and silicon bridge wafer.

[0073] Exemplary Specific State 20: Electronic package of Exemplary Specific State 19, wherein the intermediate pad is above the surface of the dielectric layer.

[0074] Exemplary Specific Pattern 21: An electronic package of Exemplary Specific Pattern 20, wherein an intermediate pad for a first interconnect is coupled to an intermediate pad via a first via through a portion of the dielectric layer, and wherein an intermediate pad for a second interconnect is coupled to a silicon bridge wafer pad via a second via through a portion of the dielectric layer.

[0075] Exemplary Specific Example 22: An electronic package of Exemplary Specific Example 20, wherein the intermediate pad of the first interconnect is directly connected to the intermediate pad, and wherein the intermediate pad of the second interconnect is directly connected to the silicon bridge wafer pad.

[0076] Exemplary Specific Form 23: Electronic package of Exemplary Specific Forms 17, 18, 19, 20, 21 or 22, wherein the center line of the first interconnect is offset from the center line of the intermediate pad, and wherein the center line of the second interconnect is offset from the center line of the silicon bridge wafer pad.

[0077] Exemplary Specific Form 24: Electronic package of Exemplary Specific Forms 17, 18, 19, 20, 21, 22 or 23, wherein the first part of the cavity is within the coverage area of ​​the wafer, and wherein the second part of the cavity is outside the coverage area of ​​the wafer.

[0078] Exemplary Specific 25: An electronic package of Exemplary Specific 17, 18, 19, 20, 21, 22, 23 or 24, further comprising a second chip, wherein the second chip is coupled to a silicon bridge chip via a third interconnect comprising an intermediate pad and a bump above the intermediate pad. Simple Explanation of the Diagram

[0079] [Figure 1A] is a cross-sectional view of an electronic package based on a specific configuration, which includes a heterogeneous nested interposer layer.

[0080] [Figure 1B] is an enlarged version of Figure 1A based on a specific configuration, which more clearly illustrates the interconnection between the chip and the interposer, as well as between the chip and the nested components.

[0081] [Figure 1C] is an enlarged version of Figure 1A based on a specific pattern, demonstrating the alignment correction provided by the interconnection of the intermediate layer and nested components.

[0082] [Figure 2A] is a cross-sectional view of an electronic package based on a specific configuration, which includes a heterogeneous nested interposer layer.

[0083] [Figure 2B] is a magnified portion of Figure 2A based on a specific configuration, which more clearly illustrates the interconnection between the chip and the interposer, as well as between the chip and the nested components.

[0084] [Figure 2C] is an enlarged version of Figure 2A based on a specific pattern, demonstrating the alignment correction provided by the interconnection of the intermediate layer and nested components.

[0085] [Figures 3A-3K] illustrate cross-sectional views of the specific configuration disclosed herein, representing various operations in a method for fabricating a nested interposer layer with silicon via bridge wafers.

[0086] [Figure 4A] is a plan view of an electronic package based on a specific configuration, which has a heterogeneous nested interposer layer.

[0087] [Figure 4B] is a cross-sectional view of the electronic package along line B-B' based on the specific state of Figure 4A.

[0088] [Figure 4C] is a cross-sectional view of the electronic package along line C-C' based on the specific state of Figure 4A.

[0089] [Figure 5] is a plan view of an electronic package based on a specific configuration, which has a heterogeneous nested interposer layer comprising a plurality of interposer substrates.

[0090] [Figure 6] A cross-sectional view illustrating the specific form disclosed herein, representing the formation of an electronic system including a nested interposer layer with silicon via bridge wafers.

[0091] [Figure 7] is a schematic diagram of the computing device constructed according to the specific state. Implementation

[0092] and

[0093] 100: Electronic Packaging 120: Chip 121: Active Surface 122: Mold layer 123: Chip Pad 130: Intermediary layer 132: Mold layer 133: Padding 134: Through hole 135: Cavity 136: Intermediate Pad 137: Bump 140: Nested Components 141: Active Surface 143: Padding 144: Through-hole (TCV) for components 146: Component gasket 180: Amplification section 181: Interconnection 182: Interconnection 183: Bump 184: Intermediate padding 191: Through hole 195: Solder resist 200: Electronic Packaging 220: Chip 221: Active Surface 222: Mold layer 223: Chip Pad 230: Intermediary Layer 232: Mold layer 233: Padding 234: Through hole 235: Cavity 236: Intermediate Pad 237: Bump 240: Nested Components 241: Active Surface 243: Padding 244: Through hole 246: Component gasket 280: Amplification Part 281: Interconnection 282: Interconnection 283: Bump 284: Intermediate Pad 295: Solder resist 300, 300A, 300B: Glass substrate or panel 302: Opening 304: Cavity 306: Opening 308: Front-side chip pad 309: Front Pier 310, 310A: Dielectric layer 311: Opening 312: Opening 314: Core Through Hole 316A: Front solder resist layer 316B: Backside solder resist layer 318A, 318B: Through holes 319A: Intermediate pad 319B: Bump 319C: Packaging substrate pad 323: Chip Pad 333A, 333B: Backing intermediary pads 334: Through hole 336: Intermediate Pad 340: Nested Components 341: Backside Dielectric 343A: Backside chip pad 343B: Bump 344: Through hole in component 346: Component gasket 347: Traces 383: Bump 384: Intermediate Pad 389: Intermediary Layer 391A, 391B: Through holes 393A, 393B: Chips 394: Bottom Filling 395A, 395B: Bumps 397: Wafer die 399: Multi-chip structure 400: Electronic Packaging 420A, 420B, 420C: Chips 430: Intermediary Layer 435A~435E: Cavities 437: Package side bump 440: Nested Components 484: Intermediate Pad 500: Electronic Packaging 520: Chip 530A~530D: Intermediate Layer 535: Cavity 540: Nested Components 600: Electronic Assembly 602: Packaging substrate 604: Soft solder balls 606: Panel 608: Soft solder ball 612: Core or Direct Routing Layer 614: Chip side 615: Bumps or pads 616: Panel side 617: Bumps or pads 700: Computing device 702: Plate Parts 704: Processor 706: Communication Chip T: Thickness

Claims

1. An electronic package comprising: an interposer layer, wherein the interposer layer includes: an interposer substrate; a cavity that extends into but does not penetrate the interposer substrate; a through-interposer via (TIV) in the interposer substrate; and an interposer pad electrically coupled to the TIV; a nested member in the cavity, wherein the nested member includes a member pad coupled to the member through-interposer via; a core via beneath the nested member, wherein the core via is pre-formed in the interposer substrate prior to forming the cavity and embedding the nested member, the top end of the core via being below the bottom surface of the cavity and located within the vertical projection area of ​​the nested member on the interposer substrate, and being vertically aligned with the member pad and forming direct electrical coupling; and a chip coupled to the interposer pad via a first interconnect and coupled to the member pad via a second interconnect.

2. The electronic package of claim 1, wherein the first interconnect and the second interconnect each include: an intermediate pad; and a bump above the intermediate pad.

3. The electronic package of claim 2 further comprises: a dielectric layer above and around the interlayer and the nested member.

4. The electronic package of claim 3, wherein the intermediate pad is above the surface of the dielectric layer.

5. The electronic package of claim 4, wherein the intermediate pad of the first interconnect is coupled to the intermediate pad via a first via through a portion of the dielectric layer, and wherein the intermediate pad of the second interconnect is coupled to the component pad via a second via through a portion of the dielectric layer.

6. The electronic package of claim 4, wherein the intermediate pad of the first interconnect is directly connected to the intermediate pad, and wherein the intermediate pad of the second interconnect is directly connected to the component pad.

7. The electronic package of claim 1 or 2, wherein the center line of the first interconnect is offset from the center line of the intermediate pad, and wherein the center line of the second interconnect is offset from the center line of the component pad.

8. The electronic package of claim 1 or 2, wherein a first portion of the cavity is within the coverage area of ​​the wafer, and wherein a second portion of the cavity is outside the coverage area of ​​the wafer.

9. An electronic package as requested in item 1 or 2, wherein the nested component is an active component.

10. The electronic package of claim 1 or 2 further comprises: a second wafer, wherein the second wafer is coupled to the nested member by a third interconnect, the third interconnect comprising: an intermediate pad; and a bump above the intermediate pad.

11. The electronic package of claim 10, wherein the nested component electrically couples the wafer to the second wafer.

12. An electronic package as claimed in claim 1 or 2, wherein the active surface of the nested component faces the wafer.

13. The electronic package of claim 1 or 2, wherein the intermediate substrate comprises glass, ceramic, silicon, silicon carbide, alumina or organic material.

14. An electronic system comprising: a board; an interposer electrically coupled to the board, wherein the interposer includes a cavity extending into but not through the interposer substrate, a nested member within the cavity, a via-via (TIV) in the interposer substrate, and a core via extending from the nested member through the interposer substrate; a first wafer electrically coupled to the interposer and the nested member via a plurality of first interconnects; and a second wafer electrically coupled to the interposer and the nested member via a plurality of second interconnects, wherein... The core via is pre-formed in the intermediate substrate before the cavity is formed and the nested component is embedded. The top of the core via is located below the bottom surface of the cavity and within the vertical projection area of ​​the nested component on the intermediate substrate. It is aligned vertically with the component pad of the nested component and forms direct electrical coupling.

15. The electronic system of claim 14, wherein the nested component electrically couples the first wafer to the second wafer.

16. The electronic system of claim 14 or 15, further comprising: a package substrate, wherein the package substrate is electrically coupled to the board, and wherein the interlayer is electrically coupled to the package substrate.

17. An electronic package comprising: an interposer, wherein the interposer includes: a glass substrate; a cavity that extends into but does not penetrate the glass substrate; a through-glass via (TGV) in the glass substrate; and an interposer pad electrically coupled to the TGV; a silicon bridge wafer in the cavity, wherein the silicon bridge wafer includes a silicon bridge wafer pad coupled to the silicon via; a core via beneath the silicon bridge wafer, wherein the core via is pre-formed in the glass substrate before forming the cavity and embedding the silicon bridge wafer, the top end of the core via being located below the bottom surface of the cavity and within the vertical projection area of ​​the silicon bridge wafer on the glass substrate, and being vertically aligned with the silicon bridge wafer pad and forming direct electrical coupling; and a wafer coupled to the interposer pad via a first interconnect and coupled to the silicon bridge wafer pad via a second interconnect.

18. The electronic package of claim 17, wherein the first interconnect and the second interconnect each include: an intermediate pad; and a bump above the intermediate pad.

19. The electronic package of claim 18 further comprises: a dielectric layer above and around the interposer and the silicon bridge wafer.

20. The electronic package of claim 19, wherein the intermediate pad is above the surface of the dielectric layer.

21. The electronic package of claim 20, wherein the intermediate pad of the first interconnect is coupled to the intermediate pad via a first via through a portion of the dielectric layer, and wherein the intermediate pad of the second interconnect is coupled to the silicon bridge wafer pad via a second via through a portion of the dielectric layer.

22. The electronic package of claim 20, wherein the intermediate pad of the first interconnect is directly connected to the intermediate pad, and wherein the intermediate pad of the second interconnect is directly connected to the silicon bridge wafer pad.

23. The electronic package of claim 17 or 18, wherein the center line of the first interconnect is offset from the center line of the intermediate pad, and wherein the center line of the second interconnect is offset from the center line of the silicon bridge wafer pad.

24. The electronic package of claim 17 or 18, wherein a first portion of the cavity is within the coverage area of ​​the wafer, and wherein a second portion of the cavity is outside the coverage area of ​​the wafer.

25. The electronic package of claim 17 or 18 further comprises: a second wafer, wherein the second wafer is coupled to the silicon bridge wafer via a third interconnect, the third interconnect comprising: an intermediate pad; and a bump above the intermediate pad.

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