Setup method for adjusting the temperature conditions of an epitaxy process

Abstract

This invention relates to a method for setting up an epitaxial process to form a useful layer on a acceptor substrate, the useful layer and the acceptor substrate comprising silicon, the setting up method being performed prior to processing the acceptor substrate, the method comprising: a) selecting a type of test substrate from a silicon-based wafer, wherein: - the thickness of the test substrate is 20% to 40% smaller than a conventional thickness for a given substrate diameter, and / or - the test substrate has an interstitial oxygen concentration of less than 10 ppma ASTM'79, and / or - the test substrate comprises an SOI stack comprising a dielectric layer and a single-crystal silicon thin film with a thickness of less than or equal to 300 nanometers; b) establishing initial temperature conditions defining temperatures to be applied to at least two regions of the test substrate to be processed; c) performing an epitaxial process at the initial temperature conditions to form the useful layer on the selected type of test substrate; subsequently measuring slip line defects; d) a) Change the temperature of at least two regions of the substrate to establish new temperature conditions; e) Perform an epitaxial process under the new temperature conditions to form the useful layer on one of the selected types of new test substrates; then measure slip line defects; f) Compare the number of slip line defects measured on the test substrate and select the temperature conditions that produce the fewest slip line defects.

Description

Technical Field

[0001] This invention relates to a method for adjusting temperature conditions to minimize thermal stress before processing the substrate. This initial setting ensures the quality of the substrate at the end of the epitaxial process and guarantees optimal use of the associated epitaxial equipment. Prior Technology

[0002] Epitaxial growth methods, including the growth of silicon layers, are commonly used in the fields of semiconductor materials and microelectronics. The associated equipment typically employs an epitaxial chamber where the atmosphere (the properties of the gases and pressures) and temperature are controlled, and the substrate to be processed is supported by a support structure within the chamber.

[0003] As the diameter of the substrate increases (200mm, 300mm, even 450mm), and with the densification of each substrate component, defects generated during the fabrication process (especially epitaxy) must be controlled and limited as carefully as possible. Defects such as slip lines are particularly important because they affect large areas of the substrate; these are typically defects generated during high-temperature heat treatment, a process involved in epitaxial growth.

[0004] Establishing a process window (especially temperature-related) for a given epitaxial process is common. Epitaxial processes typically consist of forming a useful layer on a acceptor substrate. Defining the characteristics (composition, thickness, crystal structure, and quality) of the acceptor substrate and the useful layer to be formed allows for obtaining a given structure at the end of the epitaxial process. As shown in Figure 1, treating an acceptor substrate within the process window allows for a satisfactory final structure in terms of the dimensional characteristics and overall quality (number of defects not exceeding specified limits) of the useful layer.

[0005] The process tolerances are typically checked periodically by handling test substrates between batches of several recipient substrates.

[0006] Sometimes, the process window is not precisely defined enough to ensure consistent behavior across all acceptor substrates. In fact, because the physical properties of acceptor substrates can vary between the same batch or consecutive batches, it is not uncommon to observe quality fluctuations between final structures even when epitaxial processes are performed in a similar manner within the process window. These quality fluctuations can lead to uncontrolled slip lines on certain structures. Besides yield losses, these fluctuations can also interrupt the use of the epitaxial equipment for readjustment, thus reducing uptime. Summary of the Invention

[0007] This invention proposes a solution to overcome the aforementioned problems. The invention relates to a method for setting up an epitaxial process aimed at forming a useful layer on a acceptor substrate in an epitaxial apparatus; the setting method is performed before processing the acceptor substrate to adjust the temperature conditions of the epitaxial process to minimize thermal stress on the substrate to be processed. This setting method ensures a high degree of repeatability of the acceptor substrate behavior after the epitaxial process is performed, particularly with the absence (or minimal presence) of slip line defects in the final structure.

[0008] This invention proposes a method for setting up an epitaxial process, the process of which aims to form a useful layer on a acceptor substrate in an epitaxial device, the useful layer and the acceptor substrate comprising silicon, the setting method being performed before processing the acceptor substrate, the method comprising: a) Select one type of test substrate from silicon-based wafers, wherein: For substrates with diameters of 200 mm and 300 mm, the conventional thicknesses are 725 micrometers and 775 micrometers, respectively. However, the thickness of the tested substrate at a given diameter is between 20% and 40% smaller than the conventional thickness, and / or The test substrate has an interstitial oxygen concentration of less than 10 ppma according to ASTM '79, and / or The test substrate includes an SOI stack containing a dielectric layer and a single-crystal silicon thin film with a thickness of less than or equal to 300 nanometers. b) Establish initial temperature conditions that define the temperatures to be applied to at least two regions of the substrate to be treated in the epitaxial equipment; c) An epitaxial process is performed under these initial temperature conditions to form the useful layer on the selected type of test substrate to obtain an initial test structure; then, slip line defects on the initial test structure are measured. d) Change the temperature of at least two areas to be applied to the substrate to establish new temperature conditions relative to the initial temperature conditions; e) Perform an epitaxial process under the new temperature conditions to form the useful layer on one of the selected types of new test substrates to obtain a new test structure; then measure the slip line defects on the new test structure; f) Compare the number of slip line defects measured on the test structure and select the epitaxial process temperature conditions that produce the fewest slip line defects.

[0009] Other advantages and non-limiting features of the present invention are as follows, which may be implemented individually or in any technically feasible combination: For other new temperature conditions, steps d) and e) may be repeated once or more before step f). The epitaxial device includes a plurality of epitaxial chambers, wherein: Steps b) and d) are performed in parallel rather than sequentially; each step is performed in a different epitaxial chamber. Steps c) and e) are performed in parallel, and the initial test substrate and the new test substrate are placed in the different epitaxial chambers; For other new temperature conditions, after step f), repeat steps d) and e) once or more; then repeat step f). Repeat steps d) and e) 2 to 5 times; The measurement of slip line defects is performed using an optical surface scanning tool; The target for the number of slip line defects corresponds to a cumulative slip line length of less than 20 mm, preferably less than 5 mm; These temperature conditions define the temperatures to be applied to the central and peripheral regions of the substrate to be processed in the epitaxial equipment; These temperature conditions define the temperature shift between the central region and the three peripheral regions of the substrate to be treated in the epitaxial equipment; The temperature variation between the initial temperature condition and the new temperature condition applied to at least two areas of the substrate ranges from -30°C to +30°C. The epitaxial process involves temperatures between 600°C and 1200°C, an atmosphere of at least one gas selected from TCS, DCS, SiH4, SiCl4, Si2H4, Si3H8, and GeH4, and a pressure between ultra-high vacuum and atmospheric pressure. The useful layer formed during the epitaxial process is made of silicon and has a thickness between 0.3 micrometers and 30 micrometers. The useful layer formed during the epitaxial process is made of silicon and germanium and has a thickness between 50 nanometers and 1000 nanometers.

[0010] The present invention also relates to an epitaxial process for performing an epitaxial process aimed at forming a useful layer on a acceptor substrate in an epitaxial apparatus, the useful layer and the substrate comprising silicon; the aforementioned setting method is performed before processing the acceptor substrate, and the acceptor substrate is an SOI substrate. Simple Explanation of the Diagram

[0011] Other features and advantages of the present invention can be seen with reference to the accompanying drawings, as presented in the following embodiments of the invention, wherein: Figure 1 illustrates the typical process window for epitaxial wafer fabrication, where conditions such as temperature are adjusted based on defects generated on the test wafer. Figure 2 illustrates the distribution of defect severity (slip line defects) of the structure obtained according to step c) of the setting method of the present invention; Figure 3 illustrates the defect distribution of the structure obtained after step e) of the setting method according to the present invention; Figure 4 illustrates a comparison between the conventional process tolerance range and the narrow process tolerance range defined by the method according to the present invention; Figure 5 illustrates an example of a setting method for implementing the present invention; Figure 6 illustrates another example of the setting method for implementing the present invention. Implementation

[0012] The present invention relates to a method for setting up an epitaxial process, the epitaxial process being designed to form a useful layer on a acceptor substrate in an epitaxial device, the useful layer and the acceptor substrate comprising silicon.

[0013] The acceptor substrate is made of or primarily of monocrystalline silicon; in particular, the acceptor substrate may be a silicon-on-insulator (SOI) substrate with a silicon top layer thickness ranging from 0.1 to 2.0 micrometers, an embedded silicon oxide thickness ranging from 0.05 to 5.0 micrometers, and a substrate wafer formed of silicon.

[0014] The acceptor substrate can be in the form of a circular wafer with standard dimensions, such as 200 mm or 300 mm, or even a diameter of 450 mm, as is common in the field of microelectronics. For a given diameter, these substrates have conventional thicknesses: typically, thicknesses of 725 micrometers, 775 micrometers, and 925 micrometers correspond to diameters of 200 mm, 300 mm, and 450 mm, respectively.

[0015] The epitaxially grown useful layer on top of the acceptor substrate can be made of polycrystalline silicon or monocrystalline silicon, with a thickness ranging from 0.3 micrometers to 30 micrometers. It can be p-type or n-type doped, with a concentration ranging from 1E13 / cm3 to approximately 1E19 / cm3.

[0016] As an alternative, the useful layer can be made of silicon-germanium with a thickness ranging from 50 nm to 1000 nm.

[0017] The epitaxial process using the method described in this invention is based on chemical vapor deposition (CVD) technology. It typically involves temperatures ranging from approximately 600°C (silicon-germanium) or 900°C (silicon) to around 1200°C, which falls within the high-temperature range. Depending on the properties of the target useful layer, the process atmosphere may contain at least one gas selected from TCS (trichlorosilane), DCS (dichlorosilane), SiH₄ (silane), SiCl₄ (silicon tetrachloride), Si₂H₄ (disilylenes), Si₃H₈ (propane), and GeH₄ (germanane), and the pressure during the epitaxial process can be selected between ultra-high vacuum and atmospheric pressure.

[0018] This setup is performed before processing the substrate to define precise and advantageous process allowances, that is, to minimize the thermal stress on the substrate during epitaxial growth in the relevant epitaxial equipment. Slip line defects are known to be caused by thermal stresses applied to the substrate during high-temperature heat treatment. Advantageous process allowances are specifically defined to avoid or highly limit the occurrence of such defects.

[0019] The method of setting up the present invention first includes step a) selecting a silicon-based test substrate type, the physical and structural characteristics of which make the test substrate highly sensitive to slip line defects.

[0020] The silicon-based wafers corresponding to the first type of test substrate have a thickness that is 20% to 40% smaller than the conventional thickness of wafers of the same diameter. For example, for a test substrate with a diameter of 200 mm, the thickness is selected to be between 450 and 550 micrometers; for a test substrate with a diameter of 300 mm, the thickness is selected to be between 500 and 600 micrometers. This test substrate can be undoped or heavily doped P-type or N-type. Heavy doping means that the dopant concentration is higher than 1 x 10¹⁸ / cm³.

[0021] Regarding the thickness range of the test substrate selected for the first type, the applicant has identified a process tolerance range particularly suitable for improving the epitaxial process. In fact, due to increased sensitivity to thermal stress, a smaller thickness of the treated substrate can increase the appearance of slip lines. Nevertheless, the thickness is maintained at 60% or greater than the conventional thickness to avoid side effects such as fracture due to thermal stress or mechanical processing.

[0022] According to the second type, the test substrate is a silicon-based wafer with an interstitial oxygen concentration of less than 10 ppma ASTM'79 (i.e., 5E17 Oi / cm 3).

[0023] The low interstitial oxygen content of the substrate used in this test promoted the formation of slip lines during high-temperature treatment, which is due to the reduction of dislocation locking caused by oxygen deposits in silicon.

[0024] The third type of test substrate corresponds to a silicon-based wafer with an SOI stack on its front side, the SOI stack including a buried dielectric layer and a single-crystal silicon thin top layer with a thickness of less than or equal to 300 nanometers. The dielectric layer is typically made of silicon oxide and its thickness can be between 0.5 and 5.0 micrometers.

[0025] The presence of SOI stacks on silicon wafers can increase the mechanical stress on the test substrate, making it more sensitive to slip line defects. The thin top layer of the SOI stack may also be more sensitive to slip lines caused by thermal stress.

[0026] In step a) of the setup method of the present invention, other types of test substrates may be selected, and according to this setup method, such test substrates exhibit any combination of the characteristics of the first, second, and third types. The most precise process tolerance range can be defined by a test substrate having a thin thickness (first type), a low interstitial oxygen content (second type), and comprising an SOI stack with a thickness of less than or equal to 300 nanometers on its front side (third type).

[0027] It should be noted that the characteristics of these test substrates are independent of the characteristics of the acceptor substrate to be treated. The type of test substrate is selected solely for its thermal stress sensitivity and will help to define, as accurately as possible, the epitaxial process temperature conditions that generate the lowest stress on the acceptor substrate, regardless of the nature of these acceptor substrates. According to a preferred embodiment, the test substrate used in this setup method is different from and completely independent of the acceptor substrate to which the epitaxial process is to be applied.

[0028] The setting method then includes step b) establishing initial temperature conditions Ti, which define the temperature of at least two regions of the substrate to be processed in the epitaxial apparatus during the epitaxial process.

[0029] Depending on the epitaxial equipment, the heating elements and their configuration around the substrate can vary. Heating is typically based on a lamp system, which is configured to heat the inner (central) and outer (peripheral) areas of the substrate after treatment, such as the Centura® system from Applied Materials. Alternatively, the lamp system can be configured to offset the temperatures of the three edge zones (referred to as the front, side, and back zones) of the treated substrate relative to the central zone temperature, such as the Epsilon® system from ASM.

[0030] The initial temperature condition Ti can be selected within the available process allowances, or based on the process conditions already used for the previously treated acceptor substrate, or based on the last optimized process conditions. It should be noted that although the last optimized process is one that has been previously adjusted, the minimum stress process conditions may change over time due to tool drift or due to periodic maintenance.

[0031] Referring to Figure 4, these initial temperature conditions Ti can, for example, be selected at the center of the conventional process tolerance range. It should be noted that the conventional process tolerance range is conventionally defined using a standard wafer with conventional thickness and physical properties, or directly using a acceptor substrate. The latter is costly and largely dependent on the characteristics of the acceptor substrate.

[0032] Next, the setup method includes step c), which involves performing an epitaxial process at an initial temperature condition Ti to form a useful layer on a selected type of test substrate. This yields an initial test structure comprising the test substrate and the useful layer epitaxially grown on top of it.

[0033] Next, step c) includes measuring slip line defects on the initial test structure.

[0034] The measurement of slip line defects is performed using an optical surface scanning tool, such as the SP series equipment from KLA Corporation.

[0035] Figure 2 illustrates an example of a measurement distribution map, highlighting slip line defects on the periphery of the test structure. Due to the cumulative length of slip lines across the entire wafer, the number of these defects is assessed first, with edge exclusion of 0.5 to 5 mm ultimately considered. In Figure 2, the test structure has a diameter of 200 mm, and the cumulative slip line length is approximately 5 x 10³ mm.

[0036] When the test structure exhibits numerous slip line defects, as shown in Figure 2, after step c) of the setup method, the expected epitaxial process temperature conditions Ti will not allow the acceptor substrate to maintain stable and repeatable behavior over time, even if some of the final structures (referring to the acceptor substrate on which the useful layer is grown) do not show any slip line defects. Since different types of test substrates are highly sensitive to slip line defects, the setup method of this invention can identify temperature conditions that may cause excessive thermal stress on the treated substrate within the limits of conventional processes; this level of thermal stress can easily damage at least a portion of the acceptor substrate due to variations in physical properties within the same batch of acceptor substrates or between different batches.

[0037] The next step d) of this setting method is to establish a new temperature condition Tn by changing the temperature of at least two areas of the substrate to be treated compared with the initial temperature condition Ti.

[0038] Between the initial temperature condition Ti and the new temperature condition Tn, the temperature change applied to at least two regions of the treated substrate is advantageously within the range of -30°C to +30°C.

[0039] Temperature adjustments between different regions of the substrate after treatment will affect the thermal stress applied to the substrate during epitaxial growth.

[0040] Next, the setup method includes step e), which involves forming a useful layer on a new test substrate of a selected type by performing an epitaxial process under new temperature conditions Tn. Step e) results in a new test structure comprising the new test substrate and the useful layer grown on top of it. Slip line defects are then measured on said structure using the same equipment and process formulation as in step c).

[0041] The measurement distribution of the new test structure is shown in Figure 3: it is clear that the number of slip lines is drastically reduced. The cumulative length of the target slip lines on the test structure is preferably less than 20 mm, or even less than 5 mm.

[0042] Step f) of this setting method involves comparing the number of slip line defects measured on the initial test structure and the new test structure, and selecting the epitaxial process temperature conditions that produce the fewest slip line defects. Ideally, the fewest defects correspond to the target cumulative slip line length mentioned above, with the ultimate goal of zero defects.

[0043] If neither the initial test structure nor the new test structure exhibits the correct degree of defect, the setup method envisions repeating steps d) and e) once or multiple times after step f) for other new temperature conditions Tn', Tn'', Tn''', etc. Then, step f) is repeated to compare the resulting new test structures.

[0044] The setting method of the present invention may also include repeating steps d) and e) once or multiple times for other new temperature conditions Tn', Tn'', Tn''', etc. before implementing step f); and then applying the step of comparing the number of slip line defects to the prepared plurality of test structures.

[0045] When an epitaxial device comprises multiple epitaxial chambers, different temperature conditions can typically be defined independently within these chambers. Therefore, steps b) and d) are performed in parallel, not sequentially, with each step applied to a different epitaxial chamber. For example, if five chambers are available, step b) will be applied to the first chamber, step d) with the first new temperature condition Tn will be applied to the second chamber, step d) with the second new temperature condition Tn' will be applied to the third chamber, and so on. Thus, a total of five temperature conditions (initial and new) will be established across five different chambers.

[0046] Next, steps c) and e) are also performed in parallel, with the initial test substrate and the new test substrate placed in different chambers.

[0047] In step f), the initial test structure treated with the initial temperature condition Ti, and the four new test structures treated with different temperature conditions Tn, Tn', Tn'', and Tn''', can be used to compare the number of slip lines.

[0048] Figure 4 illustrates the narrow process window identified using the method of this invention. This corresponds to the temperature conditions resulting in no or minimal slip line defects when using the highly sensitive test substrate type defined by this invention. These temperature conditions ensure extremely high repeatability and stability of the acceptor substrate's behavior when it is processed according to the epitaxial process described above.

[0049] Before or after step f), the present invention advantageously repeats steps d) and e) 2 to 5 times.

[0050] Next, the epitaxial process based on the temperature conditions selected in step f) can be carried out on the batches of acceptor substrates.

[0051] [Example] [1] [:] [, The epitaxial equipment is a Centura® machine. The epitaxial process is designed to grow a 20-micron-thick useful silicon layer. The process begins with a 30-second bake at 1100°C, followed by 10 minutes of epitaxial growth at 1100°C. The lamp power of the heating system can be independently adjusted to define the following temperatures: The internal lighting fixtures define the temperature to be applied to the central area of ​​the substrate to be treated, and The temperature to be applied to the outer perimeter of the substrate is defined by the external light fixture.

[0052] The heating system includes a top light and a bottom light, which are respectively opposite the front and back of the substrate for use in the central (interior) and peripheral (exterior) areas.

[0053] The baseline conditions are set as follows: The power ratio of the bottom lights (internal and external) is 60%, meaning the ratio of the bottom light power to the total light power is 0.6. The power ratio of the interior ceiling lights is 70%, meaning the ratio of the power of the interior ceiling lights to the total ceiling lights is 0.7. The bottom inner light power ratio is 45%, meaning the ratio of the bottom inner light power to the total bottom light power is 0.45.

[0054] The test substrate type selected for this setup corresponds to the first type described above. Specifically, a silicon wafer with a radius of 200 mm, a thickness of 500 micrometers, and a high boron doping density (20 mohm·cm) is used as the test substrate. It should be noted that other types can also be selected.

[0055] The table in Figure 5 shows the various temperature conditions established and applied to the test substrate in the first embodiment. Steps d) and e) were performed five times for the five new temperature conditions Tn, Tn', Tn'', Tn''', and Tn''''. Temperature variations between different conditions were controlled by increasing or decreasing the percentage of internal power provided by the top and bottom lights. In this example, the inner power ratio varied between +10% and -25%, with similar variations between the top and bottom.

[0056] This can lead to an increase or decrease in the temperature difference between the internal and external zones (i.e., between the central and peripheral zones of the treated substrate). The temperature difference associated with changes in the internal power ratio is typically in the range of 3°C to 30°C.

[0057] It should be noted that the internal power ratio can vary in different ways at the top and bottom.

[0058] After forming useful layers on the initial test structure and five new test structures under relevant temperature conditions, step f) shows slip lines on the initial test structure and three other test structures (as shown in the table in Figure 5). However, the two test structures treated with Tn''' and Tn'''' temperature conditions do not exhibit any slip lines.

[0059] Compared to conventional process tolerances associated with the target epitaxial process, the method of setting up this invention allows for the definition of a narrower process tolerance: the associated temperature conditions ensure minimal thermal stress on the substrate to be treated. Thus, with this method, any acceptor substrate can be safely processed within the defined narrow process tolerance.

[0060] [Example] [2] [:] [, The epitaxial equipment is an Epsilon® machine. The epitaxial process is designed to grow a 20-micron-thick useful silicon layer. The process begins with a 30-second bake at 1100°C, followed by 10 minutes of epitaxial growth at 1100°C. The lamp power of the heating system can be independently adjusted to define the temperature offset between the central region of the substrate and three edge regions, referred to as the front, side, and back regions, located at 12h, 3h, and 6h along the wafer edge, respectively.

[0061] The baseline conditions are set as follows: The central temperature is set to 1100°C; The forward offset is -25°C, corresponding to a front zone temperature of 1075°C; The lateral offset is -15°C, corresponding to a lateral zone temperature of 1085°C. The back offset is -50°C, corresponding to a back zone temperature of 1050°C.

[0062] The type of test substrate selected for this setup corresponds to the second type described above. Specifically, a silicon wafer with a diameter of 200 mm, a thickness of 725 micrometers, and low interstitial oxygen content is used as the test substrate. It should be noted that other types can also be selected.

[0063] The table in Figure 6 shows the various temperature conditions established and applied to the test substrate in the second embodiment. Steps d) and e) were performed five times for the five new temperature conditions Tn, Tn', etc. The temperature variation between the different temperature conditions was controlled by increasing or decreasing the temperature offset between the central zone and the three edge zones.

[0064] In this example, the offset varies from +5°C to -20°C, and this applies to all three peripheral zones. It should be noted that the offset can be varied differently for each of the three edge zones, thus controlling each zone individually. For example, the offsets for the front, side, and rear zones could be selected as -10°C, -5°C, and -7°C, respectively, to fine-tune temperature conditions and allow for lower thermal stress.

[0065] After forming useful layers on the initial test structure and five new test structures under relevant temperature conditions, step f) shows slip lines on the initial test structure and three other test structures (as shown in the table in Figure 6). However, the two test structures treated with Tn''' and Tn'''' temperature conditions do not exhibit any slip lines.

[0066] In this second example, compared to the conventional process tolerances associated with the target epitaxial process, the method of setting this invention also allows for defining a narrower process tolerance: the associated temperature conditions ensure minimal thermal stress on the substrate to be treated. Thus, with this method, any acceptor substrate can be safely processed within the defined narrow process tolerance.

[0067] Of course, the present invention is not limited to the embodiments described, and modifications and variations can be made without departing from the scope of the present invention as defined by the claims.

[0068] Ti: Initial temperature conditions Tn,Tn',Tn'',Tn''',Tn''': New temperature conditions

[0069]

Claims

1. A method for setting up an epitaxial process to form a useful layer on a acceptor substrate in an epitaxial apparatus, the useful layer and the acceptor substrate comprising silicon, the method being performed prior to processing the acceptor substrate, the method comprising: a) Select a type of test substrate from a silicon-based wafer that differs from the acceptor substrate, wherein: for substrates with diameters of 200 mm and 300 mm, the conventional thicknesses are 725 μm and 775 μm, respectively, but the thickness of the test substrate at a given diameter is between 20% and 40% smaller than the conventional thickness, and / or the test substrate has an interstitial oxygen concentration of less than 10 ppma ASTM'79, and / or the test substrate comprises an SOI stack comprising a dielectric layer with a thickness ranging from 0.5 to 5.0 μm, and a single-crystal silicon film with a thickness of less than or equal to 300 nm; b) Establish initial temperature conditions that define the temperatures to be applied to at least two regions of the test substrate to be processed in the epitaxial equipment; c) Perform an epitaxial process at the initial temperature conditions to form the useful layer on the test substrate to obtain an initial test substrate; then measure slip line defects on the initial test substrate; d) a) Change the temperature of at least two regions of the substrate to establish new temperature conditions compared to the initial temperature conditions; e) Perform an epitaxial process under the new temperature conditions to form the useful layer on one of the selected types of new test substrates to obtain a new test substrate; then measure slip line defects on the new test substrate; f) Compare the number of slip line defects measured on each of the test substrates and select the epitaxial process temperature conditions that produce the fewest slip line defects.

2. As in request item 1, where, Before step f), steps d) and e) may be repeated once or multiple times for other new temperature conditions.

3. The method of claim 1 or 2, wherein the epitaxial device comprises a plurality of epitaxial chambers, and wherein: Steps b) and d) are performed in parallel rather than sequentially, and each step is performed in a different epitaxial chamber. Then steps c) and e) are performed in parallel, and the initial test substrate and the new test substrate are set in the different epitaxial chambers.

4. As in request 1, wherein after step f), steps d) and e) may be repeated once or more for other new temperature conditions; then step f) is repeated.

5. As in the method of request item 1, 2 or 4, wherein steps d) and e) are repeated between 2 and 5 times.

6. The method of claim 1, wherein the measurement of slip line defects is performed using an optical surface scanning tool.

7. The method of claim 6, wherein the target number of slip line defects corresponds to a cumulative slip line length of less than 20 mm, preferably less than 5 mm.

8. The method of claim 1, 2 or 4, wherein the temperature conditions define the temperatures to be applied to the central and peripheral regions of the substrate to be processed in the epitaxial apparatus.

9. The method of claim 1, 2 or 4, wherein the temperature condition defines a temperature offset between a central region and a peripheral region of a substrate to be processed in the epitaxial apparatus.

10. The method of claim 1, wherein the temperature variation between the initial temperature condition and the new temperature condition to be applied to at least two areas of the substrate ranges from -30°C to +30°C.

11. The method of claim 1, wherein the epitaxial process involves a temperature between 600°C and 1200°C, includes an atmosphere of at least one gas selected from TCS, DCS, SiH4, SiCl4, Si2H4, Si3H8, GeH4, and a pressure between ultra-high vacuum and atmospheric pressure.

12. The method of claim 1, wherein the useful layer formed during the epitaxial process is made of silicon and has a thickness between 0.3 micrometers and 30 micrometers.

13. The method of claim 1, wherein the useful layer formed during the epitaxial process is made of silicon and germanium and has a thickness between 50 nanometers and 1000 nanometers.

14. An epitaxial process for performing an epitaxial process aimed at forming a useful layer on a acceptor substrate in an epitaxial apparatus, the useful layer and the acceptor substrate comprising silicon, wherein the method of any one of claims 1 to 13 is performed prior to processing the acceptor substrate, wherein the acceptor substrate is an SOI substrate.

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