Multi-chip apparatus

Abstract

An integrated circuit (IC) package can be manufactured having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer. The first side of the interposer includes a plurality of first bonding pads, which are equally coupled to a plurality of first bonding pads of the first IC chip, and the second side of the interposer includes a plurality of second bonding pads, which are equally coupled to a plurality of first bonding pads of the second IC chip. In one embodiment of this description, a liquid-cooled three-dimensional IC (3D IC) package can be formed, wherein at least two IC devices can be stacked with a liquid-cooled interposer. In another embodiment, the liquid-cooled 3D IC package can be electrically attached to an electronic board. This application discloses and claims other embodiments.

Description

[Technical Field]

[0001] The embodiments described herein are generally related to the field of integrated circuit packaging manufacturing, and more specifically, to an integrated circuit assembly including a plurality of microfluidic channels for thermal management of an integrated circuit chip. [Previous Technology]

[0002] The integrated circuit industry is committed to producing faster, smaller and thinner integrated circuit packages for use in a variety of electronic products, including but not limited to computer servers and portable products such as portable computers, tablets, mobile phones, digital cameras and the like.

[0003] As part of this work, integrated circuit packages containing multiple integrated circuit devices, such as microelectronic dies, have been developed. These multiple integrated circuit device packages are referred to in the art as multi-device, multi-chip package (MCP), or partitioned devices, and offer the potential to increase architectural flexibility at a reduced cost, but require an appropriate interconnect density between integrated circuit devices. As those skilled in the art will understand, interconnect density is an important consideration because an insufficient number of integrated circuit device connectors will limit the bandwidth capability of the affected integrated circuit device interface, and thus reduce the communication efficiency and capability between several integrated circuit devices.

[0004] To address interconnection issues, a bridging element can be embedded in a substrate to which integrated circuit devices are attached. These bridging elements support dense interconnections between integrated circuit devices, such as from the edge of a first integrated circuit device to the edge of a second integrated circuit device, and can support several signal lines passing through the bridging element itself. Instead of using expensive silicon intermediaries with through-silicon vias, the bridging element can be a non-active silicon structure or an active silicon device embedded in the substrate, thereby enabling dense interconnections between integrated circuit devices only when needed. Standard flip-chip processes can be used to connect integrated circuit devices to the substrate for robust power delivery, and to the bridging elements connected within the substrate. Therefore, an resulting integrated circuit package can be significantly smaller than an integrated circuit package that is only interconnected with conductive paths within the substrate. [Summary of the Invention]

[0005] According to one embodiment of the present invention, a multi-chip device is specifically provided, comprising: an intermediary; one or more microfluidic channels through the intermediary; a first integrated circuit (IC) chip attached to a first side of the intermediary; and a second IC chip attached to a second side of the intermediary, wherein the first side of the intermediary includes a plurality of first bonding pads that are equally coupled to a plurality of bonding pads of the first IC chip, and the second side of the intermediary includes a plurality of second bonding pads that are equally coupled to a plurality of bonding pads of the second IC chip.

Implementation Method

[0020] In the following detailed description, reference is made to the accompanying drawings, which illustrate specific embodiments in which the claimed subject matter can be practiced. These embodiments are described in great detail to enable those skilled in the art to practice the subject matter. It should be understood that the various embodiments, though different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein relating to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter. The reference to "an embodiment" or "an embodiment" in this description means that a particular feature, structure, or characteristic described in that embodiment is included in at least one implementation contained in this description. Therefore, the use of the phrase "an embodiment" or "in one embodiment" does not necessarily refer to the same embodiment. Furthermore, it should be understood that the position or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description is not intended to be restrictive, and the scope of the subject matter is defined solely by the appended claims, and, as appropriately interpreted, together with the equivalents that should be enjoyed by the appended claims. In the diagrams, similar numbers throughout refer to the same or similar elements or functions, and the elements shown therein are not necessarily shown to scale. In fact, individual elements may be enlarged or reduced to make it easier to understand the elements in the context of this description.

[0021] The terms “above,” “to,” “between,” and “on top” as used herein may refer to the relative position of one layer with respect to another layer. A layer “above” or “on top” or “to” another layer may be in direct contact with that other layer or may have one or more intermediate layers. A layer “between” several layers may be in direct contact with those layers or may have one or more intermediate layers.

[0022] The term "package" generally refers to a self-contained carrier of one or more dies, wherein the dies are attached to a package substrate and can be encapsulated for protection, wherein integrated or wire-connected interconnects are located between the dies, and leads, pins, or bumps are located on the external portion of the package substrate. The package may contain a single die or multiple dies, providing a specific function. The package is often mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components to form a larger circuit.

[0023] Here, the term "core" generally refers to a substrate of an integrated circuit package built on a board, card, or wafer containing a non-flexible rigid material. Typically, a small printed circuit board is used as a core, to which integrated circuit devices and discrete passive components can be soldered. Typically, the core has several through-holes extending from one side to the other, allowing circuitry on one side of the core to be directly coupled to circuitry on the opposite side of the core. The core can also serve as a platform for constructing layers of conductors and dielectric materials.

[0024] Here, the term "coreless" generally refers to a substrate of an integrated circuit package that does not have a core. The absence of a core allows for a higher density package architecture because the vias have relatively large size and pitch compared to high-density interconnects.

[0025] Here, the term "pad side" as used herein generally refers to the side of the substrate of an integrated circuit package that is closest to the plane to which it is attached to a printed circuit board, motherboard, or other package. This is in contrast to the term "die side," which is the side of the substrate of an integrated circuit package to which one or more dies are attached.

[0026] Herein, the term "dielectric" generally refers to any amount of non-conductive material constituting the structure of a package substrate. For the purposes of this disclosure, the dielectric material may be incorporated into an integrated circuit package as a layer of a laminated film or as a resin molded over an integrated circuit die mounted on a substrate.

[0027] Herein, the term "metallization" generally refers to a metal layer formed on and through the dielectric material of a package substrate. These metal layers are typically patterned to form metallic structures, such as traces and bonding pads. Metallization of a package substrate may be confined to a single layer or in multiple layers separated by dielectric layers.

[0028] Here, the term "bonding pad" generally refers to the metallization structure that terminates integrated circuit packages and integrated traces and vias in the die. The term "solder pad" is sometimes used instead of "bonding pad" and has the same meaning.

[0029] Here, the term "solder bump" generally refers to a solder layer formed on a bonding pad. The solder layer generally has a circular shape, hence the name "solder bump".

[0030] Here, the term "substrate" generally refers to a planar platform comprising dielectric and metallized structures. The substrate mechanically supports and electrically couples one or more IC dies to a single platform, wherein the one or more IC dies are encapsulated by a moldable dielectric material. The substrate typically includes solder bumps on both sides serving as interconnects. One side of the substrate, commonly referred to as the "die side," includes solder bumps for wafer or die bonding. The opposite side of the substrate, commonly referred to as the "pad side," includes solder bumps for bonding a package to a printed circuit board.

[0031] Here, the term "assembly" generally refers to a group of components that form a single functional unit. These components may be separate and mechanically assembled into a functional unit, wherein the components are removable. In another instance, the components may be permanently joined together. In some instances, the components are integrated together.

[0032] Throughout this specification and in the scope of the claims, the term “connection” means a direct connection between connected objects, such as an electrical, mechanical or magnetic connection, without any intermediate means.

[0033] The term “coupled” means a direct or indirect connection between connected objects, such as a direct electrical, mechanical, magnetic or fluid connection, or an indirect connection via one or more passive or active intermediate devices.

[0034] The terms "circuit" or "module" can refer to one or more passive and / or active components configured to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0035] Vertical orientation is in the z-direction, and it should be understood that the references to "top," "bottom," "above," and "below" refer to relative positions in the usual sense in the z-dimension. However, it should be understood that embodiments are not necessarily limited to the orientations or configurations illustrated in the figures.

[0036] The terms “substantially,” “nearly,” “roughly,” “almost,” and “approximately” generally refer to within + / - 10% of a target value (unless otherwise specifically indicated). The use of ordinal adjectives such as “first,” “second,” and “third” to describe a common object, unless otherwise specified, merely indicates that different instances of similar objects are mentioned and is not intended to imply that the objects described must be in a given sequence, whether in time, space, hierarchy, or any other manner.

[0037] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0038] Views labeled "section," "profile," and "plane" correspond to orthogonal planes within a Cartesian coordinate system. Therefore, sectional and profile views are taken with respect to the xz-plane, while plan views are taken with respect to the xy-plane. Generally, the profile view in the xz-plane is the sectional view. Where appropriate, axes are marked on the diagram to indicate its orientation.

[0039] Referring to FIG1, one embodiment of an integrated circuit (IC) package 10 (e.g., a three-dimensional IC (3D IC) package) may include an interposer 11, one or more microfluidic channels 12 passing through the interposer 11 (indicated by dashed lines in FIG1 as a hidden structure within the interposer 11), a first IC chip 13 attached to a first side 11a of the interposer 11, and a second IC chip 14 attached to a second side 11b of the interposer 11. In some embodiments, the first side 11a of the interposer 11 includes a plurality of first bonding pads 11c, which are equivalently coupled to a plurality of first bonding pads 13a of the first IC chip 13, and the second side 11b of the interposer 11 includes a plurality of second bonding pads 11d, which are equivalently coupled to a plurality of first bonding pads 14a of the second IC chip 14. The interposer 11 and the first and second IC chips 13 and 14 may be made of any suitable material and may be attached to each other by any known process. The microfluidic channel 12 can be formed through the interposer 11 by any conventional process, including mechanical drilling using a drill bit, laser drilling, wet etching or dry etching, laser-assisted etching, etc. In some embodiments, as described in further detail herein, the interposer 11 and the first and second IC chips 13 and 14 can be attached to each other by a hybrid bonding process, and the microfluidic channel 12 can be formed in the interposer 11 by a photolithography and etching process.

[0040] Referring to FIG2, an embodiment of a 3D IC package 20 can be similarly assembled into package 10, with similar elements indicated by similar numbers. In the 3D IC package 20, an intermediary 11 may be included as a bridge 21 between a first IC wafer 13 and a second IC wafer 14. For example, the bridge 21 may include one or more metal vias 25 or other circuitry or interconnects that couple the first IC wafer 13 to the second IC wafer 14 outside the region of the microfluidic channel 22. The bridge 21 may be made of any suitable material through any known process.

[0041] Referring to FIG3, one embodiment of a 3D IC package 30 can be similarly assembled into a package 10, with similar elements indicated by similar numbers. In the 3D IC package 30, the intermediary 11 may include a top portion 32 attached to a bottom portion 33. A first side 32a of the top portion 32 includes a plurality of first bonding pads 32b, which are equally coupled to a plurality of first bonding pads 33b on a first side 33a of the bottom portion 33. In some embodiments, separating the intermediary 11 into two parts allows the microfluidic channels 35 to be deeper and can also be configured to meet the specific cooling requirements of stacked ICs. In the 3D IC package 30, both the top and bottom portions 32, 33 of the intermediary 11 include individual portions of one or more microfluidic channels 35.

[0042] In some embodiments, only one of the top and bottom portions of the intermediary 11 may include the one or more microfluidic channels. Referring to FIG4, an embodiment of a 3D IC package 40 may be similarly assembled as package 30, wherein similar elements are indicated by similar numbers. In the 3D IC package 40, the intermediary 11 may include a top portion 42 attached to a bottom portion 43, and only the bottom portion 43 of the intermediary 11 includes one or more microfluidic channels 45.

[0043] Referring to FIG5, an embodiment of a 3D IC package 50 can be similarly assembled into a package 30, with similar elements indicated by the same numbers. In the 3D IC package 50, the interposer 11 may include a top portion 52 attached to a bottom portion 53, and both the top portion 52 and the bottom portion 53 of the interposer 11 include individual portions of one or more microfluidic channels 55. As shown in FIG1 to 5, several embodiments may include any useful number of microfluidic channels, and such channels may include any useful shape or cross-sectional shape (e.g., square, rectangular, circular, elliptical, polygonal, etc.).

[0044] Referring to FIG6, one embodiment of a 3D IC package 60 can be similarly assembled into a package 30, with similar elements indicated by similar numbers. As shown in FIG6, the interposer 11 may include a top portion 62 attached to a bottom portion 63, and both the top and bottom portions 62, 63 of the interposer 11 include individual portions of the one or more microfluidic channels 65. In the 3D IC package 60, at least one of the one or more microfluidic channels 65 includes at least one heat dissipation structure 66 protruding into the at least one microfluidic channel 65. For example, the structure 66 may be any suitable material made by any known process and may have any useful shape (for example, such as a pin, column, pyramid, etc.).

[0045] Referring to Figures 7A to 7D, an embodiment of a 3D IC package 70 can be similarly assembled into a package 30, with similar elements indicated by similar numbers. In the 3D IC package 70, one or more microfluidic channels 72 include at least one first microfluidic channel 73 and a second microfluidic channel 74, wherein a first cross-sectional area 73a (see Figure 7B) of the first microfluidic channel 73 perpendicular to a first flow direction A at a first internal portion 73b of the first microfluidic channel 73 is different from a second cross-sectional area 74a (see Figure 7B) of the second microfluidic channel 74 perpendicular to a second flow direction B at a second internal portion 74b of the second microfluidic channel 74. In other words, channel 74 is larger than channel 73. As shown in Figures 7C and 7D, a first cross-sectional area 75a (see Figure 7C) of one or more microfluidic channels 72 perpendicular to a first flow direction C at an inlet 75 of the intermediate member 11 is smaller than a second cross-sectional area 76a (see Figure 7D) of one or more microfluidic channels 72 perpendicular to a second flow direction D at an outlet 76 of the intermediate member 11. The outlet 76 is in fluid communication with the inlet 75 of the intermediate member 11. In other words, as shown, the outlet 76 is larger than the inlet 75.

[0046] Referring to FIG8, one embodiment of a liquid-cooled 3D IC package 80 may include an IC package 82 having an IC stack including at least a first IC chip 83 and a second IC chip 84, and a housing 85 attached to the IC package 82. The housing 85 includes at least one inlet 85a and at least one outlet 85b. The IC package 82 may be further configured to include one or more liquid-cooled features or patterns including any of the embodiments described herein. For example, the IC package 82 may further include an intermediary 87 attached between the first IC chip 83 and the second IC chip 84, and one or more microfluidic channels 88 passing through the intermediary 87 and in fluid communication with at least one inlet 85a and one outlet 85b of the housing 85. In some embodiments, a first side of the intermediary 87 includes a plurality of first bonding pads that are coupled to a plurality of first bonding pads of the first IC chip 83, and a second side of the intermediary 87 includes a plurality of second bonding pads that are coupled to a plurality of first bonding pads of the second IC chip 84.

[0047] For example, the first IC chip 83, the interposer 87, and the second IC chip 84 can be attached to each other by a hybrid bonding method. In some embodiments, the interposer 87 may include a bridging element between the first IC chip 83 and the second IC chip 84. For example, the interposer 87 may include an attachment to a top portion of a bottom portion (e.g., wherein a first side of the top portion includes a plurality of first bonding pads, which are coupled to a plurality of first bonding pads on a first side of the bottom portion), and either or both of the top and bottom portions of the interposer include individual portions of one or more microfluidic channels 88. In some embodiments, at least one of the one or more microfluidic channels 88 includes at least one heat dissipation structure protruding into the at least one microfluidic channel 88.

[0048] The microfluidic channel 88 may have any useful configuration and cross-sectional area. In some embodiments, one or more microfluidic channels 88 may include at least one first microfluidic channel and one second microfluidic channel, wherein a first cross-sectional area in the first microfluidic channel perpendicular to a first flow direction at a first internal portion of the first microfluidic channel is different from a second cross-sectional area in the second microfluidic channel perpendicular to a second flow direction at a second internal portion of the second microfluidic channel. Similarly, the inlet 88a and outlet 88b of the intermediary 87 may have any useful configuration and cross-sectional area. In some embodiments, a first cross-sectional area in one or more microfluidic channels 88 perpendicular to a first flow direction at an inlet 88a of the intermediary 87 is smaller than a second cross-sectional area in one or more microfluidic channels 88 perpendicular to a second flow direction at an outlet 88b of the intermediary 87, wherein the outlet 88b is in fluid communication with the inlet 88a of the intermediary 87.

[0049] Referring to FIG9, one embodiment of an electronic system 90 may include a board 91; a power supply 92 providing power to one or more IC chips; an IC package 93 coupled to the board 91 and the power supply 92, the IC package 93 including an IC stack having at least one first IC chip 93a and a second IC chip 93b; and a housing 94 attached to the IC package 93. The housing 94 includes at least one inlet 94a and at least one outlet 94b. As shown in FIG9, the system 90 may also include a pump 95 coupled to at least one inlet 94a and at least one outlet 94b of the housing 94, and a heat dissipation device 96 coupled between at least one outlet of the housing and the pump.

[0050] The IC package 93 may be further configured to include one or more liquid-cooled features or configurations, including any of the embodiments described herein. For example, the IC package 93 may further include an intermediary 93c attached between a first IC wafer 93a and a second IC wafer 93b, and one or more microfluidic channels 93d passing through the intermediary 93c and in fluid communication with at least one inlet 94a and one outlet 94b of the housing 94. In some embodiments, a first side of the intermediary 93c includes a plurality of first bonding pads equally coupled to a plurality of first bonding pads of the first IC wafer 93a, and a second side of the intermediary 93c includes a plurality of second bonding pads equally coupled to a plurality of first bonding pads of the second IC wafer 93b. For example, the intermediary 93c may be included as a bridge between the first IC chip 93a and the second IC chip 93b, and the intermediary 93c may include a top portion attached to a bottom portion (e.g., a first side of the top portion includes a plurality of first bonding pads, which are coupled to a plurality of first bonding pads on a first side of the bottom portion).

[0051] Some embodiments provide several microfluidic channels built into a support substrate for liquid cooling in hybrid bonding technologies. Thermal management of a 3D IC can be problematic due to limited heat dissipation capacity. Some packages may include several microfluidic channels on a single side of the package and / or may include a specific cooling module attached to a single side of a wafer, but may not provide satisfactory thermal management for the 3D IC due to single-side attachment. The heat dissipation path adds thermal resistance to the stacked silicon wafers further away from the heat sink.

[0052] Some embodiments may overcome one or more of the aforementioned problems by forming microfluidic channels for liquid cooling of adjacent ICs on an intermediate support substrate. By applying liquid cooling to the middle of the 3D IC, for example, some embodiments may more effectively cool the chip from both sides. In addition, some embodiments include an on-chip heat radiator to further improve cooling efficiency.

[0053] Referring to Figures 10 and 11, one embodiment of an electronic system 100 may include an IC package 110 coupled to a micropump 150 and a heat dissipation device 160 (e.g., a radiator, a fan, etc.). In this example, the IC package 110 includes a cooling module 112, with a cooling fluid inlet 114 coupled to an outlet of the micropump 150, a cooling fluid outlet 116 coupled to an inlet of the micropump 150, and a liquid cooling path through the heat dissipation device 160.

[0054] The IC package 110 includes a package substrate 120 attached to a cooling module 112 to provide a sealed enclosure 124 for cooling fluid. A 3D IC stack 130 is attached between the cooling module 112 and the package substrate 120 within the sealed enclosure 124. The stack 130 includes at least a first silicon IC 132 and a second silicon IC 134, which are attached to opposite sides of an intermediate support substrate 136 (e.g., an intermediary). The substrate 136 includes one or more microfluidic channels 138 in fluid communication with a cooling fluid inlet 114 and a cooling fluid outlet 116 of the cooling module 112.

[0055] As shown in Figures 10 and 11, an intermediate support substrate 136 with microfluidic channels 138 is placed between two silicon wafers 132 and 134. A liquid coolant is pumped by a micropump 150 and flows through the microfluidic channels 138, carrying heat to a heat dissipation device 160 (e.g., an external radiator or fan). In some embodiments, the flow rate of the liquid cooling system can be electronically controlled by thermal management logic components based on the output of one or more temperature sensors integrated on wafers 132 and / or 134 (e.g., and / or substrate 136).

[0056] In one embodiment of this description, a microfluidic channel 138 is formed in an intermediate support substrate 136 for liquid cooling of a 3D IC stack 130 utilizing a hybrid bonding technology. Any suitable material can be used for the intermediate support substrate 136, and any known process can be employed to hybrid bond the first and second ICs 132 and 134 to the substrate 136 (e.g., or two portions of the substrate 136 bonded to each other, as described in further detail below). For example, wafers 132 and 134 may be silicon, and each of the silicon wafers 132 and 134 may have several external dielectric layers (e.g., silicon dioxide (SiO2)) and several metal bonding pads compatible with the die stack using a hybrid bonding technology. The second IC wafer 134 may be attached to the package substrate 120 via any known process including solder interconnects such as solder balls or solder bumps.

[0057] Conventional die stacking uses solder interconnects subject to certain size limitations. Hybrid bonding technology removes many of these limitations and allows for several orders of magnitude improvement in die-to-die interconnect density. In one embodiment of this description, hybrid bonding replaces solder-covered copper pillars with copper pads that are substantially coplanar with the substrate / die surface. These surfaces are treated by a chemical mechanical polishing (CMP) step, which creates an extremely flat and smooth dielectric surface. The electrical connection is formed via a two-step process. The first step is performed at room temperature, in which the two substrate / die surfaces are brought into contact. This creates an immediate bond between several dielectric interfaces, but does not form a complete electrical connection. The second step is performed by heating the two components at an elevated temperature, which causes the facing copper pads to expand and come into contact with each other to form the electrical connection. This also further enhances the dielectric-to-dielectric bonding created in the first step. This temperature is maintained long enough to allow the contacting copper pads to diffuse into each other and form a permanent metallic bond that remains after the grains cool.

[0058] Referring to Figures 12-13, an embodiment of a 3D IC stack 200 illustrates how it may include two or more IC wafers and more than one liquid-cooled interposer. The 3D IC stack 200 includes a substrate formed by stacking four IC wafers 202, 206, 208, and 212 and two interposers 204 (having top and bottom 204t, 204b) and 210 (having top and bottom 210t, 210b). Each of the stacked substrates 202 to 212 includes an outer layer 214 having several bonding pads suitable for hybrid bonding and dielectric material. The bonding of the two portions of interposers 204 and 210 to each other provides a hermetically sealed microfluidic channels 205 and 211. Intermediates 204 and 210 also include metal vias 216 (e.g., through both top 204t, 210t and bottom 204b, 210b) to provide electrical connections between adjacent IC wafers (e.g., and potentially through all stacked IC wafers, where IC wafers can provide through-through electrical connections).

[0059] Referring to Figures 14-15, a 3D IC stack 300 includes a first IC wafer 310, a support substrate 320 (e.g., an intermediary having a top portion 330 and a bottom portion 340), and a second IC wafer 350. The intermediary 320 includes an inlet 321, an outlet 322, and a plurality of microfluidic channels 323, 324, and 325, which are in fluid communication with the inlet 321 and the outlet 322. To enhance the overall cooling efficiency of the entire system, the channels on the support substrate can be designed according to the power density of the associated regions of the silicon wafer in the 3D IC. For example, regions with higher power density may have wider channels, while regions with lower power density may have narrower channels (e.g., or no channels).

[0060] As illustrated in Figure 14, one region of the intermediate 320 provides a wider channel 323 with a loop (e.g., for cooling a region with high power density), another region of the intermediate provides a narrower channel 324 to cool a region with lower power density, and yet another region of the intermediate 320 provides a medium-width channel 325 without a loop to cool a region with medium power density. Other regions of the intermediate 320 do not provide channels (e.g., for lower power density regions). For extremely high power densities, these channels can be designed to flow around the region for more efficient heat dissipation (e.g., similar to channel 323). Although not shown in the figure, the 3D IC stack 300 may also include an on-chip radiator that uses bonding pads with a hybrid bonding interface to further improve cooling efficiency.

[0061] As shown in FIG. 14, the intermediary 320 includes a plurality of metal vias 326 passing through it (e.g., in both the top portion 330 and the bottom portion 340) so that the intermediary 320 serves as a bridge between two IC chips 310 and 350. In the 3D IC stack 300, the top portion 330 may be substantially mirrored to the bottom portion 340 according to the configuration of the channels 323, 324 and 325 and the metal vias 326, such that corresponding portions of the two portions 330 and 340 are substantially aligned during stacking as shown in FIG.

[0062] Figures 16 and 17 show two examples of the process for fabricating microfluidic channels in individual 3D IC packages 375 and 385. As shown in Figure 16, several channels 376 can be fabricated on one of the lower halves 377b of the support substrate. The upper half 377t is flat and no strict alignment tolerances are imposed during the assembly process. The thickness of each half 377b, 377t can be adjusted to cool the two wafers equally or to stand out on the wafer with a higher power density. As shown in Figure 17, mirrored channels 386t and 386b can be fabricated on the two halves of the support substrate (e.g., the upper half 387t and the lower half 387b) and joined together to form a complete microfluidic channel. Using two halves requires precise alignment between the two halves, but a deeper channel can be fabricated, thereby potentially improving cooling efficiency.

[0063] Figures 18-23 illustrate one embodiment of the fabrication of an integrated circuit package. As shown in Figure 18, a support wafer 402 and a small wafer 404 each include hybrid bonding interfaces 402a and 404a. In Figure 19, the support wafer 402 and the small wafer 404 are hybrid-bonded to each other. The support wafer 402 may be thinned, and the hybrid bonding interface 402b may be attached to the exposed side of the support wafer 402 (e.g., although not shown in the figure, several through-holes may be connected to several bonding pads on opposite sides of the support wafer 402). In Figure 20, a microfluidic channel top portion 405t is formed in the support wafer 402. In one embodiment of this description, the microfluidic channel 405t is formed by a photolithography pattern and etching process.

[0064] In FIG. 21, the support wafer 402 and the small wafer wafer 404 are divided into two or more individual dies 406. In FIG. 22, a second small wafer wafer 414 (e.g., a substrate wafer) may be fabricated, similar to that described above regarding the bonding of the small wafer wafer 404, and is hybrid-bonded to a second support wafer 412 (e.g., via hybrid bonding interfaces 412a and 414a). A hybrid bonding portion in interface 412b is added to the second support wafer 412, and a microfluidic channel bottom portion 405b is formed in the second support wafer 412. In FIG. 23, one or more of the dies 406 are hybrid-bonded to the second support wafer 412 to form a complete, hermetically sealed microfluidic channel 405.

[0065] Referring to Figures 24A and 24B, one embodiment of an intermediary 440 includes a plurality of channels 442 from individual inlets to individual outlets. The channels 442 may have different widths (e.g., depending on the power profile of the grain to be cooled). The channels 442 may be substantially straight as shown (e.g., or may be curved / winding in other embodiments). Some of the channels 442 may include several pins or pillars 444 for improved heat dissipation. For example, in other embodiments, such pillars may extend partially through the channel thickness as shown (e.g., or may extend through the entire thickness (top to bottom) in other embodiments). When viewed from above (see Figure 24A), such pillars may have a circular cross-section as shown (e.g., or may have a square, rectangular, triangular, or other cross-section in other embodiments).

[0066] Referring to FIG25, one embodiment of an intermediary 450 includes a plurality of channels 452 from individual inlets to individual outlets. The channels 452 may have an increasing width from the inlet to the outlet, such that the cross-sectional area of ​​the outlet is larger than the cross-sectional area of ​​the inlet (e.g., perpendicular to the flow direction).

[0067] In any of the above embodiments, the channel width and height can be in the range of 50 μm to 1000 μm, and the channel length can be in the range of 5 mm to 30 mm. When included, the column in the planar dimension (e.g., for the diameter of a cylinder or the side of a square column) can be in the range of 10 μm to 100 μm.

[0068] Any suitable material can be used for the intermediates, leads, pillars, etc. For example, suitable materials include highly thermally conductive materials to facilitate heat transfer and removal of the grains. Silicon, silicon carbide, or aluminum nitride are examples of suitable thermally conductive materials. Other suitable materials include glass. Low or high resistivity materials can be used depending on the application. In some embodiments, low resistivity materials can be used to increase thermal efficiency.

[0069] Figure 26 illustrates an electronic or computing device 500 according to one embodiment of this description. The computing device 500 may include a housing 501 in which a plate 502 is disposed. The computing device 500 may include several integrated circuit components, including but not limited to: a processor 504, at least one communication chip 506A, 506B, electrically dependent memory 508 (e.g., DRAM), non-electrically dependent memory 510 (e.g., ROM), flash memory 512, a graphics processor or CPU 514, a digital signal processor (not shown), a cryptographic processor (not shown), a chipset 516, an antenna, a display (touchscreen display), a touchscreen controller, a battery / power supply, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a large-capacity storage device (not shown) (such as a hard disk drive, a CD, a DVD, etc.). Any of these integrated circuit components may be physically and electrically coupled to board 502. In some implementations, at least one of these integrated circuit components may be part of processor 504.

[0070] This communication chip enables wireless communication for transferring data to and from the computing device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data via a non-solid-state medium using modulated electromagnetic radiation. This term does not imply that such related devices do not contain any wires, although in some embodiments they may be wire-free. The communication chip may implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Range Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives of the above, and any other wireless protocols designated as 3G, 4G, 5G, and higher. The computing device may include a plurality of communication chips. For example, a first communication chip may be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0071] The term "processor" can refer to any device or part of a device that processes electronic data from a register and / or memory to convert the electronic data into other electronic data that can be stored in the register and / or memory.

[0072] At least one of these integrated circuit components may include an integrated circuit package including an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, wherein the first side of the interposer includes a plurality of first bonding pads equally coupled to a plurality of first bonding pads of the first IC chip, and the second side of the interposer includes a plurality of second bonding pads equally coupled to a plurality of first bonding pads of the second IC chip (e.g., and one or more of other features or features of the embodiments described herein). System 500 may further include a cooling module, a pump, and / or a heat dissipation device (not shown in the figures).

[0073] In various embodiments, the computing device may be a laptop, a lightweight laptop, a notebook computer, an ultra-thin laptop, a smartphone, a tablet computer, a digital assistant (PDA), an ultra-thin mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other embodiments, the computing device may be any other electronic device for processing data.

[0074] It should be understood that the main content of this specification is not necessarily limited to the specific applications illustrated in Figures 1-26. The main content of this specification can be applied to other integrated circuit devices and assemblies, as well as any suitable electronic applications, as will be understood by those skilled in the art.

[0075] The following examples relate to other embodiments, and the details in these examples may be used anywhere in one or more embodiments. Example 1 is an apparatus comprising an intermediary, one or more microfluidic channels through the intermediary, a first integrated circuit (IC) chip attached to a first side of the intermediary, and a second IC chip attached to a second side of the intermediary, wherein the first side of the intermediary includes a plurality of first bonding pads that are coupled to a plurality of first bonding pads of the first IC chip, and the second side of the intermediary includes a plurality of second bonding pads that are coupled to a plurality of first bonding pads of the second IC chip.

[0076] In Example 2, the main content of Example 1 may optionally include: the intermediary is included as a bridge between the first IC chip and the second IC chip.

[0077] In Example 3, the main content of any of Examples 1 to 2 may optionally include: the intermediary includes a top portion attached to a bottom portion, wherein a first side of the top portion includes a plurality of first engagement pads, which are equally coupled to a plurality of first engagement pads on a first side of the bottom portion.

[0078] In Example 4, the main content of Example 3 may optionally include: only one of the top and bottom portions of the medium includes the one or more microfluidic channels.

[0079] In Example 5, the main content of Example 3 may optionally include: either of the top and bottom portions of the intermediate component includes individual portions of the one or more microfluidic channels.

[0080] In Example 6, the main content of any one of Examples 1 to 5 may optionally include: at least one of the one or more microfluidic channels includes at least one heat dissipation structure protruding into the at least one microfluidic channel.

[0081] In Example 7, the main content of any of Examples 1 to 6 may optionally include: the one or more microfluidic channels include at least one first microfluidic channel and one second microfluidic channel, and wherein a first cross-sectional area in the first microfluidic channel that is perpendicular to a first flow direction at a first internal portion of one of the first microfluidic channels is different from a second cross-sectional area in the second microfluidic channel that is perpendicular to a second flow direction at a second internal portion of one of the second microfluidic channels.

[0082] In Example 8, the main content of any of Examples 1 to 7 may optionally include: a first cross-sectional area in one or more microfluidic channels that is perpendicular to a first flow direction at one inlet of the intermediary is smaller than a second cross-sectional area in one or more microfluidic channels that is perpendicular to a second flow direction at one outlet of the intermediary, and the outlet is in fluid communication with the inlet of the intermediary.

[0083] Example 9 is an apparatus comprising an integrated circuit (IC) package including an integrated circuit stack including at least a first IC chip and a second IC chip, and a housing attached to the IC package, the housing including at least one inlet and at least one outlet, wherein the IC package further includes an intermediary attached between the first IC chip and the second IC chip, and one or more microfluidic channels passing through the intermediary and in fluid communication with at least one inlet and one outlet of the housing, and wherein a first side of the intermediary includes a plurality of first bonding pads equivalently coupled to a plurality of first bonding pads of the first IC chip, and a second side of the intermediary includes a plurality of second bonding pads equivalently coupled to a plurality of first bonding pads of the second IC chip.

[0084] In Example 10, the main content of Example 9 may optionally include: the intermediary is included as a bridge between the first IC chip and the second IC chip.

[0085] In Example 11, the main content of any of Examples 9 to 10 may optionally include: the intermediary includes a top portion attached to a bottom portion, wherein a first side of the top portion includes a plurality of first engagement pads, which are equally coupled to a plurality of first engagement pads on a first side of the bottom portion.

[0086] In Example 12, the main content of Example 11 may optionally include: only one of the top and bottom portions of the medium includes the one or more microfluidic channels.

[0087] In Example 13, the main content of Example 11 may optionally include: the top and bottom portions of the medium both include individual portions of the one or more microfluidic channels.

[0088] In Example 14, the main content of Example 9, wherein at least one of the one or more microfluidic channels includes at least one heat dissipation structure protruding into the at least one microfluidic channel.

[0089] In Example 15, the main content of Example 9 may optionally include: the one or more microfluidic channels include at least one first microfluidic channel and one second microfluidic channel, and wherein a first cross-sectional area of ​​the first microfluidic channel that is perpendicular to a first flow direction at a first internal portion of the first microfluidic channel is different from a second cross-sectional area of ​​the second microfluidic channel that is perpendicular to a second flow direction at a second internal portion of the second microfluidic channel.

[0090] In Example 16, the main content of Example 9 may optionally include: a first cross-sectional area in one or more microfluidic channels that is perpendicular to a first flow direction at one inlet of the intermediary is smaller than a second cross-sectional area in one or more microfluidic channels that is perpendicular to a second flow direction at one outlet of the intermediary, and the outlet is in fluid communication with the inlet of the intermediary.

[0091] Example 17 is an electronic system comprising a board; a power supply for providing power to one or more integrated circuit (IC) chips; an IC package coupled to the board and the power supply, the IC package including an integrated circuit stack including at least one first IC chip and a second IC chip; and a housing attached to the IC package, the housing including at least one inlet and at least one outlet, wherein the IC package further includes an intermediary attached between the first IC chip and the second IC chip, and one or more microfluidic channels passing through the intermediary and in fluid communication with at least one inlet and one outlet of the housing, and wherein a first side of the intermediary includes a plurality of first bonding pads equally coupled to a plurality of first bonding pads of the first IC chip, and a second side of the intermediary includes a plurality of second bonding pads equally coupled to a plurality of first bonding pads of the second IC chip.

[0092] In Example 18, the main content of Example 17 may optionally include: the intermediary is included as a bridge between the first IC chip and the second IC chip.

[0093] In Example 19, the main content of Example 17 further includes a pump coupled to at least one inlet and at least one outlet of the housing.

[0094] In Example 20, the main content of Example 19 may optionally further include: a heat dissipation device coupled between at least one outlet of the housing and the pump.

[0095] In Example 21, the main content of any of Examples 17 to 20 may optionally include: the intermediary includes a top portion attached to a bottom portion, wherein a first side of the top portion includes a plurality of first engagement pads, which are equally coupled to a plurality of first engagement pads on a first side of the bottom portion.

[0096] In Example 22, the main content of Example 21 may optionally include: only one of the top and bottom portions of the medium includes the one or more microfluidic channels.

[0097] In Example 23, the main content of Example 21 may optionally include: both of the top and bottom portions of the medium include individual portions of the one or more microfluidic channels.

[0098] In Example 24, the main content of any of Examples 17 to 23 may optionally include: at least one of the one or more microfluidic channels includes at least one heat dissipation structure protruding into the at least one microfluidic channel.

[0099] In Example 25, the main content of any of Examples 17 to 24 may optionally include: the one or more microfluidic channels include at least one first microfluidic channel and one second microfluidic channel, and wherein a first cross-sectional area of ​​the first microfluidic channel perpendicular to a first flow direction at a first internal portion of the first microfluidic channel is different from a second cross-sectional area of ​​the second microfluidic channel perpendicular to a second flow direction at a second internal portion of the second microfluidic channel.

[0100] In Example 26, the main content of any of Examples 17 to 25 may optionally include: a first cross-sectional area in one or more microfluidic channels that is perpendicular to a first flow direction at one inlet of the intermediary, which is smaller than a second cross-sectional area in one or more microfluidic channels that is perpendicular to a second flow direction at one outlet of the intermediary, and the outlet is in fluid communication with the inlet of the intermediary.

[0101] After several detailed embodiments of the present invention have been described in detail, it should be understood that the present invention as defined by the appended claims should not be limited to the specific details set forth in the above description, as there may be many obvious variations without departing from its spirit or scope. [Simplified Explanation of the Diagram]

[0006] The subject matter of this disclosure is specifically pointed out and clearly claimed in the concluding section of the specification. The foregoing description and other features of this disclosure will become more fully apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings. It should be understood that the accompanying drawings illustrate only some embodiments according to this disclosure and are therefore not to be considered as limiting the scope of this disclosure. This disclosure will be explained with additional specific content and detail through the use of the accompanying drawings to more readily identify the advantages of this disclosure, wherein:

[0007] Figures 1-6 are exemplary side views of individual integrated circuit packages according to several embodiments of the present description.

[0008] Figures 7A-D are a top view, a cross-sectional view (along line 7B), a front view and a rear view of a three-dimensional integrated circuit package according to one embodiment of this description.

[0009] Figure 8 is an exemplary side view of a liquid-cooled three-dimensional integrated circuit package according to one embodiment of the present description.

[0010] Figure 9 is a block diagram of an electronic system according to one embodiment of the present description.

[0011] Figure 10 is a block diagram of another electronic system according to one embodiment of this description.

[0012] Figure 11 is a side cross-sectional view of an integrated circuit package according to one embodiment of the present description.

[0013] Figures 12 and 13 are exemplary side views of a three-dimensional integrated circuit stack according to one embodiment of the present description.

[0014] Figures 14 and 15 are an exploded view and a perspective view illustrating another three-dimensional integrated circuit stack according to one embodiment of this description.

[0015] Figures 16 and 17 are exemplary perspective views of individual processes for manufacturing a three-dimensional integrated circuit stack according to one embodiment of the present description.

[0016] Figures 18-23 are side cross-sectional views of a process for manufacturing an integrated circuit package according to one embodiment of the present description.

[0017] Figures 24A-B are exemplary top and side cross-sectional views of an intermediary according to one embodiment of the present description.

[0018] Figure 25 is an illustrative top view of another intermediary according to one embodiment of this description.

[0019] Figure 26 is an electronic system according to one embodiment of this description.

Claims

1. A multi-chip device comprising: an interposer; one or more microfluidic channels through the interposer; a first integrated circuit (IC) chip attached to a first side of the interposer; and a second IC chip attached to a second side of the interposer, wherein the first side of the interposer includes a plurality of first bonding pads equally coupled to a plurality of bonding pads of the first IC chip, and the second side of the interposer includes a plurality of second bonding pads equally coupled to a plurality of bonding pads of the second IC chip, and wherein the interposer includes a top portion attached to a bottom portion, wherein a first side of the top portion includes a plurality of bonding pads equally coupled to a plurality of bonding pads on a first side of the bottom portion facing the top portion.

2. The multi-chip device as claimed in claim 1, wherein the intermediary includes one or more metal vias between the first IC chip and the second IC chip.

3. The multi-chip device of claim 1, wherein the bonding pads on the first side of the top portion are mixed-bonded to the bonding pads on the first side of the bottom portion.

4. The multi-chip device as claimed in claim 1, wherein the top portion and the bottom portion of the intermediate each include individual portions of the one or more microfluidic channels.

5. The multi-chip device of any one of claims 1 to 4, further comprising: at least one heat dissipation structure protruding into one of the one or more microfluidic channels.

6. A multi-chip device as claimed in any one of claims 1 to 4, wherein the one or more microfluidic channels include a first microfluidic channel and a second microfluidic channel, and wherein a first cross-sectional area of ​​the first microfluidic channel perpendicular to a first flow direction at a first internal portion of one of the first microfluidic channels is different from a second cross-sectional area of ​​the second microfluidic channel perpendicular to a second flow direction at a second internal portion of one of the second microfluidic channels.

7. A multi-chip device as claimed in any of claims 1 to 4, wherein a first cross-sectional area of ​​the one or more microfluidic channels perpendicular to a first flow direction at an inlet of the intermediary is smaller than a second cross-sectional area of ​​the one or more microfluidic channels perpendicular to a second flow direction at an outlet of the intermediary, the outlet being in fluid communication with the inlet of the intermediary.

8. The multi-chip device of claim 1, further comprising: an IC package including the intermediary, the first IC chip and the second IC chip; and a housing attached to the IC package, the housing including at least one inlet and at least one outlet.

9. The multi-chip device of claim 8 further includes: a plate coupled to the IC package; and a power supply for providing power to the first IC chip and / or the second IC chip.

10. The multi-chip device of claim 8, further comprising: a pump coupled to the at least one inlet and the at least one outlet of the housing; and / or a temperature monitor on the first IC chip and circuitry coupled to the temperature monitor for controlling a flow rate of fluid through the one or more microfluidic channels.

11. A multi-chip device comprising: one or more microfluidic channels through an intermediary, the intermediary including a first portion attached to a second portion, wherein a first side of the first portion includes a plurality of bonding pads equally coupled to a plurality of bonding pads on the first side of the second portion; a first integrated circuit (IC) chip including a plurality of bonding pads attached to a second side of the first portion, the second side of the first portion being opposite to the first side of the first portion; and a second IC chip including a plurality of bonding pads attached to a second side of the second portion, the second side of the second portion being opposite to the first side of the second portion.

12. The multi-chip device as claimed in claim 11, wherein the intermediary includes one or more metal vias between the first IC chip and the second IC chip.

13. The multi-chip device of claim 11, wherein the bonding pads on the first side of the first portion are mixed-bonded to the bonding pads on the first side of the second portion.

14. The multi-chip device as claimed in claim 11, wherein the first portion and the second portion of the intermediate each include individual portions of the one or more microfluidic channels.

15. The multi-chip device of any one of claims 11 to 14, further comprising: at least one heat dissipation structure protruding into one of the one or more microfluidic channels.

16. A multi-chip device as claimed in any one of claims 11 to 14, wherein the one or more microfluidic channels include a first microfluidic channel and a second microfluidic channel, and wherein a first cross-sectional area of ​​the first microfluidic channel perpendicular to a first flow direction at a first internal portion of one of the first microfluidic channels is different from a second cross-sectional area of ​​the second microfluidic channel perpendicular to a second flow direction at a second internal portion of one of the second microfluidic channels.

17. A multi-chip device as claimed in any of claims 11 to 14, wherein a first cross-sectional area of ​​the one or more microfluidic channels perpendicular to a first flow direction at an inlet of the intermediary is smaller than a second cross-sectional area of ​​the one or more microfluidic channels perpendicular to a second flow direction at an outlet of the intermediary, the outlet being in fluid communication with the inlet of the intermediary.

18. The multi-chip device of claim 11, further comprising: an IC package including the intermediary, the first IC chip and the second IC chip; and a housing attached to the IC package, the housing including at least one inlet and at least one outlet.

19. The multi-chip device of claim 18, further comprising: a plate coupled to the IC package; and a power supply for providing power to the first IC chip and / or the second IC chip.

20. The multi-chip device of claim 18, further comprising: a pump coupled to the at least one inlet and the at least one outlet of the housing; and / or a temperature monitor on the first IC chip and circuitry coupled to the temperature monitor for controlling a flow rate of fluid through the one or more microfluidic channels.

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