Semiconductor device and method of manufacturing the same

Abstract

In a semiconductor device, a first stack is located above a substrate and includes a first pair of transistors and a second pair of transistors stacked above the substrate. A second stack is located above the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked above the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is adjacent to the first capacitor and stacked with the first and second stacks. The first set of transistors in the first and second stacks are coupled to each other to form a static random access memory (DRAM) cell. The second set of transistors in the first and second stacks are coupled to the first and second capacitors to form a first dynamic random access memory (DRAM) cell and a second DRAM cell.

Description

[Technical Field]

[0001] This disclosure relates to microelectronic components, including semiconductor elements, transistors, and integrated circuits, including microfabrication methods. [Cross-reference to related applications]

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 161,538, filed March 16, 2021, and U.S. Patent Application No. 17 / 644,982, filed December 17, 2021, the full contents of which are incorporated herein by reference. [Previous Technology]

[0003] In the fabrication of semiconductor devices (especially at the microscale), various fabrication processes are performed, such as film deposition, etch mask formation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device components on a substrate. Historically, using microfabrication, transistors have been fabricated in a plane, with wiring / metallization systems formed above the active device plane, thus characterized as two-dimensional (2D) circuits or 2D fabrication. Miniaturization efforts have significantly increased the number of transistors per unit area in 2D circuits, but as miniaturization enters the single-digit nanometer semiconductor device fabrication node, miniaturization efforts are facing greater challenges. Semiconductor device manufacturers have expressed a demand for three-dimensional (3D) semiconductor circuits with transistors stacked on top of each other. [Summary of the Invention]

[0004] The techniques described herein include novel memory cells. One embodiment includes a memory cell containing a single SRAM bit cell and two DRAM cells for a total of three bits of storage. Another embodiment includes a space-efficient transistor layout to implement a three-bit storage cell in the same footprint as a single SRAM bit cell (in CFET technology). Another embodiment includes efficient use of the space beneath the memory cell for DRAM capacitors (in CFET technology with buried power rails).

[0005] Of course, the order in which the different steps are discussed herein is presented for clarity. Generally speaking, these steps can be performed in any suitable order. Furthermore, while each of the different features, techniques, configurations, etc., may be discussed in different places within this disclosure, it should be noted that each concept can be implemented independently of or in combination with each other. Accordingly, the present invention can be implemented and viewed in many different ways.

[0006] It should be noted that this summary does not explicitly describe every embodiment and / or incremental novel aspects of the disclosed invention or the claimed invention. Rather, this summary only provides a preliminary discussion of different embodiments and corresponding novel aspects relative to the prior art. For additional details and / or possible perspectives regarding the invention and its embodiments, please refer to the following further discussion of the implementation methods of this disclosure and the corresponding drawings.

[0007] According to one aspect of this disclosure, a semiconductor device is provided. The semiconductor device may include a first transistor stack located above a top surface of a substrate. The first transistor stack may include a first pair of transistors and a second pair of transistors stacked above the substrate. The semiconductor device may include a second transistor stack located above the top surface of the substrate and adjacent to the first transistor stack. The second transistor stack may include a third pair of transistors and a fourth pair of transistors stacked above the substrate. The semiconductor device may include a first capacitor stacked with the first transistor stack and the second transistor stack. The semiconductor device may also include a second capacitor adjacent to the first capacitor and stacked with the first transistor stack and the second transistor stack. In this semiconductor device, a first group of transistors in the first transistor stack and the second transistor stack may be coupled to each other to form a static random access memory (SRAM) cell. Furthermore, a second set of transistor systems in the first transistor stack and the second transistor stack is coupled to the first capacitor and the second capacitor to form a first dynamic random access memory (DRAM) cell and a second DRAM cell, wherein the first DRAM cell and the second DRAM cell are stacked and coupled to the SRAM cell.

[0008] In some embodiments, the first pair of transistors may include a first transistor and a second transistor above the substrate. The second pair of transistors may include a third transistor and a fourth transistor above the second transistor. The third pair of transistors may include a fifth transistor and a sixth transistor above the fifth transistor above the substrate, and the fourth pair of transistors may include a seventh transistor and an eighth transistor above the sixth transistor.

[0009] In some embodiments, each of the transistors in the first and second stacks may include one or more channel regions and a gate region. The one or more channel regions may extend along a horizontal direction parallel to the top surface of the substrate, be stacked above the substrate along a vertical direction perpendicular to the top surface of the substrate, and be spaced apart from each other. The gate region may surround the one or more channel regions.

[0010] In some embodiments, the first group of transistors in the first transistor stack and the second transistor stack may include the second, third, fourth, sixth, seventh, and eighth transistors. The second group of transistors in the first transistor stack and the second transistor stack may include the first and fifth transistors.

[0011] In some embodiments, the first capacitor may have a trench shape extending from the top surface of the substrate into the substrate and located within the substrate. The second capacitor may have a trench shape extending from the top surface of the substrate into the substrate and located within the substrate. The first capacitor may be coupled to the first transistor to form the first DRAM cell, and the second capacitor may be coupled to the fifth transistor to form the second DRAM cell.

[0012] The second transistor may be an n-type transistor, and the third transistor may be a p-type transistor, wherein the second and third transistors may form a first inverter structure of one of the SRAM cells. The sixth transistor may be an n-type transistor, and the seventh transistor may be a p-type transistor, wherein the sixth and seventh transistors may form a second inverter structure of one of the SRAM cells. The first inverter structure and the second inverter structure may be cross-coupled. The fourth transistor may be an n-type transistor serving as a first access transistor of one of the SRAM cells and coupled to the first inverter structure, and the eighth transistor may be an n-type transistor serving as a second access transistor of one of the SRAM cells and coupled to the second inverter structure.

[0013] The semiconductor device may include a first buried power rail (BPR) located in the substrate, adjacent to and coupled to the first capacitor, and having a source power supply voltage (VSS) applied to it. The semiconductor device may include a second BPR located in the substrate, coupled to a source region of the third transistor and a source region of the seventh transistor, and having a drain power supply voltage (VDD) applied to it. The semiconductor device may also include a third BPR located in the substrate, adjacent to and coupled to the second capacitor, and having the VSS applied to it. In some embodiments, the second BPR may be disposed between the first and third BPRs.

[0014] The semiconductor device may include a first interconnect structure serving as a first bit line and coupled to a source region of the first transistor and a source region of the fourth transistor. The semiconductor device may include a second interconnect structure serving as a second bit line and coupled to a source region of the fifth transistor and a source region of the eighth transistor. The semiconductor device may include a third interconnect structure serving as a word line of the SRAM cell and coupled to a gate region of the fourth transistor and a gate region of the eighth transistor. The semiconductor device may include a fourth interconnect structure serving as a word line of the first DRAM cell and coupled to a gate region of the first transistor. The semiconductor device may also include a fifth interconnect structure serving as a word line of the second DRAM cell and coupled to a gate region of the fifth transistor.

[0015] In some embodiments, the first group of transistors in the first transistor stack and the second transistor stack may include the first, second, third, fifth, sixth, and seventh transistors. The second group of transistors in the first transistor stack and the second transistor stack may include the fourth and eighth transistors.

[0016] In some embodiments, the first transistor may be an n-type transistor, and the second transistor may be a p-type transistor, wherein the first and second transistors may form a first inverter structure of one of the SRAM cells. The fifth transistor may be an n-type transistor, and the sixth transistor may be a p-type transistor, wherein the fifth and sixth transistors may form a second inverter structure of one of the SRAM cells. The first inverter structure and the second inverter structure may be further cross-coupled. The third transistor may be an n-type transistor serving as a first access transistor of one of the SRAM cells and coupled to the first inverter structure, and the seventh transistor may be an n-type transistor serving as a second access transistor of one of the SRAM cells and coupled to the second inverter structure.

[0017] In some embodiments, the first capacitor may be located above the fourth transistor and has one of a trench shape extending in the vertical direction and one of a plate shape extending in the horizontal direction. The second capacitor may be located above the eighth transistor and has one of a trench shape extending in the vertical direction and one of a plate shape extending in the horizontal direction. The first capacitor may be coupled to the fourth transistor to form the first DRAM cell, and the second capacitor may be coupled to the eighth transistor to form the second DRAM cell.

[0018] The semiconductor device may further include a first interconnect structure serving as a first bit line and coupled to a source region of the third transistor and a source region of the fourth transistor. The semiconductor device may include a second interconnect structure serving as a second bit line and coupled to a source region of the seventh transistor and a source region of the eighth transistor. The semiconductor device may include a third interconnect structure serving as a word line of the SRAM cell and coupled to a gate region of the third transistor and a gate region of the seventh transistor. The semiconductor device may include a fourth interconnect structure serving as a word line of the first DRAM cell and coupled to a gate region of the fourth transistor. The semiconductor device may include a fifth interconnect structure serving as a word line of the second DRAM cell and coupled to a gate region of the eighth transistor.

[0019] In some embodiments, the semiconductor device may include a first BPR located in the substrate, coupled to the first capacitor, and having the VSS applied. The semiconductor device may include a second BPR located in the substrate, coupled to a source region of the second transistor and a source region of the sixth transistor, and having the VDD applied. The semiconductor device may also include a third BPR located in the substrate, coupled to the second capacitor, and having the VSS applied. In some embodiments, the second BPR may be disposed between the first and third BPRs.

[0020] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. In this method, a first transistor stack may be formed above a top surface of a substrate, wherein the first transistor stack may include a first pair of transistors and a second pair of transistors stacked above the substrate. A second transistor stack may be formed above the substrate and adjacent to the first transistor stack, wherein the second transistor stack may include a third pair of transistors and a fourth pair of transistors stacked above the substrate. A first capacitor may be formed to be stacked with the first transistor stack and the second transistor stack. A second capacitor may be formed to be adjacent to the first capacitor and to be stacked with the first transistor stack and the second transistor stack. A first group of transistors in the first transistor stack and the second transistor stack may be coupled to each other to form an SRAM cell. In the first transistor stack and the second transistor stack, a second group of transistors can be coupled to the first capacitor and the second capacitor to form a DRAM cell and a second DRAM cell, which are stacked and coupled to the SRAM cell.

[0021] In some embodiments, the first pair of transistors may include a first transistor and a second transistor above the substrate. The second pair of transistors may include a third transistor and a fourth transistor above the second transistor. The third pair of transistors may include a fifth transistor and a sixth transistor above the fifth transistor. The fourth pair of transistors may include a seventh transistor and an eighth transistor above the sixth transistor.

[0022] In some embodiments, each of the transistors in the first and second stacks may include one or more channel regions and a gate region. The one or more channel regions may extend along a horizontal direction parallel to the top surface of the substrate, be stacked above the substrate along a vertical direction perpendicular to the top surface of the substrate, and be spaced apart from each other. The gate region may surround the one or more channel regions.

[0023] To form the first and second capacitors, the first capacitor may be formed having a trench shape, extending from the top surface of the substrate into the substrate, and located in the substrate. The second capacitor may be formed having a trench shape, extending from the top surface of the substrate into the substrate, and located in the substrate. The first capacitor may be coupled to the first transistor to form the first DRAM cell, and the second capacitor may be coupled to the fifth transistor to form the second DRAM cell.

[0024] In some embodiments, the second transistor may be an n-type transistor, and the third transistor may be a p-type transistor, wherein the second and third transistors may form a first inverter structure of one of the SRAM cells. The sixth transistor may be an n-type transistor, and the seventh transistor may be a p-type transistor, wherein the sixth and seventh transistors may form a second inverter structure of one of the SRAM cells. The first inverter structure and the second inverter structure may be further cross-coupled. The fourth transistor may be an n-type transistor serving as a first access transistor of one of the SRAM cells and coupled to the first inverter structure, and the eighth transistor may be an n-type transistor serving as a second access transistor of one of the SRAM cells and coupled to the second inverter structure.

[0025] In this method, a first BPR may be formed in the substrate, adjacent to and coupled to the first capacitor, and having the VSS applied. A second BPR may be formed in the substrate, coupled to a source region of the third transistor and a source region of the seventh transistor, and having the VDD applied. A third BPR may be formed in the substrate, adjacent to and coupled to the second capacitor, and having the VSS applied. In some embodiments, the second BPR may be disposed between the first and third BPRs.

[0026] In this method, a first interconnect structure can be formed as a first bit line and coupled to a source region of the first transistor and a source region of the fourth transistor. A second interconnect structure can be formed as a second bit line and coupled to a source region of the fifth transistor and a source region of the eighth transistor. A third interconnect structure can be formed as a word line of the SRAM cell and coupled to a gate region of the fourth transistor and a gate region of the eighth transistor. A fourth interconnect structure can be formed as a word line of the first DRAM cell and coupled to a gate region of the first transistor. A fifth interconnect structure can be formed as a word line of the second DRAM cell and coupled to a gate region of the fifth transistor.

Implementation Method

[0034] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and not limitations. Furthermore, in the various examples of this disclosure, component symbols and / or letters may be repeated. This repetition is for simplification and clarity and does not in itself limit the relationship between the various embodiments and / or configurations discussed.

[0035] Furthermore, for ease of explanation, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature shown in the figure and another element or feature. The purpose of these spatial relative terms is to indicate that, in use or operation, in addition to the orientation shown in the figure, different orientations of the device are also included. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative terms used herein can be interpreted similarly accordingly.

[0036] Throughout the specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, material, or characteristic described with respect to that embodiment is included in at least one embodiment, but does not imply that it exists in every embodiment. Therefore, the phrase "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular feature, structure, material, or characteristic may be combined in any suitable manner.

[0037] The technology described herein includes a novel combination of an SRAM cell and two DRAM bit cells, with a space-efficient layout. Static Random Access Memory (SRAM) cells are well known. A conventional SRAM bit cell consists of a cross-coupled pair of inverters to provide electrically stable circuitry for storing one bit of data. The pair of inverters is connected to two bit line signals (e.g., BL, BLB) using two separate transistors. This is commonly referred to as a hexatransistor or "6T" bit cell. An exemplary schematic circuit diagram of SRAM cell 100 can be shown in FIG1. ​​As shown in FIG1, SRAM cell 100 may include an n-type transistor M2 and a p-type transistor M3 that can form a first inverter 102. SRAM cell 100 may include an n-type transistor M0 and a p-type transistor M1 that can form a second inverter 104. The first inverter 102 and the second inverter 104 may be cross-coupled. For example, the gate terminals of transistor M3 and transistor M2 can be coupled to the drain terminals of transistor M1 and transistor M0. The gate terminals of transistor M1 and transistor M0 can be coupled to the drain terminals of transistor M3 and transistor M2. The SRAM cell 100 may also include a first access transistor M4 and a second access transistor M5. Transistor M4 may be an n-type transistor and coupled to a first inverter 102. Transistor M5 may be an n-type transistor and coupled to a second inverter 104. The SRAM cell may also include a first bit line BL 106 and a second bit line BLB, whereby the first bit line BL 106 is coupled to the source terminal of transistor M4, and the second bit line BLB is coupled to the source terminal of transistor M5. SRAM cell 100 may include word lines WLS 110 coupled to the gate terminals of transistor M4 and transistor M5 to control transistors M4 and M5. Operating voltages may be applied to SRAM cell 100. For example, a drain supply voltage (VDD) may be applied to the source terminals of transistor M3 and transistor M1. A source supply voltage (VSS) may be applied to the source terminals of transistor M2 and transistor M0.

[0038] Dynamic Random Access Memory (DRAM) cells are also well known. A conventional DRAM cell may include a single transistor connected to a capacitor. An exemplary schematic diagram of a DRAM cell 200 may be shown in FIG2. As shown in FIG2, the DRAM cell 200 may include an access transistor M6 and a capacitor 202 coupled to each other. For example, the source terminal of transistor M6 may be coupled to the positive terminal of capacitor 202. The DRAM cell 200 may also include a word line 206 coupled to the gate terminal of M6 and a bit line 204 coupled to the source terminal of transistor M6. The negative terminal of capacitor 202 may be further coupled to VSS. In a memory cell, the word line provides current to select which row of bits (or memory cells) to read or write. The bit line either reads the bits (or memory cells) on the corresponding word line or allows current applied to the bit line to program the bits (or memory cells). Thus, by acting on the word line and the bit line, a specific cell is selected for reading or writing.

[0039] Typically, both SRAM and DRAM cells are used in the cache hierarchy or level in a computing system (e.g., a microprocessor). The fastest (SRAM) cells are very close to the computing elements of the processor, while DRAM cells are used in some lower levels, such as Level 3 cache.

[0040] A typical processor cache subsystem may have SRAM caches as Level 1 and Level 2, and DRAM caches as Level 3. A Level 1 cache miss (e.g., an attempt to access a data element that does not exist in the cache) may force a fetch from the Level 2 cache. A Level 2 cache miss may force a fetch from the Level 3 cache. Although the details differ between processors, it is quite common for L1, L2, and L3 cache access times to have ratios of 1 to 10 to 100. For example, an L1 cache miss may result in a 10-fold time penalty. It should be understood that the time penalty increases with the cache level.

[0041] Significant efforts have been required to optimize the size and speed of the cache subsystem for a particular processor. However, processor performance is limited by the so-called "memory wall," which is the ever-growing speed gap between the CPU and the memory outside the CPU chip. A key factor in the memory wall is the speed / density trade-off between SRAM and DRAM cells. Even a small (single-digit percentage) reduction in the area of ​​an SRAM cell can result in a larger cache size and can have a dramatic impact on overall processor performance. Therefore, one objective of this disclosure is to introduce a new memory cell that combines a single SRAM cell with two DRAM cells in a space-efficient layout.

[0042] Figure 3 illustrates a circuit diagram of the memory cell 300 disclosed herein. As shown in Figure 3, the memory cell 300 can be formed based on a combination of an SRAM cell 300A and two DRAM cells 300B and 300C. The SRAM cell 300A can be the same as the SRAM cell 100 in Figure 1, and the two DRAM cells 300B and 300C can be the same as the DRAM cell 200 in Figure 2. In addition, the memory cell 300 may include a first word line WLS 302, a second word line WLB1 304, and a third word line WLB2 306. The first word line WLS 302 is coupled to the gate terminals of transistor M4 and transistor M5, the second word line WLB1 304 is coupled to the gate terminal of transistor M6, and the third word line WLB2 306 is coupled to the gate terminal of transistor M7. The memory cell 300 may also include a first bit line BL 308 and a second bit line BLB 310, with the first bit line BL 308 coupled to the source terminals of transistor M6 and transistor M4, and the second bit line BLB 310 coupled to the source terminals of transistor M7 and transistor M5.

[0043] The SRAM and DRAM elements (e.g., 300A, 300B, and 300C) designed herein can operate in the same manner as conventional and discrete SRAM and DRAM elements. Detailed operation of memory cell 300 can be described as follows. During static operation (e.g., when there is no activity in memory cells 300A-300C), word lines WLS 302, WLB1 304, and WLB2 306 can be held at ground. For read / write operations of SRAM bit cell (or SRAM cell) 300A, the first word line WLS 302 can be held at VDD, and the first bit line BL 308 and the second bit line BLB 310 can be adjusted as normally performed by an SRAM cell. For read / write operations of DRAM cells 300B and 300C, one or both of word lines WLB1 304 and WLB2 306 can be held at VDD. The first bit line BL 308 can be used to read or write the value of DRAM cell 300B, and the second bit line BLB 310 can be used to read or write the value of DRAM cell 300C.

[0044] It should be noted that the memory cell 300 may further include support circuitry for operation. For example, the memory cell 300 may include a precharge circuit and a sense amplifier circuit. The precharge circuit precharges the bit lines to VDD to speed up read and write operations. The sense amplifier circuit is configured to detect what value is stored in the SRAM or DRAM cell during a read operation and display that value at an output. The memory cell 300 may be further coupled to a row decoder, column decoder, or other support circuitry. The row decoder and column decoder can assist in identifying specific SRAM or DRAM cells for operation.

[0045] Please note that various cell layouts can be used. Also note that while specific technology definitions are used to illustrate the embodiments herein, the technologies described herein can be applied to other stackable device technologies. The embodiments described herein can be used with a CFET 3.4 device configuration, where 3 represents 3 nm manufacturing technology and 4 can represent a dual-stacked CFET including four transistors. Furthermore, each of the four transistors can include one or more (e.g., two) nanosheets as channel regions, and buried power rails (BPRs) can be located below the dual-stacked CFET. The nanosheets in the dual-stacked CFET can be designed as NMOS or PMOS. Figure 4 shows a perspective view of a dual-stacked CFET formed using CFET 3.4 technology.

[0046] As shown in FIG. 4, the transistor stack (or stack) 400 may include a first CFET 400A stacked above the substrate 402 and a second CFET 400B stacked above the first CFET 400A. The first CFET 400A may include a first transistor 400A_1 and a second transistor 400A_2 stacked above the substrate 402. The second CFET 400B may include a third transistor 400B_1 and a fourth transistor 400B_2 stacked above the first CFET 400A. Each transistor in the stack 400 may include a two-nanometer wafer that serves as a channel region and extends along a direction parallel to the substrate 402 (e.g., the Y direction). For example, the first transistor 400A_1 may include two-nanometer wafers 404 stacked above the substrate 402 and spaced apart from each other. Of course, FIG. 4 is only an example, and each transistor may include any number of nanometer wafers based on the device design.

[0047] Referring again to FIG4, each of CFETs 400A and 400B may also include a gate region surrounding a nanosheet (or channel region) of the transistor. For example, the first CFET 400A may include a gate region 418 surrounding nanosheets (or channel regions) 404 and 406, respectively. The second CFET 400B may include a gate region 420 surrounding nanosheets 408 and 410, respectively. The gate region may include a barrier layer, a work function layer, and a gate filler. The stack 400 may further include a plurality of metal lines (or interconnect structures) 412 located above the second CFET 400B and coupled to the transistors (e.g., 400A_1, 400A_2, 400B_1, and 400B_2). Depending on the circuit design, the metal lines (or interconnect structures) 412 may serve as the bit lines (e.g., 308 and 310) and word lines (302-306) shown in FIG. 3. The stack 400 may further include buried power rails (BPRs) 414 and 416 located in the substrate 402 and providing operating voltages (e.g., VDD and VSS). In some embodiments, the stack 400 may include one or more deep trench capacitors 422-424 located in the substrate 402 and configured adjacent to the BPRs.

[0048] Depending on the circuit design, the transistors in the stack 400 can be n-type or p-type. In an exemplary embodiment, transistors 400A_1, 400A_2, and 400B_2 can be n-type, and transistor 400B_1 can be p-type. Of course, depending on the circuit design, transistors 400A_1, 400A_2, and 400B_2 can be p-type, and 400B_1 can also be n-type.

[0049] In a related example, a given SRAM bit cell formed by CFET 3.4 technology can use a stack of two adjacent 3.4 elements (or a stack of two transistors formed by CFET 3.4 technology), for a total of eight elements (or transistors). Each of the two 3.4 element stacks can have characteristics similar to stack 400. However, in the two 3.4 stacks, only six of the eight elements are needed for the operation of the SRAM cell, and two of the eight elements will be unused. In this disclosure, the two unused transistors can be used to form the DRAM cell shown in FIG. 3. Therefore, the memory cell shown in FIG. 3, including the SRAM cell and the two DRAM cells, can be formed by CFET 3.4 technology.

[0050] FIG5 shows a first exemplary cross-sectional layout (or layout) 500 of the memory cell 300 shown in FIG3. As shown in FIG5, the memory cell 300 may be formed based on a stack (or stack) of two transistors 500A and 500B. Each of the stacks 500A and 500B may have a configuration similar to that of the stack 400. The stack 500A may include a first CFET and a second CFET, the first CFET including a first pair of transistors 500_1 above the substrate 501, and the second CFET including a second pair of transistors 500_2 above the first pair of transistors 500_1. The first pair of transistors 500_1 may include a first transistor M6 above the substrate 501 and a second transistor M2 above the first transistor M6. The second pair of transistors 500_2 includes a third transistor M3 above the second transistor M2 and a fourth transistor M4 above the third transistor M3. Stack 500B may include a third CFET and a fourth CFET. The third CFET includes a third pair of transistors 500_3 above the substrate 501, and the fourth CFET includes a fourth pair of transistors 500_4 above the third pair of transistors 500_3. The third pair of transistors 500_3 may include a fifth transistor M7 above the substrate 501 and a sixth transistor M0 above the first transistor M7. The fourth pair of transistors 500_4 may include a seventh transistor M1 above the sixth transistor M0 and an eighth transistor M5 above the seventh transistor M1. Furthermore, layout 500 may include a first BPR 502 with an applied operating voltage VSS, a second BPR 504 with an applied operating voltage VDD, and a third BPR 506 with an applied operating voltage VSS. In some embodiments, the second BPR 504 may be configured between the first and second BPRs 502 and 506.

[0051] Furthermore, in layout 500, the first capacitor C1 and the second capacitor C2 can be deep trench capacitors adjacent to the first BPR 502 and the third BPR 506, respectively. The positive polarity of the first capacitor C1 can be coupled to the source terminal of the first transistor M6, and the negative polarity of the first capacitor C1 can be coupled to the first BPR 502 to which an operating voltage VSS is applied. The positive polarity of the second capacitor C2 can be coupled to the source terminal of the fifth transistor M7, and the negative polarity of the second capacitor C2 can be coupled to the third BPR 506 to which an operating voltage VSS is applied. In addition, the second BPR 504 can be coupled to the source terminals of the third transistor M3 and the seventh transistor M1, and is applied with VDD. The source terminals of the second transistor M2 and the sixth transistor M0 can be coupled to one of the first and third BPRs 502 and 506 to which an operating voltage VSS is applied.

[0052] In some embodiments, transistors M0-M7 may have element parameters similar to those of transistors M0-M7 shown in FIG. 3 (e.g., width, length, and n-type / p-type). Capacitors C1 and C2 may have element parameters similar to those of capacitors C1 and C2 shown in FIG. 3 (e.g., size or capacitance value). Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 in stack 500A, and the sixth transistor M0, the seventh transistor M1, and the eighth transistor M5 in stack 500B, can form the SRAM cell 300A shown in FIG. 3. Furthermore, the second transistor M2 and the third transistor M3 in stack 500A can form the first inverter of SRAM cell 300A, and the sixth transistor M0 and the seventh transistor M1 in stack 500B can form the second inverter of SRAM cell 300A. As shown in FIG. 3, the first inverter and the second inverter are coupled to each other. Furthermore, in stack 500A, the first transistor M6 can be coupled to the first capacitor C1 to form the first DRAM cell 300B, and in stack 500B, the second transistor M7 can be coupled to the second capacitor C2 to form the second DRAM cell 300C. Similar to Figure 3, in stack 500A, the second transistor M2 and in stack 500B, the sixth transistor M0 can be coupled to one of the first BPR 502 and the third BPR 506, and are applied with an operating voltage VSS. In stack 500A, the third transistor M3 and in stack 500B, the seventh transistor M1 can be coupled to the second BPR 504, and are applied with an operating voltage VDD.

[0053] The cross-sectional layout diagram 500 of memory cell 300 may also include a plurality of interconnect structures (not shown), such as interconnect structure 412 in Figure 4, which may be located above the fourth transistor M4 and the eighth transistor M5. According to the circuit diagram shown in Figure 3, the interconnect structure may serve as bit lines (e.g., 308 and 310) and word lines (302-306) coupled to the corresponding transistors. Therefore, moving to the bottom element (e.g., M6 and M7) in the transistor stack (e.g., 500A and 500B) will have access elements (e.g., M6 and M7) of DRAM bit cells (or DRAM cells 300B and 300C). Above the DRAM bit cell access elements (e.g., M6 and M7), there are two elements (e.g., M2 and M3) that form cross-coupled inverters for SRAM cell 300A. At the top of the component stack are two SRAM access components (e.g., M4 and M5) for the BL and BLB signals.

[0054] Figure 5 also shows the locations of deep trench (DT) capacitors C1 and C2. The embedded power rails (VDD, VSS) 502-506 are part of the 3.4 technology. DT capacitors C1 and C2 for DRAM bit cells are shown as being adjacent to the VSS power rails (or BPR 502 and BPR 506), respectively. The 3.4 technology requires a very high aspect ratio (e.g., 40:1) structure to accommodate the capacitor sizes required for DRAM bit cells constructed beneath access elements (e.g., transistors M6 and M7).

[0055] FIG6 shows a second exemplary cross-sectional layout (or layout) 600 of the memory cell 300 shown in FIG3. Compared to layout 500, the capacitor in layout 600 may be located above the transistors instead of in the substrate. As shown in layout 600, the memory cell 300 may be formed based on a stack (or stack) of two transistors 600A and 600B. Stack 600A may include a first CFET and a second CFET, the first CFET including a first pair of transistors 600_1 above the substrate 601, and the second CFET including a second pair of transistors 600_2 above the first pair of transistors 600_1. The first pair of transistors 600_1 may include a first transistor M2 above the substrate 601 and a second transistor M3 above the first transistor M2. The second pair of transistors 600_2 includes a third transistor M4 above the second transistor M3 and a fourth transistor M6 above the third transistor M4. Stack 600B may include a third CFET and a fourth CFET. The third CFET includes a third pair of transistors 600_3 above the substrate 601, and the fourth CFET includes a fourth pair of transistors 600_4 above the third pair of transistors 600_3. The third pair of transistors 600_3 may include a fifth transistor M0 above the substrate 601 and a sixth transistor M1 above the first transistor M0. The fourth pair of transistors 600_4 may include a seventh transistor M5 above the sixth transistor M1 and an eighth transistor M7 above the seventh transistor M5. Furthermore, memory cell 300 may include a first power rail 602 with an applied operating voltage VSS, a second power rail 604 with an applied operating voltage VDD, and a third power rail 606 with an applied operating voltage VSS. In some embodiments, the second power rail 604 may be configured between the first and third power rails 602 and 606. The first power rail 602, the second power rail 604, and the third power rail 606 can be embedded power rails buried in the substrate 601. Furthermore, the first capacitor C1 can be located above the fourth transistor M6 in the stack 600A, and the second capacitor C2 can be located above the eighth transistor M7 in the stack 600B.

[0056] In some embodiments, transistors M0-M7 may have element parameters similar to those of transistors M0-M7 shown in FIG. 3 (e.g., width, length, and n-type / p-type). Capacitors C1 and C2 may have capacitance values ​​similar to those of capacitors C1 and C2 shown in FIG. 3. The first transistor M2, the second transistor M3, and the third transistor M4 in stack 600A, and the fifth transistor M0, the sixth transistor M1, and the seventh transistor M5 in stack 600B, may form the SRAM cell 300A shown in FIG. 3. Furthermore, the first transistor M2 and the second transistor M3 in stack 600A may form the first inverter of SRAM cell 300A, and the fifth transistor M0 and the sixth transistor M1 in stack 600B may form the second inverter of SRAM cell 300A. As shown in FIG. 3, the first inverter and the second inverter are coupled to each other. Furthermore, the fourth transistor M6 in stack 600A can be coupled to the first capacitor C1 to form the first DRAM cell 300B, and the eighth transistor M7 in stack 600B can be coupled to the second capacitor C2 to form the second DRAM cell 300C. Similar to Figure 3, the source terminal of the first transistor M2 in stack 600A and the source terminal of the fifth transistor M0 in stack 600B can be coupled to one of the first power rail 602 and the third power rail 606, and coupled to the operating voltage VSS. The source terminal of the second transistor M3 in stack 600A and the source terminal of the sixth transistor M1 in stack 600B can be coupled to the second power rail 604, and coupled to the operating voltage VDD. The positive terminal of the first capacitor C1 can be coupled to the source terminal of the fourth transistor M6, and the negative terminal of the first capacitor C1 can be coupled to one of the first power rail 602 and the third power rail 606 to which the voltage VSS is applied. The positive polarity of the second capacitor C2 can be coupled to the source terminal of the eighth transistor M7, and the negative polarity of the second capacitor C2 can be coupled to one of the first power rail 602 and the third power rail 606 on which a voltage VSS is applied.

[0057] It should be noted that power rails 602-604 may also be located above the first and second capacitors C1 and C2. The layout diagram 600 of the memory cell 300 may include a plurality of interconnect structures (not shown), such as interconnect structure 412 in FIG. 4, which may be located above the first and second capacitors C1 and C2. According to the circuit diagram shown in FIG. 3, the interconnect structure may serve as bit lines (e.g., 308 and 310) and word lines (302-306) coupled to the corresponding transistors. Furthermore, the first and second capacitors C1 and C2 may have structures different from those shown in FIG. 5. For example, in one embodiment, the first capacitor C1 and the second capacitor C2 may have a plate-like shape, such that the first capacitor C1 and the second capacitor C2 may be metal-insulating-metal capacitors (MIMCap) extending along the top surface of the substrate 601. In another embodiment, the first capacitor C1 and the second capacitor C2 may be stacked capacitors, such that the first capacitor C1 and the second capacitor C2 may still have a trench shape extending along a vertical direction perpendicular to the substrate, but formed in a dielectric stack. The dielectric stack may be located above the fourth and eighth transistors M6 and M7.

[0058] The novel memory cells (e.g., 300) described herein triple the memory capacity without exceeding the additional cell footprint of an SRAM cell. However, the required support circuitry will increase beyond that of a typical SRAM design. The design disclosed herein uses three word-line signals with associated address management. The bit-line and sense amplifier designs are configured to meet the electrical requirements of both SRAM and DRAM cells for reading and writing. Finally, the entire array is configured to support the refresh requirements of the DRAM cells.

[0059] This novel memory cell can be used in a variety of ways in the cache subsystem. For example, when an SRAM bit cell includes a conventional L1 cache and two DRAM bits include a novel L2 cache. A cache miss in the L1 level of memory will force a read from L2. In a conventional system, this would result in a loss of 10 cycles. However, using the techniques described herein, L2 (e.g., DRAM bits) is accessed in less than half the time (depending on other factors). Reducing L2 cache latency by approximately half can dramatically improve overall processor performance.

[0060] Understandably, many alternative configurations are considered herein. For example, the techniques described herein can be applied to other forms of memory in various stackable configurations, including MRAM (magnetoresistive random access memory), RRAM (resistive random access memory), etc. For those techniques that do not use BSP (back-side power supply), capacitors (e.g., MIMCap or stacked capacitors) on top of the SRAM can be used instead of DT capacitors. DRAM cells can be used both below and above SRAM cells. For example, DRAM cells can be located below the SRAM cell in Figure 5 and above the SRAM cell in Figure 6.

[0061] Specific details, such as the particular geometry of the processing system and the various components used therein, as well as the description of the processing, have been set forth in the foregoing description. However, it should be understood that the technology described herein can be implemented in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limiting purposes. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, specific numbers, materials, and configurations have been set forth to provide a complete understanding. Nevertheless, embodiments may be implemented without such specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and therefore any redundant description may be omitted.

[0062] Various techniques have been described as multiple separate operations to aid in understanding the various embodiments. The order of description should not be construed as implying that these operations are necessarily sequentially related. In fact, these operations do not need to be performed in the order stated. The operations may be performed in a different order than in the embodiments described. In additional embodiments, various additional operations may be performed, and / or the operations may be omitted.

[0063] As used herein, "substrate" or "target substrate" generally refers to an object processed according to the present invention. A substrate may contain any material portion or structure of an element, particularly a semiconductor or other electronic element, and may be, for example, a substrate structure, such as a semiconductor wafer, a photomask, or a layer, such as a thin film, on or covering a substrate structure. Therefore, a substrate is not limited to any particular substrate structure, underlayer or overlay, patterned or unpatterned, but is contemplated to include any such layer or substrate structure, and any combination of layers and / or substrate structures. The description may refer to specific types of substrates, but this is for illustrative purposes only.

[0064] Those skilled in the art will also understand that many variations can be made to the operation of the above-described technique, while still achieving the same objective of the present invention. Such variations should be covered by the scope of this disclosure. Therefore, the above description of the embodiments of the present invention is not restrictive. Any limitations of the embodiments of the present invention are presented in the following claims. [Simplified Explanation of the Diagram]

[0027] The nature of this disclosure can be best understood from the following embodiments and in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the various features are not drawn to scale. In practice, the dimensions of the various features may be enlarged or reduced for clarity of discussion.

[0028] Figure 1 is a schematic circuit diagram of a static random access memory (SRAM) memory cell according to certain embodiments.

[0029] Figure 2 is a schematic circuit diagram of a dynamic random access memory (DRAM) memory cell according to certain embodiments.

[0030] Figure 3 is a schematic circuit diagram of a memory cell based on a combination of SRAM memory cells and DRAM memory cells according to certain embodiments.

[0031] Figure 4 is a perspective view of a complementary field-effect transistor (CFET) structure according to certain embodiments.

[0032] Figure 5 is a cross-sectional view of a first exemplary memory cell based on a combination of SRAM memory cells and DRAM memory cells according to certain embodiments.

[0033] Figure 6 is a cross-sectional view of a second exemplary memory cell based on a combination of SRAM memory cells and DRAM memory cells according to certain embodiments.

Claims

1. A semiconductor element, comprising: A first transistor stack is located above a top surface of a substrate, the first transistor stack including a first pair of transistors and a second pair of transistors stacked on the substrate; a second transistor stack is located above the top surface of the substrate and adjacent to the first transistor stack, the second transistor stack including a third pair of transistors and a fourth pair of transistors stacked on the substrate; a first capacitor is stacked with the first transistor stack and the second transistor stack; and a second capacitor is adjacent to the first capacitor and stacked with the first transistor stack and the second transistor stack, wherein: a first group of transistor systems in the first transistor stack and the second transistor stack are coupled to each other to form a static random access memory (SRAM) cell, and a second group of transistor systems in the first transistor stack and the second transistor stack are coupled to the first capacitor and the second capacitor to form a first dynamic random access memory (DRAM) cell and a second DRAM cell, the first DRAM cell and the second DRAM cell being stacked and coupled to the SRAM cell.

2. The semiconductor device as claimed in claim 1, wherein: The first pair of transistors includes a first transistor and a second transistor above the substrate; the second pair of transistors includes a third transistor and a fourth transistor above the second transistor; the third pair of transistors includes a fifth transistor and a sixth transistor above the fifth transistor above the substrate; and the fourth pair of transistors includes a seventh transistor and an eighth transistor above the sixth transistor.

3. The semiconductor device as claimed in claim 2, wherein: Each of the transistors in the first and second transistor stacks includes (i) one or more channel regions that extend along a horizontal direction parallel to the top surface of the substrate, are stacked on the substrate along a vertical direction perpendicular to the top surface of the substrate, and are spaced apart from each other, and (ii) a gate region surrounding the one or more channel regions.

4. The semiconductor device as described in claim 3, wherein: The first group of transistors in the first transistor stack and the second transistor stack includes the second, third, fourth, sixth, seventh and eighth transistors, and the second group of transistors in the first transistor stack and the second transistor stack includes the first and fifth transistors.

5. The semiconductor device as described in claim 4, wherein: The first capacitor has a trench shape, extends from the top surface of the substrate into the substrate, and is located in the substrate. The second capacitor has a trench shape, extends from the top surface of the substrate into the substrate, and is located in the substrate. The first capacitor is coupled to the first transistor to form the first DRAM cell, and the second transistor is coupled to the fifth transistor to form the second DRAM cell.

6. The semiconductor device as claimed in claim 5, wherein: The second transistor system is an n-type transistor, the third transistor system is a p-type transistor, and the second and third transistor systems form a first inverter structure of one of the SRAM cells. The sixth transistor system is an n-type transistor, the seventh transistor system is a p-type transistor, and the sixth and seventh transistor systems form a second inverter structure of one of the SRAM cells. The first inverter structure and the second inverter structure are cross-coupled. The fourth transistor system is an n-type transistor, which serves as a first access transistor of one of the SRAM cells and is coupled to the first inverter structure. The eighth transistor system is an n-type transistor, which serves as a second access transistor of one of the SRAM cells and is coupled to the second inverter structure.

7. The semiconductor device as described in claim 5 further includes: A first embedded power rail (BPR) is located in the substrate, adjacent to and coupled to the first capacitor, and is supplied with a source power supply voltage (VSS); a second BPR is located in the substrate, coupled to a source region of the third transistor and a source region of the seventh transistor, and is supplied with a drain power supply voltage (VDD); and a third BPR is located in the substrate, adjacent to and coupled to the second capacitor, and is supplied with the VSS.

8. The semiconductor device as described in claim 6 further includes: A first interconnect structure serves as a first bit line and is coupled to a source region of the first transistor and a source region of the fourth transistor; a second interconnect structure serves as a second bit line and is coupled to a source region of the fifth transistor and a source region of the eighth transistor; a third interconnect structure serves as a word line of the SRAM cell and is coupled to a gate region of the fourth transistor and a gate region of the eighth transistor; a fourth interconnect structure serves as a word line of the first DRAM cell and is coupled to a gate region of the first transistor; and a fifth interconnect structure serves as a word line of the second DRAM cell and is coupled to a gate region of the fifth transistor.

9. The semiconductor device as claimed in claim 3, wherein: The first group of transistors in the first transistor stack and the second transistor stack includes the first, second, third, fifth, sixth and seventh transistors, and the second group of transistors in the first transistor stack and the second transistor stack includes the fourth and eighth transistors.

10. The semiconductor device as claimed in claim 9, wherein: The first transistor system is an n-type transistor, the second transistor system is a p-type transistor, and the first and second transistor systems form a first inverter structure of one of the SRAM cells. The fifth transistor system is an n-type transistor, the sixth transistor system is a p-type transistor, and the fifth and sixth transistor systems form a second inverter structure of one of the SRAM cells. The first inverter structure and the second inverter structure are cross-coupled. The third transistor system is an n-type transistor, which serves as a first access transistor of one of the SRAM cells and is coupled to the first inverter structure. The seventh transistor system is an n-type transistor, which serves as a second access transistor of one of the SRAM cells and is coupled to the second inverter structure.

11. The semiconductor device as claimed in claim 10, wherein: The first capacitor is located above the fourth transistor and has one of a trench shape extending in the vertical direction and one of a plate shape extending in the horizontal direction. The second capacitor is located above the eighth transistor and has one of a trench shape extending in the vertical direction and one of a plate shape extending in the horizontal direction. The first capacitor is coupled to the fourth transistor to form the first DRAM cell, and the second capacitor is coupled to the eighth transistor to form the second DRAM cell.

12. The semiconductor device as claimed in claim 11 further includes: A first interconnect structure serves as a first bit line and is coupled to a source region of the third transistor and a source region of the fourth transistor; a second interconnect structure serves as a second bit line and is coupled to a source region of the seventh transistor and a source region of the eighth transistor; a third interconnect structure serves as a word line of the SRAM cell and is coupled to a gate region of the third transistor and a gate region of the seventh transistor; a fourth interconnect structure serves as a word line of the first DRAM cell and is coupled to a gate region of the fourth transistor; and a fifth interconnect structure serves as a word line of the second DRAM cell and is coupled to a gate region of the eighth transistor.

13. The semiconductor device as claimed in claim 11 further includes: A first embedded power rail (BPR) is located in the substrate, coupled to the first capacitor, and is supplied with a source power supply voltage (VSS); a second BPR is located in the substrate, coupled to a source region of the second transistor and a source region of the sixth transistor, and is supplied with a drain power supply voltage (VDD); and a third BPR is located in the substrate, coupled to the second capacitor, and is supplied with the VSS.

14. A method for manufacturing a semiconductor device, comprising: A first transistor stack is formed above a top surface of a substrate, the first transistor stack including a first pair of transistors and a second pair of transistors stacked on the substrate; a second transistor stack is formed above the substrate and adjacent to the first transistor stack, the second transistor stack including a third pair of transistors and a fourth pair of transistors stacked on the substrate; a first capacitor is formed, stacked with the first transistor stack and the second transistor stack; and a second capacitor is formed, adjacent to the first capacitor and stacked with the first transistor stack and the second transistor stack, wherein: a first group of transistor systems in the first transistor stack and the second transistor stack are coupled to each other to form a static random access memory (SRAM) cell, and a second group of transistor systems in the first transistor stack and the second transistor stack are coupled to the first capacitor and the second capacitor to form a first dynamic random access memory (DRAM) cell and a second DRAM cell, the first DRAM cell and the second DRAM cell being stacked and coupled to the SRAM cell.

15. A method for manufacturing a semiconductor device as described in claim 14, wherein: The first pair of transistors includes a first transistor and a second transistor above the substrate; the second pair of transistors includes a third transistor and a fourth transistor above the second transistor; the third pair of transistors includes a fifth transistor and a sixth transistor above the fifth transistor above the substrate; and the fourth pair of transistors includes a seventh transistor and an eighth transistor above the sixth transistor.

16. A method for manufacturing a semiconductor device as described in claim 15, wherein: Each of the transistors in the first and second transistor stacks includes (i) one or more channel regions that extend along a horizontal direction parallel to the top surface of the substrate, are stacked on the substrate along a vertical direction perpendicular to the top surface of the substrate, and are spaced apart from each other, and (ii) a gate region surrounding the one or more channel regions.

17. A method for manufacturing a semiconductor device as claimed in claim 16, wherein forming the first and second capacitors comprises: The first capacitor is formed having a trench shape, extending from the top surface of the substrate into the substrate and located in the substrate, and the second capacitor is formed having a trench shape, extending from the top surface of the substrate into the substrate and located in the substrate, wherein the first capacitor is coupled to the first transistor to form the first DRAM cell, and the second transistor is coupled to the fifth transistor to form the second DRAM cell.

18. A method for manufacturing a semiconductor device as described in claim 17, wherein: The second transistor system is an n-type transistor, the third transistor system is a p-type transistor, and the second and third transistor systems form a first inverter structure of one of the SRAM cells. The sixth transistor system is an n-type transistor, the seventh transistor system is a p-type transistor, and the sixth and seventh transistor systems form a second inverter structure of one of the SRAM cells. The first inverter structure and the second inverter structure are cross-coupled. The fourth transistor system is an n-type transistor, which serves as a first access transistor of one of the SRAM cells and is coupled to the first inverter structure. The eighth transistor system is an n-type transistor, which serves as a second access transistor of one of the SRAM cells and is coupled to the second inverter structure.

19. The method for manufacturing a semiconductor device as described in claim 17 further includes: A first embedded power rail (BPR) is formed, which is located in the substrate, adjacent to and coupled to the first capacitor, and is subjected to a source power supply voltage (VSS). A second BPR is formed, which is located in the substrate, coupled to a source region of the third transistor and a source region of the seventh transistor, and is subjected to a drain power supply voltage (VDD). A third BPR is formed, which is located in the substrate, adjacent to and coupled to the second capacitor, and is subjected to the VSS.

20. The method for manufacturing a semiconductor device as described in claim 17 further includes: A first interconnect structure is formed, which serves as a first bit line and is coupled to a source region of the first transistor and a source region of the fourth transistor. A second interconnect structure is formed, which serves as a second bit line and is coupled to a source region of the fifth transistor and a source region of the eighth transistor. A third interconnect structure is formed, which serves as a word line of the SRAM cell and is coupled to a gate region of the fourth transistor and a gate region of the eighth transistor. A fourth interconnect structure is formed, which serves as a word line of the first DRAM cell and is coupled to a gate region of the first transistor. A fifth interconnect structure is formed, which serves as a word line of the second DRAM cell and is coupled to a gate region of the fifth transistor.

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