Wordline driver architecture of integrated devices

Abstract

The various embodiments described herein relate to a device with a word line driver that provides word line signals to word lines based on a column select signal and a column clock signal. The device may have column selector logic that provides the column select signal to the word line driver based on a first input signal in the peripheral voltage domain. The device may also have a level offset circuitry that provides the column clock signal to the word line driver in the core voltage domain based on a second input signal in the peripheral voltage domain.

Description

[Technical Field]

[0001] The present invention is associated with various wordline driver schemes and techniques for various memory-related applications in the design of physical circuit layouts. [Previous Technology]

[0002] This section is intended to provide information related to understanding the various techniques described herein. As meant by the title of such section, this is a discussion of the relevant technology, which shall not in any way mean that it is prior technology. Usually, the relevant technology may or may not be considered as prior. It should therefore be understood that any statements in this section should be read in this view and should not be read as any acknowledgment of prior technology.

[0003] In some modern designs, it is known that memory circuits generally involve the use of power gated power supply. However, these learned memory circuits can exhibit persistent power leakage caused by the limited cutoff capability of the power-gated transistor, which can lead to leaked DC paths when the word line is in high state. Unfortunately, the word line rise time may be negatively affected due to leaked DC current. Therefore, there is a need to improve the design of zigzag drives in various memory-related applications. [Invention Contents]

[0004] Described herein is an embodiment of a device having a word line driver that provides a word line signal to a word line based on a row of selection signals and a row of clock signals. The device may have column selector logic that provides the column selection signal to the wordline driver based on a first input signal in a peripheral voltage domain. The device may have a bit-parallel offset circuit system that provides the row clock signal in a core voltage domain to the wordline driver based on a second input signal in the peripheral voltage domain.

[0005] Described herein is an embodiment of a device having a one-word line driver that provides a one-word line signal to a one-word line based on a row of selection signals, a row of clock signals, and all swapping power signals. The device may have column selector logic that provides the column selection signal to the wordline driver based on a first input signal in a peripheral voltage domain. The device may have a bit-parallel offset circuit system that provides the row clock signal in a core voltage domain to the wordline driver based on a second input signal in the peripheral voltage domain. The bit-quasi-offsetter circuit system may provide the switching power signal to a one-power connection of the wordline driver based on such second input signal.

[0006] This description pertains to an embodiment of a device having a word line driver that provides a word line signal to a word line based on a column select signal, a column clock signal, a word line precharge signal, and a word line feedback signal. The device may have column selector logic that provides the column select signal to the word line driver based on a first input signal in a peripheral voltage domain. Furthermore, the device may have a level offset circuitry that provides the column clock signal to the word line driver in a core voltage domain based on a second input signal in the peripheral voltage domain. The level offset circuitry may provide the word line precharge signal to a first power connection of the word line driver based on the second input signals, and the word line signal may be fed back to a second power connection of the word line driver as a word line feedback signal.

Implementation Method

[0008] The various embodiments described herein are associated with various word line driver solutions and techniques for various memory-related applications in physical circuit layout designs. Furthermore, in some embodiments, the various solutions and techniques described herein provide a robust word line driver architecture that can be used to implement programmable high-speed word line level offsets for memory applications. In other embodiments, the various solutions and techniques described herein provide a robust word line driver architecture that can be used to implement high-speed word line level offsets with programmable power cutoff in relevant memory applications. Further, in other embodiments, the various solutions and techniques described herein provide a robust word line driver architecture that can be used to implement low-power extension range level offsets for SRAM word line drivers in other relevant memory applications.

[0009] Some proposed designs attempt to introduce high-speed word line drivers (WLDs) with integrated level offsets (LS), which improve dual-rail range and reduce DC current leakage. This embodiment enables low-voltage designs to be used in on-chip (e.g., CPU / SoC) related applications to save power. As described in more detail herein, various word line driver designs can be used for level offset of column clock signals from the peripheral voltage domain (VDDPE) to the core voltage domain (VDDCE) by implementing a bypass level offset with programmable bypass inputs. In this case, when VDDPE = VDDCE, the programmable bypass level offset can be used to disable level offset functionality, thereby improving performance. Some advantages of this circuitry include improved level offset range and reduced DC current, with only a slight or no impact on word line clock rise timing. Other advantages include, for example, minimal or no impact on word line clock fall timing when VDDPE >= VDDCE, and in some cases, such as when VDDPE < VDDCE, minimal or no impact on word line clock fall timing. Furthermore, the programmable bypass level offsetter described herein can be used in various other applications, such as, for example, dummy word line (DWL) driver circuitry and write driver (YW) circuitry. For instance, a DWL level offsetter driver design with programmable bypass can be used in DWL and YW applications to improve the level offset range at the VDDPE < VDDCE corner without negatively impacting timing at the VDDPE = VDDCE corner.

[0010] Some proposed designs attempt to introduce high-speed word line drivers (WLDs) with programmable power cutoff to improve dual-rail range and reduce DC current leakage. This embodiment enables various low-voltage designs to be used in some on-chip (e.g., CPU / SoC) related applications to save power. As described in more detail herein, various word line driver designs can be used to control the power-gated word line and core voltage supply with column clock signals. In this example, when the column clock is high, the control signal can be used to selectively cut off the word line driver, which can be cut off during bypass operation. Thus, during VDDPE >= VDDCE, the bypass is set to logic 1, which can be used to clamp a column clock control signal, which is typically in an active operating state. Some advantages of this WLD circuitry system may refer to improved level offset range along with reduced DC current, with only a slight or even no impact on the word line clock rise timing. Other advantages may refer to the fact that, for example, when VDDPE >= VDDCE, there is little or no effect on the word line clock fall timing, and in some cases, such as when VDDPE < VDDCE, there is little or no effect on the word line clock fall timing.

[0011] Furthermore, some proposed designs attempt to introduce high-speed and low-power extended-range level offsetters for word line driver applications, which can reduce (or eliminate) PMOS contention at level offset boundaries through closed-loop feedback, thereby reducing (or eliminating) PMOS contention in NAND-based level offsetter designs used in some word line drivers. Compared to conventional designs, this embodiment provides supported extended dual-rail range, which reduces active-mode quiescent DC current. This WLD design also allows the peripheral logic power supply of a single chip (e.g., SOC) to be scaled down to lower voltages for power savings. As described in more detail herein, various word line driver designs can be used to provide feedback devices to cut off the closed-loop system during the word line rising edge to extend the level offset range. In addition, additional pre-charge devices can be used to restore power supply to the PMOS devices to enable the word line falling edge. Some advantages may refer to improved level offset range in multiple Vt and single Vt configurations. Other advantages may refer to improved word line rising edge and / or delay due to reduced (or eliminated) PMOS contention, resulting in robust word line pulses at level offset boundaries. In some cases, quiescent DC current in active mode can be reduced during level offset operation. In other cases, quiescent DC current in active mode can be completely eliminated during level offset operation. Furthermore, when VDDCE = VDDPE, there may be no decay in word line rising or falling edge delay. Otherwise, when VDDCE > VDDPE, word line rising edge decay on the falling edge may be nonexistent due to the level offset delay.

[0012] Memory architecture can refer to various volatile and non-volatile memories, such as, for example, static random access memory (SRAM) and / or magnetoresistive random access memory (MRAM). The memory architecture may include a memory circuit system having a core array of memory cells or bit cells accessible via data access lines, such as one or more word lines and bit lines. In SRAM applications, a data access line refers to a complementary bit line (BL, NBL), and in MRAM applications, a data access line refers to at least one bit line (BL) and at least one source line (SL).

[0013] This document will describe various implementation schemes of word line driver solutions and technologies for some memory applications with reference to Figures 1 to 5.

[0014] Figure 1 illustrates a word line driver architecture 104 according to various embodiments described herein.

[0015] In some embodiments, the word line driver architecture 104, together with other associated circuitry, can be implemented as a system or device having integrated circuit (IC) components configured and coupled together as an assembly or combination of components providing physical circuitry design and associated structures. In some cases, methods of designing, providing, building, manufacturing, and fabricating the word line driver architecture 104 into an integrated system or device may involve the use of the various IC circuitry components described herein to implement associated word line driver schemes and technologies. Furthermore, the word line driver architecture 104 can be integrated with computing circuitry systems and various other associated components on a single chip, and furthermore, the word line driver architecture 104 can be implemented in embedded systems related to automotive, electronics, mobile, server, and Internet of Things (IoT) applications (including, for example, remote sensor nodes and / or various other associated components).

[0016] As shown in FIG1, the word line driver architecture 104 may include various circuit systems and components configured to operate in different voltage domains, such as, for example, the peripheral voltage domain (VDDPE) and the core voltage domain (VDDCE). For example, the word line driver architecture 104 may include a logic device (L1) that operates in the peripheral voltage domain (VDDPE). In addition, the word line driver architecture 104 may include a bit quasi-offset 108 that operates in both the peripheral voltage domain (VDDPE) and the core voltage domain (VDDCE). Furthermore, the word line driver architecture 104 may include a word line driver group 114 having multiple word line driver circuits (e.g., RL0 / D0, RL1 / D1, RL2 / D2, RL3 / D3) that operate in the core voltage domain (VDDCE).

[0017] In some embodiments, the logic device (L1) receives multiple input signals (e.g., g0, g1) and provides a row select signal in the VDDPE domain. In some cases, the logic device (L1) may refer to a NOR gate configuration; however, in other cases, various other logic gates may be used to achieve similar behavior. Furthermore, the input signals (e.g., g0, g1) can be used as a 2-bit row select input.

[0018] In some embodiments, the level offset 108 may receive one or more input signals (e.g., inp_sig) and provide a clock signal (e.g., rowclk<0>) to a first word line driver circuit (e.g., RL0 / D0). In various cases, the level offset 108 may include various circuit systems and components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. These features and various other configurations related to the level offset 108 will be described in more detail herein.

[0019] In some embodiments, word line driver group 114 may include multiple word line driver circuits (e.g., RL0 / D0, RL1 / D1, RL2 / D2, RL3 / D3), which operate in the core voltage domain (VDDCE). For example, as shown in FIG1, word line driver group 114 may include four (4) word line driver circuits (e.g., RL0 / D0, RL1 / D1, RL2 / D2, RL3 / D3), which operate in the VDDCE domain. The first word line driver circuit (RL0 / D0) may include logic devices (RL0, D0), which are configured to receive input signals (rowclk<0>, rowsel) and provide a first word line signal (WL<0>) as an output to the first word line (WL0). Similarly, the second word line driver circuit (RL1 / D1) may include logic devices (RL1, D1) configured to receive input signals (rowclk<1>, rowsel) and provide a second word line signal (WL<2>) as an output to the second word line (WL1). Similarly, the third word line driver circuit (RL2 / D2) may include logic devices (RL2, D2) configured to receive input signals (rowclk<2>, rowsel) and provide a third word line signal (WL<3>) as an output to the third word line (WL2). Further, similarly, the fourth word line driver circuit (RL3 / D3) may include logic devices (RL3, D3) configured to receive input signals (rowclk<3>, rowsel) and provide a third word line signal (WL<3>) as an output to the third word line (WL3).

[0020] In various other embodiments, word line driver group 114 may refer to a scalable word line driver group having any number (e.g., N) of word line driver circuitry coupled to any number of corresponding word lines (WL). These features and various other morphologies associated with the scalable word line driver group and / or word line driver circuitry may be used with the various word line driver schemes and techniques described herein.

[0021] In various embodiments, the word line driver architecture 104 can be utilized in various memory applications, such as, for example, random access memory (RAM) (including static RAM (SRAM), magnetoresistive RAM (MRAM), and / or some other similar types of memory). Furthermore, the word line driver architecture 104 can be implemented as an integrated circuit (IC) with a dual-track memory architecture and any associated circuitry. The word line driver architecture 104 can be integrated with arithmetic circuitry systems and associated components on a single chip, and furthermore, the word line driver architecture 104 can be implemented in various embedded systems for automotive, electronic, mobile, server, and IoT applications.

[0022] Furthermore, the word line driver architecture 104 can be implemented in various core bit array circuit systems having memory cell arrays, wherein each memory cell may be referred to as a bit cell (BC). Furthermore, each memory cell (or bit cell) can be configured to store at least one data bit value (e.g., a data value associated with logic "0" or "1"). Additionally, the memory array may include any number (N) of memory cells (or bit cells) configured in any applicable configuration, such as, for example, a two-dimensional (2D) memory array having any number (N) of rows (N_rows) and any number (N) of columns (N_columns), wherein the memory cells are configured in a 2D grid pattern with associated indexing capabilities.

[0023] Figures 2A to 2D illustrate various related diagrams of word line driver architectures according to various embodiments described herein. Specifically, Figure 2A shows Figure 200A of word line driver architecture 204A, Figure 2B shows Figure 200B of a level offset (LS1) circuit system with bypass, Figure 2C shows another Figure 200C of a dummy word line driver (DWL) circuit system 204C, and Figure 2D shows another Figure 200D of a level offset (LSD) circuit system with bypass.

[0024] In some embodiments, the word line driver architecture 204A may refer to a system or device having various integrated circuit (IC) components configured and coupled together as an assembly or combination of components providing a physical circuit layout design and various related structures. In some cases, methods of designing, providing, building, manufacturing, and fabricating the word line driver architecture 204A into an integrated system or device may involve the use of the various IC circuit systems and components described herein to implement associated word line driver schemes and technologies. Furthermore, the word line driver architecture 204A may also be integrated with arithmetic circuit systems and / or related components on a single chip, and the word line driver architecture 204A may be implemented in embedded systems for automotive, electronic, mobile, server, and IoT applications.

[0025] As shown in Figure 2A, the word line driver architecture 204A may have various circuit systems and components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. For example, the word line driver architecture 204A may include a logic device (L1) that operates in the peripheral voltage domain (VDDPE). Furthermore, the word line driver architecture 204A may include a level offset circuit system 208 that operates in both the VDDPE and VDDCE domains. Additionally, the word line driver architecture 204A may include a group of word line drivers having one or more word line driver circuits (e.g., RL0 / D0, RL1 / D1, RL2 / D2, RL3 / D3) that operate in the core voltage domain (VDDCE). In this context, for the sake of simplicity, a first word line driver circuit (RL0 / D0) is shown; however, this description can be similarly applied to scalable word line driver groups with any number of word line driver circuits to achieve similar behavior and results as described herein.

[0026] In some embodiments, the logic device (L1) receives input signals (e.g., g0, g1) and provides a row select signal (rowsel) in the VDDPE domain. In some cases, the logic device (L1) may refer to a NOR gate configuration; however, in other cases, various other logic gates may be used to achieve similar behavior. Furthermore, the input signals (e.g., g0, g1) can be used as a 2-bit row select input.

[0027] In some embodiments, the level offset circuit system 208 may receive one or more input signals (e.g., bypass, nxrow, ngtp) and provide a column clock signal (e.g., rowclk<0>) to the first word line driver circuit (RL0 / D0). In various cases, the level offset circuit system 208 may have various circuit systems and components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. In some cases, the level offset circuit system 208 may include various logic devices (e.g., L2, L3, L4, L5) along with a level offset (LS1), configured to perform various level offset operations as described herein. In some cases, the logic devices (L2, L3, L4, L5) may have a logic device (L2) operating as an inverter that receives a bypass input signal and provides an inverted bypass signal (nbypass) to the level offset (LS1). Logic devices (L2, L3, L4, L5) may include a logic device (L3) operating as a NOR gate, which receives input signals (nxrow, ngtp) and then provides an internal column clock signal (irowclk) to a level offset unit (LS1) and to the logic device (L4). The level offset unit (LS1) may receive an nbypass signal, receive the irowclk signal, and then provide a level-offset internal column clock signal (irowclk_ls) to the logic device (L4). Logic devices (L2, L3, L4, L5) may include a logic device (L4) operating, for example, as a NOR gate, which receives the irowclk_ls signal, receives the irowclk signal, and then provides an inverted rowclk<0> signal to the logic device (L5). The logic devices (L2, L3, L4, L5) may include a logic device (L5) operating as an inverter, which receives the inverted rowclk<0> signal and then provides the rowclk<0> signal. These features and various other states related to the level offset (LS1) will be described in more detail herein with reference to FIG2B.

[0028] In some embodiments, the first word line driver circuit (RL0 / D0) may include logic devices (RL0, D0) configured to receive input signals (rowclk<0>, rowsel) and provide a first word line signal (WL<0>) as an output to the first word line (WL0). As described herein, in various embodiments, the first word line driver circuit (RL0 / D0) may be part of a scalable word line driver group having any number (e.g., N) of word line driver circuits coupled to any number of corresponding word lines (WL). These features and / or various other morphologies associated with the scalable word line driver group and word line driver circuits may be used with the various word line driver schemes and techniques described herein.

[0029] In some operational embodiments with reference to FIG2A, word line driver architecture 204A may refer to a device having word line drivers (e.g., RL0, D0) that provide word line signals (e.g., WL<0>) to word lines (WL0) based on column select signals (e.g., rowsel) and column clock signals (e.g., rowclk<0>). Furthermore, the device may have column selector logic (e.g., L1) that provides column select signals (e.g., rowsel) to word line drivers (e.g., RL0 / D0) based on first input signals (e.g., go, g1) in the peripheral voltage domain (VDDPE). In addition, the device may have a level offset circuit system 208 that provides a column clock signal (e.g., rowclk<0>) to a word line driver (RL0 / D0) in the core voltage domain (VDDCE) based on a second input signal (e.g., bypass, nxrow, ngtp, or more) in the peripheral voltage domain (VDDPE).

[0030] In various cases, the word line driver (RL0 / D0) operates in the core voltage domain (VDDCE), and furthermore, the column selector logic (L1) operates in the peripheral voltage domain (VDDPE). The word line driver (RL0 / D0) may have a first logic (RL0) and a second logic (D0), which are serially coupled and operate in the VDDCE domain. The first logic (RL0) may provide a complementary word line signal (NWL<0>) to the second logic (D0) based on the column select signal (rowsel) and / or the column clock signal (rowclk<0>). In addition, the second logic (D0) may receive the complementary word line signal (NWL<0>) from the first logic (RL0) and provide a word line signal (WL<0>) to the word line (WL0) based on the complementary word line signal (NWL<0>).

[0031] In various cases, the level offset circuit system 208 includes a bypass level offsetter (LS1) configured to operate as a level offsetter based on a bypass signal (nbypass) in a first logic state. Furthermore, the bypass level offsetter (LS1) can also be configured to operate as a clamp based on a bypass signal (nbypass) in a second logic state different from the first logic state. In some scenarios, when the peripheral voltage levels in the VDDPE domain are substantially similar to (e.g., equal to) the core voltage levels in the VDDCE domain, the bypass level offsetter (LS1) can be configured to disable level offset functionality to improve performance. In other scenarios, when the peripheral voltage levels in the VDDPE domain are substantially different from (e.g., at least lower than) the core voltage levels in the VDDCE domain, the bypass level offsetter (LS1) is configured to enable level offset functionality.

[0032] Furthermore, in various cases, the level offset circuit system 208 may include input logic (e.g., L2, L3) configured to operate in the VDDPE domain, and additionally, the level offset circuit system 208 may also include output logic (e.g., L4, L5) configured to operate in the VDDCE domain. Furthermore, the input logic (e.g., L2, L3) may provide a bypass signal (e.g., nbypass) and an internal column clock signal (e.g., irowclk) to the bypass level offsetter (LS1) based on a second input signal (e.g., bypass, nxrow, ngtp). The bypass level offsetter (LS1) may provide a level-offset column clock signal (irowclk_ls) to the output logic (e.g., L4) in the VDDCE domain based on the bypass signal (e.g., nbypass) from the input logic (e.g., L2, L3) in the VDDPE domain and the internal column clock signal (e.g., irowclk). The output logic (e.g., L4, L5) can provide column clock signals (e.g., rowclk<0>) to word line drivers (e.g., RL0, D0) in the VDDCE domain based on the internal column clock signal (e.g., irowclk) from the input logic (e.g., L3) in the VDDPE domain and the level-offset column clock signal (e.g., irowclk_ls) from the bypass level offsetter (LS1) in the VDDCE domain.

[0033] Figure 2B shows a bypass level offset (LS1) circuit system associated with the bypass level offset (LS1) in Figure 2A. As shown in Figure 2B, the bypass level offset (LS1) circuit system may include various circuit systems and / or components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. Thus, the bypass level offset (LS1) circuit system in Figure 2B may be referred to as the bypass level offset (LS1) in Figure 2A.

[0034] In some embodiments, the bypass level offset (LS1) may include input logic (e.g., LG1, I1), which is configured to receive input signals (e.g., nbypass, irowclk) and then provide output signals to a transistor stack (e.g., T1 / T2 / T3 and T4 / T5 / T6). As shown, the first transistor stack (T1 / T2 / T3) may include a transistor T1 coupled between the supply voltage VDDCE and transistor T2, and transistor T2 is coupled between transistor T1 and transistor T3, and furthermore, transistor T3 is coupled between transistor T2 and ground. In addition, the output from the logic gate (LG1) may be coupled to the gates of transistors T2 and T3 and the input of logic gate (I1), and the output of logic gate (I1) may be coupled to the gates of transistors T5 and T6. Furthermore, the level-shifted output signal (irowclk_ls) can be provided by an internal node (n1) located between transistors T2 and T3, and the internal node (n1) can be coupled to the gate of transistor T4. Another internal node (n2) can be cross-coupled to the gate of transistor T1, and furthermore, the internal node (n2) can be located between transistors (T5, T6). As shown in the figure, the internal nodes (n1, n2) can be cross-coupled to the gates of transistors (T1, T4), wherein the output is provided by the internal node (n1).

[0035] Furthermore, in some cases, the logic gates (LG1, I1) can be configured to operate in the VDDPE domain, and further, the transistor stacks (T1 / T2 / T3 and T4 / T5 / T6) can be configured to operate in the VDDCE domain. In various cases, the first logic gate (LG1) may refer to a NAND gate, and the second logic gate (I1) may refer to an inverter. Further, the transistors (T1, T2, T4, T5) may refer to PMOS transistors, and the transistors (T3, T6) may refer to NMOS transistors; however, various other transistor configurations can be used to achieve similar behavior, results, and characteristics.

[0036] Figure 2C shows a virtual word line driver (DWL) circuit system 204C, which may be related, for example, to the bypass level offset (LS1) in Figures 2A and 2B. As shown in Figure 2C, the virtual word line driver (DWL) circuit system 204C may have a virtual level offset (LSD) circuit system with various circuit systems and / or components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. Furthermore, the virtual level offset (LSD) circuit system can be used to drive a virtual word line (DWL).

[0037] In some embodiments, the dummy level offset (LSD) circuitry is configured to operate in both the VDDPE and VDDCE domains, and furthermore, the dummy word line driver (DWL) circuitry 204C may include a logic gate (LGD). As shown in FIG2C, the dummy level offset (LSD) may be configured to receive an input signal (e.g., nbypass, ngtp) and then provide a level-offset ngtp signal (e.g., ngtp_ls). Additionally, the logic gate (LGD) may be configured to receive the ngtp signal, receive the level-offset ngtp signal (e.g., ngtp_ls), and then provide a dummy word line signal (dwl) to the DWL.

[0038] Figure 2D shows a bypassed level offset (LSD) circuit system associated with the dummy level offset (LSD) in Figure 2C. As shown in Figure 2D, the bypassed level offset (LSD) circuit system may include various circuit systems and / or components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. In some cases, the bypassed level offset (LSD) circuit system in Figure 2D may be referred to as the bypassed dummy level offset (LSD) in Figure 2C.

[0039] In some embodiments, the dummy level offset (LSD) may include input logic (e.g., LG2, I2), which is configured to receive input signals (e.g., nbypass, ngtp) and provide output signals to the transistor stack (TD1 / TD2 / TD3 and TD4 / TD5 / TD6). As shown, the first transistor stack (TD1 / TD2 / TD3) may have a transistor TD1 coupled between the supply voltage VDDCE and transistor TD2, and transistor TD2 is coupled between transistor TD1 and transistor TD3. Furthermore, another transistor TD3 is coupled between transistor TD2 and ground. In addition, the output from the logic gate (LG2) may be coupled to the gates of transistors TD2 and TD3 and the input of logic gate (I2), and the output of logic gate (I2) may be coupled to the gates of transistors TD5 and TD6. Furthermore, the level-shifted output signal (ngtp_ls) can be provided by an internal node (n3) located between transistors TD2 and TD3, and the internal node (n3) can be coupled to the gate of transistor TD4. Another internal node (n4) can be cross-coupled to the gate of transistor TD1, and furthermore, the internal node (n4) can be located between transistors (TD5, TD6). In some cases, as shown in Figure 2D, the internal nodes (n3, n4) can be cross-coupled to the gates of transistors (TD1, TD4), wherein the output is provided by the internal node (n3).

[0040] Furthermore, in some cases, the logic gates (LG2, I2) can be configured to operate in the VDDPE domain, and the transistor stacks (TD1 / TD2 / TD3 and TD4 / TD5 / TD6) can be configured to operate in the VDDCE domain. Further, the first logic gate (LG2) may refer to a NAND gate, and the second logic gate (I2) may refer to an inverter. Additionally, the transistors (TD1, TD2, TD4, TD5) may refer to PMOS transistors, and the transistors (TD3, TD6) may refer to NMOS transistors; however, various other transistor configurations can be used to achieve similar behavior, results, and characteristics.

[0041] Figures 3A to 3C illustrate various related diagrams of word line driver architectures according to various embodiments described herein. Specifically, Figure 3A shows Figure 300A of word line driver architecture 304A, Figure 3B shows Figure 300B of a level offset (LS2) circuit system with bypass, and Figure 3C shows Figure 300C of word line driver (WLD) circuit system 304C.

[0042] In some embodiments, the word line driver architecture 304A may refer to a system or device having various integrated circuit (IC) components configured and coupled together as an assembly or combination of components providing a physical circuit layout design and various related structures. In some cases, methods of designing, providing, building, manufacturing, and fabricating the word line driver architecture 304A into an integrated system or device may involve the use of the various IC circuit systems and components described herein to implement associated word line driver schemes and technologies. Furthermore, the word line driver architecture 304A may also be integrated with arithmetic circuit systems and / or related components on a single chip, and the word line driver architecture 304A may be implemented in embedded systems for automotive, electronic, mobile, server, and IoT applications.

[0043] As shown in Figure 3A, the word line driver architecture 304A may have various circuit systems and components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. For example, the word line driver architecture 304A may include a logic device (L1) that operates in the peripheral voltage domain (VDDPE). Furthermore, the word line driver architecture 304A may include a level offset circuit system 308 that operates in both the VDDPE and VDDCE domains. Additionally, the word line driver architecture 304A may include a group of word line drivers having one or more word line driver circuits (e.g., RL0 / D0, RL1 / D1, RL2 / D2, RL3 / D3) that operate in the core voltage domain (VDDCE). In this context, for the sake of simplicity, a first word line driver circuit (RL0 / D0) is shown; however, this description can be similarly applied to scalable word line driver groups with any number of word line driver circuits to achieve similar behavior and results as described herein.

[0044] In some embodiments, the logic device (L1) receives input signals (e.g., g0, g1) and provides a row select signal (rowsel) in the VDDPE domain. In some cases, the logic device (L1) may refer to a NOR gate configuration; however, in other cases, various other logic gates may be used to achieve similar behavior. Furthermore, the input signals (e.g., g0, g1) can be used as a 2-bit row select input.

[0045] In some embodiments, the level offset circuit system 308 may receive one or more input signals (e.g., xrow, ngtp, nxrow) and provide a column clock signal (e.g., rowclk<0>) to the first word line driver circuit (RL0 / D0). In various cases, the level offset circuit system 308 may have various circuit systems and components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. In some cases, the level offset circuit system 308 may include various logic devices (e.g., L2, L3, L5, L6, L7) together with the level offset (LS2), which are configured to perform various level offset operations as described herein. In some cases, the logic devices (L2, L3, L5, L6, L7) may have a logic device (L2) operating as an inverter that receives the input signal ngtp and then provides an inverted ngtp signal (gtp) to the logic device (L6). The logic devices (L2, L3, L5, L6, L7) may include a logic device (L3) operating as a NOR gate, which receives input signals (nxrow, ngtp) and provides an internal column clock signal (Vddc_rowclk_ctrl) to the level offset unit (LS2). Furthermore, the level offset unit (LS2) may receive a bypass signal, receive the Vddc_rowclk_ctrl signal, and provide a level-offset column clock signal (Vddc_ctrl) to the logic device (L5). The logic devices (L2, L3, L5, L6, L7) may include a logic device (L5) operating as, for example, an inverter, which receives the Vddc_ctrl signal and provides an inverted Vddc_ctrl signal (Vddc_ctrl_b) to the switching device (S1). The logic devices (L2, L3, L5, L6, L7) may include a logic device (L7) operating as an inverter, which receives the output from the logic device (L6) and then provides the rowclk<0> signal to the first word line driver circuit (RL0 / D0). These features and various other configurations related to the level offset (LS2) will be described in more detail herein with reference to FIG3B.

[0046] In some embodiments, the switching device (S1) may be a transistor coupled between a supply voltage (Vddc) and the power connection of the logic device (RL0) of the first word line driver circuit (RL0 / D0). Alternatively, the switching device (S1) may refer to a PMOS transistor activated by the Vddc_ctrl_b signal, which is provided by the logic device (L5). In other cases, various other switching transistors may be used to provide switching power signals with similar behavior and results.

[0047] In some embodiments, the first word line driver circuit (RL0 / D0) may include logic devices (RL0, D0) configured to receive input signals (rowclk<0>, rowsel) and provide a first word line signal (WL<0>) as an output to the first word line (WL0). The logic device (RL0) may include multiple power connections configured to receive a Vddc_rowclk signal from a switching device (S1) and also receive Vddc_rowclk as a Vddce supply signal. As described herein, in various embodiments, the first word line driver circuit (RL0 / D0) may be part of a scalable word line driver group having any number (e.g., N) of word line driver circuits coupled to any number of corresponding word lines (WL). These features and / or various other morphologies associated with the scalable word line driver group and word line driver circuits may be used with the various word line driver schemes and techniques described herein.

[0048] In some operational embodiments with reference to FIG3A, word line driver architecture 304A may refer to a device having word line drivers (e.g., RL0, D0) that provide word line signals (e.g., WL<0>) to word lines (WL0) based on column select signals (e.g., rowsel), column clock signals (e.g., rowclk<0>), and switching power signals. Furthermore, the device may have column selector logic (e.g., L1) that provides column select signals (e.g., rowsel) to word line drivers (e.g., RL0 / D0) based on a first input signal (e.g., go, g1) in the VDDPE domain. Additionally, the device may include a level offset circuit system 308 that provides column clock signals (e.g., rowclk<0>) to word line drivers (RL0 / D0) in the VDDCE domain based on a second input signal (e.g., xrow, ngtp, nxrow) in the VDDPE domain. In some cases, the level offset circuitry 308 may also provide a power connection to the word line driver (RL0 / D0) based on a second input signal (e.g., xrow, ngtp, nxrow).

[0049] In various cases, the word line driver (RL0 / D0) operates in the core voltage domain (VDDCE), and the column selector logic (L1) operates in the peripheral voltage domain (VDDPE). The word line driver (RL0 / D0) may have a first logic (RL0) and a second logic (D0), which are coupled in series and operate in the VDDCE domain. The first logic (RL0) may provide a complementary word line signal (NWL<0>) to the second logic (D0) based on the column select signal (rowsel), the column clock signal rowclk<0>, and the switching power signal (Vddc_rowclk). Furthermore, the second logic (D0) may receive the complementary word line signal (NWL<0>) from the first logic (RL0) and then provide a word line signal (WL<0>) to the word line (WL0) based on the complementary word line signal (NWL<0>).

[0050] In various cases, the level offset circuit system 308 includes a bypass level offset (LS2) configured to operate as a level offset based on a bypass signal in a first logic state. Furthermore, the bypass level offset (LS2) can also be configured to operate as a clamp based on a bypass signal in a second logic state different from the first logic state. The level offset circuit system 308 may include a power gate switch (S1) coupled between the core power supply (Vddc) and the word line driver (RL0 / D0). The power gate switch (S1) may be activated by an internal control signal (Vddc_ctrl / Vddc_ctrl_b) provided by the bypass level offset (LS2) in the core voltage domain (VDDCE). Furthermore, the level offset circuit system 308 may include input logic (e.g., L2, L3, L6, L7) operating in the VDDPE domain, and furthermore, the level offset circuit system 308 may include output logic (e.g., L5, S1) operating in the VDDCE domain, and further still, the input logic (e.g., L2, L3, L6, L7) may provide a column clock control signal (Vddc_rowclk) to the bypass level offset unit (LS2) based on a second input signal (e.g., xrow, ngtp, nxrow).

[0051] In some scenarios, the bypass level offsetter (LS2) provides a level-offset control signal (Vddc_ctrl) to the output logic (L5, S1) in the core voltage domain (VDDCE) based on the column clock control signal (Vddc_rowclk_ctrl) from the input logic (L3) in the peripheral voltage domain (VDDPE) and the bypass signal (bypass). In other scenarios, the output logic (L5) provides an internal control signal (Vddc_ctrl_b) to the gate of the power gate switch (S1) in the core voltage domain (VDDCE) based on the column clock control signal (Vddc_rowclk_ctrl) from the input logic (L3) in the peripheral voltage domain (VDDPE) and the level-offset control signal (Vddc_ctrl) from the bypass level offsetter (LS2) in the core voltage domain (VDDCE).

[0052] Figure 3B shows a bypass level offset (LS2) circuit system associated with the bypass level offset (LS2) in Figure 3A. As shown in Figure 3B, the bypass level offset (LS2) circuit system may include various circuit systems and / or components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. Thus, the bypass level offset (LS2) circuit system in Figure 3B may be referred to as the bypass level offset (LS2) in Figure 3A.

[0053] In some embodiments, the bypass level offset (LS2) may include input logic (e.g., LG3, I3), which is configured to receive input signals (e.g., bypass, Vddc_rowclk_ctrl) and provide output signals to a transistor stack (e.g., T11 / T12 / T13 and T14 / T15 / T16). As shown, the first transistor stack (T11 / T12 / T13) may include transistor T11 coupled between the supply voltage VDDCE and transistor T12, and furthermore, transistor T12 is coupled between transistor T11 and transistor T13, and furthermore, transistor T13 is coupled between transistor T12 and ground. In addition, the output from the logic gate (LG3) may be coupled to the gates of transistors T12 and T13 and the input of logic gate (I3), and the output of logic gate (I3) may be coupled to the gates of transistors T15 and T16. Furthermore, the level-shifted output signal (Vddc_ctrl) can be provided by an internal node (n5) located between transistors T12 and T13, and the internal node (n5) can be coupled to the gate of transistor T14. Another internal node (n6) can be cross-coupled to the gate of transistor T11, and in addition, the internal node (n6) can be located between transistors (T15, T16). As shown in the figure, the internal nodes (n5, n6) can be cross-coupled to the gates of transistors (T11, T14), and the output is provided by the internal node (n5).

[0054] Furthermore, in some cases, the logic gates (LG3, I3) can be configured to operate in the VDDPE domain, and further, the transistor stacks (T11 / T12 / T13 and T14 / T15 / T16) can be configured to operate in the VDDCE domain. In various cases, the first logic gate (LG3) may refer to a NOR gate, and the second logic gate (I3) may refer to an inverter. Additionally, the transistors (T11, T12, T14, T15) may refer to PMOS transistors, and the transistors (T13, T16) may refer to NMOS transistors; however, other transistor configurations may be used to achieve similar behavior, results, and characteristics.

[0055] Figure 3C shows a word line driver (WLD) circuit system 304C, as associated with the word line drivers (e.g., RL0, D0) in Figure 3A. As shown in Figure 3C, the word line driver (WLD) circuit system 304C may include various circuit systems and / or components configured to operate in the VDDCE domain. In some cases, the word line driver (WLD) circuit system 304C may include a first column logic device (RL0) having transistors (e.g., S1, T21, T22, T23, T24) configured and coupled together to provide an NWL<0> signal to a second column logic device (D0) based on input signals (e.g., rowsel, rowclk<0>, Vddc_ctrl_b<0>) provided to the gates of the transistors (e.g., S1, T21, T22, T23, T24).

[0056] In various embodiments, transistors (S1, T21) are coupled in series between the supply voltage (Vddc) and the output node (outn), and transistor (T22) is coupled between the supply voltage (Vddce) and the output node (outn). Furthermore, transistors (T23, T24) may be coupled between the output node (outn) and ground. The output node (outn) may also be coupled to the input of a column logic device (D0), which operates as an inverter to receive an output signal (NWL<0>) as an output from the first column logic and to provide a WL<0> signal to the word line (WL0). The Vddc_ctrl_b signal is coupled to the gate of the power gate switching transistor (S1) for its activation. The rowclk<0> signal is coupled to the gate of the transistor (T21, T24) to enable it, and the rowsel signal is coupled to the gate of the transistor (T22, T23) to enable it.

[0057] Figures 4A to 4C illustrate various related diagrams of word line driver architectures according to various embodiments described herein. Specifically, Figure 4A shows Figure 400A of word line driver architecture 404A, Figure 4B shows Figure 400B of a level offset (LS3) circuit system with bypass, and Figure 4C shows Figure 400C of word line driver (WLD) circuit system 404C.

[0058] In some embodiments, the word line driver architecture 404A may refer to a system or device having various integrated circuit (IC) components configured and coupled together as an assembly or combination of components providing a physical circuit layout design and various related structures. In some cases, methods of designing, providing, building, manufacturing, and fabricating the word line driver architecture 404A into an integrated system or device may involve the use of the various IC circuit systems and components described herein to implement associated word line driver schemes and technologies. Furthermore, the word line driver architecture 404A may also be integrated with arithmetic circuit systems and / or related components on a single chip, and the word line driver architecture 404A may be implemented in embedded systems for automotive, electronic, mobile, server, and IoT applications.

[0059] As shown in Figure 4A, the word line driver architecture 404A may have various circuit systems and components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. For example, the word line driver architecture 404A may include a logic device (L1) that operates in the peripheral voltage domain (VDDPE). Furthermore, the word line driver architecture 404A may include a level offset circuit system 408 that operates in both the VDDPE and VDDCE domains. Additionally, the word line driver architecture 404A may include a group of word line drivers having one or more word line driver circuits (e.g., RL0 / D0, RL1 / D1, RL2 / D2, RL3 / D3) that operate in the core voltage domain (VDDCE). In this context, for the sake of simplicity, a first word line driver circuit (RL0 / D0) is shown; however, this description can be similarly applied to scalable word line driver groups with any number of word line driver circuits to achieve similar behavior and results as described herein.

[0060] In some embodiments, the logic device (L1) receives input signals (e.g., g0, g1) and provides a row select signal (rowsel) in the VDDPE domain. In some cases, the logic device (L1) may refer to a NOR gate configuration; however, in other cases, various other logic gates may be used to achieve similar behavior. Furthermore, the input signals (e.g., g0, g1) can be used as a 2-bit row select input.

[0061] In some embodiments, the level offset circuit system 408 may receive one or more input signals (e.g., xrow, ngtp) and then provide a column clock signal (e.g., rowclk<0>) to the first word line driver circuit (RL0 / D0). In some cases, the level offset circuit system 408 may include various circuit systems and / or components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. In some cases, the level offset circuit system 408 may include various logic devices (e.g., L2, L5, L6, L7) together with the level offset (LS3), which are configured to perform various level offset operations as described herein. In some cases, the logic devices (L2, L5, L6, L7) may have a logic device (L2) operating as an inverter that receives the input signal (ngtp) and then provides an inverted ngtp signal (gtp) to the logic device (L6). Furthermore, the level offsetter (LS3) can receive a bypass signal, receive a gpt signal, and provide a level-offset word line precharge signal (nwlprech) to the logic device (L5). Additionally, the logic devices (L2, L5, L6, L7) may include a logic device (L5) operating as, for example, an inverter, which receives the nwlprech signal and provides an inverted nwlprech signal (wlprech) to the logic device (RL0). The logic devices (L2, L5, L6, L7) may include a logic device (L7) operating as an inverter, which receives the output from the logic device (L6) and then provides a rowclk<0> signal to the word line driver circuitry (RL0 / D0). These features and various other configurations related to the level offsetter (LS3) will be described in more detail herein with reference to FIG4B.

[0062] In some embodiments, the first word line driver circuit (RL0 / D0) may include logic devices (RL0, D0) configured to receive input signals (rowclk<0>, rowsel) and provide a first word line signal (WL<0>) as an output to the first word line (WL0). The logic device (RL0) may include multiple power connections configured to receive a wlprech signal from the logic device (L5) and a word line feedback signal (wl_fb) from the output of the logic device (D0). As described herein, in various other embodiments, the first word line driver circuit (RL0 / D0) may be part of a scalable word line driver group having any number (e.g., N) of word line driver circuits coupled to any number of corresponding word lines (WL). These features and / or various other morphologies associated with the scalable word line driver group and word line driver circuits may be used with the various word line driver schemes and techniques described herein.

[0063] In some operational embodiments with reference to FIG4A, word line driver architecture 404A may refer to a device having word line drivers (e.g., RL0, D0) that provide word line signals (e.g., WL<0>) to word lines (e.g., WL0) based on column select signals (e.g., rowsel), column clock signals (e.g., rowclk<0>), word line precharge signals (e.g., wlprech), and word line feedback signals (wl_fb). Furthermore, the device may have column selector logic (e.g., L1) that provides column select signals (e.g., rowsel) to word line drivers (e.g., RL0 / D0) based on first input signals (e.g., go, g1) in VDDPE. Furthermore, the device may include a level offset circuitry 408 that provides a column clock signal (e.g., rowclk<0>) to the word line driver (RL0 / D0) in the VDDCE domain based on a second input signal (e.g., xrow, ngtp) in the VDDPE domain. The level offset circuitry 408 may also provide a level offset circuitry (LS3) that provides a word line precharge signal (e.g., wlprech) to the first power connection (RL0 / D0) of the word line driver based on the second input signal (e.g., xrow, ngtp). Additionally, in some cases, the word line signal (WL<0>) may be fed back to the second power connection of the word line driver (RL0 / D0) as a word line feedback signal (wl_fb).

[0064] In various cases, the word line driver (RL0 / D0) operates in the core voltage domain (VDDCE), and furthermore, the column selector logic (L1) operates in the peripheral voltage domain (VDDPE). The word line driver (RL0 / D0) may have a first logic (RL0) and a second logic (D0), which are serially coupled and operate in the VDDCE domain. The first logic (RL0) may provide a complementary word line signal (NWL<0>) to the second logic (D0) based on the column select signal (rowsel), the column clock signal rowclk<0>, the word line precharge signal (wlprech), and the word line feedback signal (wl_fb). Further, the second logic (D0) may receive the complementary word line signal (NWL<0>) from the first logic (RL0) and then provide a word line signal (WL<0>) to the word line (WL0) based on the complementary word line signal (NWL<0>). The second logic (D0) provides the word line feedback signal (wl_fb) to the power connection of the logic device (RL0).

[0065] In various cases, the word line driver (RL0 / D0) may include multiple power connections, including, for example, a first power connection and a second power connection. As shown in FIG4A, the first power connection of the word line driver (RL0 / D0) may refer to the first power connection of the first logic (RL0), and the second power connection of the word line driver (RL0 / D0) may refer to the second power connection of the first logic (RL0). Furthermore, as shown in FIG4A, the wlprech signal can provide to the first power connection of the first logic (RL0), and further, the wl_fb signal can provide to the second power connection of the first logic (RL0).

[0066] In various cases, the level offset circuit system 408 includes a bypass level offset (LS3) configured to operate as a level offset based on a bypass signal in a first logic state. Furthermore, the bypass level offset (LS3) can also be configured to operate as a clamp based on a bypass signal in a second logic state different from the first logic state. Additionally, the level offset circuit system 408 may have input logic (e.g., L2, L6, L7) operating in the VDDPE domain, and furthermore, the level offset circuit system 408 may have output logic (e.g., L5) operating in the VDDCE domain. Moreover, the input logic (e.g., L2, L6, L7) may provide a gtp signal to the bypass level offset (LS3) as another input based on a second input signal (e.g., xrow, ngtp).

[0067] In some scenarios, the input logic (L2) may provide a global timing pulse (gtp) signal to the bypass level offsetter (LS3) based on the second input signal (ngtp). Furthermore, the bypass level offsetter (LS3) provides a level-offset precharge signal (nwlprech) to the output logic (L5) in the VDDCE domain based on the global timing pulse (gtp) signal from the input logic (L2) in the VDDPE domain and the bypass signal. Additionally, the output logic (L5) provides a word line precharge signal (wlprech) in the VDDCE domain to the first power connection of the logic device (RL0) of the word line driver (RL0 / D0) based on the level-offset precharge signal (nwprech) in the VDDCE domain.

[0068] Figure 4B shows a bypass level offset (LS3) circuit system associated with the bypass level offset (LS3) in Figure 4A. As shown in Figure 4B, the bypass level offset (LS3) circuit system may include various circuit systems and / or components configured to operate in different voltage domains, such as, for example, the VDDPE domain and the VDDCE domain. Thus, the bypass level offset (LS3) circuit system in Figure 4B may be referred to as the bypass level offset (LS3) in Figure 4A.

[0069] In some embodiments, the bypass level offset (LS3) may include input logic (e.g., LG4, I4), which is configured to receive input signals (e.g., bypass, gtp) and provide output signals to a transistor stack (e.g., T31 / T32 / T33 and T34 / T35 / T36). As shown, the first transistor stack (T31 / T32 / T33) may include a transistor T31 coupled between the supply voltage VDDCE and transistor T32, and furthermore, transistor T32 is coupled between transistor T31 and transistor T33, and furthermore, transistor T33 is coupled between transistor T32 and ground. In addition, the output from the logic gate (LG4) may be coupled to the gates of transistors T32 and T33 and the input of logic gate (I4), and the output of logic gate (I4) may be coupled to the gates of transistors T35 and T36. Furthermore, the level-shifted output signal (nwlprech) can be provided by an internal node (n7) located between transistors T32 and T33, and the internal node (n7) can be coupled to the gate of transistor T34. Another internal node (n8) can be cross-coupled to the gate of transistor T31, and in addition, the internal node (n8) can be located between transistors (T35, T36). As shown in the figure, the internal nodes (n7, n8) can be cross-coupled to the gates of transistors (T31, T34), and the output is provided by the internal node (n7).

[0070] Furthermore, in some cases, the logic gates (LG4, I4) can be configured to operate in the VDDPE domain, and further, the transistor stacks (T31 / T32 / T33 and T34 / T35 / T36) can be configured to operate in the VDDCE domain. In various cases, the first logic gate (LG4) may refer to a NOR gate, and the second logic gate (I4) may refer to an inverter. Additionally, the transistors (T31, T32, T34, T35) may refer to PMOS transistors, and the transistors (T33, T36) may refer to NMOS transistors; however, other transistor configurations may be used to achieve similar behavior, results, and characteristics.

[0071] Figure 4C shows a word line driver (WLD) circuit system 404C, as associated with the word line drivers (e.g., RL0, D0) in Figure 4A. As shown in Figure 4C, the word line driver (WLD) circuit system 404C may include various circuit systems and / or components configured to operate in the VDDCE domain. In some cases, the word line driver (WLD) circuit system 404C may include a first column logic device (RL0) having transistors (e.g., H1, H2, T41, T42, T43, T44) configured and coupled together to provide an NWL<0> signal to a second column logic device (D0) based on input signals (e.g., rowsel, rowclk<0>, wlprech) provided to the gates of the transistors (e.g., H1, H2, T41, T42, T43, T44).

[0072] In various embodiments, transistors (H1, T41) are series-coupled between the supply voltage (Vddce) and the output node (outn), and transistors (H2, T42) are series-coupled between the supply voltage (Vddce) and the output node (outn). Additionally, transistors (T43, T44) may be coupled between the output node (outn) and ground. The output node (outn) may also be coupled to the input of a column logic device (DO), which operates as an inverter to receive an output signal (NWL<0>) as an output from the first column logic and provides a WL<0> signal to the word line (WL0). The wlprech signal is coupled to the gate of the first head transistor (H1) for its activation. The wl_fb signal is coupled to the gate of the second head transistor (H2) for its activation. Furthermore, the rowclk<0> signal is coupled to the gate of the transistor (T41, T44) for starting them, and the rowsel signal is coupled to the gate of the transistor (T42, T43) for starting them.

[0073] In some embodiments, as shown in FIG4C, a word line precharge signal (wlprech) can be provided to the gate of the first head transistor (H1). Furthermore, a word line signal (WL<0>) can be provided as a word line feedback signal (wl_fb) to the gate of the second head transistor (H2). Additionally, the drains of the head transistors (H1, H2) can be coupled together via internal nodes (intn) to provide a shared drain.

[0074] Figure 5 illustrates a word line precharge timing waveform 504 according to various embodiments described herein. In some embodiments, the word line precharge timing waveform 504 is related to the input, output, and internal signals of the word line driver architecture 404A in Figures 4A to 4C.

[0075] As shown in Figure 5, the rising edge of the gtp pulse signal can trigger the rising edge of the wlprech pulse signal. Furthermore, the rising edge of the rowsel pulse signal can also trigger (and / or at least assist in triggering) the rising edge of the rowclk pulse signal. Additionally, the rising edge of the rowclk pulse signal can trigger the falling edge of the nwl signal, which in turn triggers the rising sloping edge of the wl signal. In some cases, the falling edge of the nwl signal may be curved, as it descends slowly until the resistance from the PMOS is removed.

[0076] The scope of the claims should be intended to be limited to the embodiments and illustrations provided herein, but includes modified forms of such embodiments, including portions thereof, and combinations of elements of different embodiments according to the claims. It should be understood that in the development of any such embodiments, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific objectives, such as complying with system-related and business-related limitations that may vary with the implementation. Furthermore, it should be understood that such development efforts may be complex and time-consuming, but remain routine in design, production, and manufacturing for those skilled in the art to which this disclosure pertains.

[0077] Detailed references have been provided to various embodiments, examples of which are illustrated in the accompanying drawings. In the following embodiments, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein can be practiced without such specific details. In some other instances, methods, procedures, components, circuits, and networks well-known have not been described in detail to avoid unnecessarily obscuring the details of the embodiments.

[0078] It should also be understood that although the terms "first," "second," etc., may be used herein to describe various elements, such elements should not be limited to these terms. These terms are used only to distinguish between elements. For example, a first element may be called a second element, and similarly, a second element may be called a first element. Both the first element and the second element are elements, but they are not considered to be the same element.

[0079] The terms used in the description of this disclosure provided herein are for the purpose of describing specific embodiments and are not intended to limit the disclosure provided herein. When used in the description of this disclosure provided herein and in the appended claims, the singular forms "a / an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the terms "and / or" refer to and cover any one or more of the associated enumerated items and all possible combinations thereof. When used in this specification, the terms "include," "including," and / or "comprising" specify the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or inclusion of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0080] As used herein, the term "if" may be interpreted, depending on the context, as meaning "when," "upon," "in response to determining," or "in response to detecting." Similarly, the phrases "if it is determine" or "if [a stated condition or event] is detected" may be interpreted, depending on the context, as meaning "upon determining," "in response to determining," "upon detecting [the stated condition or event]," or "in response to detecting [the stated condition or event]." The terms “up” and “down”; “upper” and “lower”; “upwardly” and “downwardly”; “below” and “above”; and other similar terms indicating relative position above or below a given point or element may be associated with some embodiments of the various techniques described herein.

[0081] Although the foregoing pertains to various implementations of the technologies described herein, other and further implementations may be devised based on this disclosure and may be determined by the scope of the patent application below.

[0082] Although the subject matter of the application has been described in specific language of structural features and / or methodological actions, it should be understood that the subject matter of the application defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as instances of implementing the claims. [Simplified Explanation of the Diagram]

[0007] Various embodiments of the technology are described herein with reference to the accompanying drawings. However, it should be understood that the drawings only illustrate the various embodiments described herein and are not intended to limit the embodiments of the various technologies described herein. [Figure 1] A diagram illustrating a word line driver architecture according to the various embodiments described herein. [Figures 2A] to [Figure 2D] Various related diagrams illustrating a word line driver architecture according to the various embodiments described herein. [Figures 3A] to [Figure 3C] Various related diagrams illustrating a word line driver architecture according to the various embodiments described herein. [Figures 4A] to [Figure 4C] Various related diagrams illustrating a word line driver architecture according to the various embodiments described herein. [Figure 5] A waveform diagram illustrating the word line precharge timing related to the various embodiments described herein.

Claims

1. An integrated device comprising: a word line driver that provides a word line signal to a word line based on a column select signal and a column clock signal; column selector logic that provides the column select signal to the word line driver based on a first input signal in a peripheral voltage domain; and a level offset circuit system that provides the column clock signal to the word line driver in a core voltage domain based on a second input signal in the peripheral voltage domain, wherein the word line driver includes a first logic and a second logic coupled in series and operating in the core voltage domain, the first logic providing a complementary word line signal to the second logic based on the column select signal and the column clock signal.

2. The apparatus of claim 1, wherein: The word line driver operates in the core voltage domain, and the column selector logic operates in the peripheral voltage domain.

3. The apparatus as claimed in claim 2, wherein: The level offset circuit system has a bypass level offset that is configured to operate as a level offset based on a bypass signal in a first logic state, and the bypass level offset is also configured to operate as a clamp based on the bypass signal in a second logic state different from the first logic state.

4. The apparatus as claimed in claim 3, wherein: When a peripheral voltage level system in the peripheral voltage domain is substantially similar to a core voltage level in the core voltage domain, the bypass level offsetter is configured to disable level offset functionality to improve performance.

5. The apparatus as claimed in claim 3, wherein: When a peripheral voltage level in the peripheral voltage domain is lower than a core voltage level in the core voltage domain, the bypass level offset device is configured to enable level offset functionality to improve performance and reduce leakage.

6. The apparatus of claim 3, wherein the level offset circuit system has input logic operating in the peripheral voltage domain, and wherein the level offset circuit system has output logic operating in the core voltage domain.

7. The apparatus of claim 6, wherein: The input logic provides a bypass signal and an internal column clock signal to the bypass level offsetter based on the second input signals. The bypass level offsetter provides a bit offset column clock signal to the output logic in the core voltage domain based on the bypass signal and the internal column clock signal from the input logic in the peripheral voltage domain. The output logic provides the column clock signal to the word line driver in the core voltage domain based on the internal column clock signal from the input logic in the peripheral voltage domain and the bit offset column clock signal from the bypass level offsetter in the core voltage domain.

8. An integrated device comprising: a word line driver that provides a word line signal to a word line based on a column select signal and a column clock signal; column selector logic that provides the column select signal to the word line driver based on a first input signal in a peripheral voltage domain; and a level offset circuit system that provides the column clock signal to the word line driver in a core voltage domain based on a second input signal in the peripheral voltage domain, wherein: The word line driver operates in the core voltage domain, and the column selector logic operates in the peripheral voltage domain. The word line driver includes a first logic and a second logic that are series-coupled and operate in the core voltage domain. The first logic provides a complementary word line signal to the second logic based on the column select signal and the column clock signal, and the second logic receives the complementary word line signal from the first logic and provides the word line signal to the word line based on the complementary word line signal.

9. An integrated device comprising: a word line driver that provides a word line signal to a word line based on a column select signal, a column clock signal, and a switching power signal; column selector logic that provides the column select signal to the word line driver based on a first input signal in a peripheral voltage domain; and a level offset circuit system that provides the column clock signal to the word line driver in a core voltage domain based on a second input signal in the peripheral voltage domain, wherein the level offset circuit system further provides a power connection of the switching power signal to the word line driver based on the second input signals, wherein the word line driver includes a first logic and a second logic coupled in series and operating in the core voltage domain, the first logic providing a complementary word line signal to the second logic based on the column select signal and the column clock signal.

10. The apparatus of claim 9, wherein: The word line driver operates in the core voltage domain, and the column selector logic operates in the peripheral voltage domain.

11. The apparatus of claim 9, wherein: The level offset circuit system has a bypass level offset that is configured to operate as a level offset based on a bypass signal in a first logic state, and the bypass level offset is also configured to operate as a clamp based on the bypass signal in a second logic state different from the first logic state.

12. The apparatus of claim 11, wherein: The level offset circuitry includes a power gate switch coupled between a core power supply and the power connection of the word line driver, and the power gate is activated by an internal control signal provided by the bypass level offset in the core voltage domain.

13. The apparatus of claim 12, wherein: The level offset circuit system has input logic operating in the peripheral voltage domain and output logic operating in the core voltage domain. The input logic provides a series of clock control signals to the bypass level offset based on the second input signals. The bypass level offset provides a level offset control signal to the output logic in the core voltage domain based on the series of clock control signals from the input logic in the peripheral voltage domain and the bypass signal. The output logic provides the internal control signal to a gate of the power gate switch in the core voltage domain based on the series of clock control signals from the input logic in the peripheral voltage domain and the level offset control signal from the bypass level offset in the core voltage domain.

14. An integrated device as claimed in claim 10, comprising: a word line driver that provides a word line signal to a word line based on a column select signal, a column clock signal, and a switching power signal; column selector logic that provides the column select signal to the word line driver based on a first input signal in a peripheral voltage domain; and a level offset circuit system that provides the column clock signal to the word line driver in a core voltage domain based on a second input signal in the peripheral voltage domain, wherein the level offset circuit system further provides a power connection of the switching power signal to the word line driver based on the second input signals, wherein: The word line driver operates in the core voltage domain, and the column selector logic operates in the peripheral voltage domain. The word line driver includes a first logic and a second logic that are series-coupled and operate in the core voltage domain. The first logic provides a complementary word line signal to the second logic based on the column select signal, the column clock signal, and the switching power signal. The second logic receives the complementary word line signal from the first logic and provides the word line signal to the word line based on the complementary word line signal.

15. An integrated device comprising: a word line driver that provides a word line signal to a word line based on a column select signal, a column clock signal, a word line precharge signal, and a word line feedback signal; column selector logic that provides the column select signal to the word line driver based on a first input signal in a peripheral voltage domain; and a level offset circuit system that provides the column clock signal to the word line driver in a core voltage domain based on a second input signal in the peripheral voltage domain, wherein the level offset circuit system further provides the word line precharge signal to a first power connection of the word line driver based on the second input signals, and wherein the word line signal is fed back to a second power connection of the word line driver as the word line feedback signal, wherein the word line driver includes first logic and second logic coupled in series and operating in the core voltage domain, the first logic providing a complementary word line signal to the second logic based on the column select signal and the column clock signal.

16. The apparatus of claim 15, wherein: The word line driver operates in the core voltage domain, and the column selector logic operates in the peripheral voltage domain.

17. The apparatus of claim 15, wherein: The first power connection of the first logic refers to the first power connection of the word line driver, and the second power connection of the first logic refers to the second power connection of the word line driver.

18. The apparatus of claim 15, wherein: The level offset circuit system has a bypass level offset that is configured to operate as a level offset based on a bypass signal in a first logic state, and the bypass level offset is also configured to operate as a clamp based on the bypass signal in a second logic state different from the first logic state.

19. The apparatus of claim 18, wherein: The level offset circuit system has input logic operating in the peripheral voltage domain and output logic operating in the core voltage domain. The input logic provides a global timing pulse signal to the bypass level offset based on the second input signals. The bypass level offset provides a level offset precharge signal to the output logic in the core voltage domain based on the global timing pulse signal from the input logic in the peripheral voltage domain and the bypass signal. The output logic provides a word line precharge signal to the first power connection of the word line driver in the core voltage domain based on the level offset precharge signal in the core voltage domain.

20. An integrated device comprising: a word line driver that provides a word line signal to a word line based on a column select signal, a column clock signal, a word line precharge signal, and a word line feedback signal; column selector logic that provides the column select signal to the word line driver based on a first input signal in a peripheral voltage domain; and a level offset circuit system that provides the column clock signal to the word line driver in a core voltage domain based on a second input signal in the peripheral voltage domain, wherein the level offset circuit system further provides the word line precharge signal to a first power connection of the word line driver based on the second input signals, and wherein the word line signal is fed back to a second power connection of the word line driver as the word line feedback signal, wherein: The word line driver operates in the core voltage domain, and the column selector logic operates in the peripheral voltage domain. The word line driver includes a first logic and a second logic that are series-coupled and operate in the core voltage domain. The first logic provides a complementary word line signal to the second logic based on the column select signal, the column clock signal, the word line precharge signal, and the word line feedback signal. The second logic receives the complementary word line signal from the first logic and provides the word line signal to the word line and provides the word line feedback signal to the first logic based on the complementary word line signal.

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