Display pixel for display screen, and display screen

Abstract

This description relates to a display pixel (12i,j) comprising at least one light-emitting diode (LED), circuitry (40) for driving the LED, and first, second, third, and fourth conductive pads (36). The driving circuitry is powered by a first power supply voltage (Vdd) received between the first pad and the second pad. The LED is powered by a first binary signal (Vcci, Veei) received between the third pad and the second pad, alternating between a second power supply voltage (Vcc) greater than the first voltage and a third voltage less than the first voltage. The driver circuitry (40) is configured to determine a digital signal (R, G, B) based on the value of a second binary signal (Dataj) received on the fourth pad during each period of a first pulse of the first binary signal at the third voltage, and to control the LED according to the digital signal.

Description

Technical Field

[0001] This disclosure relates to a display screen having display pixels including light-emitting diodes. Prior Technology

[0002] A pixel in an image corresponds to a unit element of an image displayed on a display screen. For the display of color images, to display each pixel of the image, the display screen typically includes at least three components, also called display subpixels, each of which emits light radiation substantially in a single color (e.g., red, green, and blue). The superposition of the radiation emitted by the three display subpixels provides the observer with the color perception corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display subpixels used to display the pixels of the image is called the display pixel of the display screen. Each display subpixel may include a light source, particularly a light-emitting diode (LED).

[0003] Display pixels can be arranged in an array, with each pixel located at the intersection of a column (or row) and a row in the array. Typically, each column of display pixels is selected sequentially, and the selected columns are programmed to display the desired image pixels.

[0004] An active array is a screen driving architecture that enables all pixels in a column to remain active for the entire duration of the image, as opposed to a so-called passive array, where each column is active only for time T = T frames / N (where T frames is the duration of the image and N is the number of rows on the screen). This enables increased luminance of the display screen. Furthermore, it is possible to send low voltage or current levels on the array control pipeline, enabling a larger data flow.

[0005] In the context of screens based on micrometer-scale light-emitting diodes (LEDs) formed on electronic circuitry, the size of the LED circuitry is typically smaller than the image pixel size due to the high inherent luminescence of the LEDs. Therefore, one solution employed is to deposit these unit LEDs onto a support (also known as a panel) containing driving electronics. Another solution involves using display pixels comprising LEDs and circuitry for controlling the LEDs. Then, we discuss smart pixels. This particularly simplifies the formation of active arrays because the control electronics of the LEDs in the display pixels are largely embedded within the display pixels. Document WO 2018 / 185433 describes an example of a smart pixel.

[0006] For smart pixels, the number of conductive pads used for electrical connections between the smart pixel and the support structure imposes a constraint on the size of the smart pixel, particularly due to the minimum size of these pads and the minimum space provided between them. To limit the number of conductive pads, it is known to deliver a single power supply voltage to the display pixel, and each display pixel internally generates one or more reduced power supply voltages, specifically for controlling the bias voltage of electronic components.

[0007] The static power consumption of a display pixel corresponds to the electrical power consumed by the display pixel when it is not emitting light. This static power can be generated by leakage current of the component or by the current necessary for the internal operation of the display pixel control circuitry. In the context of smart pixels, a significant portion of the static power consumption originates from the generation of the power supply voltage within the smart pixel.

[0008] It is conceivable to provide additional conductive pads on each smart pixel to supply a reduced power supply voltage to the smart pixel, so that this power supply voltage is not generated within the smart pixel. However, this would result in an increase in the size of the smart pixel, which is not desirable.

[0009] The trend is towards an increase in the number of display pixels on a screen. The static power consumption of these display pixels then becomes a key factor. In fact, for a so-called 4K display screen with a resolution of 2,160 by 3,840 display pixels, the static power consumption can exceed 150 W.

[0010] It is necessary to reduce the static power consumption of the display screen. Summary of the Invention

[0011] The purpose of this embodiment is to provide a display screen including a light-emitting diode that overcomes all or part of the disadvantages of existing display screens including light-emitting diodes.

[0012] Another objective of the embodiments is for display pixels with a size of less than 200 μm, thereby limiting the number of interconnections between display pixels and their supports.

[0013] An embodiment provides a display pixel for displaying a screen, the display pixel including at least one light-emitting diode, circuitry for driving the light-emitting diode, and first, second, third, and fourth conductive pads. The driver circuitry is powered at least partially by a first power supply voltage received between the first and second conductive pads. The light-emitting diode is powered by a first binary signal received between the third and second conductive pads. The first binary signal alternates between a second power supply voltage greater than the first power supply voltage and a third voltage less than the first power supply voltage. The driver circuitry is configured to determine a digital signal based on the value of a second binary signal received on the fourth conductive pad during each period of a first pulse of the first binary signal at the third voltage, and to control the light-emitting diode according to the digital signal.

[0014] According to one embodiment, the driver circuit is configured to control the light-emitting diode by pulse width modulation according to the digital signal.

[0015] According to one embodiment, the display pixel includes only the first, second, third, and fourth conductive pads.

[0016] According to one embodiment, the driver circuit is configured to turn the light-emitting diode on or off at the rate of a second pulse of the first binary signal at the third voltage.

[0017] According to one embodiment, the driver circuit is configured to determine a clock signal and a third binary signal based on the second binary signal.

[0018] According to one embodiment, the driver circuit includes a storage circuit for storing binary data determined based on the third binary signal during each first pulse.

[0019] According to one embodiment, the second binary signal is intended to include a mixture of a third pulse having the same duration and a fourth pulse having the same duration longer than the duration of each third pulse, the driver circuit being configured to transmit the clock signal at the same rate as the third and fourth pulses, and the third binary signal being equal to a first state or equal to a second state according to the evolution of the third and fourth pulses.

[0020] The embodiment also provides a display screen including an array of display pixels such as those previously defined, the display screen further including transmission circuitry for transmitting, for each display pixel, a first power supply voltage between the first conductive pad and the second conductive pad, a first binary signal between the third conductive pad and the second conductive pad, and a second binary signal on the fourth conductive pad.

[0021] According to one embodiment, the transmission circuits are configured such that the first conductive pad is maintained at a first substantially constant potential, the second conductive pad is maintained at a second substantially constant potential, and the third conductive pad is maintained at a third potential, the third potential alternating between a first value and a second value, wherein the first value is greater than the first potential and the second value is equal to the second potential, or the first value is equal to the first potential and the second value is less than the second potential.

[0022] According to one embodiment, the transmission circuit is configured to transmit the third voltage, which is equal to zero voltage.

[0023] According to one embodiment, the transmission circuits are configured to transmit the second binary signal alternating between two potentials, the absolute difference between the two potentials being less than the second power supply voltage.

[0024] According to one embodiment, the transmission circuits are configured to transmit the first binary signal, which for the display of an image includes the alternation of a first pulse and a second pulse at a third voltage for a first duration, each second pulse having a second duration shorter than the first duration.

[0025] According to one embodiment, the duration between two successive pairs of the second pulse is increased or decreased. Simple Explanation of the Diagram

[0026] The prior features and advantages, as well as others, will be described in detail below in the accompanying drawings by way of illustration and non-limitation of specific embodiments, in which:

[0027] Figure 1 partially and schematically illustrates a known example of a display screen;

[0028] Figure 2 is a very simplified cross-sectional view showing a known instance of a pixel;

[0029] Figure 3 is a bottom view showing the pixels in Figure 2;

[0030] Figure 4 shows a known example of the pixel-based block diagram shown in Figure 2;

[0031] Figure 5 shows a known example of a timing diagram of the display pixel signals in Figure 4;

[0032] Figure 6 partially and schematically illustrates an embodiment of the display screen according to the present invention;

[0033] Figure 7 shows a block diagram of the display pixels of the display screen in Figure 6 according to an embodiment of the present invention;

[0034] Figure 8 shows a timing diagram of the display pixel signals in Figure 7;

[0035] Figure 9 shows a block diagram of the display pixels of the display screen in Figure 6 according to another embodiment of the present invention; and

[0036] Figure 10 shows a timing diagram of the signals of the display pixels in Figure 9. Implementation

[0037] The same features have been designated by the same reference in the various figures. Specifically, structural and / or functional features shared across the various embodiments may have the same reference and may be provided with the same structure, spatial and material properties. For clarity, steps and elements useful only for understanding the embodiments described herein have been illustrated and described in detail.

[0038] In the following description, when referring to terms that define absolute position such as “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or terms that define relative position such as “above,” “below,” “up,” “down,” etc., or terms that define direction such as “horizontal,” “vertical,” etc., unless otherwise specified, the reference to the orientation of the diagram or the reference to the display screen in its normal use position is involved.

[0039] Unless otherwise indicated, when referring to two components connected together, this condition indicates no direct connection of any intermediate component other than a conductor; and when referring to two components coupled together, this condition indicates that the two components can be connected or coupled by one or more other components. Furthermore, a signal that alternates between a first constant state, indicated as "0" (e.g., low), and a second constant state, indicated as "1" (e.g., high), is called a "binary signal." Different binary signals of the same electronic circuit may have different high and low states. In practice, binary signals may correspond to voltage or current, which may not be completely constant in the high or low states. Furthermore, in the following description, the source and drain of a MOS transistor are referred to as the "power terminals" of an insulated-gate field-effect transistor or a MOS transistor.

[0040] Furthermore, unless otherwise specified, when referring to the voltage at the conductive pad, the difference between the potential at the conductive pad and a reference potential considered to be equal to 0 V, such as ground, shall be taken into account.

[0041] Unless otherwise specified, the expressions "approximately," "closely," "substantially," and "about" indicate within 10%, and preferably within 5%. Furthermore, the expression "substantially constant" means that the change relative to the reference value over time is less than 10%.

[0042] Figure 1 partially and schematically illustrates a known example of a display screen 10. The display screen 10 includes, for example, display pixels 12i,j arranged in M ​​columns and N rows, where M is an integer ranging from 1 to 8,000 and N is an integer ranging from 1 to 16,000, i is an integer ranging from 1 to M, and j is an integer ranging from 1 to N. For example, in Figure 1, M and N equal 6. Each display pixel 12i,j is coupled to a source at a low reference potential Gnd, for example, ground, via electrode 14i, and to a source at a high reference potential Vcc via electrode 16j. For example, electrode 14i is shown aligned along the columns in Figure 1, and electrode 16j is shown aligned along the rows in Figure 1; an inverted arrangement is possible. The power supply voltage of the display screen corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd. The power supply voltage depends particularly on the configuration of the light-emitting diodes and on the technology used to manufacture the light-emitting diodes. For example, the power supply voltage can be approximately from 4 V to 5 V.

[0043] For each column, display pixels 12i,j in the column are coupled to column electrode 18i. For each row, display pixels 12i,j in the row are coupled to row electrode 20j. The display screen 10 includes a selection circuit 22 coupled to the column electrodes 18i and adapted to transmit selection and timing signals Comi on each column electrode 18i. The display screen 10 includes a data transmission circuit 24 coupled to the row electrodes 20j and adapted to transmit data signals Dataj on each row electrode 20j. The selection circuit 22 and the control circuit 24 are controlled by, for example, a circuit 26 including a microprocessor.

[0044] Figure 2 is a very simplified cross-sectional view of a known example of display pixels 12 i,j, and Figure 3 is a bottom view of display pixels 12 i,j. Each display pixel 12 i,j includes control circuitry 30 covered by display circuitry 32. Display circuitry 32 includes at least one light-emitting diode (LED), preferably at least three LEDs. The display pixel includes a lower surface 34 and an upper surface 35 opposite to the lower surface 34, surfaces 34 and 35 being preferably planar and parallel. Control circuitry 30 further includes conductive pads 36 on the lower surface 34, not shown in Figure 2. Control circuitry 30 may correspond to an integrated circuit including electronic components, particularly insulated-gate field-effect transistors, also known as MOS transistors, or thin-film transistors, also known as TFTs. Preferably, display circuitry 32 includes only LEDs and the conductive elements of these LEDs, and control circuitry 30 includes all electronic components necessary for controlling the LEDs of display circuitry 32. As a variation, the display circuit 32 may also include other electronic components besides the light-emitting diodes (LEDs). The LEDs may be 2D LEDs comprising a stack of planar layers, also known as planar LEDs, or 3D LEDs each comprising three-dimensional semiconductor elements covered by an active region. In Figure 2, the LEDs are shown connected to a common anode. However, it is desirable to arrange the LEDs according to another configuration. As an example, the LEDs may be connected to a common cathode or connected independently of each other.

[0045] According to one embodiment, display pixel 12i,j includes three display sub-pixels that emit light at a first wavelength, a second wavelength, and a third wavelength. According to one embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0046] Each conductive pad 36 is intended to connect to one of the electrodes 14i, 16j, 18i, and 20j schematically shown in Figure 2. The first conductive pad 36 is coupled to the source of the low reference potential Gnd. The second conductive pad is coupled to the source of the high reference potential Vcc. The third conductive pad 36 is coupled to the column electrode 18i and receives the selection and timing signal Comi. The fourth conductive pad 36 is coupled to the row electrode 20j and receives the data signal Dataj. The size of the conductive pads 36 and the layout of the conductive pads 36 on the surface 34 are specifically imposed by the design rules of the display pixels 12i,j and by the assembly method of the display pixels 12i,j in the display screen 10.

[0047] Figure 4 shows a known example of a block diagram of display pixels 12 i,j of display screen 10. In Figure 4, the power supply voltage for the electronic components that power the block is indicated on each block.

[0048] According to one example, display pixels 12 i,j include at least three light-emitting diodes (LEDs), with individual LEDs shown in Figure 4. Each LED is connected in series to a controllable power supply CS, such as a MOS transistor. In this example, for each LED, the anode of the LED is coupled, for example, to a conductive pad 36 receiving a high reference potential Vcc, and the cathode of the LED is coupled, for example, to a terminal of the controllable power supply CS, with another terminal of the controllable power supply CS coupled to a conductive pad 36 receiving a low reference potential Gnd.

[0049] Display pixels 12 i,j further include circuitry 40 for driving a controllable power supply CS. Driver circuitry 40 may specifically include electronic components such as MOS transistors. It may be desirable to power the electronic components of driver circuitry 40 using a reduced power supply voltage, less than 4 V, for example, about 1 V or about 1.8 V; this reduced power supply voltage corresponds, for example, to a voltage that may be applied between the power terminals of the MOS transistor. For this purpose, display pixels 12 i,j include circuitry 42 (Vdd generation) for transmitting a reduced power supply voltage Vdd, specifically used for the power supply of driver circuitry 40, according to the power supply voltage Vcc. Circuitry 42 includes, for example, a voltage divider.

[0050] According to one embodiment, the detection and timing signal Com i received at one of the conductive pads 36 of each display pixel 12 i,j is a binary signal alternating between a low state "0" and a high state "1", where the low state corresponds to a low reference potential Gnd and the high state "1" corresponds to a low voltage less than the reduced power supply voltage Vdd, for example, approximately 1 V. The data signal Data j is a binary signal alternating between a low state "0" and a high state "1", where the low state corresponds to a low reference potential Gnd and the high state "1" corresponds to a low voltage less than the reduced power supply voltage Vdd, for example, approximately 1 V.

[0051] Driver circuit 40 includes circuit 44 (Clk and data separation) coupled to conductive pad 36, which receives data signal Dataj and transmits clock signal Clk and data Data according to data signal Dataj. Driver circuit 40 includes circuit 46 (mode selection), which receives signals Clk and Data, is coupled to conductive pad 36 that receives selection and timing signals Comi, and is configured to transmit signals Clk and Data to storage circuit 48 (color data register) or to transmit PWM signals to circuit 50 (LED driver) for controlling controllable power supply CS associated with each light-emitting diode (LED). Storage circuit 48 is configured to store color signals R, G, B representing the image pixels to be displayed. Circuit 50 is adapted to control the controllable power supply CS coupled to the LED with signals I_red, I_green, and I_blue, which are obtained from color signals R, G, B and from PWM signals.

[0052] As will be described below, in order to limit the number of conductive pads 36 per display pixel 12i,j, the data signal Dataj is enabled by the determination of the clock signal and color signals R, G, B for each display pixel 12i,j, which represent the light intensity required for radiation at the first, second, and third wavelengths.

[0053] Figure 5 shows a timing diagram of the signals received by display pixels 12 i,j with the structure shown in Figure 4 during the display of an image on the display screen 10.

[0054] Potentials Vcc and Gnd are generally constant. The image pixels of the new image to be displayed are displayed sequentially from column 1 to column M. The call frame duration T displays two consecutively selected, separate durations for the same column of screen 10. The timing diagrams for signals Com 1 and Data 1 will be detailed for column 1. It is known that the timing diagram for signal Com i is similar to that for signal Com 1, but with a temporal shift. The display of a new image pixel via display pixel 12 1,j in column 1 includes a first phase P1, followed by a second phase P2, where j varies from 1 to N. During phase P1, the data signal Data j is transmitted to each display pixel 12 1,j in column 1; only signal Data 1 is shown in Figure 5. During the second phase P2, the light-emitting diode of each display pixel 12 1,j is controlled according to the color signals R, G, B determined based on the data signal Data j.

[0055] During the first phase P1, the selection and timing signal Com 1 is set to state "1". The setting of the long-duration signal Com 1 to state "1" is detected by circuitry 46 for each display pixel 12 1,j in the first column, thus enabling the selection of the display pixel 12 1,j in that column, while display pixels in other columns are not selected. During the first phase P1, the data signal Data j is transmitted on the row electrode 20 j. For each display pixel 12 1,j, circuitry 44 determines the clock signal Clk and the data Data based on the pulses of the data signal Data j. For example, each pulse of the data signal Data j may have a first duration or a second duration longer than the first duration. The signal Clk may correspond to a sequence of pulses of the same duration, which have a rising edge of the same duration that coincides with the rising edge of the pulses of the data signal Data j within a possible constant offset. Data can correspond to a binary signal at state "0" when the pulse of signal Data j has a first duration, and a binary signal at state "1" when the pulse of signal Data j has a second duration. Circuit 46, selected by signal Com i at state "1", transmits data Data at the rate of clock signal Clk. This data is stored in circuit 50 in the form of digital signals R, G, and B, which have bits provided by the successive values ​​of signal Data. The end of the first cycle P1 for the column corresponds to the beginning of the first cycle P1 for the next column.

[0056] According to one embodiment, the light-emitting diodes (LEDs) of display pixels 12 1,j are controlled by pulse width modulation (PWM). For this purpose, during the second phase P2, the timing signal Com 1 is selected to represent the repetition of pulses at state "1". These pulses are transmitted via circuit 46 of each display pixel 12 1,j in the first column to circuit 50 (signal PWM) to evaluate the operation circuit 50 for controlling the LEDs via pulse width modulation. The number of pulses in the succession corresponds to the number of bits in each digital signal R, G, and B. For example, when the power supply CS corresponds to a MOS transistor, this transistor is turned on or off at the rate of PWM pulses according to the value "0" or "1" of each bit of the color signal R, G, or B, starting with the most significant bit. This transistor is maintained on or off until the next pulse of signal Com 1. The duration between two successive pulses of signal Com 1 is divided by two each time, such that the total duration of the light-emitting diode being on depends on the value of the color signal R, G, or B. The pulse succession of signal Com 1 repeats until the first phase P1 below column 1, with a single repetition illustrated as an example in Figure 5.

[0057] The static power consumption of display pixels 12 i,j is attributed to electronic components other than the MOS transistors of the driver circuit 40, particularly the effective portion of circuit 42 used to transmit the reduced power supply voltage Vdd. Current trends are increasing the number of display pixels 12 i,j on the display screen 10. The static power consumption of the display pixels can then become a critical factor. In fact, for a so-called 4K display screen 10 with a resolution of 2,160 by 3,840 display pixels, the static power consumption of the display screen 10 can exceed 150 W.

[0058] It is conceivable that, in addition to those shown in 3, additional conductive pads 36 be provided on each display pixel 12 i,j to transfer an additional high reference potential Vdd to the display pixel 12 i,j, so that the reduced power supply voltage Vdd is not generated within the display pixel 12 i,j. However, it may not be possible, and therefore may not be desirable, to add additional conductive pads 36 without increasing the lateral dimensions of the display pixels 12 i,j.

[0059] According to one embodiment of the present invention, one of the conductive pads 36 is used to receive a high power supply voltage Vcc and another conductive pad 26 is used to receive a reduced power supply voltage Vdd, without modifying the total number of conductive pads 36. Herein, the generation of the reduced power supply voltage is no longer performed within each display pixel 12i,j, and the static power consumption of the display screen is reduced. Furthermore, the lateral dimensions of the display pixels 12i,j do not need to be modified. However, to operate with the same number of conductive pads 36, the structure of the driver circuit 40 of the display pixels 12i,j is modified, and some of the signals supplied to the display pixels 12i,j are modified.

[0060] Figure 6 partially and schematically illustrates one embodiment of a display screen 60. The display screen 60 includes all the elements of the display screen 10 of Figure 1, except that electrode 16j, where j varies from 1 to N, transmits a reduced power supply voltage Vdd, and column electrode 18i, where i varies from 1 to M, transmits a high power supply voltage Vcci containing a portion of a timing signal. In the same manner as for the display screen 10, row electrode 20j transmits data signal Dataj, and electrode 14i transmits a column reference potential.

[0061] Figure 7 shows an example of a block diagram of display pixels 12 i,j of display screen 60. Display pixels 12 i,j of display screen 60 have the same structure as display pixels 12 i,j of display screen 10 shown in Figure 4, except that this display pixel does not include circuitry 42 for transmitting the reduced power supply voltage Vdd, and this display pixel further includes circuitry 62 (Vcc pulse detection) for detecting pulses of signal Vcc i, which transmits the selection and timing signal Com i to selection circuitry 46. The reduced power supply voltage Vdd is transmitted directly via one of the conductive pads 36.

[0062] Figure 8 shows a timing diagram of the signals received by display pixels 12 i,j with the structure shown in Figure 7 during the display of an image on display screen 60.

[0063] Potentials Vdd and Gnd are substantially constant. Each signal Vcc i, varying from 1 to M, is a binary signal that changes between state "1" when signal Vcc i equals the previously described high-power supply voltage Vcc, for example, approximately 4 V to 5 V, and state "0" when signal Vcc i is substantially equal to the low reference potential GND. Each signal Vcc i exhibits a first phase P1, followed by a second phase P2. During phase P1, data signal Data j is transmitted to each display pixel 12i,j in the i-th column; only signal Data 1 is shown in Figure 8. During the second phase P2, the light-emitting diodes of each display pixel 12i,j are controlled according to color signals R, G, B determined based on data signal Data j.

[0064] The signal Com i supplied by circuit 62 for each display pixel 12 i,j thus varies between state "0" and state "1", complementing the signal Vcc i. State "0" corresponds, for example, to a low reference potential GND, and state "1" corresponds, for example, to a low voltage equal to, for example, a reduced power supply voltage Vdd, such as approximately 1 V. The remaining operation of the driver circuit 40 is therefore the same as previously described with respect to Figure 5. Specifically, during the first phase, the signal Vcc i is set to state "0". The long duration of the signal Vcc i being set to state "0" is detected by circuits 62 and 46 for each display pixel 12 i,j in the i-th column, and thus enables the display pixel 12 i,j selected in this column, while the display pixels in other columns are not selected. During the first phase P1, the data signal Data j is transmitted on the row electrode 20 j. For each display pixel 12 i,j, the clock signal Clk and the data Data are determined based on, for example, the pulses of the data signal Data j as previously described. Circuit 46, selected by signal Com i in state "1", transmits data Data at the rate of clock signal Clk. This data is stored in circuit 50 in the form of digital signals R, G, and B, which have bits provided by successive values ​​of signal Data.

[0065] During the second phase P2, signal Vcc i exhibits a repetition of the pulses at state "0", which are converted into pulses at state "1" by circuit 62 of each display pixel 12 i,j in the i-th column. These pulses are transmitted to circuit 50 (PWM signal) by circuit 46 of each display pixel 12 i,j in the i-th column to evaluate the operation of circuit 50 for controlling the light-emitting diode (LED) by pulse width modulation, for example, as previously described.

[0066] Advantageously, the duration of the pulse of each signal Vcc i at state "0" during phases P1 and P2 is shorter than at least 75%, more preferably at least 80%, and more preferably at least 85% of the frame duration T. The signal Vcc i is therefore equal to the high-power supply voltage Vcc most of the time, and the power supply voltage of the LED is substantially unaffected by the pulses of signal Vcc i. This would not be the case if the high-power supply voltage were transmitted by a data signal Data j that varies substantially permanently between high and low states.

[0067] In the embodiment described previously with respect to Figure 7, the light-emitting diode (LED) is in a common anode configuration. However, it is desirable to arrange the LED in a common cathode configuration.

[0068] Figure 9 shows an example of a block diagram of display pixels 12 i,j of display screen 60, wherein the light-emitting diodes (LEDs) of display pixels 12 i,j are in a common cathode configuration. The display pixels 12 i,j shown in Figure 9 have the same structure as the display pixels 12 i,j shown in Figure 7, except that the signal Vcc i is replaced by the signal Vee i, the cathode of the LED is coupled to, for example, a conductive pad 36 that receives the signal Vee i, and the anode of the LED is coupled to, for example, a terminal of a controllable power supply CS, and another terminal of the controllable power supply CS is connected to a conductive pad 36 that receives a reduced power supply voltage Vdd.

[0069] Figure 10 illustrates a timing diagram of signals received by display pixels 12 i,j having the structure shown in Figure 9 when an image is displayed on display screen 60. Each signal Vee i, varying from 1 to M, is a binary signal that varies between state "1" where the signal Vee i is equal to the previously described reduced power supply voltage Vdd, for example, approximately 1 V or 1.8 V, and state "0" where Vee i is at a reference potential less than the reference potential GND, for example, at a negative potential, specifically approximately -2.2 V or -3 V, such that the difference between potential Vdd and potential Vee is equal to the previously described high power supply voltage Vcc. According to one embodiment, signal Vee i varies as previously described with signal Com i. In this embodiment, circuit 62 is not present because signal Vee i varies as with signal Com i, and signal Vee i can be directly used by circuit 46. However, since the dynamics of signal Vee i are different from those of signal Com i, it is desirable to provide a circuit 62 suitable for transmitting signal Com i according to signal Vee i.

[0070] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. Specifically, PWM modulation can be generated internally in the control circuitry 30 of display pixels 12i,j to avoid using the signal Comi to generate the PWM modulation. Other embodiments may also not use PWM modulation, but instead use linear driving of light-emitting diodes (LEDs). Other embodiments may also use other electro-optical components, such as organic light-emitting diodes (OLEDs).

[0071] Finally, the practical implementation schemes of the described embodiments and variations are based on the functional instructions given above and are within the capabilities of those skilled in the art. Specifically, regarding the second embodiment described in Figure 9, it is advantageous to use an SOI (silicon-on-insulator) type structure to facilitate negative voltage management.

[0072] 10: Display screen 12 i,j: Display pixels 14 i: Electrode 16 j: Electrode 18 i: Column Electrode 20 j: Row electrode 22: Selection Circuit 24: Transmission Circuit 26: Circuit 30: Control Circuit 32: Display circuit 34: Lower surface 35: Upper surface 36: Conductive pad 40: Driver circuit 42: Circuit 44: Circuit 46: Circuit 48: Storage circuit 50: Circuit 60: Display screen 62: Circuit Com i: Select timing signal Data j: Data signal LED: Light Emitting Diode Gnd: Low reference potential Vcc: Reference potential Vcc i: High power supply voltage / signal Vee i:signal Vdd: Reduced power supply voltage CS: Controllable power supply Clk: Clock signal Data: Documents R, G, B: Color signals I_red, I_green, I_blue: Signals P1: First Phase P2: Second Phase T: Call frame duration PWM: signal

[0073] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A display pixel (12i,j) for a display screen (60), the display pixel comprising at least one light-emitting diode (LED), a driver circuit (40) for driving the LED, and first, second, third, and fourth conductive pads (36), the driver circuit (40) being powered at least partially by a first power supply voltage (Vdd) received between the first conductive pad and the second conductive pad, the LED being powered by a first binary voltage (Vdd) received between the third conductive pad and the second conductive pad. The first binary signal is powered by a control signal (Vcci, Veei), which alternates between a second power supply voltage (Vcc) greater than the first power supply voltage and a third voltage less than the first power supply voltage. The driver circuit (40) is configured to determine a digital signal (R, G, B) based on the value of a second binary signal (Dataj) received on the fourth conductive pad during each period of the first pulse of the first binary signal at the third voltage, and to control the light-emitting diode according to the digital signal.

2. The display pixel as described in claim 1, wherein the driver circuit (40) is configured to control the light-emitting diode (LED) by pulse width modulation according to the digital signal (R, G, B).

3. The display pixels as described in claim 1 or 2 include only the first, second, third, and fourth conductive pads (36).

4. The display pixel as described in claim 1 or 2, wherein the driver circuit (40) is configured to turn the light-emitting diode (LED) on or off at the rate of a second pulse of the first binary signal (Vcci, Veei) at the third voltage.

5. The display pixel as described in claim 1 or 2, wherein the driver circuit (40) is configured to determine a clock signal (Clk) and a third binary signal (Data) based on the second binary signal (Dataj).

6. The display pixel as claimed in claim 5, wherein the driver circuit (40) includes a storage circuit (50) for storing binary data determined based on the third binary signal at each first pulse.

7. The display pixel as claimed in claim 5, wherein the second binary signal (Dataj) is intended to include a mixture of one of a third pulse having the same duration and a fourth pulse having the same duration longer than the duration of each third pulse, the driver circuit (40) being configured to transmit the clock signal (Clk) at the same rate as the third and fourth pulses, and the third binary signal (Data) being equal to a first state or a second state according to the evolution of the third and fourth pulses.

8. A display screen (60) comprising an array of display pixels (12i,j) according to any one of claims 1 to 7, the display screen further comprising transmission circuitry (22, 24) for transmitting, for each display pixel, a first power supply voltage (Vdd) between the first conductive pad and the second conductive pad, a first binary signal (Vcci, Veei) between the third conductive pad and the second conductive pad, and a second binary signal (Dataj) on the fourth conductive pad.

9. The display screen as claimed in claim 8, wherein the transmission circuits (22, 24) are configured to maintain the first conductive pad (36) at a substantially constant first potential (Vdd), the second conductive pad at a substantially constant second potential (GND), and the third conductive pad at a third potential, the third potential alternating between a first value and a second value, wherein the first value is greater than the first potential and the second value is equal to the second potential, or the first value is equal to the first potential and the second value is less than the second potential.

10. The display screen as described in claim 8 or 9, wherein the transmission circuits (22, 24) are configured to transmit the third voltage equal to zero voltage.

11. The display screen as described in claim 8 or 9, wherein the transmission circuits (22, 24) are configured to transmit the second binary signal (Dataj) alternating between two potentials, the absolute difference between the two potentials being less than the first power supply voltage (Vdd).

12. The display screen as described in claim 8 or 9, wherein the transmission circuits (22, 24) are configured to transmit the first binary signal (Vcci, Veei), the first binary signal for displaying an image comprising an alternation of a first pulse and a second pulse at the third voltage for a first duration, each second pulse having a second duration shorter than the first duration.

13. The display screen as described in claim 12, wherein the duration between the two pairs of the succession of the second pulse increases or decreases.

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