Method and computing device for automated standard cell design

Abstract

In one embodiment, a method includes: receiving data representing a circuit, including the arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more devices, where N is equal to the minimum number of segments; and generating individual portions of the grouped devices to form a physical layout representing a physical manifestation of the circuit, such that when the individual portions are integrated together, the individual portions form a physical manifestation of the circuit.

Description

[Technical Field]

[0001] [Cross-reference to related applications] This application claims priority to U.S. Application No. 17 / 219,539, filed March 31, 2021, which is a continuation-in-part of U.S. Nonprovisional Patent Application No. 17 / 122,689, filed December 15, 2020, which claims priority to U.S. Provisional Application No. 63 / 007,705, filed April 9, 2020. These applications are incorporated herein by reference in their entirety.

[0002] This disclosure is generally related to semiconductor devices and methods, and in particular embodiments to a method for automating standard cell design. [Previous Technology]

[0003] Integrated circuits may include one or more types of transistors. Planar transistors are a very common transistor technology. Planar transistors are manufactured using conventional planar (layer-by-layer) fabrication processes, wherein the transistor junction surfaces extend to the semiconductor surface in a plane. For example, Figure 1 shows an exemplary planar transistor 100.

[0004] A non-planar transistor, also known as a three-dimensional (3D) transistor, is a transistor whose transistor junctions reach the semiconductor surface in different planes, such as a raised source-to-drain channel, exemplified by a three-sided gate transistor, or a raised channel from the source to the drain (called a fin), exemplified by a fin field-effect transistor (FET) (FinFET). The gate of a FinFET is positioned on both sides, three sides, or four sides of the channel, or surrounds the channel, forming a dual-gate structure. Figures 2A and 2B show exemplary 3D three-sided gate transistors 200 and FinFETs 250.

[0005] Another example of a non-planar transistor is a nanosheet (NS) transistor (also known as a lateral gate-around (LGAA) transistor). Figure 3 shows an example.

[0006] Complementary FETs (CFETs) are another type of non-planar 3D transistor, in which, for example, two FETs (e.g., nFET and pFET) are stacked vertically with a vertical common gate forming a horizontal channel. For example, Figure 4 shows an exemplary CFET 400. As can be seen from Figure 4, CFETs have the advantage of resulting in simplified access to the FET terminals, which can lead to a smaller layout.

[0007] Figure 5 illustrates an exemplary vertical transistor (VFET) 500, wherein the source-gate-drain system of each transistor is stacked vertically. A VFET is called a vertical transistor because the channels are vertical, as shown in Figure 5. [Summary of the Invention]

[0008] According to one embodiment, a method includes: receiving data representing a circuit, including the arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; dividing the devices into N segments based on common features shared between two or more devices, wherein N is equal to the minimum number of segments; and generating separate portions of the grouped devices to form a physical layout representing the physical manifestation of the circuit, such that when the separate portions are integrated together, the separate portions form the physical manifestation of the circuit.

[0009] According to one embodiment, a computing device is used to generate a standard cell layout of a standard cell library. The computing device includes: a processor; and a non-transient computer-readable storage medium coupled to the processor and storing a program executable by the processor, the program including instructions for: receiving data representing a circuit, including the arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared among two or more of the devices, where N is equal to the minimum number of segments; and generating separate portions of the grouped devices to form a physical layout representing a physical manifestation of the circuit, such that when the separate portions are integrated together, the separate portions form a physical manifestation of the circuit.

[0010] According to one embodiment, a method includes: receiving data representing a circuit, including arrangements of devices, inputs, outputs, and power sources, wherein the circuit includes a plurality of nodes, and wherein the devices include a plurality of n-type field-effect transistors (nFETs) and a plurality of p-type field-effect transistors (pFETs); identifying the pFETs and nFETs of the circuit from the received data; identifying different nodes of the plurality of nodes based on the received data; and assigning a terminal count to each of the identified nodes based on the received data to form a plurality of terminal counts. The number of terminals, wherein each terminal count indicates the number of terminals of the devices coupled to the corresponding node of the identified nodes; a minimum number of segments is determined based on the number of terminal counts of the complex terminal count having an odd number; and the devices are divided into N segments based on common features shared between two or more devices, where N is equal to the minimum number of segments; and separate portions of the grouped devices are generated to form a physical layout representing the physical manifestation of the circuit, such that when the separate portions are integrated together, the separate portions form the physical manifestation of the circuit.

Implementation Method

[0032] The manufacture and use of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are only for illustrating specific ways of making and using the invention and do not limit the scope of the invention.

[0033] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments based on the description. These embodiments may be obtained without one or more specific details, or may be obtained by other methods, components, materials, and the like. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure the different forms of the embodiments. References to "embodiment" in this specification indicate that a particular configuration, structure, or feature described in relation to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this specification do not necessarily refer entirely to the same embodiment. Furthermore, particular constructions, structures, or features may be combined in any suitable manner in one or more embodiments.

[0034] Embodiments of the present invention will be described in a specific context as a method for generating standard logic cell designs in FinFET devices, CFET devices, or 3D CFET devices. Embodiments of the present invention can be used with other types of transistor technologies, such as other types of 3D transistors, such as VFETs and three-sided gate transistors.

[0035] In one embodiment of the invention, the circuit design is automatically converted into a corresponding physical layout based on a circuit netlist. In some embodiments, prior to conversion into a physical layout, the placement and routing of standard cells are automatically generated and optimized based on netlists corresponding to standard cells. After the devices (e.g., transistors) are automatically placed and routed in an optimized manner according to the netlists of standard cells, the physical layout of the standard cells is generated.

[0036] Developing new semiconductor technology nodes, such as 10-nanometer nodes (N10), 7-nanometer nodes (N7), or 5-nanometer nodes (N5), involves generating models and cell libraries so that circuits and devices can be designed using the new nodes. For example, Figure 6 shows a flowchart of an exemplary semiconductor technology design flow 600.

[0037] During step 602, a semiconductor technology node is defined. For example, during step 602, the basic standard cell and bit cell types to be implemented for the technology node are selected, and connectivity (e.g., track planning, line stacking, and power delivery networks) and design rules, profiles, and arc routing are identified.

[0038] During step 604, a process design kit (PDK) is manually generated for the semiconductor node. A PDK is a set of libraries and related materials, such as model files, physical variation rule files, etc., that allow the design of circuits and devices using specific semiconductor technology nodes. For example, during step 604, a design rule manual (DRM) and design rule check (DRC) files are generated.

[0039] During step 606, the basic standard cells identified during step 602 are manually arranged to create a standard cell library 608. The standard cell library is typically manually optimized during step 606 to, for example, minimize the amount of space occupied by the cells and make them usable by the Placement and Routing (PNR) tool during step 622.

[0040] During step 610, the performance of the standard cell is simulated in a test bench simulation environment. Simulating the standard cell during step 610 advantageously allows for testing of the standard cell at an early stage of the semiconductor node development cycle.

[0041] During step 612, parasitic extraction of standard cells is performed, and during step 614, the PDK is updated based on the results of the parasitic extraction. For example, during step 614, the PDK is updated with front-end process (FEOL) and includes parasitic resistance and capacitance.

[0042] During step 616, a net table containing standard cell cells from the results of parasitic extraction is generated.

[0043] During step 618, a Spice model is generated using technical computer-aided design (TCAD). During step 620, the Spice model generated during step 618 is used together with the netlist generated during step 616 to characterize the standard cell (e.g.) variations in process, voltage, and temperature (PVT).

[0044] During step 622, the digital circuits defined by the design netlist (e.g., written in Verilog or VHDL) are synthesized (placed in the layout) and routed based on connection information using standard cells from the standard cell library 608 (from step 602).

[0045] During step 624, for example for optimization purposes, the power performance area (PPA) of the blocks designed using the design netlist received during step 622 is evaluated.

[0046] When developing a new semiconductor node using method 600, feedback loops may exist around each step. For example, if there are a large number of DRC errors after performing steps 604 and 606, the library architecture may have to be changed. Achieving an acceptable pinout density when building the standard cell library 608 can also be an iterative process. For example, after one or more iterations of step 606, a first version of the standard cell library may achieve a low pinout density (e.g., 60%) before achieving a final higher pinout density (e.g., 75%).

[0047] Design rules and process modifications may also need to be based on the results from step 620, and additional changes may be required if the PPA target is not met during step 624. Therefore, in some cases, performing the steps of method 600 may take several months, such as six months or longer. Due to the long lead time of some steps, some feedback loops are omitted, resulting in the standard cell design being effectively fixed after execution, which may lead to solutions with lower optimization levels and may require restrictive design rules.

[0048] As semiconductor nodes shrink (e.g., from N7 to N5, then to N3, and even smaller), routing congestion may increase, potentially adding to the complexity of designing standard cell libraries. As semiconductor nodes transition to even smaller nodes, the use of non-planar transistors and 3D integration (e.g., using any type of transistor stack) becomes increasingly possible. Performing placement and routing of stacked transistors and / or non-planar transistors may require considering multiple placement and routing options to achieve an optimal placement with, for example, high placement density and / or ease of placement via automated routing tools. Therefore, as semiconductor technology nodes become smaller, manually evaluating all placement options for optimizing standard cell placement and manually designing standard cells for standard libraries may become too complex, too expensive, and / or too time-consuming to perform effectively or practically. Consequently, smaller devices may not inherently guarantee better miniaturization, power, performance, and / or cost.

[0049] In one embodiment of the invention, a standard cell library with optimized layout is automatically generated based on a technology definition. In some embodiments, by automatically generating the layout of standard cells, new semiconductor technology nodes can be evaluated based on standard cells generated in the context of placement and routing (rather than isolatedly, prior to placement and routing) to, for example, determine miniaturization, power, performance, and cost in significantly less time (e.g., weeks vs. months) compared to manually performing the placement of standard cells. For example, Figure 7A shows a flowchart of an embodiment of a semiconductor technology design flow 700 according to an embodiment of the invention.

[0050] As shown in Figure 7A, design flow 700 is similar to design flow 600, but includes step 702 for automatically generating standard cells. By automatically generating standard logic cells, some embodiments advantageously and significantly reduce the amount of time (e.g., from months to weeks) spent generating an optimized standard cell library, for example, by omitting the execution of one or more steps 604, 606, and 614, while automatically generating the standard cell library and associated PDK during step 702.

[0051] For example, in some embodiments, the design rules in the PDK (step 604) are replaced with instructions (e.g., rules) for the automatic generation of standard cells (during step 702). In some embodiments, since the behavior of the instructions (e.g., procedural instructions) for the automatic generation of standard cells (in step 702) is more predictable than that of a human designer performing manual cell layout during step 606, perhaps only (e.g., substantially) fewer rules are needed. Furthermore, advanced technology nodes may be highly constrained. Therefore, in some embodiments, it may be more efficient to instruct the automatic standard cell generation system (in step 702) to design the layout of standard cells, rather than instructing humans during manual layout design (step 606) on what to avoid to conform to, for example, a broad list of rules constrained by advanced nodes.

[0052] Therefore, in some embodiments, the Design Rule Check (DRC) platform in the PDK can be eliminated because standard cells can be correctly generated by construction. For example, in some embodiments, automatic cell generation of standard cells can correctly and systematically generate layouts optimized to meet semiconductor node requirements. Therefore, in some embodiments, removing the step of manually laying out standard cells (step 606) and replacing it with automatic standard cell placement during step 702 will advantageously allow for optimized and correct placement of standard cells that meet semiconductor node requirements in a (e.g., substantially) shorter timeframe.

[0053] In some embodiments, step 614 can be eliminated by directly running the resistance and capacitance extraction in the simulation (step 610). In some embodiments, performing such parasitic extraction during step 610 is advantageously permitted by, for example, the consistency of the output generated during step 702. Even though performing parasitic extraction during step 610 may be more time-consuming than running the abstract extraction platform during step 614 in some embodiments, performing parasitic extraction during step 610 can advantageously provide efficiency for early iterative optimization.

[0054] A standard cell (e.g., those in standard libraries 608 and 708) is a physical representation of a normalized Boolean logic function. An example of a standard cell is a half-adder, which is configured to add two binary numbers. Other examples of standard cells include NAND gates, NOR gates, D-type flip-flops, arithmetic logic units (ALUs), etc. In some embodiments, a standard cell library may include more than 50 standard cells, for example, between 50 and 100 standard cells, such as 80 standard cells.

[0055] In some embodiments, method 700 may be implemented in a computing device coupled to memory for storing a program executable by the process, wherein the program includes instructions for performing method 700. For example, FIG7B illustrates a computing device 750 according to an embodiment of the present invention. As shown, computing device 750 includes a processor 752 coupled to memory 754, a display 756, and a communication interface 758. In some embodiments, processor 752 may be implemented as a general-purpose processor, an application-specific integrated circuit (ASIC), a microprocessor, or other processing logic capable of interpreting and executing instructions stored in memory 754.

[0056] The display 756 is configured to display, for example, a layout diagram (e.g., generated during step 702). The display 756 may be a computer screen and may be implemented in any manner known in the art.

[0057] Memory 754 is configured to store a program including instructions for performing, for example, method 700. Memory 754 is also configured to temporarily or permanently store digital files of intermediate or final output generated during method 700 (e.g., during step 702). Memory 754 may be implemented in any manner known in the art, for example, as non-volatile memory.

[0058] The communication interface 758 is configured to transmit, for example, intermediate or final output generated during method 700 (e.g., during step 702) to other computing devices and / or other storage media, such as digital files including layout information of the standard cell library 708.

[0059] In some embodiments, one or more steps of method 700 may be implemented in different computing devices.

[0060] Figures 8A-8D illustrate four different representations of a half-adder cell according to an embodiment of the present invention. Figure 8A shows a truth table for a half-adder, where A and B are the first and second inputs, respectively, and C and S are the output carry and sum, respectively. Figure 8B shows a schematic diagram 800 of implementing the truth table of Figure 8A in a CMOS circuit.

[0061] Figure 8C shows a netlist for implementing circuit 800. In some embodiments, the connectivity list is, for example, an abstract representation of the design or layout of electronic components required to implement the desired logical behavior of a standard cell design, which can be stored in a digital archive.

[0062] As shown in Figure 8C, the netlist includes all components of circuit 800 (transistors in this example), specifying the gate, input, and output signals of each transistor. The netlist also includes references to power sources (VDD and VSS), where a power source can be understood as a node or track capable of transmitting power to the transistor. In some embodiments, the netlist (also called a connectivity list) includes transistor names that reference the connections of the transistor's input, output, and gate signals. For example, transistor M13 is the rightmost NMOS transistor in Figure 8B, connected to VSS (GND), node N4, and carry output. As shown in Figure 8B, node N4 provides common electrical characteristics, features, or connections between transistors M3, M4, M5, M6, M8, and M12. The remaining nodes represent common connections between the transistors shown in Figure 8B. In some embodiments, the netlist of Figure 8C can be extended to include other circuit details, such as the type of transistor (n-type or p-type).

[0063] Figure 8D illustrates an exemplary physical layout of circuit 800 using a 5.5T (i.e., cell height = 5.5 metal tracks) FinFET design. In some embodiments, a netlist (e.g., as shown in Figure 8C) is input data for performing step 702. For example, in some embodiments, generating a netlist is a first step in converting a circuit design existing in a theoretical or virtual model (e.g., Figure 8B) into a physical representation or physical layout (e.g., Figure 8D).

[0064] Figure 9 shows a flowchart of an embodiment of a method 900 for automatically generating the physical layout of standard cells based on a netlist according to an embodiment of the present invention. Step 702 can be executed as method 900 and can be implemented by computing device 750.

[0065] Method 900 can be understood as a method including device placement steps (steps 902, 904, 906, 908, 910, 912, 914, and 918) and device routing steps (steps 916 and 920). In some embodiments, the device placement step may be performed automatically (e.g., as described in method 900), while the placement step may be performed in a conventional manner. In some embodiments, the device routing step may be performed automatically (e.g., as described in method 900), while the placement step may be performed in a conventional manner.

[0066] During step 902, a netlist is received and transistor pairs with a first type of shared connectivity (e.g., gates connected together) are identified. In some embodiments, the first type of connectivity may be a free connectivity, where the term "free connectivity" can be understood as: a connectivity that can be formed by placement without routing work. In some embodiments, the first type of connectivity may be referred to as the most important free connectivity. In some embodiments, such as in planar transistors, FinFETs, and tri-gate transistors, the gates of complementary transistors are the first type of free connectivity, where a single multi-gate can switch between p-type and n-type transistors. In other embodiments, such as in architectures based on heterogeneous sequential 3D integration, the first type of free connectivity may be different from the gate (e.g., source / drain). Some embodiments may exhibit more than one free connectivity. For example, in a stacked transistor architecture, the first type of free connectivity may relate to horizontal connectivity between transistors in the same stack layer, and the second type of free connectivity may relate to vertical connectivity between transistors in different layers of the stack.

[0067] During step 904, objects are formed for each of the transistor pairs identified in step 902, wherein each object is identified by inputs and outputs (e.g., common gate input and nFET and pFET inputs and outputs). In some embodiments, the objects are stylized objects, such as object-oriented data structures, matrices, or vectors, such as tensors. In some embodiments, the objects formed during step 904 do not specify the signal flow direction, and such signal flow can be reversed (e.g., between drain and source) without altering functionality.

[0068] During step 906, the transistor pairs generated during step 904 are clustered based on their common inputs / outputs. For example, after identifying the inputs and outputs of each transistor pair, the two transistor pairs are clustered together when they share a common connection (e.g., the transistor pairs are connected to the same node). In some embodiments, clustering is performed by associating the transistor pairs with, for example, indicators (e.g., stored in the transistor pairs) or database tables (e.g., stored in memory 754). In some embodiments, other programming techniques known in the art may be used.

[0069] During step 908, the transistor pair objects are flipped to align the common input / output of the transistor pair objects, thereby clustering the flipped transistor pair objects while sharing a common input / output. In some embodiments, this flipping step is performed, for example, by means of data structure, vector, or matrix transformation. In some embodiments, other programming techniques known in the art may be used. In some embodiments, steps 906 and 908 may be performed together.

[0070] During step 910, transistor pairs and clusters of transistor pairs are merged into a larger cluster by overlapping common inputs / outputs. In some embodiments, the merging step is performed by associating the inputs / outputs of transistor pairs, for example, using indicators or database tables. In some embodiments, other programming techniques known in the art may be used. In some standard cells, the entire logic function may be visualized in a single cluster during step 910. In some standard cells, more than one cluster may be used to visualize the entire logic function.

[0071] During step 912, unnecessary internal nodes (also referred to as closed internal nodes or completed nodes) are identified and eliminated. In some embodiments, the elimination of unnecessary internal nodes is performed, for example, by removing references to nodes from a set of open nodes stored in memory 754. Nodes that require further connectivity (e.g., nodes that should be connected to another node but were not connected as a cluster during step 910) are identified.

[0072] During step 914, the cluster is arranged according to a technology-specific routing track plan in the cluster diagram, for example, to resemble the final physical layout image. In some embodiments, the track plan includes routing rules (e.g., minimum metal length, connection limits, etc.) and the number of tracks. For example, in some embodiments, the technology-specific routing track plan may require a single row, and therefore, in such techniques, the cluster is arranged in a single row. Other techniques may allow multiple rows, such as 2, 4, or more (which may be referred to as multi-column height cells). In some embodiments, the cluster extends beyond a single column, for example, 20 rows or more. In some embodiments, cluster diagram generation includes the generation of a digital file that includes location information of components identified in the netlist of the track plan, such as the positions of gate, source, and drain contacts relative to different tracks and rows of the track plan.

[0073] In some embodiments, a cost function can be used to reward the arrangement, for example, based on reducing internal wiring congestion within cells. In some embodiments, a machine learning-trained model can be used, for example, to optimize the placement based on a cost function (e.g., reducing internal wiring congestion within cells).

[0074] During step 916, open nodes (e.g., nodes that still need to be connected after steps 912 or 914) are identified in the cluster graph. For example, a node to be connected to external circuitry (e.g., pins) or a node to be connected to other nodes within the cluster can be identified as an open node. In some embodiments, the identification of open nodes may be performed, for example, using bits in a recorder or data structures in memory 754 that indicate whether a node needs to be connected.

[0075] During step 918, each row of the technology-specific wiring track plan is mapped to a predefined technology construct from a set of predefined technology constructs. This set of predefined technology constructs includes a limited number (e.g., all possible implementations) of the basic devices (e.g., pFETs and nFETs) in a particular technology-specific wiring track plan. In some embodiments, this set of predefined technology constructs is manually generated. For example, as will be described in more detail later with respect to, for example, FIG11K, in some embodiments, each construct may be obtained in layout form. In some embodiments, the mapped layout constructs are stored in a digital archive in the form of (e.g., partial) physical semiconductor layouts. In some embodiments, a different set of constructs may be used instead of the constructs shown in FIG11K to map the track plan (e.g., as shown in FIG11I) to a physical layout.

[0076] After selecting and placing a predefined technical configuration according to the output of step 914, routing of the remaining open nodes is performed using, for example, readily available routing tools. The output of step 920 is the final layout, which may, for example, be displayed on a screen and / or printed on paper or other media, and / or may be output, for example, for generating a corresponding mask for semiconductor device manufacturing, wherein the semiconductor device manufacturing can be performed by applying a photoresist and patterning a substrate based on the generated mask.

[0077] In some embodiments, files associated with intermediate steps during steps 902, 904, 906, 908, 910, 912, 914, 916, 918, and / or 920 may (e.g., temporarily or permanently) be stored in memory 754 and may be read from memory 754 during steps 902, 904, 906, 908, 910, 912, 914, 916, 918, and / or 920. For example, in some embodiments, objects (such as transistor pairs, transistor pairs, flipped transistor pairs, etc.) may be stored in memory 754 and read back from memory 754 during or after the step of creating the object. Digital files, including information related to track planning, routing, placement, and layout (e.g., generated during steps 914, 916, 918, and / or 920), can also be stored in memory 754 and can be read from memory 754 during or after the step of creating the file. Representations of objects and / or information (e.g., stored in digital files) created or used during any of steps 902, 904, 906, 908, 910, 912, 914, 916, 918, and / or 920 can be displayed on display 756 during or after the step of creating or using the object or information.

[0078] In some embodiments, the resulting physical layout of (e.g., one or more) standard cells (e.g., or the entire standard cell library 708) (e.g., which may be stored in a digital archive in memory 754) can be used for RC extraction (during step 612) and allows the generation of a corresponding netlist including parasitic parameters (step 616) for performing cell characterization (620).

[0079] In some embodiments, the execution of one or more of steps 902, 904, 906, 908, 910, 912, 914, 916, and / or 918 advantageously improves the means for generating standard cell layouts for a standard cell layout library by, for example, by reducing the time spent achieving, for example, the optimal layout for a particular track plan, which advantageously allows for the evaluation of technical nodes early in the design phase.

[0080] Figure 10 shows a flowchart of an embodiment of a method 1000 for designing and manufacturing integrated circuits using a standard cell library 708 according to an embodiment of the present invention.

[0081] During step 1002, the synthesis, placement, and routing of the integrated circuit design netlist are performed using standard cells from the standard cell library 708. During step 1004, a (e.g., complete) design simulation is performed based on the integrated circuit layout generated during step 1002. During step 1006, a mask set is fabricated having masks corresponding to the layout generated during step 1002. The mask set includes a set of masks having geometry corresponding to patterns of metal, oxide, or semiconductor layers constituting the integrated circuit assembly. During step 1008, the mask set is sent to a semiconductor foundry for, for example, integrated circuit fabrication using a lithography process.

[0082] Figures 11A-11L illustrate the performance of a method 900 for converting the netlist (half-adder) of Figure 8C into a physical layout using non-stacked FinFET technology according to an embodiment of the present invention. For example, Figures 11A, 11B, 11C, 11D, 11E, and 11F illustrate steps 902, 904, 906, 908, 910, and 912, respectively. Step 914 is shown in Figures 11G and 11I. Step 916 is shown in Figure 11I, and steps 918 and 920 are shown in Figures 11J and 11L, respectively.

[0083] Figure 11A illustrates a pair of complementary transistors with a common gate according to an embodiment of the present invention (step 902). For example, the netlist of Figure 8C includes pMOS transistors M0, M1, M2, M3, M4, M5, and M6, and nMOS transistors M7, M8, M9, M10, M11, M12, and M13. As shown in Figure 11A, pMOS-nMOS pairs with a common gate are identified and paired together. For example, pMOS transistor M0 and nMOS transistor M7 share a common gate (the gates of transistors M0 and M7 are connected to node N1). PMOS transistor M1 and nMOS transistor M9 share a common gate (connected to node B). PMOS transistor M2 and nMOS transistor M10 share a common gate (connected to node A). PMOS transistor M3 and nMOS transistor M8 share a common gate (connected to node N4). PMOS transistor M4 and nMOS transistor M11 share a common gate (connected to node A). PMOS transistor M5 and nMOS transistor M12 share a common gate (connected to node B). PMOS transistor M6 and nMOS transistor M13 share a common gate (connected to node N4).

[0084] Although Figure 11A shows step 902 applied to a FinFET device, similar or identical steps can be performed for other technologies (e.g., for CFET devices).

[0085] In some embodiments, each complementary transistor pair identified in FIG11A becomes an object, as shown in FIG11B. The object may be a data structure, tensor vector, or others. For example, as shown in FIG11B, the object identified in FIG11 (step 902) may be represented as a transistor icon. For example, the complementary transistor pair M0 / M7 is represented as object 1102, having a gate input N1 (which is connected to the gates of transistors M0 and M7) and input / output terminals VDD, VSS, and Sum. The complementary transistor pair M1 / M9 is represented as object 1104, having a gate input B (which is connected to the gates of transistors M1 and M9) and input / output terminals VDD, VSS, N0, and N2. Complementary transistor pair M2 / M10, designated as object 1106, has gate input A (connected to the gates of transistors M2 and M10) and input / output terminals N0, VSS, N1, and N2. Complementary transistor pair M3 / M8, designated as object 1108, has gate input N4 (connected to the gates of transistors M3 and M8) and input / output terminals VDD, N2, and N1. Complementary transistor pair M4 / M11, designated as object 1110, has gate input A (connected to the gates of transistors M4 and M11) and input / output terminals VDD, VSS, N4, and N3. Complementary transistor pair M5 / M12, designated as object 1112, has gate input B (connected to the gates of transistors M5 and M12) and input / output terminals VDD, N3, and N4. The complementary transistor pair M6 / M13 is designated as object 1114, having a gate input N4 (connected to the gates of transistors M6 and M13) and input / output terminals VDD, VSS, and Carry.

[0086] In some embodiments, the transistor icon of the identified object (e.g., as shown in FIG11B) may be displayed on the display 756.

[0087] Although Figure 11B shows step 904 applied to a FinFET device, similar or identical steps can be performed for other technologies (e.g., for CFET devices).

[0088] Figures 11C-11F illustrate the steps of a method 900 for optimizing and / or modifying the arrangement of transistors within the construction of an electrical design when implemented with FinFET, for example, making the final physical layout or arrangement of the electrical design components smaller and / or easier to route and implement the actual operation of the electrical design (in this example, a half-adder).

[0089] FIG11C illustrates associating transistor pairs into clusters based on common input / output connections according to an embodiment of the present invention (step 906). For example, transistor pairs 1102 and 1114 share common inputs / outputs (VDD and VSS). Transistor pairs 1112 and 1110 share common inputs / outputs (VDD, N3, and N4). Transistor pairs 1110 and 1104 share common inputs / outputs (VDD and VSS). Transistor pairs 1104 and 1106 share common inputs / outputs (NO and VSS). As shown in FIG11C, three clusters (1122, 1124, and 1126) are identified.

[0090] In some embodiments, transistor pairs can be mirrored completely or partially about the y-axis without altering their functionality. Therefore, as shown in FIG11C, transistors in transistor pairs that can benefit from flipping (e.g., due to shared connectivity) can be identified. As shown in FIG11C, in this example, transistors M0, M7, M12, M4, M11, and M10 are identified for flipping.

[0091] As can be seen from Figure 11C, other clusters and transistor pair associations are possible (e.g., objects 1108 and 1106 can be associated based on common nodes N1 and N2). As can also be seen in Figure 11C, other transistor flips can be identified (e.g., flipping transistor 1112 based on shared connection VDD while not flipping transistor 1110). In some embodiments, all possible associations and permutations of transistor pairs are evaluated, and an association that results in fewer clusters is selected.

[0092] In some embodiments, all possible associations and permutations of transistor pairs and transistor flips are evaluated, and associations that result in fewer clusters and / or minimize the distance between nodes are selected.

[0093] FIG11D illustrates the transistor pair objects after cluster association and transistor flipping (as identified in FIG11C) based on the common input / output connection (step 908) according to an embodiment of the present invention.

[0094] FIG11E illustrates the merging of (e.g., repeated shared) nodes after step 908 (step 910) according to an embodiment of the invention. For example, each transistor pair object (e.g., as shown in FIG11D) includes a gate node (connected to the gate of the complementary transistor), two inputs, and two outputs (for each complementary transistor). During step 910, repeated shared nodes are merged, and the resulting cluster may have fewer inputs / outputs than the transistor pairs they combine. For example, cluster 1122 includes four input / output nodes (Sum, VDD, VSS, and Carry) in addition to gate nodes N1 and N4, fewer than the six input / output nodes shown in cluster 1122 in FIG11D. In cluster 1124, nodes N4 (between transistors M5 and M4), N3 (between transistors M12 and M11), VDD (between transistors M4 and M1), VSS (between transistors M11 and M9), N0 (between transistors M1 and M2), and N2 (between transistors M9 and M10) are merged. Node N1 is merged from cluster 1126. In some embodiments, the transistor icons of the merged clusters are displayed on display 756 (e.g., as shown in FIG11E).

[0095] Figure 11F illustrates the elimination (step 912) of nodes that are only local to a cluster and do not require external connectivity (whether internally or to other clusters) according to an embodiment of the invention. For example, in cluster 1122, no node is eliminated because Sum and Carry are external pins of the standard cell, VDD and VSS are power source nodes, and nodes N1 and N4 are gate nodes. In cluster 1124, nodes N3 and N0 are local nodes to cluster 1124 and are therefore eliminated. Node N4 requires further internal connectivity (between the current path terminals of transistor M12 and M5) and is therefore not eliminated (node ​​N4 is also connected to other clusters and is therefore retained for this reason). Nodes N2 and N1 are connected to clusters 1122 and / or 1126 and are therefore not eliminated. Nodes A and B are external pins of the standard cell and are therefore not eliminated. In cluster 1126, no nodes are eliminated. In some embodiments, the transistor icons of the resulting cluster are displayed on display 756 (e.g., as shown in FIG11F).

[0096] FIG11G illustrates the arrangement of clusters 1122, 1124, and 1126 in a technology-specific wiring track plan (step 914) according to an embodiment of the present invention. In this example, the wiring track plan is limited to a single-row complementary transistor pair, and therefore, clusters 1122, 1124, and 1126 are arranged in a single row (as shown in FIG11G). In some embodiments, transistor icons of the resulting cluster arrangement are displayed on a display 756 (e.g., as shown in FIG11G).

[0097] FIG11H illustrates a 3D view of a technology-specific wiring track plan for a non-stacked FinFET according to an embodiment of the present invention. As shown in FIG11H, the track plan includes four signal tracks (1134, 1136, 1140, and 1142). Signal tracks 1134 and 1136 can be used to route the gate or source / drain of a pFET using contacts. Signal tracks 1140 and 1142 can be used to route the gate or source / drain of an nFET using contacts. It should be understood that the 3D view shown in FIG11H is a non-limiting example corresponding to a specific arrangement of devices in the track plan (in this example, corresponding to configuration 1193 shown in FIG11K), and, for example, the placement of contacts and other connections can be different, different nodes can be connected, or they can be omitted, depending on the specific connections to be made (e.g., as shown in the various configurations illustrated in FIG11K).

[0098] It should be understood that the track plan shown in FIG11H is a non-limiting example of possible track plans. For example, track plans with different numbers of tracks or different accesses to the tracks may also be used. For example, in some embodiments, the track plan may include fewer than four signal tracks, such as three or two. In some embodiments, the track plan includes more than four tracks, such as five, six, eight, or more tracks.

[0099] FIG11I illustrates a mapping (e.g., step 914) of a cluster arrangement, such as that shown in FIG11G, to a technology-specific wiring track plan illustrated in FIG11H, according to an embodiment of the present invention. As shown, the wiring track plan includes a single row of tracks, including tracks 1132, 1134, 1136, 1140, and 1142. Tracks 1132 and 1144 correspond to power rails VDD and VSS (or ground), respectively. Track 1138 illustrates the separation between the nMOS and pFET, as it is not used for routing signals (in this example, the pFET is located in the upper half above track 1138, and the nFET is located in the lower half below track 1138). Tracks 1134, 1136, 1140, and 1142 are available signal wiring tracks that can be routed.

[0100] Each row shown in Figure 11I represents a possible location of a node or electrically isolated structure, such as a diffusion interruption. Diffusion interruptions can be used for isolation purposes, for example, when transistors cannot be positioned such that the output of one transistor becomes the input of an adjacent transistor. For example, rows 1131, 1133, 1135, and 1137 represent diffusion interruptions that can be filled with virtual polysilicon. In some embodiments, such diffusion interruptions separate clusters and separate half-adder cells from adjacent cells. In some embodiments, diffusion interruptions separate clusters. For example, in Figure 11I, diffusion interruptions 1133 and 1135 separate clusters 1122, 1124, and 1126, and diffusion interruptions 1131 and 1137 separate half-adder cells from adjacent cells.

[0101] Rows 1141, 1143, 1145, 1147, 1149, 1151, 1153, 1155, 1157, 1159, 1161, 1163, 1165, 1167, 1169, 1171, and 1173 correspond to transistor nodes and are also shown in Figure 11G. Therefore, the cells at the intersections of rows 1141, 1143, 1145, 1147, 1149, 1151, 1153, 1155, 1157, 1159, 1161, 1163, 1165, 1167, 1169, 1171, and 1173 with columns 1132, 1134, 1136, 1140, 1142, and 1144 correspond to possible transistor node locations. For example, row 1141 includes current path nodes for transistors M5 (connected to VDD in columns 1132 and row 1141) and M12 (connected to node N4 in columns 1142 and row 1141); row 1143 includes gate nodes for transistors M5 (connected to node B in columns 1134 and row 1143) and M12 (connected to cells in columns 1142 and row 1143 and connected to cells in columns 1134 and row 1143); row 1145 includes current path nodes for transistors M5 (in columns 1134 and row 1145), M4 (connected to node N4 in columns 1136 and row 1145 and connected to the current path of transistor M5 in columns 1134 and row 1145), and M11 (connected to the gate of transistor M5 in columns 1142 and row 1145 and in columns 1142 and row 1143); and so on.

[0102] Figure 11I also illustrates the identification of open nodes in a technology-specific cabling track plan (step 916). For example, nodes B and N1 are identified in track 1134 of cluster 1124. Node N4 is identified in track 1136 of cluster 1124. Node A is identified in track 1140 of cluster 1124. Nodes N4 and N2 are identified in track 1142 of cluster 1124. Node N1 is identified in track 1134 of cluster 1126. Node N4 is identified in track 1136 of cluster 1126. Node N2 is identified in track 1142 of cluster 1126. Node N1 is identified in track 1134 of cluster 1122. Node N4 is identified in track 1136 of cluster 1122. Node C (Carry) is identified in track 1140 of cluster 1122. Node S (Sum) is identified in track 1142 of cluster 1122. Open connections within each cluster are also identified, for example, they may be made of metal at a higher level. For example, nodes N4 in tracks 1136 and 1142 of cluster 1124 can be connected to each other using metal M1 (e.g., a first metal layer above the top of the semiconductor substrate).

[0103] As shown in Figure 11I, the cell located in row 1141 and column 1142 corresponds to node N4 of transistor M12. The cell located in row 1143 and column 1134 corresponds to node B of transistor M5. The cell located in row 1145 and column 1136 corresponds to node N4 of transistor M5. The cell located in row 1147 and column 1140 corresponds to node A of transistor M11 (the gate node is shared between complementary cells). The cell located in row 1151 and column 1134 corresponds to node B of transistor M1. The cell located in row 1153 and column 1142 corresponds to node N2 of transistor M9. The cell located in row 1155 and column 1140 corresponds to node A of transistor M10. The cell located in row 1157 and column 1134 corresponds to node N1 of transistor M2. The cell located at row 1159 and column 1142 corresponds to node N2 of transistor M8. The cell located at row 1161 and column 1136 corresponds to node N4 of transistor M3. The cell located at row 1163 and column 1134 corresponds to node N1 of transistor M3. The cell located at row 1165 and column 1142 corresponds to node S (Sum) of transistor M7. The cell located at row 1167 and column 1134 corresponds to node N1 of transistor M0. The cell located at row 1171 and column 1136 corresponds to node N4 of transistor M6. The cell located at row 1173 and column 1136 corresponds to node C (Carry) of transistor M13.

[0104] The cell at power source rail 1132, identified as VDD (cells at rows 1141, 1149, 1159, and 1169) corresponds to the VDD node (e.g., for external connection). The cell at power source rail 1144, identified as VSS (cells at rows 1149, 1157, and 1169) corresponds to the VSS (ground) node (e.g., for external connection).

[0105] As shown in Figure 11I, some nodes are shared among more than one cell. Therefore, in some embodiments, more than one cell can be used for routing connections (e.g., cells located in rows 1145, columns 1134, and 1136 can all be used to connect node N4). In some embodiments, all possible cell selections are evaluated, and the cell that results in the shortest wiring (shortest connection) is selected (in this example, the cell located in row 1145, column 1136 results in a shorter connection to the cell at row 1141, column 1142, and is therefore selected). In some embodiments, similar nodes are assigned to the same track (in this example, node N4 is routed using track 1136).

[0106] In some embodiments, a representation of a track plan, such as that shown in FIG11I, is displayed on a display 756 (e.g., as shown in FIG11I).

[0107] FIG11J illustrates the mapping of each row (rows 1131, 1133, 1135, 1141, 1143, 1145, 1147, 1149, 1151, 1153, 1155, 1157, 1159, 1161, 1163, 1165, 1167, 1169, 1171, and 1173, e.g., as shown in FIG11I) in a technology-specific wiring track plan according to an embodiment of the present invention from a set of predefined technology constructions to predefined technology constructions (also referred to as device layout constructions, e.g., as shown in FIG11K) (step 918). Although gaps between constructions are shown in FIG11J, such gaps may not exist in the actual placement of the constructions in the layout.

[0108] This set of predefined technical configurations includes a limited number of possible implementations (e.g., all possible implementations) of the basic device (e.g., transistor) in a specific technical routing track plan. For example, FIG11K illustrates a set of predefined technical configurations with source / drain and gate connections for the 5.5T FinFET technology illustrated in FIG11A-11L according to an embodiment of the invention. For example, configuration 1170 corresponds to a diffusion interruption (e.g., implemented in rows 1131, 1133, 1135, and 1137). Configurations 1170-1193 correspond to possible implementations of pFETs and nFETs in the routing plan, including different possible locations of source, gate, and drain connections. For example, configurations 1171, 1172, 1173, and 1174 correspond to possible gate connections of complementary transistors, wherein the shared gate contact is located on tracks 1134, 1136, 1140, or 1142, respectively. Configuration 1175 corresponds to the VDD and VSS connections of the pFET and nFET, respectively. Configuration 1176 corresponds to the VDD connection of the pFET. Configuration 1177 corresponds to the VDD connection of the pFET and the nFET signal contact on track 1140. Configuration 1178 corresponds to the VDD connection of the pFET and the nFET signal contact on track 1142. Configuration 1180 corresponds to the VSS connection of the nFET and the pFET signal contact on track 1134. Configuration 1181 corresponds to the VSS connection of the nFET and the pFET signal contact on track 1136. Configuration 1182 corresponds to a closed node without connections. Configurations 1183-1186 correspond to the pFET signal contacts on tracks 1134, 1136, 1140, and 1142, respectively. Configurations 1187-1190 correspond to the connected pFET and nFET source / drain terminals, which have signal contacts on tracks 1134, 1136, 1140, and 1142, respectively. Configuration 1191 corresponds to the connected pFET and nFET source / drain terminals, with no other connections. Configuration 1191 corresponds to a split gate (the gates of the pFET and nFET with independent contacts). Configuration 1193 corresponds to the pFET signal contact on track 1134 and the nFET signal contact on track 1142.

[0109] Lines 1143, 1151, and 1167 are implemented as construct 1171. Lines 1161 and 1171 are implemented as construct 1172. Lines 1147 and 1155 are implemented as construct 1173. Other lines are implemented with other constructs. For example, lines 1141 and 1159 are implemented as construct 1177; line 1145 is implemented as construct 1184; lines 1149 and 1169 are implemented as construct 1175; line 1153 is implemented as construct 1186; line 1157 is implemented as construct 1180; line 1163 is implemented as construct 1187; line 1165 is implemented as construct 1190; and line 1173 is implemented as construct 1189.

[0110] In some embodiments, a representation of a trajectory plan constructed (e.g., as shown in FIG11J) is displayed on a display 756 (e.g., as shown in FIG11J).

[0111] Figure 11L shows the final layout of the half-adder according to an embodiment of the present invention, wherein off-the-shelf tools are used to perform routing of open nodes between the constructions (step 920). As shown in Figure 11L, signal routing tracks are routed at track 1134 between rows 1143 and 1151, making contact for input B in rows 1143 and 1151. Signal routing tracks are routed at track 1134 between rows 1157 and 1167, making contact for node N1 in rows 1157, 1163, and 1167. Signal routing tracks are routed at track 1140 between rows 1145 and 1155, making contact for input A of the half-adder in rows 1147 and 1155. Signal routing tracks are routed at track 1142 between rows 1153 and 1159, making contact for node N2 in rows 1153 and 1159.

[0112] In some embodiments, a representation of the final layout, such as that shown in FIG11L, is displayed on display 756 (e.g., as shown in FIG11L).

[0113] As shown in Figures 11A-11L, method 900 can be implemented in non-stacked FinFET transistors (e.g., the type shown in Figure 3). Similar or identical methods can be implemented in other types of non-stacked transistor architectures, such as non-stacked planar transistors (e.g., the type shown in Figure 1), non-stacked three-sided gate transistors (e.g., the type shown in Figure 2A), and non-stacked NS transistors (e.g., the type shown in Figure 3). Similar implementations of method 900 can be performed on non-stacked CFETs (e.g., the type shown in Figure 4) and non-stacked VFETs (e.g., the type shown in Figure 5). For example, Figures 12A-12D illustrate the execution of steps 914, 916, 918, and 920 for converting the arrangement of the cluster shown in Figure 11G into a physical layout using non-stacked CFET technology according to an embodiment of the invention.

[0114] Figures 12A and 12B show 3D views of a technology-specific wiring track plan for a single stack of CFETs according to an embodiment of the present invention.

[0115] In the track layouts shown in Figures 12A and 12B, when implemented in the configuration shown in Figure 12A, the pFET can be connected to tracks 1134 and 1136, and the nFET can be connected to tracks 1140 and 1142. As shown in Figures 12A and 12B, the CFET track layout can also connect the source / drain by horizontal routing in the layer without using contacts, wherein the source / drain is located using one of two layers of local interconnects.

[0116] FIG12C illustrates a mapping (e.g., step 914) of a device arrangement (e.g., as shown in FIG11G) according to an embodiment of the invention to the technology-specific wiring track plan shown in FIG12A and 12B. As shown, the mapping for non-stacked CFETs illustrated in FIG12C is very similar to the mapping for non-stacked FinFETs illustrated in FIG11I. However, the mapping in FIG12C does not use the metal connection at a higher horizontal position for node N4 in rows 1141 and 1145, because local interconnects can be used for such connections. FIG12 also shows that diffusion interruptions 1233 and 1235, respectively corresponding to diffusion interruptions 1133 and 1135, do not extend to the entire row to allow connections between clusters of node N2 (between clusters 1124 and 1126) and clusters of node N4 (between clusters 1124, 1126 and 1122).

[0117] Figure 12D shows the final layout of the half-adder in the track plan shown in Figures 12A and 12B according to an embodiment of the present invention, and its mapping is shown in Figure 12C. As shown in Figure 12D, the signal routing track is routed at track 1134 between rows 1143 and 1151, and makes contacts for input B in rows 1143 and 1151. The signal routing track is routed at track 1134 between rows 1157 and 1167, and makes contacts for node N1 in rows 1157, 1163, and 1167. The signal routing track is routed at track 1140 between rows 1145 and 1155, and makes contacts in rows 1147 and 1155 for input A of the half-adder. The signal routing track is routed at track 1142 between rows 1153 and 1159, and makes contacts in rows 1153 and 1159 for node N2.

[0118] Method 900 can also be implemented in transistor technologies with transistor stacking, such as stacked planar transistors, stacked FinFETs, stacked three-sided gate transistors, stacked N / S transistors, stacked CFETs, and stacked VFETs. For example, Figures 13A-13J illustrate the effectiveness of method 900 for converting the netlist (half-adder) of Figure 8C into a physical layout using stacked CFET technology according to an embodiment of the present invention. Similar or identical methods can be applied to other stacked transistor architectures.

[0119] Figures 13A and 13B illustrate steps 902 and 904, respectively. Figures 13C and 13D illustrate step 906 and illustrate the stacking nature of the technique, for example, as indicated by two layers of transistors stacked on top of each other. Figure 13E illustrates step 908. Figures 13F and 13H illustrate step 910 and illustrate the additional vertical routing path implemented by the stacked transistor technique. Step 912 is shown in Figure 13H. As will be described in more detail later, in the embodiments shown in Figures 13A-13J, steps 916 and 920 may be omitted (e.g., if there are no remaining open nodes to be routed).

[0120] FIG13A illustrates a paired complementary transistor with a common gate (step 902) according to an embodiment of the present invention. FIG13B illustrates a transistor pair corresponding to the pairing step performed during step 902 according to an embodiment of the present invention (step 904). As shown in FIG13A and 13B, for stacked CFET devices, steps 902 and 904 may be performed in a similar or identical manner to non-stacked devices (e.g., non-stacked FinFET devices (e.g., as shown and described with respect to FIG11A and 11B respectively)).

[0121] Figures 13C-13H illustrate the steps of method 900 for, for example, optimizing and / or modifying the arrangement of transistor pairs within an electrical design construct such as that implemented with stacked CFETs, for example, making the physical layout or arrangement system of the resulting electrical design components (e.g., smaller and / or easier to route and implement the actual operation of the electrical design (in this example, a half-adder). Figures 13C and 13D illustrate associating transistor pairs into clusters based on common connections according to an embodiment of the invention (step 906).

[0122] As will be described in more detail later, since stacked transistor architectures such as stacked CFETs allow for vertical stacking of transistors (e.g., stacking of CFETs), the track layout can allow for vertical sharing of gate connections between transistors (e.g., between two CFETs). Thus, in some embodiments, the transistor-to-object-to-cluster association is based on a common gate, which, in addition to a common input / output connection, can be shared across columns in a dual-track layout (e.g., via the gates of vertically connected CFETs). For example, as shown in Figures 13C and 13D, transistor pairs 1304 and 1306 share common nodes N0 and N2, transistor pairs 1304 and 1312 share common node B, transistor pairs 1306 and 1310 share node A, transistor pairs 1312 and 1310 share nodes VDD and N3, transistor pairs 1314 and 1308 share node N4, transistor pairs 1302 and 1314 share nodes VDD and VSS, and transistor pairs 1302 and 1308 share common node N1. As shown in Figures 13C and 13D, a cluster (1322) is identified.

[0123] As shown in FIG13D, transistors M10, M0, M7, M5, M12, M11, M3 and M8 are identified as flipped. FIG13E illustrates the transistor pair objects (step 908) after the cluster association step and the transistor flipping step (identified in FIG13C and 13D) based on the common input / output / gate connection according to an embodiment of the present invention.

[0124] In some embodiments, the possibility of performing vertical connections in addition to horizontal connections can significantly increase the complexity of the placement work for achieving optimal results.

[0125] Figures 13F-13H illustrate the merging of nodes (step 910) after step 908 (e.g., repeated sharing) according to an embodiment of the present invention. As shown in Figure 13F, further opportunities for optimization are first identified before the merging operation. For example, as shown in Figure 13F, open nodes are first identified. For example, transistor pairs 1314, 1312, and 1310 all have node N4 as an open node. Transistor pairs 1314 and 1308 open node N2. Transistor pairs 1306, 1302, and 1308 open node N1.

[0126] As shown in Figure 13G, based on open nodes, transistor pairs 1304 and 1312 are swapped, and transistor pairs 1306 and 1310 are swapped. In some embodiments, all possible associations and permutations of transistor pairs and transistor flips are evaluated, and such associations result in a smaller number and / or minimize the distance between nodes.

[0127] FIG13H shows a cluster 1322 after the merging step (step 910) and after the elimination of nodes that are only local to the cluster and do not require external connectivity (whether internally or to other clusters) according to an embodiment of the present invention (step 912). FIG13H also shows an electrically isolated structure, such as a virtual polycrystalline silicon film forming diffusion interruptions 1324 and 1326.

[0128] FIG13I illustrates a 3D view of a technology-specific wiring track plan for a 2-layer stacked CFET according to an embodiment of the present invention. As shown in FIG13I, the track plan includes four top signal tracks (1334, 1336, 1340, and 1342) and two bottom signal tracks (1348 and 1356). In some embodiments, signal tracks 1334 and 1336 may be used to route the top gate or source / drain of the top nFET using contacts. In some embodiments, signal tracks 1340 and 1342 may be used to route the top gate or source / drain of the pFET using contacts. In some embodiments, signal track 1348 may be used to route the bottom gate or source / drain of the bottom pFET using contacts. In some embodiments, signal track 1356 may be used to route the bottom gate or source / drain of the nFET using contacts. In some embodiments, the top gate may be connected to the bottom gate by eliminating (e.g., not forming) the insulating layer between the top gate and the bottom gate. It should be understood that the 3D view shown in Figure 13I is a non-limiting example corresponding to a specific arrangement of the devices in the orbital plan, and the placement of the devices can be changed (e.g., the pFET and nFET can be flipped), and the connections may be different (e.g., flipped).

[0129] Figure 13J illustrates a mapping (e.g., step 914) of a device arrangement (e.g., as shown in Figure 13H) to the technology-specific wiring track plan shown in Figure 13I according to an embodiment of the present invention. As shown, the wiring track plan includes two tracks, including top-level tracks (tracks 1332, 1334, 1336, 1340, 1342, and 1344) and bottom-level tracks (tracks 1346, 1348, 1356, and 1358). Tracks 1332 and 1344 correspond to the top-level power source rails VDD and VSS (or ground), respectively. Tracks 1346 and 1358 correspond to the bottom-level power source rails VDD and VSS (or ground), respectively. Tracks 1338 and 1352 illustrate the separation between nMOS and pFET and are not used for routing signals. Tracks 1350 and 1354 are not used. Tracks 1334, 1336, 1340, and 1342 are available signal routing tracks that can be used to route signals from the CFET in the top layer. Tracks 1348 and 1356 are available signal routing tracks that can be used to route signals from the CFET in the bottom layer.

[0130] Each row shown in Figure 13I represents a possible location of a node or electrically isolated structure, such as a diffusion interruption. Rows 1341, 1343, 1345, 1347, 1349, 1351, 1353, 1355, 1357, and 1359 correspond to transistor nodes and are also shown in Figure 13G.

[0131] Figure 13I also illustrates the identification of open nodes in a technology-specific cabling track plan (step 916), and the use of track node connections and vertical interlayer gate connections (e.g., by eliminating the isolation layer between the top and bottom gates).

[0132] From the mapped track plan, for example, as shown in FIG13J, the final layout can be generated by arranging predefined technical configurations based on the rows of the track plan of FIG13J (step 918), and then routing open nodes (if any) using, for example, conventional routing tools. FIG13K shows a portion of a set of predefined technical configurations having source / drain and gate connections for two-layer stacked CFET technology according to an embodiment of the invention. The configurations in the set shown in FIG13K can be used, for example, to map the track plan shown in FIG13J to the final layout in a manner similar to that shown with respect to FIG11I-11L.

[0133] Figure 14 illustrates a flowchart of an embodiment of a method 1400 for generating a transistor cluster according to an embodiment of the present invention. In some embodiments, steps 906, 908, 910, and 912 may be performed as method 1400. Thus, in some embodiments, reaching the physical layout from the netlist may involve, for example, performing methods / steps 902, 904, 1400, 914, 916, 918, and 920. Method 1400 may be implemented by a computing device 750.

[0134] In some embodiments, performing method 1400 results in generating the shortest possible strings of nFETs and pFETs for a given netlist by connecting matched source / drain terminals. In some embodiments, these shortest possible strings of nFETs and pFETs are then paired to maximize the number of connections between common gates.

[0135] Figures 15A-15I illustrate various possible outputs of the execution method 1400 according to an embodiment of the present invention. Figure 14 can be understood by referring to Figures 15A-15I.

[0136] During step 1402, entries in the netlist (e.g., entries in the netlist of FIG8C (half-adders)) are classified as nFETs and pFETs. For example, FIG15A shows sorted pFET netlist 1502 and sorted nFET netlist 1504 of the netlist of FIG8C according to an embodiment of the present invention.

[0137] During step 1404, the number of source / drain (SD) terminals associated with each connection (node) is counted. Counting is performed on the nFET netlist and the pFET netlist. For example, Figure 15B shows lists 1512 and 1514 with counts associated with each connection of the pFET netlist and the nFET netlist, respectively.

[0138] During step 1406, the total number of connections and the total number of connections with an odd count are determined for each sorted list generated during step 1402 (e.g., based on the output of step 1404). For example, Figure 15C shows the total number of connections and the total number of connections with an odd count for sorted pFET netlist 1502 and sorted nFET netlist 1504.

[0139] As shown in Figure 15C, the pFET netlist 1502 includes two odd-numbered source / drain counts, corresponding to Sum (count is 1) and Carry (count is 1), and the nFET netlist 1504 includes six odd-numbered source / drain counts, corresponding to N1 (count is 1), N2 (count is 3), N4 (count is 1), Sum (count is 1), and Carry (count is 1). As shown in Figure 15C, in some embodiments, the number of odd-numbered counts associated with the supply rails (e.g., VDD / VSS) is ignored and / or undetermined.

[0140] In some embodiments, steps 1402 and 1404 may be omitted, and the count generated during step 1406 may be obtained, for example, by directly processing the netlist (e.g., directly processing the netlist of FIG8C), for example by iterating through each entry of the netlist and maintaining an independent counter for each connection.

[0141] During step 1408, the minimum number of segments (also called transistor strings), the minimum number of breaks between segments, and the minimum width of the cell are determined. For example, in some embodiments, the minimum number of segments, Segmin, is determined by the following formula (1): where OddCountpFET and OddCountnFET correspond to the total number of connections of pFET and nFET, respectively, having an odd number of connections as determined during step 1406. For example, in the embodiment shown in FIG. 15C, ... Therefore, when method 1400 is applied to the netlist of FIG. 8C, three transistor clusters can be generated. In some embodiments, the minimum number of segments, Segmin, is considered to be the target number of segments.

[0142] In some embodiments, the minimum number of internal breakpoints between segments (e.g., diffused breakpoints or other breaks in the active channel, for example) is determined by the following equation (2). For example, in the embodiment shown in FIG15C, equation 2 can be used, for example, with a single diffused breakpoint (e.g., each diffused breakpoint has only one virtual polysilicon). For a dual diffused breakpoint technique, the minimum number of internal breakpoints can be determined by multiplying the result of equation 2 by 2.

[0143] In some embodiments, the minimum width of the cell, CellWidthmin, is determined by the following formula (3) where numpFET and numnFET are the total number of transistors in the pFET and nFET netlists, Breakedge is the number of interruptions associated with the edge of the cell side (e.g., typically equal to 1), d is equal to the number of virtual polysilicon per diffused interruption for this technique (e.g., d = 1 for single diffused interruption technique, d = 2 for double diffused interruption technique), and Breakspmin and Breaksnmin are the minimum number of internal interruptions in the pFET and nFET, respectively, wherein Breakspmin and Breaksnmin can be determined by the following formula (4) (5) For example, in the embodiment shown in FIG15C, and for single diffused interruption technique, . Therefore, the cell of Figure 8C can be represented in a single diffusion interruption technique with 10 polysilicon orbitals (e.g., one polysilicon per transistor, one polysilicon per internal diffusion interruption, half a polysilicon on the left edge of the cell, and half a polysilicon on the right edge of the cell).

[0144] In some embodiments, the minimum number of segments determined during step 1408 corresponds to the theoretical minimum number of segments required to implement the netlist (e.g., the netlist of FIG. 8C) in the layout. In some embodiments, the minimum number of breaks determined during step 1408 corresponds to the theoretical minimum number of breaks required to implement the netlist (e.g., the netlist of FIG. 8C) in the layout. In some embodiments, the minimum cell width determined during step 1408 corresponds to the theoretical minimum cell width required to implement the netlist (e.g., the netlist of FIG. 8C) in the layout.

[0145] During step 1410, source / drain terminals associated with a source / drain count of 2 (e.g., as determined during step 1406) are combined. Therefore, in some embodiments, the output generated during step 1410 includes a transistor arrangement comprising transistor pairs, transistor pair strings, and / or individual transistors. For example, FIG15D shows transistors arranged in a transistor string in the netlist of FIG8C according to an embodiment of the invention, wherein source / drain terminals associated with a source / drain count of 2 (e.g., as shown in FIG15B) are combined.

[0146] As shown in FIG15D, the source / drain terminals (SD terminals N0, N1, and N4 of the pFETS and SD terminal N3 of the nFETS) counted as 2 in FIG15B are merged. As will be explained later with respect to FIG15E, in some embodiments, some of the transistors merged during step 1410 may be de-merged to support another connection (e.g., based on a common gate).

[0147] During step 1412, possible endpoints of the segment are identified. For example, in some embodiments, all source / drain terminals having connections associated with a count of 1 are identified as endpoints of the segment. For example, in the embodiment shown in FIG15B, for pFETs, source / drain terminals connected to Sum and Carry are identified as possible endpoints, while for nFETs, source / drain terminals connected to nodes N1, N4, Sum, and Carry are identified as possible endpoints.

[0148] During step 1414, the transistor groups generated during step 1412 are further chained together to reach the target number of segments. For example, in some embodiments, the transistor groups generated during step 1412 are chained together in the target number of segments using an exhaustive search. The best solution (e.g., minimum cell size, cell with fewer metal layers for internal interconnection, lowest parasitic properties of one or more particular nodes, etc.) is selected from the possible solutions obtained using the exhaustive search method. In some embodiments, an exhaustive search for all possible ways in which the transistor groups generated during step 1412 can be chained together is less complex than evaluating all possible arrangements of the transistors in the original netlist that can be chained together. For example, as can be seen from Figures 15A and 15D, evaluating all possible arrangements of the transistor groups in Figure 15D (which have 4 pFET groups and 6 nFET groups) to reach the target 3-segment system is less complex than evaluating all possible arrangements of the transistors in Figure 15A (which have 7 pFETs and 7 nFETs).

[0149] In some embodiments, after performing step 1414, steps 914, 916, 918 and 920 may be performed, for example, as described with respect to method 900.

[0150] In some embodiments, the step of determining how to chain the transistor groups generated during step 1412 together to achieve a target number of segments includes: connecting pFETs and nFETs sharing a common gate; swivel source / drain terminals associated with an odd number of segments and the start and / or end of a segment; swivel source / drain terminals connected to the same open node close to each other; and connecting pFETs and nFETs together to form an inverter. For example, in some embodiments, performing step 1414 includes performing step 1416.

[0151] During step 1416, the transistor groups generated during step 1412 are further grouped based on a shared common gate and arranged such that the grouped transistors form compatible transistor strings. In some embodiments, the start and / or end source / drain terminals of a segment are selected from a group of source / drain terminals associated with an odd number of counts (from step 1406). In some embodiments, further refinement is performed (e.g., by flipping transistors or transistor arrangements) to achieve a target number of segments and / or further optimize the transistor placement.

[0152] In some embodiments, multiple transistor arrangements are possible when step 1416 is performed. In some embodiments, the optimal solution (e.g., minimum cell size, cell with a smaller number of metal layers for internal interconnection, minimum parasitic characteristics of one or more particular nodes, etc.) is selected from the possible transistor arrangements obtained when step 1416 is performed using an exhaustive search method. In some embodiments, an exhaustive search of all possible transistor arrangements obtained after performing step 1416 is less complex than evaluating all possible ways in which the transistor groups generated during step 1412 can be connected together.

[0153] Figures 15E-15H illustrate the execution of step 1416 on the transistor arrangement generated during step 1410 (as shown in Figure 15D) according to an embodiment of the invention to form three target segments (as determined during step 1408). As shown in Figure 15E, transistor arrangements 1546, 1548, 1560, and 1562 may be grouped together based on their common gate, for example, as cluster 1122. In some embodiments, the step of achieving this grouping may be based on the determination that transistor arrangements 1546, 1548, 1560, and 1562 form (e.g., output) inverters. In some embodiments, the step of achieving this grouping may be based on the determination that M0 and M7 share a common gate (N7), transistors M6 and M13 share a common gate (N4), and nodes Carry and Sum are both associated with odd counts and therefore can be positioned at the endpoints of the segments.

[0154] After grouping transistor arrangements 1546, 1548, 1560, and 1562, transistor arrangement 1554 is selected to form a second segment (cluster 1126), as shown in FIG15F. As shown in FIG15F, transistor M8 is grouped with transistor M3 to form cluster 1126. In some embodiments, the step of achieving this grouping may be based on the determination that M8 and M3 share a common gate (N4), and that nodes N1 and N2 are both associated with an odd number of counts and therefore can be placed at the end of the segment. In some embodiments, the grouping may be based on the determination that among the remaining nFET transistor groups (1552, 1554, 1556, and 1558), M8 (1554) is the only transistor not associated with input nodes A and B. Therefore, by forming a cluster with transistor M8, inputs A and B are not separated between multiple segments.

[0155] As shown in Figure 15E, the formation of cluster 1126 causes transistor arrangement 1542 to lose transistor M3 and become transistor arrangement 1543 (by canceling the merging of transistors M3 and M2) to facilitate the common gate shared by transistors M8 and M3. Therefore, Figure 15E shows that during step 1416, multiple possible arrangements can be evaluated before the target number of segments is reached.

[0156] Figure 15G illustrates the formation of a compatible transistor string to achieve three target segments according to an embodiment of the present invention. As shown in Figure 15G, supply rails VDD and VSS are considered in this step for merging purposes. Also as shown in Figure 15G, when determining the transistor order of the transistor string, a common gate is considered as follows: transistors M2 and M10 share a common gate (A), transistors M1 and M9 share a common gate (B), transistors M4 and M11 share a common gate (A), and transistors M5 and M12 share a common gate (B).

[0157] Once a compatible transistor string is formed, a third cluster can be formed by connecting a common gate, as shown in FIG15H. As shown in FIG15H, clusters 1524, 1122, and 1126 can be generated by performing step 1416 on the transistor arrangement shown in FIG15D. When step 1416 is performed on the transistor arrangement shown in FIG15D (e.g., clusters 1122, 1124, and 1126 as shown in FIG11G), other 3-cluster configurations can also be generated during step 1416.

[0158] During step 1418, the number of segments obtained during step 1414 is compared with a minimum number of segments (e.g., determined during step 1408). If the number of segments obtained during step 1414 is higher than the minimum number of segments, step 1414 is executed again (e.g., by trying different possible transistor arrangements). If the number of segments obtained in step 1414 is equal to the minimum number of segments, the segments generated during step 1414 are arranged in a single column during step 1420. For example, FIG15I illustrates segments 1524, 1122, and 1124 (as shown in FIG15G) arranged in a single column according to an embodiment of the present invention.

[0159] During step 1422, the cell width is determined based on the segments arranged in a single column (e.g., from step 1420). If the cell width is greater than the minimum cell width (e.g., from step 1408), step 1414 is performed again (e.g., by trying different possible transistor arrangements). If the cell width is equal to the minimum cell width, the segments generated during step 1420 are further processed (e.g., during steps 914, 916, 918, and 920) to obtain a physical layout.

[0160] As shown in Figure 15I, the cell shown in Figure 15I has 10 polycrystalline silicon orbitals. For example, the cell shown in Figure 15I has 7 polycrystalline silicon orbitals associated with the transistor (as shown in rows 1573, 1575, 1577, 1579, 1583, 1585, and 1591), 2 polycrystalline silicon orbitals associated with the internal diffusion interruption (as shown in rows 1581 and 1589), and 1 polycrystalline silicon orbital associated with the edge of the cell (as shown in rows 1571 and 1593, which are shared with adjacent cells and are therefore each counted as half a polycrystalline silicon orbital). Since the cell shown in FIG15I has 10 polycrystalline silicon orbitals, which is equal to the minimum width of the cell determined for the netlist of FIG8C during step 1408, the cell shown in FIG15I is further processed, and step 914 is then performed, for example.

[0161] As shown in FIG14, if the number of segments in a cell is greater than the minimum number of segments, or if the width of a cell is greater than the minimum width of a cell, step 1414 can be performed iteratively. In some embodiments, step 1414 is also performed iteratively when the number of interruptions is greater than the minimum number of interruptions. In the embodiment shown in FIG15I, since two interruptions are shown, which is equal to the minimum number of interruptions determined for the netlist of FIG8C during step 1408, the cell shown in FIG15I is further processed, and step 914 is performed next, for example.

[0162] In some embodiments, after performing step 1414, the number of segments having a higher number of segments than the minimum number of segments, the width of a cell having a higher width than the minimum width of a cell, or the number of interruptions having a higher number of interruptions indicates that a smaller cell design is possible (and therefore, step 1414 can be performed again).

[0163] In some embodiments, performing method 1400 advantageously allows determining whether a particular cell design can be further improved (e.g., by comparing the characteristics of the particular cell design with the target characteristics determined during step 1408).

[0164] In some embodiments, performing method 1400 advantageously allows for optimization of cell design (e.g., reducing or minimizing cell size) without having to use an exhaustive search to evaluate all possible transistor arrangements of the netlist. These advantages may become more pronounced as cell size increases.

[0165] Although method 1400 has been described for a single-layer design, method 1400 can be applied to designs implemented in multiple layers, such as a two-layer design. For example, FIG16 shows a flowchart of an embodiment of method 1600 for generating a transistor cluster according to an embodiment of the present invention. Method 1600 includes steps 1402, 1404, 1406, 1408, 1410, 1412, 1414 (and, for example, 1416), 1418, 1420, and 1422, which can be performed in a similar manner to method 1400.

[0166] If it is determined after executing steps 1418 and 1422 that iterations of step 1414 will no longer be performed (e.g., the output of step 1418 = "No" and the output of step 1422 = "No"), then the number of layers in the design is determined during step 1624. As shown in Figure 16, for a single-layer design, method 1600 can be the same as method 1400. For a two-layer design, the segments generated during step 1414 are arranged into two columns during step 1526, and then step 914 can be performed.

[0167] In some embodiments, an exhaustive search method may be used during step 1526 to determine the placement of the segments. In some embodiments, the placement of the segments during step 1526 includes the steps of: placing a diffusion interruption in the top layer; and placing a power connector in the top layer includes stacking the power connector on top of the power connectors in the bottom layer, or stacking the power connector on top of nodes that do not require additional signal connections. For example, FIG17 shows segments 1524, 1122, and 1726 arranged in two columns according to an embodiment of the present invention (as shown in FIG15G).

[0168] As shown in Figure 17, the diffusion interruption section is located in the top layer (above transistor M4). Also as shown in Figure 17, the top layer power connector (VDD / VSS) is located on top of the bottom layer power connector (as shown in cluster 1726, which is a flip version of cluster 1126) or on a node that does not require additional signal connections (as shown in cluster 1122).

[0169] Some embodiments have the advantage of providing a metric that indicates a particular cell design can be further optimized, and providing a step to reduce the number of possible transistor arrangements that can be evaluated to the point that such a metric no longer indicates that the cell design of a particular cell can be further optimized.

[0170] Exemplary embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entire contents of the specification and the scope of the claims set forth herein.

[0171] Example 1. A method comprising: receiving data representing a circuit, including arrangements of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more devices, wherein N is equal to the minimum number of segments; and generating individual portions of the grouped devices to form a physical layout representing a physical manifestation of the circuit, such that when the individual portions are integrated together, the individual portions form a physical manifestation of the circuit.

[0172] Example 2. The method of Example 1, wherein the circuit includes a plurality of nodes and wherein terminals of the devices are coupled to the plurality of nodes, the method further includes: identifying different nodes of the plurality of nodes based on the received data; and assigning a terminal count to each of the identified nodes based on the received data to form a plurality of terminal counts, wherein each terminal count indicates the number of terminals of the devices coupled to the corresponding node of the identified nodes, wherein the step of determining the minimum number of segments includes: determining the minimum number of segments based on the number of terminal counts of the plurality of terminal counts having an odd number of counts.

[0173] Example 3. As in Example 1 or 2, wherein the devices comprise a plurality of n-type field-effect transistors (nFETs) and a plurality of p-type field-effect transistors (pFETs), the method further comprises: identifying the pFETs and nFETs of the circuit from the received data, wherein the step of forming the plurality of terminal counts comprises forming a plurality of pFET terminal counts and a plurality of nFET terminal counts, and wherein the step of determining the minimum number of segments comprises determining the minimum number of segments by the following formula: , wherein Segmin represents the minimum number of segments, OddCountpFET represents the number of pFET terminal counts with an odd count, and OddCountnFET represents the number of nFET terminal counts with an odd count.

[0174] Example 4. The method of one of Examples 1 to 3 further includes merging the terminals of the devices associated with a terminal count of 2.

[0175] Example 5. The method of one of Examples 1 to 4 further includes identifying terminals of the devices associated with an odd number of terminals, wherein the step of dividing the devices into N segments includes: selecting a first terminal from the identified terminals; and forming a first segment of the N segments, the first segment having the first terminal as an end terminal.

[0176] Example 6. The method of one of Examples 1 to 5 further includes: determining the minimum number of active channel breaks based on the minimum number of segments, wherein the step of dividing the devices into N segments further includes dividing the devices into N segments having M interruption units, where M is equal to the minimum number of segments.

[0177] Example 7. The method of any one of Examples 1 to 6 further includes: determining the minimum number of polysilicon orbitals based on the received data, wherein the step of dividing the devices into N segments further includes dividing the devices into N segments having L polysilicon orbitals, wherein L is equal to the minimum number of polysilicon orbitals.

[0178] Example 8. A method as described in any of Examples 1 to 7, wherein the apparatus comprises a plurality of n-type field-effect transistors (nFETs) and a plurality of p-type field-effect transistors (pFETs), wherein the step of determining the minimum number of polysilicon tracks comprises determining the minimum number of polysilicon tracks by the following formula: where CellWidthmin represents the minimum number of polysilicon tracks, numpFET represents the total number of pFETs in the circuit, numnFET represents the total number of nFETs in the circuit, Breakspmin represents the minimum number of internal interrupts associated with the pFETs of the circuit, and Breaksnmin represents the minimum number of internal interrupts associated with the nFETs of the circuit.

[0179] Example 9. The method of one of Examples 1 to 8 further includes: manufacturing a mask group based on the formed physical layout, and using the mask group to generate an integrated circuit.

[0180] Example 10. The method of one of Examples 1 to 9, wherein the individual portions represent one or more of the following: a diffusion mid-section, a source-drain structure, or a gate structure.

[0181] Example 11. The method of one of Examples 1 to 10, wherein the source-drain configuration includes a gate connection for the gate configuration or a power connection to a power source.

[0182] Example 12. The method of one of Examples 1 to 11, wherein the gate configuration includes a source-drain connection for the source-drain configuration or a power connection to a power source.

[0183] Example 13. The method of one of Examples 1 to 12, wherein the diffusion mid-section comprises a polycrystalline silicon film.

[0184] Example 14. The method of one of Examples 1 to 13, wherein the source-drain structure comprises an n-type region or a p-type region.

[0185] Example 15. The method of one of Examples 1 to 14, wherein the physical embodiment includes a field-effect transistor (CFET).

[0186] Example 16. The method of one of Examples 1 to 15 further includes: mapping the N segments to a target physical layout image based on a target orbital plan.

[0187] Example 17. The method of one of Examples 1 to 16, wherein the target track plan includes a single row height.

[0188] Example 18. The method of one of Examples 1 to 16, wherein the target track plan contains two or more column heights.

[0189] Example 19. The method of any one of Examples 1 to 16 or 18 further includes: placing the N segments in two columns, the two columns including a top column and a bottom column, wherein the step of placing the N segments in the two columns includes: placing only one segment of the N segments in the bottom column; placing all the diffused middle sections to separate the plurality of segments in the top column; and placing a power source terminal of a device of one segment of the top column on top of a power source terminal of only one segment of the device in the bottom column.

[0190] Example 20. A computing device for generating a standard cell layout of a standard cell library, the computing device comprising: a processor; and a non-transient computer-readable storage medium coupled to the processor and storing a program executable by the processor, the program comprising instructions for: receiving data representing a circuit, including arrangements of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared among two or more of the devices, wherein N is equal to the minimum number of segments; and generating individual portions of the grouped devices to form a physical layout representing a physical manifestation of the circuit, such that when the individual portions are integrated together, the separate portions form a physical manifestation of the circuit.

[0191] Example 21. A computing device as in Example 20, wherein the program further includes instructions for: storing the physical layout in the non-transient computer-readable storage medium; and transmitting the stored physical layout for generating a set of masks for integrated circuit production.

[0192] Example 22. A computing device, such as that of Example 20 or 21, further includes a display, wherein the program further includes instructions to display the device using icons on the display.

[0193] Example 23. A method comprising: receiving data representing a circuit, including arrangements of devices, inputs, outputs, and power sources, wherein the circuit includes a plurality of nodes, and wherein the devices include a plurality of n-type field-effect transistors (nFETs) and a plurality of p-type field-effect transistors (pFETs); identifying the pFETs and nFETs of the circuit from the received data; identifying different nodes of the plurality of nodes based on the received data; and assigning a terminal count to each of the identified nodes based on the received data to form a plurality of terminal counts, wherein each terminal... The sub-count indicates the number of terminals of the devices coupled to the corresponding nodes of the identified nodes; the minimum number of segments is determined based on the number of terminal counts of the complex terminal count with an odd count; and the devices are divided into N segments based on common features shared between two or more devices, where N is equal to the minimum number of segments; and individual parts of the grouped devices are generated to form a physical layout representing the physical manifestation of the circuit, such that when the individual parts are integrated together, the individual parts form the physical manifestation of the circuit.

[0194] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be construed as limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this specification. Therefore, the appended claims are intended to include any such modifications or embodiments. [Simplified Explanation of the Diagram]

[0011] To better understand the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0012] Figure 1 shows an exemplary planar transistor;

[0013] Figure 2A shows an exemplary 3D tri-gate transistor;

[0014] Figure 2B shows an exemplary FinFET;

[0015] Figure 3 shows an exemplary N-S transistor;

[0016] Figure 4 shows an exemplary CFET;

[0017] Figure 5 shows an exemplary VFET;

[0018] Figure 6 shows a flowchart illustrating the semiconductor technology design process;

[0019] Figure 7A shows a flowchart of a semiconductor technology design process according to an embodiment of the present invention;

[0020] FIG7B shows a computing device according to an embodiment of the present invention;

[0021] Figures 8A-8D show four different representations of a half-adder cell according to an embodiment of the present invention;

[0022] Figure 9 shows a flowchart of an embodiment of the method for automatically generating the physical layout of standard cells based on a netlist according to an embodiment of the present invention;

[0023] Figure 10 shows a flowchart of an embodiment of the method for designing and manufacturing integrated circuits using the standard cell library of Figure 7 according to an embodiment of the present invention;

[0024] Figures 11A-11L illustrate the effectiveness of the method of Figure 9 in converting the netlist of Figure 8C into a physical layout using non-stacked FinFET technology according to an embodiment of the present invention;

[0025] Figures 12A-12D illustrate the effectiveness of the steps of the method of Figure 9, which uses non-stacked CFET technology to convert the arrangement of clusters shown in Figure 11G into a physical layout according to an embodiment of the present invention;

[0026] Figures 13A-13K illustrate the effectiveness of the method of Figure 9, which uses CFET technology to convert the netlist (half-adder) of Figure 8C into a physical layout according to an embodiment of the present invention;

[0027] Figure 14 shows a flowchart of an embodiment of a method for generating a transistor cluster according to an embodiment of the present invention;

[0028] Figures 15A-15I show various possible outputs of the method of embodiment 14 according to an embodiment of the present invention;

[0029] Figure 16 shows a flowchart of an embodiment of a method for generating a transistor cluster according to an embodiment of the present invention; and

[0030] Figure 17 illustrates the segment of Figure 15G arranged in two rows according to an embodiment of the present invention.

[0031] Unless otherwise stated, the corresponding numbers and symbols in the different figures generally refer to the corresponding parts. These figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.

Claims

1. A method for generating a standard cell layout, comprising: receiving data representing a circuit, including an arrangement of devices, inputs, outputs, and power sources, the devices including transistors comprising one or more of a plurality of n-type field-effect transistors (nFETs) and a plurality of p-type field-effect transistors (pFETs); determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more of the devices, wherein N is equal to the minimum number of segments; and generating individual portions of the grouped devices to form a three-dimensional (3D) physical layout representing a physical representation of the circuit, such that when the individual portions are integrated together, the individual portions form a physical representation of the circuit, wherein the physical representation includes a three-dimensional stack of the transistors of the devices.

2. The method of claim 1, wherein the circuit includes a plurality of nodes, and wherein terminals of the devices are coupled to the plurality of nodes, the method further comprising: identifying different nodes of the plurality of nodes based on the received data; and assigning a terminal count to each of the identified nodes based on the received data to form a plurality of terminal counts, wherein each terminal count indicates the number of terminals of the devices coupled to a corresponding node of the identified nodes, wherein the step of determining the minimum number of segments comprises: determining the minimum number of segments based on the number of terminal counts of the plurality of terminal counts having an odd number of counts.

3. The method of claim 2 further includes: identifying the pFET and nFET of the circuit from the received data, wherein the step of forming the complex terminal count includes forming a complex pFET terminal count and a complex nFET terminal count, and wherein the step of determining the minimum number of segments includes determining the minimum number of segments by the following formula: where Segmin represents the minimum number of segments, OddCountpFET represents the number of pFET terminal counts with an odd count, and OddCountnFET represents the number of nFET terminal counts with an odd count.

4. The method of claim 2 further includes merging the terminals of the devices associated with a terminal count of 2.

5. The method of claim 1, further comprising identifying terminals of the devices associated with an odd number of terminals, wherein the step of dividing the devices into N segments comprises: selecting a first terminal from the identified terminals; and forming a first segment of the N segments, the first segment having the first terminal as an end terminal.

6. The method of claim 1 further includes: determining the minimum number of active channel disconnections based on the minimum number of segments, wherein the step of dividing the devices into N segments further includes dividing the devices into N segments having M interruption units, wherein M is equal to the minimum number of segments.

7. The method of claim 1, further comprising: determining the minimum number of polycrystalline silicon orbitals based on the received data, wherein the step of dividing the devices into N segments further comprises dividing the devices into N segments having L polycrystalline silicon orbitals, wherein L is equal to the minimum number of polycrystalline silicon orbitals.

8. The method of claim 7, wherein the step of determining the minimum number of polysilicon tracks comprises determining the minimum number of polysilicon tracks by means of the following formula: where CellWidthmin represents the minimum number of polysilicon tracks, numpFET represents the total number of pFETs in the circuit, numnFET represents the total number of nFETs in the circuit, Breakspmin represents the minimum number of internal interrupts associated with the pFETs of the circuit, and Breaksnmin represents the minimum number of internal interrupts associated with the nFETs of the circuit.

9. The method of claim 1 further includes: manufacturing a mask assembly based on the formed physical layout, and using the mask assembly to fabricate an integrated circuit.

10. The method of claim 1, wherein the individual portions represent one or more of the following: a diffusion mid-section, a source-drain configuration, or a gate configuration.

11. The method of claim 10, wherein the source-drain configuration includes a gate connection for the gate configuration or a power connection to a power source.

12. The method of claim 10, wherein the gate configuration includes a source-drain connection for the source-drain configuration or a power connection to a power source.

13. The method of claim 10, wherein the diffusion mid-section comprises a polycrystalline silicon film.

14. The method of claim 10, wherein the source-drain configuration comprises an n-type region or a p-type region.

15. The method of claim 1, wherein the physical embodiment includes a complementary field-effect transistor (CFET).

16. The method of claim 1 further includes: mapping the N segments to a target physical layout image based on a target orbital plan.

17. The method of request item 16, wherein the target track plan includes two or more column heights.

18. The method of claim 17 further comprises: placing the N segments in two columns, the two columns comprising a top column and a bottom column, wherein the step of placing the N segments in the two columns comprises: placing only one segment of the N segments in the bottom column; placing all the diffused middle sections to separate the plurality of segments in the top column; and placing a power source terminal of a device of one segment of the top column on top of a power source terminal of only one segment of the device in the bottom column.

19. A computing device for generating a standard cell layout of a standard cell library, the computing device comprising: a processor; and a non-transient computer-readable storage medium coupled to the processor and storing a program executable by the processor, the program comprising instructions for: receiving data representing a circuit, including arrangements of devices, inputs, outputs, and power sources, the devices including transistors comprising one or more of a plurality of n-type field-effect transistors (nFETs) and a plurality of p-type field-effect transistors (pFETs); determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared among two or more of the devices, wherein N is equal to the minimum number of segments; and generating individual portions of the grouped devices to form a three-dimensional (3D) physical layout representing a physical manifestation of the circuit, such that when the individual portions are integrated together, the individual portions form a physical manifestation of the circuit, wherein the physical manifestation includes a three-dimensional stack of the transistors of the devices.

Images