Plasma treatment equipment and RF system

Abstract

The plasma processing apparatus of the present invention comprises: a chamber; a substrate support disposed within the chamber and including a lower electrode; an upper electrode disposed above the substrate support; a first RF power supply electrically connected to the upper electrode to generate a first RF signal, wherein the first RF signal has a first power level during a first state in a repetition period and a zero power level during a second, third, and fourth state in the repetition period; a second RF power supply electrically connected to the lower electrode to generate a second RF signal, wherein the second RF signal has a zero power level during the first and second states, a second power level during the third state, and a third power level during the fourth state; and a DC power supply electrically connected to the upper electrode to generate a DC signal.

Description

[Technical Field]

[0001] This invention relates to a plasma processing device and an RF system. [Previous Technology]

[0002] With the advancement of semiconductor miniaturization, the requirement for high aspect ratio etching processes has emerged. To address this, a method called ALE (Atomic Layer Etching) has been disclosed, which promotes etching by repeatedly performing etchant deposition and ion irradiation steps. In ALE, each step is separated by switching the processing gas used in the deposition and ion irradiation steps. Furthermore, a method has been disclosed to control the high-frequency power pulses supplied to the plasma generation and bias voltage to have a specific phase difference in order to prevent the generation of standing waves from multiple high-frequency power sources within the processing container of the plasma processing apparatus (Patent Document 1). [Prior Art Documents] [Patent Documents]

[0003] Patent Document 1: Japanese Patent Application Publication No. 2016-157735 [Summary of the Invention]

[0004] [The problem the invention aims to solve]

[0005] This invention provides a plasma processing apparatus and RF system capable of performing etching that simultaneously improves selectivity, escape capability, and shape control while reducing processing time. [Technical Means for Solving the Problem]

[0006] One aspect of the plasma processing apparatus of the present invention includes: a chamber; a substrate support disposed within the chamber and including a lower electrode; an upper electrode disposed above the substrate support; a first RF power supply electrically connected to the upper electrode to generate a first RF signal, wherein the first RF signal has a first power level during a first state in a repetition period and a zero power level during a second, third, and fourth state in the repetition period; a second RF power supply electrically connected to the lower electrode to generate a second RF signal, wherein the second RF signal has a zero power level during the first and second states, a second power level during the third state, and a third power level during the fourth state; and a DC power supply electrically connected to the upper electrode to generate a DC signal. [Effects of the Invention]

[0007] According to the present invention, etching can be performed that can simultaneously improve selectivity, escape capability and shape control and shorten processing time.

Implementation Method

[0009] Hereinafter, embodiments of the disclosed plasma processing apparatus and RF system will be described in detail based on the drawings. Furthermore, the disclosed technology is not limited to the following embodiments.

[0010] In high aspect ratio etching processes, for example, when high-frequency power is supplied in a CW (Continuous Wave) manner, the bottom shape (bottom shape) of the trench formed on the etched film is rectangular, and the processing time is shorter, but etching defects (reduced escape rate) occur, resulting in a decrease in selectivity. Here, selectivity is the etching rate of the etched film / the etching rate of the mask. On the other hand, when using ALE, both escape rate and selectivity are improved, but the bottom shape becomes a slanted shape, which prolongs the processing time. That is, there is a trade-off between the improvement of escape rate and selectivity and the improvement of shape control and the reduction of processing time. Therefore, it is possible to perform etching that eliminates this trade-off, thereby achieving a balance between improved selectivity, escape rate, and shape control and reduced processing time.

[0011] [Configuration of the Plasma Processing System] Hereinafter, an example of the configuration of the plasma processing system will be described. FIG1 is a diagram showing an example of a plasma processing system according to one embodiment of the present invention. As shown in FIG1, the plasma processing system includes a capacitively coupled plasma processing device 1 and a control unit 2. Furthermore, the plasma processing system is an example of a substrate processing device. The capacitively coupled plasma processing device 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. Also, the plasma processing device 1 includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a cluster nozzle 13. The substrate support unit 11 is disposed within the plasma processing chamber 10. The cluster nozzle 13 is disposed above the substrate support unit 11. In one embodiment, the cluster nozzle 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by a cluster nozzle 13, a sidewall 10a of the plasma processing chamber 10, and a substrate support portion 11. The plasma processing chamber 10 has at least one gas supply port for supplying at least one type of processing gas to the plasma processing space 10s, and at least one gas outlet for discharging gas from the plasma processing space. The sidewall 10a is grounded. The cluster nozzle 13 and the substrate support portion 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0012] The substrate support portion 11 includes a body portion 111 and a ring assembly 112. The body portion 111 has a central region (substrate support surface) 111a for supporting a substrate (wafer) W and an annular region (ring support surface) 111b for supporting the ring assembly 112. The annular region 111b of the body portion 111 surrounds the central region 111a of the body portion 111 when viewed from above. The substrate W is disposed on the central region 111a of the body portion 111, and the ring assembly 112 is disposed on the annular region 111b of the body portion 111 in such a way that it surrounds the substrate W on the central region 111a of the body portion 111. In one embodiment, the body portion 111 includes a base and an electrostatic chuck. The base includes a conductive member. The conductive member of the base functions as a lower electrode. The electrostatic chuck is disposed on the base. The upper surface of the electrostatic chuck has the substrate support surface 111a. The ring assembly 112 includes one or more annular members. At least one of the annular members is an edge ring. Furthermore, although not shown in the figures, the substrate support 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck, the ring assembly 112, and the substrate W to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path, or a combination thereof. A heat transfer fluid such as brine or gas flows through the flow path. Additionally, the substrate support 11 may also include a heat transfer gas supply section configured to supply heat transfer gas between the back surface of the substrate W and the substrate support surface 111a.

[0013] The cluster injector 13 is configured to introduce at least one type of processing gas from the gas supply unit 20 into the plasma processing space 10s. The cluster injector 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlets 13c. The processing gas supplied to the gas supply port 13a is introduced into the plasma processing space 10s through the gas diffusion chamber 13b and the plurality of gas inlets 13c. Furthermore, the cluster injector 13 includes a conductive member. The conductive member of the cluster injector 13 functions as an upper electrode. In addition to the cluster injector 13, the gas inlet may also include one or more side gas injectors (SGIs) installed in one or more openings formed in the sidewall 10a.

[0014] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one type of process gas from the corresponding gas source 21 to the cluster nozzle 13 via the corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may also include one or more flow modulation devices for modulating or pulsedizing the flow rate of the at least one type of process gas.

[0015] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power), such as a source RF signal and a bias RF signal, to the conductive members of the substrate support portion 11 and / or the conductive members of the cluster head 13. Thereby, plasma is formed from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least part of a plasma generation unit configured to generate plasma from one or more processing gases in the plasma processing chamber 10. Furthermore, by supplying a bias RF signal to the conductive members of the substrate support portion 11, a bias potential can be generated on the substrate W, feeding the ionic components of the formed plasma into the substrate W.

[0016] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is configured to generate a source RF signal (source RF power) for plasma generation, which is coupled to a conductive member of the substrate support 11 and / or a conductive member of the cluster head 13 via at least one impedance matching circuit. In one embodiment, the source RF signal has a frequency in the range of 13 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may also be configured to generate a plurality of source RF signals with different frequencies. The generated one or more source RF signals are supplied to the conductive member of the substrate support 11 and / or the conductive member of the cluster head 13. The second RF generating unit 31b is configured to generate a bias RF signal (bias RF power) which is coupled to a conductive member of the substrate support 11 via at least one impedance matching circuit. In one embodiment, the bias RF signal has a frequency lower than that of the source RF signal. In another embodiment, the bias RF signal has a frequency in the range of 400 kHz to 13.56 MHz. In another embodiment, the second RF generation unit 31b may also be configured to generate a plurality of bias RF signals with different frequencies. One or more bias RF signals generated are supplied to the conductive members of the substrate support unit 11. Furthermore, in various embodiments, at least one of the source RF signal and the bias RF signal may also be pulsed.

[0017] Furthermore, the power supply 30 may include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generating unit 32a and a second DC generating unit 32b. In one embodiment, the first DC generating unit 32a is configured to generate a first DC signal by connecting to a conductive member of the substrate support 11. The generated first bias DC signal is supplied to the conductive member of the substrate support 11. In one embodiment, the first DC signal may also be supplied to other electrodes, such as electrodes within the electrostatic chuck. In one embodiment, the second DC generating unit 32b is configured to generate a second DC signal by connecting to a conductive member of the cluster head 13. The generated second DC signal is supplied to the conductive member of the cluster head 13. In various embodiments, at least one of the first and second DC signals may also be pulsed. Furthermore, in addition to the RF power supply 31, a first and a second DC generating unit 32a and 32b may also be provided, or a first DC generating unit 32a may be provided to replace the second RF generating unit 31b.

[0018] The exhaust system 40 may be connected, for example, to a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure within the plasma processing space 10s is adjusted by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0019] The control unit 2 processes computer-executable commands that cause the plasma processing apparatus 1 to perform the various steps described herein. The control unit 2 may be configured to control the various elements of the plasma processing apparatus 1 in a manner that executes the various steps described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include, for example, a computer 2a. The computer 2a may include, for example, a processing unit (CPU: Central Processing Unit) 2a1, a memory unit 2a2, and a communication interface 2a3. The processing unit 2a1 may be configured to perform various control actions based on a program stored in the memory unit 2a2. The memory unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or combinations thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).

[0020] [Substrate as the object of processing] Next, the substrate as the object of etching processing will be described using FIG2. FIG2 is a schematic diagram showing an example of the structure of a substrate etched by the plasma processing apparatus of this embodiment. FIG2 shows the substrate W in state 50 before processing and state 51 after processing. The substrate W has a silicon oxide film 53 and a mask 54 on a silicon substrate 52. The silicon oxide film 53 is the etched film. The mask 54 is a silicon nitride film with openings of a specific pattern, such as comb-shaped openings. The spacing between the openings is, for example, 25 to 30 nm or less, and the target value of the line CD (Critical Dimension) is, for example, 10 nm. The etching in this embodiment is as shown in state 51, in which the etching ends before the silicon oxide film 53 at the opening of the mask 54 reaches the silicon substrate 52, and the aspect ratio of the trenches of the silicon oxide film 53 is 7 or more. At this point, a requirement was put forward to improve the relationship between the etching depth 55 and the residual 56 of the mask 54, i.e., the selectivity, and to improve the shape controllability of the bottom shape 57 of the trench. Therefore, in this embodiment, by controlling the power level of the bias RF signal in the supply mode of the source RF signal and the bias RF signal supplied in the form of pulsed high-frequency power, the selectivity, escape and shape controllability are improved, and the processing time is shortened compared to the gas switching mode of ALE.

[0021] [RF Signal Supply Mode] Next, using Figures 3 and 4, the supply mode of the RF signal (high-frequency power) during the etching process will be explained in comparison with the reference example. Figures 3 and 4 are diagrams showing one example of one cycle of the RF signal in this embodiment and the reference example. Figure 3(a) shows the supply mode 60a of the reference example, and Figure 3(b) shows the supply mode 60b of this embodiment. In this embodiment, the deposition step and the etching step are repeated by repeating the supply mode 60b. One cycle of the supply mode 60b is, for example, repeated at 10000 μs (0.1 kHz). Furthermore, one cycle of the supply mode 60b can also be any cycle of 100 ms (10 Hz) or less. For example, if one cycle of supply mode 60b is taken as the repetition period and expressed in terms of repetition frequency, then the repetition period can be set to have a repetition frequency in the range of 10 Hz to 100 kHz (100 ms to 10 μs). Furthermore, in the following description and figures, the source RF signal is sometimes represented as HF (High Frequency), the bias RF signal as LF (Low Frequency), and the second DC signal as DC. Also, sometimes the RF signal being supplied is represented as "RF. PW", and the RF signal being stopped is represented as "RF Off".

[0022] The supply mode 60a of the reference example does not change the power level of the bias RF signal. Supply mode 60a, like supply mode 60b, has a cycle of 10000 μs (0.1 kHz), which is sequentially divided into three stages from the beginning: supplying HF for 2500 μs, stopping HF and LF for 2500 μs, and supplying LF for 5000 μs. In contrast, the supply mode 60b of this embodiment is sequentially divided from the beginning into four stages: supplying HF at the first power level for 2500 μs, stopping HF and LF for 2500 μs, supplying LF (RF. PW-1) at the second power level for 2500 μs, and supplying LF (RF. PW-2) at the third power level for 2500 μs.

[0023] Figure 4 shows the power levels and DC ON / OFF of each stage of supply modes 60a and 60b. Furthermore, in the following description and figures, each stage of supply mode 60a is sequentially represented as stage Ph1a, Ph2a, and Ph3a from the beginning, and each stage of supply mode 60b is sequentially represented as stage Ph1b, Ph2b, Ph3b, and Ph4b from the beginning. Furthermore, stages Ph1a and Ph1b correspond to the deposition step, and stages Ph3a, Ph3b, and Ph4b correspond to the etching step. Also, stages Ph1b, Ph2b, Ph3b, and Ph4b are examples of the first, second, third, and fourth states during the repetition period, respectively.

[0024] In the supply mode 60a shown in Figure 4(a), HF is supplied at power level A1 in stage Ph1a, the supply of HF and LF is stopped in stage Ph2a, and LF is supplied at power level A2 in stage Ph3a. DC is also supplied in stages Ph1a to Ph3a (indicated as "ON" in Figure 4(a)). On the other hand, in the supply mode 60b shown in Figure 4(b), HF is supplied at power level B1 (first power level) in stage Ph1b, the supply of HF and LF is stopped in stage Ph2b, LF is supplied at power level B2-1 (second power level) in stage Ph3b, and LF is supplied at power level B2-2 (third power level) in stage Ph4b. At this time, power level B2-1 (second power level) is greater than power level B2-2 (third power level). Furthermore, DC is supplied in stages Ph1b and Ph2b (indicated as "ON" in Figure 4(b)), and the supply of DC is stopped in stages Ph3b and Ph4b (indicated as "OFF" in Figure 4(b)). That is, compared with supply mode 60a, the power level during LF supply changes in two stages, and the DC supply is stopped during the etching step. Moreover, the change in power level during LF supply is not limited to two stages; it can change in three or more stages, or it can change continuously.

[0025] Here, under supply mode 60b, stages Ph1b to Ph4b are examples of repeated periods as described above, and the ratio of stages Ph1b to Ph4b can be changed within the repeated period. Under supply mode 60b shown in Figure 4(b), stages Ph1b to Ph4b are equally divided into 25% each. In this case, it can be said that the period of stage Ph1b is the same as the period of stage Ph2b. Also, it can be said that the period of stage Ph3b is the same as the period of stage Ph4b.

[0026] On the other hand, when changing the ratio of stages Ph1b to Ph4b, for example, the duration of stage Ph1b can be longer or shorter than the duration of stage Ph2b. Similarly, the duration of stage Ph3b can be longer or shorter than the duration of stage Ph4b. Furthermore, the duration of stage Ph2b is preferably less than 50% of the repetition period. Moreover, the ratio of stages Ph1b to Ph4b is preferably within the range of 5% to 90% of the repetition period. Furthermore, both the length and ratio of the repetition period can be changed, in which case the duration of stages Ph1b to Ph4b is preferably within the range of 0.5 microseconds to 90 milliseconds (0.5 μs to 90 ms). Furthermore, changes in the length and ratio of the duration of stages Ph1b to Ph4b can also be combined with the variation examples described later.

[0027] Regarding the relationship between the duration of stage Ph1b and stage Ph2b, if the duration of stage Ph2b is longer than that of stage Ph1b, the plasma density will be significantly reduced, resulting in a larger free radical / ion ratio. Furthermore, if the duration of stage Ph2b is longer than that of stage Ph1b, it will promote the transport of free radicals to the bottom of the trench, making etching easier and thus improving escape characteristics. On the other hand, if the duration of stage Ph2b is shorter than that of stage Ph1b, it will increase the amount of deposited material on the mask 54, thereby improving the selectivity.

[0028] When the duration of stage Ph3b is the same as that of stage Ph4b, the bottom shape of the trench can be controlled by controlling the power level B2-1 of stage Ph3b and the power level B2-2 of stage Ph4b. When the power level B2-1 of stage Ph3b is greater than the power level B2-2 of stage Ph4b, the bottom shape of the trench becomes an inclined shape. On the other hand, when the power level B2-1 of stage Ph3b is less than the power level B2-2 of stage Ph4b (refer to the variation example described later), the bottom shape of the trench becomes a rectangular shape (vertical shape). Thus, when the duration of stage Ph3b is the same as that of stage Ph4b, the bottom shape of the trench can be controlled by controlling the power level B2-1 of stage Ph3b and the power level B2-2 of stage Ph4b. Furthermore, the experimental results are shown in Figure 13, which will be described later.

[0029] Furthermore, regarding the relationship between the duration of stage Ph3b and the duration of stage Ph4b, if the duration of stage Ph3b is longer than the duration of stage Ph4b, the bottom shape of the trench becomes a rectangular shape (vertical shape). On the other hand, if the duration of stage Ph3b is shorter than the duration of stage Ph4b, the bottom shape of the trench becomes an inclined shape. That is, by controlling the duration of stage Ph3b and the duration of stage Ph4b, the bottom shape of the trench can be controlled.

[0030] Next, the second DC signal (hereinafter also simply referred to as the DC signal) supplied to the conductive member (upper electrode) of the cluster head 13 will be described using FIG5. FIG5 is a diagram showing an example of the DC signal in this embodiment. In one embodiment, as shown in FIG5(a), the DC signal has a fixed voltage level with negative polarity during the ON period. In one embodiment, as shown in FIG5(b), the DC signal has a sequence of multiple pulses with negative polarity during the ON period. For example, in stage Ph1b, the sequence of multiple pulses with negative polarity overlaps with HF on the upper electrode.

[0031] Regarding the DC signal, in the supply mode 60b shown in FIG4(b), for example, a first voltage level is set in stages Ph1b and Ph2b, and a second voltage level is set in stages Ph3b and Ph4b. At this time, the relationship between the first voltage level and the second voltage level is, for example, that the absolute value of the first voltage level is greater than the absolute value of the second voltage level. That is, the DC signal has a first voltage level during stages Ph1b and Ph2b, which has a negative polarity, and has a second voltage level during stages Ph3b and Ph4b, where the absolute value of the second voltage level is less than the absolute value of the first voltage level.

[0032] Furthermore, in the supply mode 60b shown in FIG4(b), for example, the first voltage level of the DC signal can be set to -50 V to -2500 V, and the second voltage level can be set to 0 V (zero voltage level). At this time, the first voltage level has a pulse frequency in the range of 1 kHz to 100 kHz. That is, the first voltage level has a negative DC pulse sequence with a pulse frequency in the range of 1 kHz to 100 kHz. Moreover, the DC signal can also be a non-pulsating negative polarity fixed voltage level signal, for example, in stages Ph1b to Ph4b.

[0033] Thus, in stages Ph1b and Ph2b, by supplying a DC signal, the carbon composition ratio of CF sediments, which are reactive organisms (sediments), can be increased. That is, it can help improve the mask selectivity and controllability of CD.

[0034] [Experimental Results] Next, the experimental results will be explained using FIG6. FIG6 is a diagram showing one example of the experimental results of this embodiment and the reference example. FIG6(a) shows the experimental results of the reference example corresponding to supply mode 60a and the embodiment corresponding to supply mode 60b. FIG6(b) shows the measurement locations of etching depth d1, mask residue r1 and bottom angle θ. Furthermore, in FIG6(b), an oxide layer of silicon nitride film, i.e., SiON layer 65, is formed around the mask (SiN). Furthermore, the processing conditions are as follows. Furthermore, in FIG6, the power level of LF is represented in the form of LF column (second power level) and LF-2 column (third power level). When the power level is one stage, the LF-2 column is represented as 0. Furthermore, the effective power of LF is the same in the reference example and the embodiment.

[0035] <Processing Conditions> Pressure within plasma processing chamber 10: 25 mTorr (3.33 Pa) Temperature: 133℃ Source RF signal power (60 MHz): 200 W (pulse) Bias RF signal power (12.88 MHz): Reference example: 175 W (pulse) Example: 300 W / 50 W (pulse) Second DC signal voltage: -500 V Pulse frequency: 0.1 kHz Pulse duty cycle: HF / LF / LF offset = 25 / 50 / 50% Processing gas (C4F6 / O2 / Ar) flow ratio: 0.5 / 0.47 / 100

[0036] As shown in Figure 6, regarding the etching depth d1, it reaches 40.9 nm in this embodiment, compared to 37.8 nm in the reference example. Furthermore, regarding the mask residue r1, it is 24.9 nm in this embodiment, compared to 21.5 nm in the reference example, resulting in increased mask selectivity. Also, regarding the etching time, it can be shortened to 416.7 seconds in this embodiment, compared to 444.8 seconds in the reference example. Furthermore, regarding the bottom angle θ, it is 87.5° in this embodiment, compared to 86.2° in the reference example, making the angle more upright, and the bottom shape of the embodiment is more rectangular than that of the reference example. Thus, in the supply mode of this embodiment, the selectivity is higher than the fixed power level supply mode of LF, and the bottom shape is also closer to a rectangle, thereby shortening the processing time.

[0037] [Analysis Results] <Shape Control Model> Next, the shape control model will be explained using FIG7. FIG7 is a diagram showing an example of the shape control model in this embodiment and the reference example. FIG7(a) is the shape control model in stage Ph3a of the reference example. In stage Ph3a, Ar ions generated by the second plasma are fed from the opening of the mask 54 to the bottom of the trench of the silicon oxide film 53 by means of a bias potential, thereby etching as shown in state 58.

[0038] Figure 7(b) shows the shape control model in stages Ph3b and Ph4b of the experimental example. In stage Ph3b, Ar ions generated by the second plasma are fed from the opening of the mask 54 to the bottom of the trench of the silicon oxide film 53 using a bias potential, thereby etching as shown in state 59a. In the next stage Ph4b, since the power level of the bias RF signal is reduced, the ion energy of the Ar ions generated by the second plasma decreases and the incident angle increases, thereby expanding the shape of the bottom of the trench of the silicon oxide film 53 (bottom shape) as shown in state 59b, thereby forming a rectangular shape (vertical wall).

[0039] <Selectivity Improvement Model> Next, the selectivity improvement model will be explained using FIG8. FIG8 is a diagram showing an example of the selectivity improvement model in this embodiment and the reference example. FIG8 shows the relationship between the amount of CF as a reaction product (deposit) attached to the surface of the mask 54 and the amount of CF etched during one cycle of supply modes 60a and 60b, respectively. The curve 61a shown in FIG8(a) shows the situation of supply mode 60a of the reference example. In stages Ph1a+Ph2a, the amount of CF increases as shown in curve 62a, and the amount of etched is zero as shown in curve 63a. Subsequently, in stage Ph3a, the amount of CF decreases as the amount of etched increases, and at time point 64a, the CF attached to the surface of the mask 54 disappears, and the mask 54 is damaged.

[0040] Figure 8(b) shows a graph 61b illustrating the supply mode 60b of the embodiment. In stages Ph1a+Ph2a, the amount of CF, as represented by graph 62b, increases, while the amount of etching, as shown by graph 63b, is zero. Subsequently, in stage Ph3b, the amount of CF decreases with the increase of etching, but at the end of stage Ph3b, a small amount of CF remains. Subsequently, in stage Ph4b, due to the decrease in the power level of the bias RF signal, the ion energy of Ar ions decreases, thus slowing down the decrease in the amount of remaining CF. At time point 64b, the CF adhering to the surface of the mask 54 disappears, and the mask 54 is damaged. Comparing graphs 61a and 61b, it can be seen that the supply mode 60b of this embodiment causes less damage to the mask 54 than the supply mode 60a of the reference example. That is, compared with the supply mode 60a of the reference example, the supply mode 60b of this embodiment is more capable of improving the selection ratio.

[0041] <Behavior During RF Signal Supply> Next, the behavior of each stage of the supply mode 60b of this embodiment will be explained using Figures 9 and 10. Figure 9 is a graph showing an example of the etching amount in each stage. The graph 70 shown in Figure 9 shows the etching amount of the silicon oxide film 53 in stages Ph1b, Ph3b, and Ph4b when supplying HF or LF in supply mode 60b. As shown in graph 70, it can be seen that no etching of the silicon oxide film 53 is performed in stage Ph1b, and its contribution to the etching of stage Ph1b is small. On the other hand, it can be seen that the etching of the silicon oxide film 53 is performed in stages Ph3b and Ph4b, and its contribution to the etching of stages Ph3b and Ph4b is large. Furthermore, it can be seen that the etching amount of the silicon oxide film 53 in stage Ph3b, where the power level of the bias RF signal is higher, is greater than that in stage Ph4b, where the power level is lower.

[0042] Figure 10 is a graph showing an example of the luminescence intensity at each stage. The curve 71 shown in Figure 10 illustrates the luminescence intensity in stages Ph1b, Ph3b, and Ph4b of HF or LF supply under supply mode 60b. As shown in region 72 of curve 71, it can be seen that in stage Ph1b, CF luminescence is stronger, contributing more to the formation of deposits. On the other hand, it can be seen that in stages Ph3b and Ph4b, CF luminescence is weaker, contributing less to the formation of deposits.

[0043] <Verification of Etching Speed> Next, the etching speed will be explained using FIG11. FIG11 is a diagram showing an example of the comparison of the total etching amount of this embodiment and the reference example. As shown in FIG11, in the embodiments of the reference example and this embodiment, the effective power of LF is the same, and the SiO etching amount varies with the LF power. In the reference example, when the LF power is 175 W (stage Ph3a), the SiO etching amount is 36.1 [nm / 2 min]. In contrast, in the embodiment, when the LF power is 300 W (stage Ph3b), the SiO etching amount is 63.2 [nm / 2 min], and when the LF power is 50 W (stage Ph4b), the SiO etching amount is 15.2 [nm / 2 min]. If the SiO etching amount is multiplied by the ratio of the LF power supply time in one cycle (on / (on+off)), i.e., the duty cycle, the total SiO etching amount in the reference example is 18.1 [nm / duty%]. On the other hand, in the embodiment, when the LF power is 300 W (stage Ph3b), it is 15.8 [nm / duty%], and when the LF power is 50 W (stage Ph4b), it is 3.8 [nm / duty%], thus totaling 19.6 [nm / duty%]. Therefore, the etching rate of the embodiment that processes at multiple power levels is faster than that of the reference example.

[0044] [Variation Example] In the above embodiment, under supply mode 60b, the power level of stage Ph3b supplying the bias RF signal is increased, so that the power level of stage Ph4b is lower than that of stage Ph3b. However, the relationship between the power levels of stage Ph3b and stage Ph4b can also be changed. That is, the distribution of RF power (LF power) of LF can also be changed.

[0045] Figure 12 is a diagram showing one cycle of the RF signal in the variation example. In the supply mode 60c shown in Figure 12, HF is supplied at power level B1 (first power level) in stage Ph1b, and the supply of HF and LF is stopped in stage Ph2b. Furthermore, LF is supplied at power level B2-1 (second power level) in stage Ph3b, and LF is supplied at power level B2-2 (third power level) in stage Ph4b, such that power level B2-2 is higher than power level B2-1. That is, supply mode 60c is a supply mode in which the magnitudes of power levels B2-1 and B2-2 are interchanged compared to supply mode 60b shown in Figure 4(b). That is, power level B2-1 (second power level) is less than power level B2-2 (third power level).

[0046] [Experimental Results of Variation Examples] Next, the experimental results of the variation examples will be explained using FIG13. FIG13(a) is a diagram showing an example of the experimental results when the RF power distribution of the LF is changed. FIG13(b) shows the measurement locations of etching depth d1, mask residue r1, bottom angle θ, TCD (Top Critical Dimension), and BCD (Bottom Critical Dimension). Furthermore, in FIG13(b), a SiON layer 65 as an oxide layer of silicon nitride film is formed around the mask (SiN). The processing conditions in FIG13 are the same as those in FIG6 of the above embodiment, except for the LF power distribution. FIG13 shows the experimental results when the power level distribution of stage Ph3b and stage Ph4b is changed under conditions A to F. Condition A is the same as in Figure 6, that is, the power level B2-1 of stage Ph3b is set to 300 W, and the power level B2-2 of stage Ph4b is set to 50 W. In Figure 13, in the LF power allocation column, it is represented in the form of 300 W / 50 W according to the order of power levels B2-1 and B2-2.

[0047] Furthermore, conditions B to F are also expressed in the same form according to the power levels B2-1 and B2-2, respectively. Condition B is 250 W / 100 W, condition C is 200 W / 150 W, condition D is 175 W / 175 W, condition E is 100 W / 250 W, and condition F is 50 W / 300 W. The effective power of LF is the same as under conditions A to F, and is set to 87.5 W.

[0048] Regarding the etching time, condition A is 416.7 seconds, condition B is 487.6 seconds, condition C is 515.8 seconds, condition D is 452.0 seconds, condition E is 558.8 seconds, and condition F is 556.1 seconds. Regarding the mask residue r1, condition A is 24.9 nm, condition B is 22.2 nm, condition C is 21.7 nm, condition D is 20.5 nm, condition E is 19.7 nm, and condition F is 22.4 nm. Regarding the etching depth d1, condition A is 40.9 nm, condition B is 41.3 nm, condition C is 43.0 nm, condition D is 40.6 nm, condition E is 36.3 nm, and condition F is 32.3 nm.

[0049] Regarding the difference between TCD and BCD (TCD-BCD), i.e., ΔCD, which is the fin, condition A is 3.5 nm, condition B is 2.6 nm, condition C is 2.5 nm, condition D is 2.5 nm, condition E is 1.5 nm, and condition F is 1.4 nm. Regarding the angle θ at the bottom of the cross-section, condition A is 87.55°, condition B is 88.20°, condition C is 88.40°, condition D is 88.24°, condition E is 88.80°, and condition F is 88.75°. According to the experimental results in Figure 13, condition F is the most vertical, providing excellent shape control for forming the bottom shape of the trench into a rectangular shape, but the etching time is longer. On the other hand, the mask residue r1 is the highest under condition A. Thus, the processing conditions A to F can be appropriately applied according to the required characteristics such as shape control and the aspect ratio of the trench.

[0050] Figure 14 is an example of a graph showing the trend data when the RF power distribution of the LF changes. The graph 73 shown in Figure 14 plots the etching depth d1 and the bottom angle θ in the experimental results shown in Figure 13(a). As shown in graph 73, it can be seen that the bottom angle θ tends to be vertical from condition A to condition F depending on the LF power distribution. On the other hand, it can be seen that the etching depth d1 is slightly shallower under conditions E and F than under conditions A to D, but there is no trend like that of the bottom angle θ. Therefore, it can be seen that under conditions E and F, the shape control of the supply mode that makes the power level of stage Ph4b greater than that of stage Ph3b is better.

[0051] Figure 15 is a diagram showing one example of the shape control model in the variation example. Figure 15 shows the shape control model of stages Ph3b and Ph4b in the variation example. In stage Ph3b, Ar ions generated by the second plasma are fed from the opening of the mask 54 to the bottom of the trench of the silicon oxide film 53 using a bias potential, thereby etching as shown in state 74a. At this time, in stage Ph3b, since the power level of the bias RF signal is low, the ion energy of the Ar ions generated by the second plasma is low. By increasing the incident angle, the shape of the bottom of the trench of the silicon oxide film 53 (bottom shape) can be enlarged. In the next stage Ph4b, since the power level of the bias RF signal increases, the ion energy of the Ar ions generated by the second plasma also increases, thereby making the etching rate faster than in stage Ph3b. In this case, as shown in state 74b, the shape control of forming the shape of the bottom of the trench of silicon oxide film 53 into a rectangular shape is higher than that of the supply mode 60b shown in Figure 7(b).

[0052] According to the present embodiment, the plasma processing apparatus includes: a chamber (plasma processing chamber 10); a substrate support 11 disposed in the chamber and including a lower electrode; an upper electrode disposed above the substrate support 11; a first RF power supply configured to be electrically connected to the upper electrode and generate a first RF signal (first RF generating unit 31a), wherein the first RF signal has a first power level during a first state in a repetition period and a zero power level during a second state, a third state, and a fourth state in a repetition period; a second RF power supply configured to be electrically connected to the lower electrode and generate a second RF signal (second RF generating unit 31b), wherein the second RF signal has a zero power level during the first state and the second state, a second power level during the third state, and a third power level during the fourth state; and a DC power supply (second... The DC generating unit 32b is electrically connected to the upper electrode and is configured to generate a DC signal. As a result, etching can be performed that balances improved selectivity, escape capability, and shape control with reduced processing time.

[0053] Furthermore, according to this embodiment, the DC signal has a fixed voltage level during the first, second, third, and fourth states, and this voltage level has a negative polarity. As a result, the carbon composition ratio of CF sediments, which are reactive organisms (sediments), can be increased.

[0054] Furthermore, according to this embodiment, the DC signal has a first voltage level during the first and second states, the first voltage level having a negative polarity, and a second voltage level during the third and fourth states, the absolute value of the second voltage level being less than the absolute value of the first voltage level. As a result, the carbon composition ratio of CF sediments, which are reactive organisms (sediments), can be increased, and it can help improve the mask selectivity and controllability of CD.

[0055] Furthermore, according to this embodiment, the second voltage level has a zero voltage level. As a result, the carbon composition ratio of the CF sediment, which is a reactive organism (sediment), can be increased, and it can help improve the mask selectivity and controllability of CD.

[0056] Furthermore, according to this embodiment, the first voltage level has a negative DC pulse sequence with a pulse frequency in the range of 1 kHz to 100 kHz. As a result, the carbon composition of the CF deposit, which is a reactive organism (sediment), can be higher, and it can help improve the mask selectivity and controllability of CD.

[0057] Furthermore, according to this embodiment, the second power level is greater than the third power level. As a result, the bottom shape of the trench (groove) can be formed into an inclined shape.

[0058] Furthermore, according to this embodiment, the second power level is lower than the third power level. As a result, the bottom shape of the trench can be formed into a rectangular shape (vertical shape).

[0059] Furthermore, according to this embodiment, the repetition period is 100 milliseconds or less. As a result, damage to the mask can be reduced, thereby improving the selectivity.

[0060] Furthermore, according to this embodiment, the repetition period has a repetition frequency in the range of 10 Hz to 100 kHz. As a result, damage to the mask can be reduced, thereby improving the selectivity.

[0061] Furthermore, according to this embodiment, the period of the second state is less than 50% of the repetition period. As a result, the selectivity and escape performance can be improved.

[0062] Furthermore, according to this embodiment, the period of the first state is the same as the period of the second state. As a result, the free radical / ion ratio can be controlled within a moderate range, thereby enabling control over the amount of sediment generated and the selectivity.

[0063] Furthermore, according to this embodiment, the period of the first state is longer than the period of the second state. As a result, the free radical / ion ratio can be controlled within a smaller range, thereby enabling control over the amount of sediment produced and the selectivity.

[0064] Furthermore, according to this embodiment, the period of the first state is shorter than the period of the second state. As a result, the free radical / ion ratio can be controlled within a larger range, thereby enabling control over the amount of sediment generated and the selectivity.

[0065] Furthermore, according to this embodiment, the second power level is greater than the third power level, and the duration of the third state is the same as the duration of the fourth state. As a result, the amount of etching in the depth direction can be increased, while the amount of lateral etching at the bottom end can be suppressed. Also, the bottom end shape can be formed into an inclined shape.

[0066] Furthermore, according to this embodiment, the second power level is greater than the third power level, and the period of the third state is longer than the period of the fourth state. As a result, the amount of etching in the depth direction can be increased, and the amount of lateral etching at the bottom end can be suppressed. Also, the bottom end shape can be formed into an inclined shape.

[0067] Furthermore, according to this embodiment, the second power level is greater than the third power level, and the period of the third state is shorter than the period of the fourth state. As a result, the amount of etching in the depth direction can be suppressed, and the amount of etching in the lateral direction at the bottom end can be increased. Also, the bottom end shape can be formed into a rectangular shape (vertical shape).

[0068] Furthermore, according to this embodiment, the second power level is lower than the third power level, and the duration of the third state is the same as the duration of the fourth state. As a result, the amount of etching in the depth direction can be suppressed, and the amount of etching in the lateral direction at the bottom end can be increased. Also, the bottom end shape can be formed into a rectangular shape (vertical shape).

[0069] Furthermore, according to this embodiment, the second power level is lower than the third power level, and the period of the third state is longer than the period of the fourth state. As a result, the amount of etching in the depth direction can be suppressed, and the amount of etching in the lateral direction at the bottom end can be increased. Also, the bottom end shape can be formed into a rectangular shape (vertical shape).

[0070] Furthermore, according to this embodiment, the second power level is lower than the third power level, and the period of the third state is shorter than the period of the fourth state. As a result, the amount of etching in the depth direction can be greater, and the amount of etching in the lateral direction of the bottom end can be suppressed. Also, the bottom end shape can be formed into an inclined shape.

[0071] Furthermore, according to this embodiment, the periods of the first state and the second state are within the range of 0.5 microseconds to 90 milliseconds. As a result, the free radical / ion ratio can be controlled, thereby enabling control over the amount of deposits produced and the selectivity.

[0072] Furthermore, according to this embodiment, the duration of the third state and the duration of the fourth state are within the range of 0.5 microseconds to 90 milliseconds. As a result, the bottom shape of the trench can be controlled.

[0073] Furthermore, according to this embodiment, the period of the first state and the period of the second state are within the range of 5% to 90% of the repetition period. As a result, the free radical / ion ratio can be controlled, thereby enabling control over the amount of deposits produced and the selectivity.

[0074] Furthermore, according to this embodiment, the period of the third state and the period of the fourth state are within the range of 5% to 90% of the repetition period. As a result, the bottom shape of the trench can be controlled.

[0075] Furthermore, according to this embodiment, the RF system (RF power supply 31) includes: a first RF generator configured to generate a first RF signal (first RF generation unit 31a), wherein the first RF signal has a first power level during a first state in a repetition period, and a zero power level during a second state, a third state, and a fourth state in a repetition period; and a second RF generator configured to generate a second RF signal (second RF generation unit 31b), wherein the second RF signal has a zero power level during the first and second states, a second power level during the third state, and a third power level during the fourth state. As a result, etching that can simultaneously improve selectivity, escape capability, and shape controllability while shortening processing time can be performed.

[0076] It should be considered that all the embodiments disclosed herein are merely illustrative and not limitations on the present invention. The above embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the appended patent applications.

[0077] Furthermore, in the above embodiments, a capacitively coupled plasma processing apparatus 1 that uses capacitively coupled plasma as a plasma source to perform etching and other processes on the substrate W has been described as an example, but the disclosed technology is not limited to this. As long as the apparatus uses plasma to process the substrate W, the plasma source is not limited to capacitively coupled plasma. For example, any plasma source such as inductively coupled plasma, microwave plasma, or magnetron plasma can be used.

[0078] Furthermore, the above-described embodiments and variations can be appropriately combined within the scope of not causing contradictions in the constituent content. [Simplified Explanation of the Diagram]

[0008] Figure 1 is a diagram showing an example of a plasma processing system according to one embodiment of the present invention. Figure 2 is a diagram showing an example of the structure of a substrate etched by the plasma processing apparatus of this embodiment. Figures 3(a) and (b) are diagrams showing an example of one cycle of an RF signal in this embodiment and the reference example. Figures 4(a) and (b) are diagrams showing an example of one cycle of an RF signal in this embodiment and the reference example. Figures 5(a) and (b) are diagrams showing an example of a DC signal in this embodiment. Figures 6(a) and (b) are diagrams showing an example of experimental results in this embodiment and the reference example. Figures 7(a) and (b) are diagrams showing an example of a shape control model in this embodiment and the reference example. Figures 8(a) and (b) are diagrams showing an example of a selectivity improvement model in this embodiment and the reference example. Figure 9 is a diagram showing an example of the etching amount at each stage. Figure 10 is a diagram showing an example of the luminescence intensity at each stage. Figure 11 is a graph comparing the total etching amount of this embodiment with that of the reference example. Figure 12 is a graph showing one cycle of the RF signal in a variation example. Figures 13(a) and (b) are graphs showing experimental results when the RF power distribution of the LF is changed. Figure 14 is a graph showing trend data when the RF power distribution of the LF is changed. Figure 15 is a graph showing an example of the shape control model in a variation example.

Claims

1. A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber and including a lower electrode; an upper electrode disposed above the substrate support; a first RF power supply electrically connected to the upper electrode to generate a first RF signal, wherein the first RF signal has a first power level during a first state in a repetition period and a zero power level during a second, third, and fourth state in the repetition period; a second RF power supply electrically connected to the lower electrode to generate a second RF signal, wherein the second RF signal has a zero power level during the first and second states, a second power level during the third state, and a third power level during the fourth state; and a DC power supply electrically connected to the upper electrode to generate a DC signal.

2. The plasma processing apparatus of claim 1, wherein the DC signal has a fixed voltage level during the first state, the second state, the third state and the fourth state, the voltage level having a negative polarity.

3. The plasma processing apparatus of claim 1, wherein the DC signal has a first voltage level during the first state and the second state, the first voltage level having a negative polarity, and has a second voltage level during the third state and the fourth state, wherein the absolute value of the second voltage level is less than the absolute value of the first voltage level.

4. The plasma processing apparatus of claim 3, wherein the second voltage level has a zero voltage level.

5. The plasma processing apparatus of claim 3, wherein the first voltage level has a negative DC pulse sequence having a pulse frequency in the range of 1 kHz to 100 kHz.

6. The plasma processing apparatus of any one of claims 1 to 5, wherein the second power level is greater than the third power level.

7. The plasma processing apparatus of any one of claims 1 to 5, wherein the second power level is lower than the third power level.

8. The plasma processing apparatus of any one of claims 1 to 5, wherein the repetition period is less than 100 milliseconds.

9. The plasma processing apparatus of any one of claims 1 to 5, wherein the repetition period has a repetition frequency in the range of 10 Hz to 100 kHz.

10. The plasma processing apparatus of any one of claims 1 to 5, wherein the duration of the second state is less than 50% of the repetition period.

11. The plasma processing apparatus of any one of claims 1 to 5, wherein the duration of the first state is the same as the duration of the second state.

12. The plasma processing apparatus of any one of claims 1 to 5, wherein the duration of the first state is longer than the duration of the second state.

13. The plasma processing apparatus of any one of claims 1 to 5, wherein the duration of the first state is shorter than the duration of the second state.

14. The plasma processing apparatus of claim 6, wherein the duration of the third state is the same as the duration of the fourth state.

15. The plasma processing apparatus of claim 6, wherein the duration of the third state is longer than the duration of the fourth state.

16. The plasma processing apparatus of claim 6, wherein the duration of the third state is shorter than the duration of the fourth state.

17. The plasma processing apparatus of claim 7, wherein the duration of the third state is the same as the duration of the fourth state.

18. The plasma processing apparatus of claim 7, wherein the duration of the third state is longer than the duration of the fourth state.

19. The plasma processing apparatus of claim 7, wherein the duration of the third state is shorter than the duration of the fourth state.

20. The plasma processing apparatus of any one of claims 1 to 5, wherein the duration of the first state is in the range of 0.5 microseconds to 90 milliseconds.

21. The plasma processing apparatus of claim 20, wherein the duration of the second state is in the range of 0.5 microseconds to 90 milliseconds.

22. The plasma processing apparatus of claim 21, wherein the duration of the third state is in the range of 0.5 microseconds to 90 milliseconds.

23. The plasma processing apparatus of claim 22, wherein the duration of the fourth state is in the range of 0.5 microseconds to 90 milliseconds.

24. The plasma processing apparatus of any one of claims 1 to 5, wherein the period of the first state is within the range of 5% to 90% of the repetition period.

25. The plasma processing apparatus of claim 24, wherein the period of the second state is within the range of 5% to 90% of the repetition period.

26. The plasma processing apparatus of claim 25, wherein the period of the third state is within the range of 5% to 90% of the repetition period.

27. The plasma processing apparatus of claim 26, wherein the period of the fourth state is within the range of 5% to 90% of the repetition period.

28. An RF system comprising: a first RF generator configured to generate a first RF signal, wherein the first RF signal has a first power level during a first state in a repetition period and a zero power level during a second state, a third state and a fourth state in the repetition period; and a second RF generator configured to generate a second RF signal, wherein the second RF signal has a zero power level during the first state and the second state, a second power level during the third state, and a third power level during the fourth state.

29. The RF system of claim 28, wherein the second power level is greater than the third power level.

30. The RF system of claim 28, wherein the second power level is lower than the third power level.

31. An RF system as described in any of requests 28 to 30, wherein the repetition period is less than 100 milliseconds.

32. An RF system as claimed in any of claims 28 to 30, wherein the repetition period has a repetition frequency in the range of 10 Hz to 100 kHz.

33. An RF system as described in any of requests 28 to 30, wherein the duration of the second state is less than 50% of the repetition period.

Images