Semiconductor device

Abstract

The object of this invention is to reduce the on-resistance in a semiconductor device used to conduct large currents. The semiconductor device 10 of this invention has a source terminal pin SL located between the gate terminal pin GL and the Klven terminal pin KL in top view, and electrically connected to the source terminal pin ST via a plurality of wires W3.

Description

Technical field

[0001] The present invention relates to a semiconductor device, for example, an effective technology applicable to a semiconductor device which is a constituent element of an inverter.

Prior technology

[0002] Japanese Unexamined Patent Publication No. 2008-294384 (Patent Document 1) describes a method of reducing the on-resistance of a semiconductor device formed with a power MOSFET (MetalOxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor). technology.

[0003] Japanese Patent Laying-Open No. 2009-231805 (Patent Document 2) also describes a technique for reducing the on-resistance of a semiconductor device formed with a power MOSFET. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Application Publication No. 2008-294384 [Patent Document 2] Japanese Patent Application Publication No. 2009-231805

Content of invention

[0005] [the problem to be solved by the invention]

[0006] In recent years, it has been studied to flow a large current in a semiconductor device forming a power semiconductor element. For example, it is considered that a current of about 300A flows through a semiconductor device used in a three-phase inverter. In this regard, when a large current flows through the semiconductor device, the on-resistance existing in the semiconductor device has a great influence on the performance of the semiconductor device. Therefore, means for reducing on-resistance in semiconductor devices used for passing large currents is desired. [Means to solve the problem]

[0007] A semiconductor device according to an embodiment, which is located between a pin for a gate terminal and a pin for a detection terminal in a plan view, and is connected to a current terminal through a connecting member for a current terminal among a plurality of connecting members. A pin for a current terminal that is electrically connected to a terminal.

[0008] Also, a semiconductor device in another embodiment has a current terminal connection between the gate terminal pin and the multi-function terminal pin in plan view, and through a plurality of connection members. A current terminal pin that is electrically connected to a current terminal. [Effect of Invention]

[0009] Through an embodiment, the performance of a semiconductor device can be improved.

Implementation

[0011] In all the drawings used to describe the embodiments, in principle, the same components are marked with the same symbols, and repeated descriptions are omitted. In addition, in order to make the drawings easier to understand, the top view will also be marked with hatching.

[0012] <Configuration Example of Three-Phase Inverter Circuit> The semiconductor device in this embodiment is, for example, a drive circuit for a three-phase induction motor used in an air conditioner. Specifically, the drive circuit includes an inverter circuit, and the inverter circuit is a circuit with the function of converting DC power into AC power.

[0013] FIG. 1 is a circuit diagram showing the constitution of a motor circuit including an inverter circuit and a three-phase induction motor. In FIG. 1 , the motor circuit has a three-phase induction motor MT and an inverter circuit INV. The three-phase induction motor MT is driven by three-phase voltages with different phases. Specifically, in the three-phase induction motor MT, a rotating magnetic field is generated around the conductor, that is, the rotating body RT, using three-phase alternating current called U-phase, V-phase, and W-phase with a phase difference of 120 degrees. In this case, the magnetic field rotates around the rotating body RT. This means that the magnetic flux passing through the conductor, ie the rotating body RT, changes. As a result, electromagnetic induction is generated in the conductor, that is, the rotating body RT, and an induced current flows in the rotating body RT. And, according to Fleming's left-hand rule, the induced current flows in the rotating magnetic field, which means that a force is applied to the rotating body RT, and the rotating body RT is rotated by this force. Thus, it can be seen that in the three-phase induction motor MT, the rotating body RT can be rotated by using three-phase alternating current. That is, in the three-phase induction motor MT, three-phase alternating current is required. Therefore, in the motor circuit, the three-phase alternating current is supplied to the three-phase induction motor by using the inverter circuit INV which produces alternating current from the direct current.

[0014] Hereinafter, a configuration example of the inverter circuit INV will be described.

[0015] As shown in FIG. 1, for example, in the inverter circuit INV, a switching element Q1 and a diode FWD are provided corresponding to three phases. That is, in the inverter circuit INV, for example, the constitutional requirements of the inverter circuit INV are realized by the configuration in which the switching element Q1 and the diode FWD are connected in antiparallel as shown in FIG. 1 . For example, in Figure 1, the upper arm and lower arm of the first pin LG1, the upper arm and lower arm of the second pin LG2, and the upper arm and lower arm of the third pin LG3 are respectively composed of switching elements Q1 and Diode FWD anti-parallel connection constitutes the constituent elements.

[0016] In other words, in the inverter circuit INV, the switching element Q1 and the diode FWD are connected in antiparallel between the positive potential terminal PT and each phase (U phase, V phase, W phase) of the three-phase induction motor MT, and , Between each phase of the three-phase induction motor MT and the negative potential terminal NT, the switching element Q1 and the diode FWD are also connected in antiparallel. That is, two switching elements Q1 and two diodes FWD are provided in each single phase, and six switching elements Q1 and six diodes FWD are provided in three phases. In addition, a gate control circuit GCC is connected to the gate of each switching element Q1, and the switching operation of the switching element Q1 is controlled through the gate control circuit GCC. In the inverter circuit INV configured in this way, by controlling the switching operation of the switching element Q1 by the gate control circuit GCC, the DC power is converted into the three-phase AC power, and the three-phase AC power is supplied to the three-phase AC power. Induction motor MT.

[0017] <Type of Switching Element> For example, as the switching element Q1 used in the inverter circuit INV, a power MOSFET and an IGBT (Insulated Gate Bipolar Transistor) can be mentioned.

[0018] <Necessity of Diodes> As mentioned above, the switching element Q1 is used in the inverter circuit INV, and when an IGBT is used as the switching element Q1, a diode FWD antiparallel to the IGBT must be provided.

[0019] From the point of view of realizing the switching function through the switching element Q1, it is considered that the IGBT as the switching element Q1 is needed, but the diode FWD does not need to be provided. Regarding this point, for example, when the load connected to the inverter circuit INV includes an inductance as in the case of a motor, it is necessary to provide a diode FWD. The reason for this will be described below.

[0020] When the load is a pure impedance that does not include inductance, there is no need for a diode FWD because there is no energy for backflow. However, when the load is connected to a circuit containing inductance such as a motor, there is a mode in which the load current flows in the opposite direction of the open switch. That is, when an inductance is included in the load, energy may return to the inverter circuit INV from the inductance of the load (current reverse flow).

[0021] At this time, the IGBT monomer does not have the function of circulating the reflux current, so the diode FWD must be connected in antiparallel to the IGBT. That is, in the inverter circuit INV, when an inductance is included in the load such as motor control, when the IGBT is turned off, the energy (1 / 2LI2) stored in the inductance must be released. However, the reflux current used to discharge the energy accumulated in the inductor cannot be circulated by a single IGBT. Therefore, in order to return the electric energy accumulated in this inductor, the diode FWD and the IGBT are connected in antiparallel. That is, the diode FWD has a function of passing a return current to discharge the electric energy accumulated in the inductor. From the above, it can be seen that when an IGBT is used as the switching element Q1 in an inverter circuit connected to a load including an inductance, the diode FWD must be arranged in antiparallel with the IGBT. This diode FWD is called a flywheel diode.

[0022] In contrast, when using a power MOSFET as the switching element Q1, in principle, it is not necessary to provide a flywheel diode antiparallel to the power MOSFET. The reason for this is that in the device structure of the power MOSFET, a pn junction diode, that is, a body diode is inevitably formed parasitically, and as a result, the body diode functions as a flywheel diode.

[0023] However, when using a power MOSFET as the switching element Q1, there is still a case where a Schottky diode with a forward voltage drop smaller than a pn junction diode is used as the flywheel diode.

[0024] The technical idea of ​​this embodiment can be applied to the configuration using either IGBT or power MOSFET as the switching element Q1, but in the following description, the case where the switching element Q1 is constituted by a power MOSFET is taken as an example. Moreover, the presence or absence of the flywheel diode is not directly related to the technical idea of ​​this embodiment, so the technical idea of ​​this embodiment will be explained below for the sake of brevity without the flywheel diode.

[0025] <Example of Implementation Layout of Inverter Circuit> Fig. 2 is a schematic diagram showing an example of implementation layout of an inverter circuit.

[0026] In FIG. 2, the power line VL, the lines WL1 to WL3, and the ground line GL are formed on the motherboard. A power supply potential is supplied to the power supply wiring VL, while a ground potential is supplied to the ground wiring GL. Moreover, the wiring WL1 is connected to the U phase of the three-phase induction motor, the wiring WL2 is connected to the V phase of the three-phase induction motor, and the wiring WL3 is connected to the W phase of the three-phase induction motor.

[0027] As shown in FIG. 2, the semiconductor device SA1 is connected between the power supply wiring VL and the wiring WL1, and on the other hand, the semiconductor device SA2 is connected between the wiring WL1 and the ground wiring GL. That is, the semiconductor device SA1 and the semiconductor device SA2 are connected in series between the power line VL and the ground line GL, and constitute the first pin LG1 of the inverter circuit INV shown in FIG. 1 . That is, the semiconductor device SA1 constitutes the upper arm of the first pin LG1 , and at the same time, the semiconductor device SA2 constitutes the lower arm of the first pin LG1 . Furthermore, the semiconductor device SA1 and the semiconductor device SA2 each have a semiconductor chip on which a power MOSFET functioning as the switching element Q1 is formed.

[0028] Similarly, the semiconductor device SA3 is connected between the power line VL and the line WL2, and the semiconductor device SA4 is connected between the line WL2 and the ground line GL. That is, the semiconductor device SA3 and the semiconductor device SA4 are connected in series between the power line VL and the ground line GL, and constitute the second pin LG2 of the inverter circuit INV shown in FIG. 1 . That is, the semiconductor device SA3 constitutes the upper arm of the second pin LG2, and the semiconductor device SA4 constitutes the lower arm of the second pin LG2. Furthermore, each of the semiconductor device SA3 and the semiconductor device SA4 has a semiconductor chip on which a power MOSFET functioning as the switching element Q1 is formed.

[0029] Further, the semiconductor device SA5 is connected between the power line VL and the line WL3, and the semiconductor device SA6 is connected between the line WL3 and the ground line GL. That is, the semiconductor device SA5 and the semiconductor device SA6 are connected in series between the power line VL and the ground line GL, and constitute the third pin LG3 of the inverter circuit INV shown in FIG. 1 . That is, the semiconductor device SA5 constitutes the upper arm of the third pin LG3, and at the same time, the semiconductor device SA6 constitutes the lower arm of the third pin LG3. Furthermore, each of the semiconductor device SA5 and the semiconductor device SA6 has a semiconductor chip on which a power MOSFET functioning as the switching element Q1 is formed.

[0030] As above. By arranging six semiconductor devices SA1 to SA6 in the manner shown in FIG. 2 on the motherboard on which the power supply wiring VL1, the wiring WL1 to the wiring WL3, and the ground wiring GL are formed, the corresponding inverter is realized. The actual layout of the circuit.

[0031] <Benefits of "TO Package"> In this embodiment, for example, as shown in FIG. Transistor shape) package". Here, the "TO package" is defined as a package structure in which a plurality of leads are arranged only on the first side of the semiconductor device in plan view. In this regard, "TO package" and "SON (Small Outline Non-Leaded, Small Outline Non-Leaded)" in which a plurality of pins are arranged not only on the first side of the semiconductor device but also on the second side opposite to the first side in plan view It is different from "SOP (Small Outline Package) package" and "SOP (Small Outline Package, small outline package) package", and it is also different from "QFN (Quad Flat Non-leaded) that arranges multiple pins on all four sides of the semiconductor device. , Quad Flat Package” and “QFP (Quad Flat Package, Quad Flat Package) Package” are different. Through the "TO package" adopted in this embodiment, for example, as shown in FIG. 2, a plurality of pins are arranged only on the first side of the semiconductor device SA, so compared with the above-mentioned other packages, it can be used in The advantage of easier layout when wiring on the motherboard. That is, by adopting "TO package", the actual layout corresponding to the inverter circuit can be realized through a simplified layout (refer to FIG. 2 ).

[0032] The inventor of this case is based on the premise that the semiconductor device SA is constituted by the "TO package" with the above benefits, and discusses from the viewpoint of reducing the on-resistance of the semiconductor device SA. From the viewpoint of on-resistance, there is still room for improvement as shown below, and this point will be described below.

[0033] <Room for Improvement> FIG. 3 is a diagram schematically showing the internal structure of the semiconductor device SA.

[0034] In FIG. 3, for example, a die pad DP is arranged inside the sealing body MR made of resin. A semiconductor chip CHP is mounted on this wafer pad DP. Power MOSFETs are formed on this semiconductor wafer CHP. A gate terminal GT electrically connected to the gate of the power MOSFET, a Kelvin terminal KT and a source terminal ST electrically connected to the source region of the power MOSFET are formed on the surface of the semiconductor chip CHP. On the other hand, although not shown in FIG. 3 , the drain of the power MOSFET is formed on the back surface of the semiconductor chip CHP, and the drain is electrically connected to the chip pad DP.

[0035] Next, a plurality of leads are arranged on the side S1 of the sealing body MR so as to protrude from the sealing body MR. Specifically, the plurality of pins include a pin GL for a gate terminal, a pin KL for a Kerven terminal, and a pin SL for a source terminal.

[0036] The gate terminal pin GL is electrically connected to the gate terminal GT via the wire W1 which is a connecting member for the gate terminal. Moreover, the lead KL for Kerven terminals is electrically connected to the Kerven terminal KT via the wire W2 which is the connecting member for Kerven terminals. Furthermore, the lead SL for a source terminal is electrically connected to the source terminal ST by the several wire W3 which is the connection member for source terminals.

[0037] In this way, the semiconductor device SA of the "TO package" is constituted.

[0038] Here, as shown in FIG. 3, in the semiconductor device SA, the pin KL for the Kerven terminal is arranged next to the pin GL for the gate terminal. As a result, since the relative positions of the source terminal ST and the source terminal pin SL are shifted, the wire W3 connecting the source terminal ST and the source terminal pin SL is bent. That is, in the semiconductor device SA, the source terminal ST and the pin SL for source terminals are connected using the bent wire W3. If such a curved wire W3 is used, the source terminal ST and the source terminal pin SL cannot be connected with the shortest distance, and the impedance value of the wire W3 increases.

[0039] Regarding this point, the inventor of the present case discussed a large current of about 300A flowing through the semiconductor device SA, and found that in this case, the increase in the impedance value caused by the bent wire W3 will cause a non-negligible effect in seeking to reduce the on-resistance. affect. In particular, the bent wire W3 connects the source terminal ST through which a large current flows and the source terminal pin SL, and a large current flows through the bent wire W3 itself. As a result, a slight increase in impedance caused by bending will still cause a large voltage drop and Joule heat generation. Therefore, if the bent wire W3 is used in a semiconductor device SA that flows a large current, it will cause a problem that cannot be ignored. The main reason for the performance degradation. Thus, in the "TO package" semiconductor device SA, there is still room for improvement from the viewpoint of performance improvement typified by reduction in on-resistance.

[0040] Therefore, the inventors of the present case have discussed in detail why the curved wire W3 must be used in the "TO package" semiconductor device SA, and will explain this point below.

[0041] As shown in Fig. 3, we think that the reason why the bent wire W3 must be used is mainly that the pin KL for the Kelvin terminal is arranged next to the pin GL for the gate terminal, and the pin KL for the source terminal is placed next to the pin GL for the source terminal. SL cannot be arranged in the center of side S1 corresponding to the arrangement position of source terminal ST. Regarding this point, before explaining why it is necessary to arrange the pin KL for the Kerven terminal next to the pin GL for the gate terminal, first, the technical significance of providing the pin KL for the Kerven terminal will be explained.

[0042] [Technical Significance of Setting Pins for Kerven Terminals] FIG. 4 is a circuit diagram schematically showing the connection configuration of the power MOSFET 100 when the pins KL for Kerven terminals are not provided. As shown in FIG. 4 , the power MOSFET 100 is provided between the die pad DP and the source terminal pin SL, and the "impedance R" represents, for example, package impedance including the impedance value caused by the wire W3. In addition, the gate of the power MOSFET 100 is electrically connected to the gate terminal through the pin GL.

[0043] Here, the voltage V1 between the source terminal pin SL and the gate terminal pin GL is input to the gate control circuit GCC shown in FIG. 1, for example. Furthermore, the gate control circuit GCC controls the switching operation of the power MOSFET 100 based on the input voltage V1. At this time, in order to stably control the power MOSFET 100 by the gate control circuit GCC, the voltage V1 is required to be equal to the voltage VGS shown in FIG. 4 .

[0044] However, in the connection configuration shown in FIG. 4, a large drain current ID flows between the die pad DP and the source terminal pin SL. Therefore, a large voltage drop is also generated in the package impedance ("impedance R") due to the flow of a large current. This means that the voltage V1 and the voltage VGS have a large difference in value. Therefore, in the connection configuration of the power MOSFET 100 shown in FIG. 4 , the control of the power MOSFET 100 by the gate control circuit GCC may be unstable.

[0045] On the other hand, FIG. 5 is a circuit diagram schematically showing the connection configuration of the power MOSFET 100 when the Kerven terminal pin KL is provided. In the connection configuration shown in FIG. 5, in addition to the source terminal pin SL connected to the power supply (source terminal) of the power MOSFET 100, there is also a Kerven terminal connected to the power supply (Kervin terminal) of the power MOSFET 100. with pin KL. As a result, as shown in FIG. 5, even if a large drain current ID flows between the die pad DP and the source terminal pin SL, the drain current ID does not flow to the Kerven terminal pin. KL. This means that the voltage V1 between the pin KL for the Kelvin terminal and the pin GL for the gate terminal is not affected by the voltage drop caused by the flow of the drain current ID to the package impedance ("impedance R"). Accordingly, the voltage V1 between the KL terminal pin KL and the gate terminal pin GL is substantially equal to the voltage VGS.

[0046] Therefore, with the connection configuration of the power MOSFET 100 shown in FIG. 5 , the control of the power MOSFET 100 by the gate control circuit GCC can be stabilized. In other words, it can be said that the pin KL for the Kerven terminal has "the voltage V1 having a value almost equal to the voltage VGS is input to the gate control circuit GCC without being affected by the voltage drop caused by the drain current ID, The technical significance of stabilizing the control of the power MOSFET 100 by the gate control circuit GCC.

[0047] [The reason for disposing the pins for Kerven terminals next to the pins for gate terminals] Considering the above-mentioned technical significance of setting the pins for Kerven terminals KL, in order to make the pins for gate terminals GL and the pins for gate terminals The voltage V1 between the Kerven terminal pins KL is almost equal to the voltage VGS, and it is desirable that the parasitic impedance between the gate terminal pin GL and the Kerven terminal pin KL be small. For this reason, the pin KL for the Kelvin terminal is arranged next to the pin GL for the gate terminal. Furthermore, in the "TO package", the lead wire W3 connecting the source terminal ST and the source terminal pin SL is bent as a result of arranging the KL terminal pin KL next to the gate terminal pin GL.

[0048] Regarding this point, in the above-mentioned packages other than the "TO package", there are other sides besides the first side where plural pins are arranged. Next to the pin GL, it is also possible to arrange the adjacent pin GL for the gate terminal and the pin KL for the Kelvin terminal on the second side different from the first side, and arrange the source terminal on the first side The pin SL for the source terminal can be easily realized without bending the pin SL for the source terminal. However, in the above-mentioned packages other than the "TO package", the wiring layout on the mother board is relatively complicated.

[0049] On the other hand, in the "TO package", the side where a plurality of pins are arranged is limited to the side S1, so that the advantage of easier wiring arrangement on the motherboard is obtained. On the other hand, in the "TO package", since the side on which multiple pins are arranged is limited to side S1, if the pin KL for the Kelvin terminal is placed next to the pin GL for the gate terminal, the source terminal cannot be placed The pin SL is arranged in the center of the side S1 corresponding to the arrangement position of the source terminal ST. Therefore, the Kerven terminal pin KL becomes an obstacle, and it is difficult to connect the source terminal ST and the source terminal pin SL with the wire W3 at the shortest distance, and the wire W3 must be bent. In other words, the room for improvement of the bending of the wire W3 is the room for improvement that appears in the "TO package" including the lead KL for Kerven terminals.

[0050] Therefore, in the present embodiment, there is room for improvement to overcome the bending of the wire W3 that appears in the "TO package" including the Kerven terminal pin KL. Hereinafter, the technical idea of ​​this embodiment will be described.

[0051] <Package Structure of Semiconductor Device> FIG. 6 is a schematic diagram showing the package structure of the semiconductor device 10 according to this embodiment.

[0052] In FIG. 6, the semiconductor device 10 is a "TO package" and has, for example, a die pad DP arranged inside a sealing body MR made of resin. And, the semiconductor chip CHP is mounted on the wafer pad DP. Power MOSFETs are formed on the semiconductor wafer CHP. On the surface of the semiconductor chip CHP, form the gate terminal GT electrically connected to the gate of the power MOSFET, the source terminal ST electrically connected to the source region of the power MOSFET, and electrically connected to the source region of the power MOSFET The Kerven terminal KT. At this time, as shown in FIG. 6 , the source terminal ST includes a portion located between the gate terminal GT and the Kelvin terminal KT in plan view. On the other hand, although not shown in FIG. 6 , a drain is formed on the back surface of the semiconductor chip CHP, and the drain is electrically connected to the wafer pad DP.

[0053] The source terminal ST is a "current terminal" used to flow current, and the Kervin terminal KT is a "detection terminal" used to detect voltage.

[0054] Next, as shown in FIG. 6, a plurality of leads protruding from the sealing body MR are arranged on the side S1 of the sealing body MR. In other words, a plurality of leads are arranged along the first side of the semiconductor wafer parallel to the side S1 of the sealing body MR. Specifically, the plurality of pins include a pin GL for a gate terminal, a pin KL for a Kerven terminal, and a pin SL for a source terminal. The lead GL for a gate terminal is electrically connected to the gate terminal GT via the wire (bonding wire) W1 which is a connecting member for a gate terminal. Moreover, the lead KL for Kerven terminals is electrically connected to the Kerven terminal KT via the wire (bonding wire) W2 which is the connection member for Kerven terminals. Furthermore, the source terminal lead SL is electrically connected to the source terminal ST by a plurality of wires (bonding wires) W3 which are connection members for a source terminal. In addition, in this embodiment, the wire W1, the wire W2, and the wire W3 are each made of, for example, gold (Au), but wires made of copper (Cu) may also be used.

[0055] Here, in this embodiment, as shown in FIG. 6, the pin GL for the gate terminal is not adjacent to the pin KL for the Kelvin terminal, and the pin GL for the gate terminal is connected to the pin KL for the Kelvin terminal. A plurality of pins SL for source terminals are arranged between pins KL for earphone terminals.

[0056] In addition, the plurality of wires W3 electrically connecting the source terminal ST to the source terminal pin SL are respectively extended from the y direction (the second direction) perpendicular to the x direction (the first direction) extending from the side S1. Direction) extended straight line shape. In other words, the plurality of wires W3 each have a straight shape extending only in the y direction perpendicular to the x direction.

[0057] Also, as shown in FIG. 6, plural wires W3 are connected to source terminals ST at plural positions. For example, each wire W3 is connected to the source terminal ST at the junction point P1 and the junction point P2. That is, the number of junctions between the wire W1 and the gate terminal GT is one, and the number of junctions between the wire W2 and the Kerven terminal KT is one. In contrast, each wire W3 and the source terminal ST The number of joints is 2. That is, by increasing the number of bonding positions between the source terminal ST and the plurality of wires W3, the on-resistance on the current path between the source terminal ST and the source terminal pin SL can be reduced. In addition, as shown in FIG. 6, not only the source terminal ST and the source terminal pin SL are electrically connected to each other through a plurality of wires W3, but also the wires W3 and the source terminal ST are joined at plural positions, thereby enabling A large current (300A) flows between the source terminal ST and the source terminal pin SL. In addition, in this embodiment, as shown in FIG. 6 , the case where the number of junction points between each wire W3 and the source terminal ST is two is described, but there may be more than two.

[0058] On the other hand, each wire W3 is connected to the source terminal pin SL at a junction point P3. That is, the number of junction points between each lead wire W3 and the pin SL for source terminals is one. The reason for this is that, as shown in FIG. 6 , the area of ​​the source terminal lead SL (in particular, the length of the source terminal lead SL in the y direction along which the wire W3 extends) is smaller than the area of ​​the source terminal ST (in particular, Refers to the length of the source terminal ST in the y direction extending along the wire W3) is small (short).

[0059] In this way, the semiconductor device 10 of the "TO package" is configured such that a current of, for example, 300A can flow.

[0060] <Device Structure of Power MOSFET> Next, the device structure of the power MOSFET formed on the semiconductor wafer CHP will be described. FIG. 7 is a cross-sectional view showing an important point of a semiconductor chip CHP of an n-channel trench gate power MOSFET, which is an example of a power MOSFET.

[0061] In FIG. 7, an epitaxial layer 21 made of n-type single-crystal silicon is formed on the surface of a semiconductor substrate 20 made of n+-type single-crystal silicon. The semiconductor substrate 20 and the epitaxial layer 21 constitute the drain of the power MOSFET.

[0062] A p-type well 22 is formed in a part of the epitaxial layer 21. Also, a silicon oxide film 23 is formed on a part of the surface of the epitaxial layer 21, and a plurality of grooves 24 are formed on the other part. Among the surfaces of the epitaxial layer 21, the region covered with the silicon oxide film 23 constitutes the device isolation region, while the region where the groove 24 is formed constitutes the device formation region (active region). Although not shown, the planar shape of the groove 24 is a polygon such as a quadrangle, a hexagon, or an octagon, or a stripe shape extending in one direction.

[0063] The silicon oxide film 25 constituting the gate insulating film of the power MOSFET is formed on the bottom and side walls of the trench 24. Also, a polysilicon film 26A constituting the lower gate of the power MOSFET is embedded in the trench 24 . On the other hand, a gate extraction electrode 26B composed of a polysilicon film deposited in the same step as the polysilicon film 26A is formed on the top of the silicon oxide film 23 . The lower gate (polysilicon film 26A) is electrically connected to the gate extraction electrode 26B in a region not shown.

[0064] A p-type semiconductor region 27 shallower than the trench 24 is formed in the epitaxial layer 21 of the device formation region. This p-type semiconductor region 27 is called a body region, and is a region where a channel region (inversion layer) of a power MOSFET is formed. A p-type semiconductor region 28 having an impurity concentration higher than that of the p-type semiconductor region 27 is formed on top of the p-type semiconductor region 27 , and an n+ type semiconductor region 29 is formed on top of the p-type semiconductor region 28 . The p-type semiconductor region 28 constitutes the anti-penetration layer of the power MOSFET, and on the other hand, the n+ type semiconductor region 29 constitutes the source region of the power MOSFET.

[0065] A silicon oxide film 30 and a silicon oxide film 31 of two layers are formed on the top of the device formation region where the power MOSFET is formed and the device isolation region where the gate extraction electrode 26B is formed. A connection hole 32 penetrating through the silicon oxide film 30, the silicon oxide film 31, the p-type semiconductor region 28, and the n+-type semiconductor region 29 to reach the p-type semiconductor region 27 is formed in the element formation region. A connection hole 33 penetrating through the silicon oxide film 30 and the silicon oxide film 31 to reach the gate extraction electrode 26B is formed in the device isolation region.

[0066] On the top of the silicon oxide film 31 including the connection hole 32 and the connection hole 33, for example, a laminated film of a thinner titanium-tungsten film (TiW film) and a thicker aluminum film (Al film) is formed. A source 40 and a gate 41 are formed. The source 40 formed in the device forming region is electrically connected to the source region of the power MOSFET through the connection hole 32 . At the bottom of the connection hole 32, a p+-type semiconductor region 35 for making ohmic contact between the source terminal ST and the p-type semiconductor region 27 is formed. In addition, the gate 41 formed in the device isolation region is connected to the lower gate of the power MOSFET (polysilicon film 26A) through the gate extraction electrode 26B at the bottom of the connection hole 33 .

[0067] On top of the source electrode 40 and the gate electrode 41, a surface protection film 42 composed of a laminated film of a silicon oxide film and a silicon nitride film is formed. And, the source electrode 40 is exposed by removing a part of the surface protection film 42 to form the source terminal ST, and the gate electrode 41 is exposed by removing the other part of the surface protection film to form Gate terminal GT. Moreover, although not shown in FIG. 7, Kerven terminals are also formed.

[0068] As described above, the gate terminal GT, the Kervin terminal (KT), and the source terminal ST are formed on the main surface of the semiconductor wafer CHP.

[0069] <Features of Embodiment> Next, the characteristic points of this embodiment will be described.

[0070] The characteristic point of this embodiment is that, for example, as shown in FIG. 6, in plan view, the pin for source terminal is arranged between the pin GL for gate terminal and the pin KL for Kerven terminal. SL. Thus, the source terminal pin SL can be arranged at the center of the side S1 corresponding to the arrangement position of the source terminal ST, so that the wire W3 connecting the source terminal ST and the source terminal pin SL can be suppressed from being bent. . That is, through the feature of this embodiment, the wire W3 connecting the source terminal ST and the source terminal pin SL can be formed into a straight line extending in the y direction perpendicular to the x direction in which the side S1 extends. pose. In other words, through the characteristic point of this embodiment, the plurality of wires W3 can each be formed of a straight shape extending only in the y direction perpendicular to the x direction.

[0071] As a result, through this embodiment, the plurality of wires W3 that flow a large current of about 300A will not be bent, and the increase in the on-resistance and the increase in parasitic inductance represented by the bending of the wire W3 can be suppressed. A performance degradation that cannot be ignored. That is, according to this embodiment, the source terminal ST and the source terminal pin SL can be connected by the wire W3 of the shortest length, and performance improvement of the semiconductor device 10 can be sought.

[0072] Here, as explained in the item "[Reasons for disposing the pins for Kerven terminals next to the pins for gate terminals]", in order to make the pins GL for gate terminals and the pins for Kerven terminals The voltage V1 between the terminal pins KL is almost equal to the voltage VGS, and it is desirable that the parasitic impedance between the gate terminal pin GL and the Kerven terminal pin KL be small. For this reason, a configuration is adopted in which the pin KL for the Kelvin terminal is arranged next to the pin GL for the gate terminal.

[0073] Regarding this point, the circuit that detects the voltage V1 through the pin GL for the gate terminal and the pin KL for the Kervin terminal is not a circuit for flowing current but a detection circuit for detecting voltage. The inventor of the present invention thinks that this means that even if a little impedance is applied to the detection circuit, since no large current flows, the influence of the voltage drop on the detection of the voltage V1 is less. That is, the inventors of the present invention came to the judgment that "even if the distance between the gate terminal pin GL and the Kelvin terminal pin KL is relatively long, it has little influence on the detection of the voltage V1". In contrast, the inventors of the present case believe that in the semiconductor device 10 used to flow a large current of about 300A, the increase in on-resistance and parasitic inductance caused by the bending of the wire W3 that flows a large current will cause a decrease in the performance of the semiconductor device 10. greater impact.

[0074] Considering the above content, the inventor of the present case adopts the method of "disposing the pin SL for the source terminal between the pin GL for the gate terminal and the pin KL for the Kerven terminal" in this embodiment. The structure of the feature point replaces the structure in which the pin GL for the gate terminal and the pin KL for the Kerven terminal are arranged adjacent to each other. As a result, through this embodiment, it is possible to suppress performance degradation that cannot be ignored, represented by an increase in on-resistance and an increase in parasitic inductance caused by bending of the wire W3, thereby achieving improvement in the performance of the semiconductor device 10. the remarkable effect.

[0075] [Conceptualization of Upper Terminals] In this embodiment, a power MOSFET is used as an example for the description as the switching element Q1 formed on the semiconductor chip CHP. In this case, the gate terminal GT, the Kerven terminal KT, and the source terminal ST are formed on the surface of the semiconductor wafer CHP.

[0076] However, the technical idea of ​​this embodiment is not limited to the aspect in which the switching element Q1 is constituted by a power MOSFET, and can also be applied to the embodiment in which the switching element Q1 is constituted by an IGBT. In this case, the gate terminal GT, the Kelvin terminal KT, and the emitter terminal are formed on the surface of the semiconductor wafer CHP.

[0077] Moreover, the Kerven terminal KT is a terminal for detecting voltage, and the terminal for detecting voltage is called a "detection terminal", so the Kervin terminal KT is one of the "detection terminals". In addition, the source terminal ST and the emitter terminal are terminals for passing current, and the terminals for passing current are called "current terminals", so the source terminal ST and the emitter terminal are one form of "current terminals".

[0078] Furthermore, in consideration of the description in the modified example described later, the wires (joint wires) W1 to W3 can also be replaced with "ribbon" or "clip", "wire", "Band body" and "clip" are one form of connecting components.

[0079] Based on the above content, the terminology is conceptualized as follows: (1) Gate terminal GT (2) Kerven terminal KT → "detection terminal" (3) source terminal ST and emitter terminal → "current terminal" (4) Pin GL for gate terminal (5) Pin KL for Kerven terminal → "pin for detection terminal" (6) Pin SL for source terminal (pin for emitter terminal) → "current Terminal pins" (7) Lead wire W1→"Connecting member for gate terminal" (8) Lead wire W2→"Connecting member for detection terminal" (9) Lead wire W3 (band body, clip)→"Connecting member for current terminal "

[0080] Considering such a high-level conceptualization of terms, the characteristic point of this embodiment is that "in a plan view, the "current terminal pin" is arranged between the gate terminal pin GL and the "detection terminal pin" ". In this way, the "current terminal pin" can be arranged in the center of the side corresponding to the arrangement position of the "current terminal", so the "current terminal pin" that connects the "current terminal" and the "current terminal pin" can be suppressed. Bending of connecting member". That is, with the feature of this embodiment, the "connecting member for current terminal" that connects the "current terminal" and the "pin for current terminal" can be configured in a linear shape. In other words, through the characteristic point of this embodiment, the "connecting member for current terminal" can be configured in a straight shape.

[0081] <Modification 1> FIG. 8 is a diagram showing a schematic configuration of a semiconductor device 10A according to the first modification.

[0082] As shown in FIG. 8, in the semiconductor device 10A of Modification 1, for the semiconductor device 10 shown in FIG. swap. Accordingly, in the semiconductor device 10A, the positions of the gate terminal pin GL connected to the gate terminal GT via the wire W1 and the Kerven terminal pin KL connected to the Kerven terminal KT via the wire W2 are also reversed.

[0083] As above, if the characteristic point of this embodiment of "arranging the pin SL for the source terminal between the pin GL for the gate terminal and the pin KL for the Kelvin terminal in a plan view" is adopted, it can be Realize the symmetry of the pin GL for the gate terminal and the pin KL for the Kelvin terminal. As a result, if the features of this embodiment are adopted, not only the configuration of the semiconductor device 10 shown in FIG. 6 but also the configuration of the semiconductor device 10A shown in FIG. 8 can be realized. Therefore, the technical idea of ​​this embodiment is also useful at the point of being able to increase the variation of the implementation layout.

[0084] <Modification 2> FIG. 9 is a diagram showing a schematic configuration of a semiconductor device 10B according to the second modification.

[0085] In FIG. 9, if the characteristic point of this embodiment is adopted, the source terminal pin SL can be arranged in the center of the side S1 corresponding to the arrangement position of the source terminal ST. Therefore, instead of the wire W3 shown in FIG. 6 , a strip RBN made of aluminum (Al) may be used as the source terminal connection member connecting the source terminal ST and the source terminal pin SL.

[0086] In this case, as shown in FIG. 9, the ribbon body RBN is joined to the source terminal ST at plural positions. For example, the ribbon body RBN is connected to the source terminal ST at the junction point P4 and the junction point P5. That is, the number of junctions between the wire W1 and the gate terminal GT is one, and the number of junctions between the wire W2 and the Kelvin terminal KT is one. In contrast, the junction between the body RBN and the source terminal ST The number of points is 2. That is, similar to the above-mentioned embodiment, by increasing the joint position between the source terminal ST and the ribbon body RBN, the on-resistance on the current path between the source terminal ST and the source terminal pin SL can be reduced. Here, the width of the tape body RBN used in Modification 2 is wider than the widths of the wires W1 to W3 used in the above-mentioned embodiment. In addition, as shown in FIG. 9 , not only the source terminal ST and the source terminal pin SL are electrically connected to each other through one strip RBN, but also by joining the strip RBN and the source terminal ST at plural positions, On the other hand, a large current (300 A) flows between the source terminal ST and the source terminal pin SL. In addition, in the present modification 2, as shown in FIG. 9 , the case where the number of junction points between the ribbon body RBN and the source terminal ST is two is described, but it may be two or more. In addition, the strip body RBN is connected to the source terminal pin SL at a junction point P6. That is, the number of junctions between the body RBN and the source terminal pin SL is one.

[0087] <Modification 3> FIG. 10 is a diagram showing a schematic configuration of a semiconductor device 10C according to Modification 3. In FIG.

[0088] In FIG. 10, if the feature of this embodiment is adopted, the pin SL for the source terminal can be arranged in the center of the side S1 corresponding to the arrangement position of the source terminal ST. Therefore, as the connecting member for the source terminal connecting the source terminal ST and the pin SL for the source terminal, instead of using the strip RBN shown in FIG. 9 , the strip RBN1 and the strip RBN1 shown in FIG. RBN2 replaces the wire W3 shown in FIG. 6 .

[0089] <Modification 4> FIG. 11 is a diagram showing a schematic configuration of a semiconductor device 10D according to the fourth modification.

[0090] In FIG. 11, if the characteristic point of this embodiment is adopted, the pin SL for the source terminal can be arranged at the center of the side S1 corresponding to the arrangement position of the source terminal ST. Therefore, instead of the wire W3 shown in FIG. 6 , the wide wire W4 shown in FIG. 11 may be used as the source terminal connection member connecting the source terminal ST and the source terminal pin SL.

[0091] <Modification 5> FIG. 12 is a diagram showing a schematic configuration of a semiconductor device 10E according to the fifth modification.

[0092] In FIG. 12, if the characteristic point of this embodiment is adopted, the pin SL for the source terminal can be arranged at the center of the side S1 corresponding to the arrangement position of the source terminal ST. Therefore, instead of the wire W3 shown in FIG. 6 , the clip CLP shown in FIG. 12 may be used as the source terminal connection member connecting the source terminal ST and the source terminal pin SL.

[0093] In this case, as shown in FIG. 12, the clip CLP is joined to the source terminal ST at one point. For example, the clip CLP is connected to the source terminal ST at a junction point P7. That is, the number of junction points between the wire W1 and the gate terminal GT is one, and the number of junction points between the wire W2 and the Kelvin terminal KT is one, and the number of junction points between the wire W1 and the source terminal ST is one. The quantity is also one. Here, the width of the clip CLP used in Modification 5 is wider than the widths of the wires W1 to W3 used in the above-mentioned embodiment. In addition, the thickness of the clip CLP used in the modification 5 is thicker than that of the belt body RBN used in the modification 2 above. Therefore, unlike the above-mentioned embodiment and the above-mentioned modified example 2, even if the junction position between the source terminal ST and the clip CLP is not increased, the clip CLP having the above-mentioned width and thickness and formed of copper (Cu) can be used to reduce the On-resistance on the current path between the source terminal ST and the source terminal pin SL. Also, the clip CLP and the source terminal are connected at a junction point P8 by a pin SL. That is, the number of joints between the clip CLP and the source terminal pin SL is one.

[0094] <Other benefits of the embodiment> For example, in the "TO package" in which the pin GL for the gate terminal and the pin KL for the Kelvin terminal are arranged adjacent to each other, the source terminal ST is not connected to the source terminal ST. As an example of the structure in which the lead wire W3 of the terminal lead SL is bent, a structure in which the lead wire W3 of a non-bent linear shape is arranged obliquely is also conceivable. This technology is referred to as a related technology, and the superiority of the technical idea of ​​this embodiment compared with the related technology is explained.

[0095] FIG. 13 is a diagram schematically showing the arrangement of the wire W3 for realizing the technical idea of ​​the present embodiment. In FIG. 13 , the wire W3 is formed of a straight line extending only in the y direction, and the wire angle θ representing the inclination of the wire W3 from the y direction is 0°. In this case, for example, the area of ​​the semiconductor chip required for arranging six wires W3 is represented by an occupied area 200A.

[0096] Next, FIG. 14 is a diagram schematically showing the arrangement of the wire W3 as an example of realizing the related art. In FIG. 14 , the wire W3 is composed of a straight line inclined from the y direction, and the wire angle θ representing the inclination of the wire W3 from the y direction is 12°. In this case, for example, the area of ​​the semiconductor chip required for arranging six wires W3 is represented by an occupied area 200B.

[0097] Next, FIG. 15 is a diagram schematically showing the arrangement of the wire W3 which realizes another example of the related art. In FIG. 15 , the wire W3 is composed of a straight line inclined from the y direction, and the wire angle θ representing the inclination of the wire W3 from the y direction is 45°. In this case, for example, the area of ​​the semiconductor chip required for arranging six wires W3 is represented by an occupied area 200C.

[0098] It can be seen from FIGS. 13 to 15 that the area of ​​the semiconductor chip required for disposing the six wires W3 is occupied area 200A<occupied area 200B<occupied area 200C. That is, when realizing the technical idea of ​​this embodiment and making the wire W3 a linear shape extending only in the y direction, it is possible to realize the related art by making the wire W3 a straight line inclined from the y direction. The occupied area of ​​the wire W3 in the semiconductor chip is reduced. This means that through this embodiment, when the number of wires W3 used is the same, the size of the semiconductor chip can be reduced compared with the related art. In this way, the technical idea of ​​this embodiment not only reduces the on-resistance, but is also advantageous in that the size of the semiconductor chip can be reduced.

[0099] Furthermore, other presentation methods are used to illustrate the superiority of the technical idea of ​​this embodiment compared to related technologies. FIG. 16 is a diagram schematically showing the configuration of the wiring W3 for realizing the technical idea of ​​the present embodiment when the occupied area of ​​the semiconductor chip is taken as an area of ​​200. As shown in FIG. 16, when using a wire W3 formed of a straight line extending only in the y direction, seven wires W3 can be arranged in the area 200.

[0100] On the other hand, FIG. 17 is a diagram schematically showing the configuration of the wiring W3 that implements the related technology when the occupied area of ​​the semiconductor chip is taken as an area of ​​200. As shown in FIG. 17 , when using the wire W3 formed of a linear shape inclined from the y direction, only six wires W3 can be arranged in the area 200 .

[0101] Thus, when the technical idea of ​​this embodiment is applied to the shape of the wire W3, the number of wires W3 that can be arranged in the same area 200 of the semiconductor wafer can be increased compared with the related art. This means that when using a semiconductor chip with the same size, compared with the related art, this embodiment can increase the number of wires W3 that can be arranged in the semiconductor chip, and as a result, can reduce the on-resistance. Therefore, from this point of view, the technical idea of ​​this embodiment is also preferable.

[0102] <Application Example> Next, an application example of the technical idea of ​​this embodiment will be described. Specifically, the layout of multiple pins described in this embodiment is not limited to semiconductor devices including power MOSFETs, but can also be applied to semiconductor devices including bidirectional thyristors. In other words, the contribution of the layout design of multiple pins to the commonality of semiconductor devices including power MOSFETs and semiconductor devices including bidirectional thyristors will be described.

[0103] Fig. 18 is a circuit diagram of a two-way thyristor. In addition, FIG. 19 is a diagram schematically showing the structure of a bidirectional thyristor.

[0104] A kind of so-called bidirectional thyristor system power semiconductor element, which is a semiconductor element that can control bidirectional current through a gate. In principle, as shown in FIG. 18 and FIG. 19 , the bidirectional thyristor can control the bidirectional current by connecting the thyristor 300A and the thyristor 300B that can control the current in one direction in antiparallel. Bidirectional thyristor can make current flow bidirectionally, so it is widely used in the control of AC power supply. As shown in Figure 18 and Figure 19, the bidirectional thyristor has three terminals of the main terminal MT1, the main terminal MT2 and the gate terminal GT. The flow of current may be reversed from the main terminal MT2 to the main terminal MT1. In addition, the main terminal MT1 is also called a 1st Yang electrode terminal, and the main terminal MT2 is also called a 2nd Yang electrode terminal.

[0105] FIG. 20 is a diagram schematically showing the structure of a semiconductor device 50A including a conventional bidirectional thyristor. As shown in FIG. 20 , a semiconductor chip CHP1 on which a bidirectional thyristor is formed is mounted on the wafer pad DP serving as the main terminal MT2 . And, the main terminal MT1 and the gate terminal GT are formed on the surface of the semiconductor chip CHP1. Moreover, the lead GL for gate terminals and the lead MTL for main terminals are arrange|positioned along one side of sealing body MR. Here, the gate terminal GT is electrically connected to the gate terminal pin GL by a wire W1 , and on the other hand, the main terminal MT1 is electrically connected to the main terminal pin MTL by a wire W5 . Here, as shown in FIG. 20 , plural wires W5 are joined to main terminal MT1 at plural positions, respectively. For example, each lead wire W5 is connected to the main terminal MT1 at the junction point P1 and the junction point P2. That is, the number of connection points between each wire W5 and the main terminal MT1 is two. On the other hand, each wire W5 is connected to the lead MTL for main terminals at a junction point P3. That is, the number of junction points of each lead wire W5 and the pin MTL for main terminals is one. In this way, the semiconductor device 50A is configured.

[0106] On the other hand, FIG. 21 is a diagram schematically showing the configuration of a semiconductor device 50B including a conventional power MOSFET. As shown in FIG. 21, the semiconductor chip CHP2 in which the power MOSFET was formed is mounted on the chip pad DP used as a drain. And, the source terminal ST and the gate terminal GT are formed on the surface of the semiconductor wafer CHP2. Moreover, the pin GL for gate terminals and the pin SL for source terminals are arrange|positioned along one side of sealing body MR. Here, the gate terminal GT and the gate terminal pin GL are electrically connected by a wire W1 , and on the other hand, the source terminal ST and the source terminal pin SL are electrically connected by a wire W3 . Here, as shown in FIG. 21 , plural wires W3 are joined to source terminals ST at plural positions, respectively. For example, each wire W3 is connected to the source terminal ST at the junction point P1 and the junction point P2. That is, the number of junctions between each wire W3 and the source terminal ST is two. On the other hand, each wire W3 is connected to the source terminal pin SL at a junction point P3. That is, the number of junction points between each lead wire W3 and the pin SL for source terminals is one. In this way, the semiconductor device 50B is constituted.

[0107] It can be seen from FIG. 20 and FIG. 21 that the configuration position of the gate terminal GT of the semiconductor chip CHP1 formed with a bidirectional thyristor is opposite to the configuration position of the gate terminal GT of the semiconductor chip CHP2 formed with a power MOSFET. As a result, the arrangement of the gate terminal leads GL and the main terminal leads MTL in the semiconductor device 50A is different from the arrangement of the gate terminal leads GL and the source terminal leads SL in the semiconductor device 50B. Therefore, in the conventional semiconductor device 50A and the semiconductor device 50B, it is difficult to commonize the layout of a plurality of pins. Regarding this point, if the design point of the layout of multiple pins in this embodiment is applied, the layout of multiple pins can be achieved in the semiconductor device 50A including a bidirectional thyristor and the semiconductor device 50B including a power MOSFET. of commonality. This point is explained below.

[0108] First, FIG. 6 shows a semiconductor device 10 to which the layout of a plurality of pins according to this embodiment is applied to a semiconductor device in which power MOSFETs are formed.

[0109] On the other hand, FIG. 22 shows a semiconductor device 60A in which the layout of a plurality of pins according to this embodiment is applied to a semiconductor device in which a bidirectional thyristor is formed.

[0110] Comparing both of FIG. 6 and FIG. 22, it can be seen that the semiconductor device 10 including a power MOSFET and the semiconductor device 60A including a bidirectional thyristor can be realized by applying the layout of multiple pins in this embodiment.

[0111] In particular, the multifunctional terminal pin FL shown in FIG. 22 is electrically connected to the main terminal MT1 through the wire W5A in the semiconductor device 60A including a bidirectional thyristor. On the other hand, this multifunctional terminal lead FL functions as a Kerven terminal lead KL connected to the Kerven terminal KT through the wire W2 in the semiconductor device 10 including the power MOSFET. Thereby, both the semiconductor device 10 including a power MOSFET and the semiconductor device 60A including a bidirectional thyristor are realized by applying the layout of a plurality of pins of this embodiment. That is, through this embodiment, in both the semiconductor device 10 including the power MOSFET and the semiconductor device 60A including the bidirectional thyristor, by properly using the pin FL for a multi-function terminal, multiple pins can be arranged. Common layout. Therefore, the technical idea of ​​this embodiment is also good in versatility in that it can commonize the arrangement and layout of a plurality of pins in semiconductor devices having different functions.

[0112] Also, as shown in FIG. 22, the lead wire W5A is joined to the main terminal MT1 at a plurality of positions. For example, the lead wire W5A is connected to the main terminal MT1 at the junction point P1 and the junction point P2. That is, the number of junction points of the lead wire W5A and the main terminal MT1 is two. On the other hand, the lead wire W5A is connected to the multi-function terminal pin FL at the junction point P3A. That is, the number of junction points of the lead wire W5A and the pin FL for multi-function terminals is one.

[0113] Also, as shown in FIG. 22, the lead wire W5B is joined to the main terminal MT1 at plural positions. For example, the lead wire W5B is connected to the main terminal MT1 at the junction point P1 and the junction point P2. That is, the number of junction points of the lead wire W5B and the main terminal MT1 is two. On the other hand, the lead wire W5B is connected to the main terminal pin MTL at a junction point P3B. That is, the number of junction points of the lead wire W5B and the lead MTL for main terminals is one.

[0114] Also, in FIG. 22, a semiconductor device 60A that is applicable to the layout of a plurality of pins in this embodiment is shown in a semiconductor device formed with a bidirectional thyristor, but it is not limited thereto. For example, it may also be The semiconductor device 60B is configured as shown in FIG. 23 . In this case, it is considered that the on-resistance can be reduced compared with the semiconductor device 60A because the wire W5B included in the semiconductor device 60B does not have a bent portion.

[0115] Above, the invention accomplished by the inventor of the present application has been specifically described based on the embodiment, but the present invention is not limited to the embodiment, and various changes can be made without departing from the gist thereof. [Simple description of the diagram]

[0010] FIG. 1 is a circuit diagram showing a circuit configuration including an inverter circuit and a three-phase induction motor. Fig. 2 is a schematic diagram showing an example of a practical layout for realizing an inverter circuit. FIG. 3 is a diagram schematically showing the internal structure of a semiconductor device. Fig. 4 is a circuit diagram schematically showing the connection configuration of power MOSFETs when no pins for Kerven terminals are provided. FIG. 5 is a circuit diagram schematically showing the connection configuration of the power MOSFET when the Kerven terminal pin is provided. FIG. 6 is a schematic diagram showing the package structure of the semiconductor device in the embodiment. FIG. 7 is a cross-sectional view showing an important point of a semiconductor wafer of an n-channel trench gate power MOSFET which is an example of a power MOSFET. FIG. 8 is a diagram showing a schematic configuration of a semiconductor device in Modification 1. FIG. FIG. 9 is a diagram showing a schematic configuration of a semiconductor device in Modification 2. FIG. FIG. 10 is a diagram showing a schematic configuration of a semiconductor device in Modification 3. FIG. FIG. 11 is a diagram showing a schematic configuration of a semiconductor device in Modification 4. FIG. FIG. 12 is a diagram showing a schematic configuration of a semiconductor device in Modification 5. FIG. Fig. 13 is a diagram schematically showing a wiring arrangement for realizing the technical idea of ​​the embodiment. Fig. 14 is a diagram schematically showing a wiring arrangement for realizing an example of the related art. FIG. 15 is a diagram schematically showing a wiring arrangement for realizing another example of the related art. FIG. 16 is a diagram schematically showing the configuration of wiring arrangement to realize the technical idea of ​​this embodiment when the occupied area of ​​the semiconductor chip is set to a predetermined area. Fig. 17 is a diagram schematically showing the configuration of a wiring arrangement for realizing the related art. Fig. 18 is a circuit diagram of a bidirectional thyristor. Fig. 19 is a diagram schematically showing the structure of a bidirectional thyristor. FIG. 20 is a diagram showing the structure of a semiconductor device including a conventional bidirectional thyristor. FIG. 21 is a diagram showing the configuration of a semiconductor device including a conventional power MOSFET. FIG. 22 is a diagram showing an example of a semiconductor device in which an arrangement and layout of a plurality of pins of the embodiment is applied to a semiconductor device in which a bidirectional thyristor is formed. FIG. 23 is a diagram showing another example of the layout of a plurality of pins to which the embodiment is applied in the semiconductor device in which the bidirectional thyristor is formed.

Claims

1. A semiconductor device comprising: a wafer pad; a semiconductor wafer having a surface and a back side opposite to the surface, the back side being mounted on the wafer pad facing the wafer pad; a plurality of pins disposed along a first side of the semiconductor wafer in plan view; and a plurality of connection members electrically connecting the semiconductor wafer to the plurality of pins; a power MOSFET formed on the semiconductor wafer; the semiconductor wafer comprising: a gate terminal formed on the surface and electrically connected to the gate of the power MOSFET; a Kelvin terminal formed on the surface and electrically connected to the source region of the power MOSFET; a source terminal formed on the surface and electrically connected to the source region of the power MOSFET, and including a portion located between the gate terminal and the Kelvin terminal in plan view; and a drain formed on the back side and electrically connected to the drain of the power MOSFET. The terminals formed on the surface of the semiconductor wafer are of only three types: gate terminals, Kelvin terminals, and source terminals. The plurality of pins are disposed only on one side of the first side. The plurality of pins include: gate terminal pins, electrically connected to the gate terminal via a gate terminal connecting member among the plurality of connecting members; Kelvin terminal pins, electrically connected to the Kelvin terminal via a Kelvin terminal connecting member among the plurality of connecting members; and source terminal pins, located between the gate terminal pins and the Kelvin terminal pins in top view, and electrically connected to the source terminal via a source terminal connecting member among the plurality of connecting members.

2. The semiconductor device as described in claim 1, wherein, The connecting member of the source end is formed by a shape that extends only in a second direction that is perpendicular to the first direction extending from the first side.

3. The semiconductor device as described in claim 2, wherein, The connecting component of this source terminal is a wire made of gold (Au) or copper (Cu).

4. The semiconductor device as described in claim 3, wherein, The number of connection points between the connecting member of the gate terminal and the gate terminal is one; the number of connection points between the connecting member of the Kelvin terminal and the Kelvin terminal is one; the number of connection points between the connecting member of the source terminal and the source terminal is two or more.

5. The semiconductor device as described in claim 4, wherein, The number of connecting components for the source terminal is greater than the number of connecting components for the gate terminal and the number of connecting components for the Kelvin terminal.

6. The semiconductor device as described in claim 5, wherein, The semiconductor device is configured to carry a current of 300A.

7. The semiconductor device as claimed in claim 1, wherein, The connecting component of the source tip is a strip made of aluminum (Al).

8. The semiconductor device as described in claim 7, wherein, The number of connection points between the connecting member of the gate terminal and the gate terminal is one; the number of connection points between the connecting member of the Kelvin terminal and the Kelvin terminal is one; the number of connection points between the connecting member of the source terminal and the source terminal is two or more.

9. The semiconductor device as claimed in claim 8, wherein, The semiconductor device is configured to carry a current of 300A.

10. The semiconductor device as claimed in claim 1, wherein, The connecting member of the source tip is a clamp made of copper (Cu).

11. The semiconductor device as claimed in claim 10, wherein, The number of connection points between the gate terminal and the connecting member is one; the number of connection points between the Kelvin terminal and the connecting member is one; the number of connection points between the source terminal and the connecting member is one.

12. The semiconductor device as claimed in claim 11, wherein, The semiconductor device is configured to carry a current of 300A.

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