Storage device and method of operating the same

Abstract

This invention relates to a storage device and its operating method. According to one embodiment of the invention, the storage device may include: a memory device comprising a plurality of memory chips; and a memory controller that controls the memory device on a superblock basis, the superblock comprising two or more memory blocks included in the memory device, wherein one or more superblocks may be a superblock comprising a plurality of small multi-chip regions, the small multi-chip regions comprising a portion of each memory block included in different memory chips, the memory controller being able to select a sacrifice superblock within the superblocks of the memory device in response to a garbage collection execution request received in a valid page, and the garbage collection execution request may include information about valid pages included in the small multi-chip regions.

Description

[Technical Field]

[0001] This invention relates to an electronic device, and more specifically, to a storage device and its operating method. [Previous Technology]

[0002] The storage device translates logical addresses received from the host into physical addresses and uses them; therefore, the logical regions in the host and the physical regions of the storage device are interconnected. Therefore, to improve the performance of electronic devices, a new device or method is needed that can complementaryly control the host and the storage device. [Summary of the Invention]

[0003] Embodiments of the present invention provide a storage device and its operation method that can effectively manage each piece of data according to its characteristics.

[0004] A storage device according to an embodiment of the present invention may include: a memory device including a plurality of memory chips; and a memory controller controlling the memory device on a superblock basis, the superblock including two or more memory blocks included in the memory device, wherein one or more superblocks may be a superblock including a plurality of small multi-chip regions, the small multi-chip regions including a portion of each memory block included in different memory chips, the memory controller being able to select a sacrifice superblock in the superblocks within the memory device in response to a garbage collection execution request received in a valid page, and the garbage collection execution request may include information about valid pages included in the small multi-chip regions.

[0005] The operating method according to the present invention is an operating method of a storage device, the storage device comprising: a memory device including a plurality of memory chips; and a memory controller controlling the memory device on a superblock basis, the superblock including two or more memory blocks included in the memory device, the operating method of the storage device may include the following steps: receiving a garbage collection execution request on a valid page; and selecting a sacrifice superblock from the superblocks in the memory device based on information about the valid pages included in the garbage collection execution request, wherein one or more superblocks may be a superblock including a plurality of small multi-chip regions, the small multi-chip regions including a portion of each memory block included in different memory chips.

[0006] The method of operating a controller according to an embodiment of the present invention may include the following steps: in response to a request provided along with information, selecting a sacrifice group, the sacrifice group consisting of regions, each region consisting of one or more pages partially included in each storage block in each plane of each chip in the memory device; and controlling the memory device to perform a garbage collection operation on the sacrifice group, each region in the sacrifice group being a first region in a ready-to-reset state or a second region in a full state, the step of selecting the sacrifice group may include the following steps: calculating the cost of each group in the memory device including the first region and the second region based on the number of first regions included in each group; reducing the cost in the second region included in the corresponding group as the number of valid pages included in the information increases; and selecting a sacrifice group based on the cost of the group.

[0007] This technology provides a storage device and its operation method that can effectively manage each piece of data according to its characteristics.

Implementation Method

[0009] The specific structural or functional descriptions of embodiments of the present invention disclosed in this specification or application are merely illustrative of embodiments of the present invention. Embodiments of the present invention may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0010] FIG1 is a diagram illustrating an electronic device according to an embodiment of the present invention.

[0011] Referring to Figure 1, the storage device 50 may include a memory device 100 and a memory controller 200. The storage device 50 may be a device that stores data under the control of a host 400, such as a mobile phone, smartphone, MP3 player, portable computer, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system. Alternatively, the storage device 50 may be a device that stores large amounts of data in one location under the control of the host 400, such as a server or data center.

[0012] Depending on the host interface used as the communication method with the host 400, the storage device 50 can be manufactured as any of various types of storage devices. For example, the storage device 50 can be configured as any of various types of storage devices, such as SSD, MMC, eMMC, RS-MMC, micro-MMC multimedia cards; SD, mini-SD, micro-SD secure digital cards; USB (Universal Serial Bus) storage devices, UFS (Universal Flash Storage) devices, PCMCIA (Personal Computer Memory Card International Association) card storage devices; PCI (Peripheral Component Interconnection) card storage devices; PCI-E (PCI-Express) card storage devices; CF (Compact Flash) cards; smart media cards; and memory sticks.

[0013] The storage device 50 can be manufactured in any of various types of package forms. For example, the storage device 50 can be manufactured in any of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), and WSP (wafer-level stack package).

[0014] The memory device 100 can store data. The memory device 100 operates in response to the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0015] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that can store four data bits.

[0016] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. Each memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0017] In embodiments, the memory device 100 may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, RRAM (resistive random access memory), PRAM (phase-change RAM), MRAM (magnetoresistive random access memory), or FRAM (ferroelectric random access memory). Memory devices include NAND flash memory, STT-RAM (spin transfer torque random access memory), etc. For ease of explanation, this specification assumes that memory device 100 is NAND flash memory.

[0018] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access a region selected according to the address in the memory cell array. The memory device 100 can perform operations instructed by the commands for the region selected according to the address. For example, the memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, the memory device 100 programs data into the region selected according to the address. During a read operation, the memory device 100 reads data from the region selected according to the address. During an erase operation, the memory device 100 erases the data stored in the region selected according to the address.

[0019] The memory controller 200 can control the overall operation of the storage device 50.

[0020] In this embodiment, the memory controller 200 may receive data and a logical address (LA) from the host 400. The memory controller 200 may include firmware (not shown) capable of converting the logical address (LA) into a physical address (PA), which indicates the address of a memory cell in the memory device 100 where data will be stored. Additionally, the memory controller 200 may store a logical-physical address mapping table, which constitutes the mapping relationship between the logical address (LA) and the physical address (PA), in a buffer memory.

[0021] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, or erase operations according to the request of the host 400. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, physical addresses, and data. During a read operation, the memory controller 200 can provide the memory device 100 with read commands and physical addresses. During an erase operation, the memory controller 200 can provide the memory device 100 with erase commands and physical addresses. Alternatively, the memory controller 200 can open or close zones in the memory device 100 according to the request of the host 400. An open zone can be represented as a group of logical addresses corresponding to that zone, for example, by creating a mapping table for logical addresses corresponding to partitions allocated to data by the host. A closed zone can indicate that no write request will be made to store data in that zone until an open request for that zone is received again. The host 400 can provide such requests to open or close zones as separate requests, or they can be provided together with other requests such as write requests.

[0022] In this embodiment, the memory controller 200 may generate commands, addresses, and data independently of requests from the host 400 and transmit the generated commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data for performing programming operations, read operations, and erase operations that accompany wear leveling, read reclaim, garbage collection, etc.

[0023] In an embodiment, the memory controller 200 may include a flash translation layer. The flash translation layer can convert a logical address (LA) corresponding to a request received from the host 400 into a physical address (PA), and output the converted physical address (PA) to the memory device 100.

[0024] For example, as described above, the flash translation layer can convert a logical address (LA) corresponding to a programming request into a physical address (PA), or it can convert a logical address (LA) corresponding to a read request into a physical address (PA), or it can convert a logical address (LA) corresponding to an erase request into a physical address (PA). The flash translation layer can output the converted physical address (PA) to the memory device 100, and the memory device 100 can perform operations on the page or memory block corresponding to the physical address (PA).

[0025] In this embodiment, the memory controller 200 can receive logical addresses from the file system 420 and convert the received logical addresses into consecutive physical addresses. When consecutive physical addresses are output to the memory device 100, the memory device 100 can perform consecutive operations corresponding to the consecutive physical addresses. At this time, the consecutive physical addresses can be determined according to the type of the allocated region. The type of region will be explained in more detail with reference to Figures 4 and 5.

[0026] In an embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 400 and the buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data used to control the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 400 in the buffer memory and then transfer the data temporarily stored in the buffer memory to the memory device 100.

[0027] In various embodiments, the buffer memory can serve as both operational memory and fast buffer memory of the memory controller 200. The buffer memory can store code or commands executed by the memory controller 200. Alternatively, the buffer memory can store data processed by the memory controller 200.

[0028] In an embodiment, the buffer memory may be implemented as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Memory Bus Dynamic Random Access Memory).

[0029] In various embodiments, the buffer memory may be connected to the storage device 50 externally. In this case, a volatile memory device connected to the storage device 50 externally may serve as the buffer memory.

[0030] In this embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 in an interleaved manner to improve operational performance. The interleaved manner can be a manner in which the operations of at least two memory devices 100 overlap. Alternatively, the interleaved manner can be a manner in which the operations of multiple groups divided within a memory device 100 overlap. In this case, a group can be one or more memory die units or one or more memory plane units.

[0031] The host 400 can utilize technologies such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory Express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), and RDIMM (Registered Dual In-line Memory Module). The storage device 50 communicates with at least one of various communication methods, including DIMM (Load Reduced DIMM) and LRDIMM (Load Reduced DIMM).

[0032] In this embodiment, host 400 may include application 410. Application 410 is also referred to as an application program and may be software that executes within an operating system (OS). Application 410 may process data in response to user input. For example, application 410 may process data in response to user input and transmit a request to file system 420 for storing the processed data in memory device 100 of storage device 50.

[0033] The file system 420 can respond to a request transmitted from the application by allocating logical addresses (LAs) for the data to be stored. In an embodiment, the file system 420 may be a Log structure File System (LFS). A Log structure File System (LFS) can generate records by taking into account the attributes of the input data and can allocate partitions corresponding to the data based on the records. In this case, a partition may be a set of logical addresses. Therefore, allocating a partition can represent allocating logical addresses corresponding to the corresponding data. The data in the allocated partitions can be stored sequentially in the storage area of ​​the memory device 100 corresponding to the partitions. For example, the Log structure File System (LFS) may be a flash-friendly file system (F2FS). A Flash-Friendly File System (F2FS) is a record-based file system designed with the characteristics of Solid State Drives (SSDs) in mind, which can increase the parallelism within the SSD by using multi-head records. Different partitions can be allocated for data that generate different records. A Log structure File System (LFS) cannot overwrite data. When data is modified, the Record Structure File System (LFS) can reallocate the logical address corresponding to the data to be modified and write the data to the corresponding physical area.

[0034] Data requested to be written by application 410 can be stored in host memory (not shown) in the host and can be flushed to storage device 50 via device interface (not shown) according to requests from the application. Host memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM.

[0035] Figure 2 is a diagram used to illustrate the memory device of Figure 1.

[0036] Referring to FIG2, the memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit 140, and control logic 150.

[0037] The memory cell array 110 includes multiple memory blocks (BLK1~BLKi). The multiple memory blocks (BLK1~BLKi) are connected to the address decoder 130 via row lines (RL). The multiple memory blocks (BLK1~BLKi) are connected to the input / output circuitry 140 via column lines (CL). In an embodiment, the row lines (RL) may include word lines, source select lines, and drain select lines. In an embodiment, the column lines (CL) may include bit lines.

[0038] In an embodiment, the memory cell array 110 may include one or more memory dies, and each memory die may include one or more planes, each plane including one or more memory blocks.

[0039] Furthermore, the multiple memory blocks (BLKs) included in the memory cell array 110 can be divided into two or more super blocks (SBs). A super block (SB) can be a unit for the control logic 150 to manage the multiple memory blocks (BLKs) included in the memory cell array 110. A super block (SB) can be a set of memory blocks (BLKs) that perform read operations and / or write operations simultaneously or within the same time period, or perform read operations and / or write operations in combination or in association, or a super block (SB) can be a set of memory blocks (BLKs) that perform read operations and / or write operations for a single command, or a super block (SB) can be a set of memory blocks (BLKs) that perform read operations and / or write operations in combination or simultaneously in the memory cell array 110. In addition, a group of memory blocks (BLKs) that are different from each other in terms of management or operation can be referred to as a super block (SB). Each of two or more superblocks (SBs) can be the same size. That is, each of two or more superblocks (SBs) can contain the same number of memory blocks (BLKs). Alternatively, at least one of two or more superblocks (SBs) can have a different size than the others. That is, at least one superblock (SB) can contain a different number of memory blocks (BLKs) than the others. Furthermore, each of two or more superblocks (SBs) can contain two or more memory blocks (BLKs) located on the same memory chip. In contrast, each of two or more superblocks (SBs) can contain two or more memory blocks (BLKs) located on two or more different memory chips.

[0040] Each of the plurality of memory blocks (BLK1~BLKi) includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, memory cells connected to the same word line may be defined as a physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each memory cell of the memory device 100 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0041] In this embodiment, the voltage generation unit 120, the address decoder 130, and the input / output circuit 140 can be collectively referred to as the peripheral circuit. The peripheral circuit can drive the memory cell array 110 under the control of the control logic 150. The peripheral circuit can drive the memory cell array 110 to perform programming operations, read operations, and erase operations.

[0042] The voltage generating unit 120 is configured to generate multiple operating voltages using the external power supply voltage supplied to the memory device 100. The voltage generating unit 120 operates in response to the control of the control logic 150.

[0043] In this embodiment, the voltage generating unit 120 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generating unit 120 is used as the operating voltage of the memory device 100.

[0044] In this embodiment, the voltage generating unit 120 can generate multiple operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generating unit 120 can be configured to generate various voltages required by the memory device 100. For example, the voltage generating unit 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0045] The voltage generating unit 120 includes a plurality of pumping capacitors that receive an internal power supply voltage to generate a plurality of operating voltages with different voltage levels, and the voltage generating unit 120 can selectively activate the plurality of pumping capacitors to generate a plurality of operating voltages in response to the control of the control logic 150.

[0046] The generated operating voltages can be supplied to the memory cell array 110 through the address decoder 130.

[0047] Address decoder 130 is connected to memory cell array 110 via row lines (RL). Address decoder 130 is configured to operate in response to control of control logic 150. Address decoder 130 can receive addresses (ADDR) from control logic 150. Address decoder 130 can decode block addresses in the received address (ADDR). Address decoder 130 selects at least one memory block from memory blocks (BLK1~BLKi) based on the decoded block address. Address decoder 130 can decode row addresses in the received address (ADDR). Address decoder 130 can select at least one word line from the word lines of the selected memory block based on the decoded row address. In an embodiment, address decoder 130 can decode column addresses in the received address (ADDR). Address decoder 130 can connect input / output circuitry 140 and memory cell array 110 based on the decoded column addresses.

[0048] For example, address decoder 130 may include elements such as row decoder, column decoder, address buffer.

[0049] The input / output circuit 140 may include multiple page buffers. These page buffers can be connected to the memory cell array 110 via bit lines. During programming operations, data can be stored in selected memory cells based on the data stored in the multiple page buffers.

[0050] During a read operation, data stored in the selected memory cell can be sensed via bit lines, and the sensed data can be stored in the page buffer.

[0051] Control logic 150 can control address decoder 130, voltage generator 120, and input / output circuit 140. Control logic 150 can operate in response to commands (CMDs) transmitted from external devices. Control logic 150 can generate control signals in response to commands (CMDs) and addresses (ADDRs) to control peripheral circuits.

[0052] Figure 3 is a diagram used to illustrate the memory cell array of Figure 2.

[0053] Referring to Figure 3, the memory cell array 110 may include more than one memory chip, and each memory chip may include more than one plane, which includes more than one memory block. Although Figure 3 shows the memory cell array 110 including four memory chips (DIE#0, DIE#1, DIE#2, DIE#3), the number of memory chips is not limited to this. Multiple memory chips can transmit to or receive from the memory controller through multiple channels, and each channel can be connected to more than one memory chip. For example, if a channel is connected to a memory chip, a memory chip can receive one command at a time, and the planes included in a memory chip can process the commands received by the memory chip in parallel.

[0054] FIG4 is a diagram illustrating the superblock allocation process of a storage device according to an embodiment of the present invention.

[0055] Referring to Figures 1 and 4, the file system 420 of the host 400 generates records for data requested to be written by the application 410 based on the attributes of the data, and classifies the data accordingly and determines partition groups including partitions to be allocated to the data. According to various criteria, the data can be divided into a first type of data allocated to the first partition 422a in the first partition group 421a and a second type of data allocated to the second partition 422b in the second partition group 421b. The data allocated by the file system to the first partition 422a in the first partition group 421a can be stored in a small single-die zone 112a in the first superblock 111a of the memory device 100 under the control of the memory controller 200, and the data allocated by the file system to the second partition 422b in the second partition group 421b can be stored in a small multi-die zone 112b in the second superblock 111b of the memory device 100. The first partition group 421a corresponds to the first superblock 111a; therefore, the first partition 422a corresponds to the small single-cell region 112a. The characteristic of the first partition 422a, which can be assigned as a new partition regardless of the partition order in the partition group, is consistent with the characteristic of the small single-cell region 112a managed per memory cell. Furthermore, the first partition 422a and the small single-cell region 112a have the same characteristic: both the first partition 422a and the small single-cell region 112a can perform reset or erase operations on a partition or region basis. Furthermore, the characteristics of the second partition 422b, which is assigned as a new partition according to the partitioning order in the partition group, conform to the characteristics of a small polycrystalline region 112b formed across multiple memory cells. The second partition 422b and the small polycrystalline region 112b share the same characteristic: neither the second partition 422b nor the small polycrystalline region 112b can be reset or erased on a per-partition or per-region basis. Reset or erase operations are performed on a per-partition or per-superblock basis only after their respective second partition groups 421b and second superblocks 111b are in a reset or eraseable state. The allocation and reset of the first partition 422a and the second partition 422b will be explained in more detail with reference to Figures 6 to 11, and the morphology of the small single-cell region 112a and the small polycrystalline region 112b will be explained in more detail with reference to Figure 5.

[0056] The first partition 422a in the first partition group 421a can be allocated regardless of the partition order, and in response to a partition allocation request from the host 400 to store data of the allocated partition, the memory controller 200 can allocate a small single-cell region 112a that forms a region in a memory cell. The second partition 422b in the second partition group 422b can be allocated according to the partition order, and in response to a partition allocation request from the host 400 to store data of the allocated partition, the memory controller 200 can allocate a small multi-cell region 112b that forms a region comprising a part of a memory block in multiple memory cells. In response to a partition allocation request from the host 400, when the memory controller 200 replies with information that there are no additional allocable regions in the currently used superblock, the file system 420 can allocate partitions in the new partition group after allocating the new partition group. In response, the memory controller 200 can store data of the newly allocated partition after allocating the new superblock and the new regions included therein. Alternatively, the file system 420 may not receive information about the superblock and zones from the memory controller 200, and may automatically allocate new partition groups and the partitions included in them.

[0057] FIG5 is a diagram illustrating the superblock management of a storage device according to an embodiment of the present invention.

[0058] Referring to Figures 1, 4, and 5, the memory cell array 110 may include multiple memory chips, for example, it may include four memory chips (DIE#0~DIE#3). Additionally, each memory chip may include multiple planes, and each plane may include multiple memory blocks, for example, it may include four planes PLANE#0~PLAINE#3. The memory controller 200 can control the memory cell array 110 by dividing it into multiple superblocks. A superblock may include two or more memory blocks included in the memory cell array 110. A superblock may include multiple zones. A superblock can be formed across multiple memory chips, and as shown in Figure 5, a superblock can be formed across all memory chips. A superblock can be divided into a first superblock 111a and a second superblock 111b based on the shape of the zones included therein. In a storage device according to an embodiment of the present invention, a superblock, which serves as a unit for the memory controller 200 to control the memory device 100, may consist only of a second superblock 111b including a small polycrystalline region 112b, or may include a second superblock 111b including a small polycrystalline region 112b and a first superblock 111a including a small monocrystalline region 112a.

[0059] The small single-cell regions 112a included in the first superblock 111a may include more than one block in a memory cell. For example, as shown in FIG5, for each memory cell, the region including one memory cell block in planes 0 to 3 can be designated as a zone. Therefore, the first superblock 111a may include four small single-cell regions 112a, with each memory cell forming a small single-cell region 112a.

[0060] The small polycrystalline regions 112b included in the second superblock 111b may include a portion of each block included in different memory chips. For example, as shown in FIG5, the small polycrystalline regions 112b may be formed across all four memory chips (DIE#0~DIE#3) and may include only a portion of each memory block included in each plane. For example, as shown in FIG5, only 1 / 4 of the page of each memory block included in each plane may be included. Therefore, the second superblock 111b may be formed across all memory chips and may include four small polycrystalline regions 112b formed to include only a portion of the page of each memory block.

[0061] In one embodiment, the first superblock 111a and the second superblock 111b can be the same size. That is, the first superblock 111a and the second superblock 111b can include the same number of memory blocks. Additionally, the small single-chip region 112a and the small multi-chip region 112b can be the same size. That is, the number of pages included in the small single-chip region 112a and the small multi-chip region 112b can be the same. The small single-chip region 112a can be formed in one memory chip, while the small multi-chip region 112b can be formed across multiple memory chips. Therefore, in the case of the small multi-chip region 112b, it can operate in a die-interleaved manner; specifically, as shown in FIG5, when the small multi-chip region 112b is formed across all memory chips, it can operate in a full-die interleaved manner. However, different small multi-chip regions 112b cannot be allocated and programmed simultaneously. Furthermore, since a small multi-chip region only includes a portion of each memory block, it cannot be erased immediately when a specific region needs to be erased. It can only be erased when all pages of each memory block contained within that region can be erased—that is, when all regions of a superblock containing that region can be erased. Therefore, while small multi-chip regions offer the advantage of interleaved operation at the memory chip level, limitations during programming and erasing may make them unsuitable for storing data with high input / output frequencies. Therefore, by simultaneously using a first superblock and a second superblock, relatively small-capacity or high-input / output frequency data can be stored in the small single-chip region of the first superblock, and relatively large-capacity or low-input / output frequency data can be stored in the small multi-chip region of the second superblock, thereby improving the performance of the storage device.

[0062] A zone, representing a physical region included in a superblock, such as a small single-cell zone or a small multi-cell zone, can be divided into a full state, an empty state, and an active state. A full state indicates that data is stored in all zones within the zone, and there are no empty zones. An empty state indicates that no data is stored in any zone, and the zone is empty. An active state indicates that data is stored in only a portion of the zone, and can be either open or closed. An open state indicates that data is currently being programmed in a zone where only a portion of the zone is stored; a closed state indicates that no data is currently being programmed in a zone where only a portion of the zone is stored.

[0063] Furthermore, in the case of a small multi-chip region, a "ready to reset" state can be further included. The region reset operation can represent an operation that makes the region empty by erasing it. Erasing can be performed on a memory block basis, as shown in FIG5. In the case of a small multi-chip region 112b, only a portion of each of the multiple memory blocks is included. On the other hand, in the case of a small single-chip region 112a, more than one entire memory block can be included. Therefore, when a specific small single-chip region 112a is to be reset, that region can be erased immediately. On the other hand, when a specific small multi-chip region 112b is to be reset, that region can be erased when all pages of each memory block partially included in that region can be erased, that is, when all regions including the superblock of that region can be erased. Therefore, when a reset operation is performed on a small polycrystalline region 112b, the region is not immediately erased, but is converted to a ready-to-reset state. When all the small polycrystalline regions 112b in the second superblock 111b, which includes the small polycrystalline region 112b, are converted to the ready-to-reset state, all the small polycrystalline regions 112b in the superblock can be erased at once to convert to an empty state.

[0064] Figure 6 is a diagram illustrating the structure of a partition allocated by a file system.

[0065] Referring to Figure 6, a partition may include multiple logical addresses. The logical addresses included in a partition may be consecutive or non-consecutive addresses. Allocating a partition for data may indicate that logical addresses within the partition have been allocated. Information about the addresses included in each partition may be included in the memory of the host or the memory of the storage device. Logical addresses may be allocated sequentially according to the size of the data to be written. For example, when there is a write request for data D1 and D2 of a specific size and the partitions in Figure 5 are allocated to data D1 and D2, logical addresses LA1 to LA3 may be allocated to D1, and logical addresses LA4 and LA5 may be allocated to D2.

[0066] Figure 7 is a diagram illustrating the process of allocating a new partition to the first partition group by the file system.

[0067] Referring to Figure 7, a partition group in which new partitions can be allocated regardless of the partition order within the partition group can be defined as the first partition group 421a. In this case, the logical addresses of the partitions included in the partition group can be contiguous, and the logical addresses can increase as the partition number in the partition group increases. Therefore, the partition order can represent the partition number order within the partition group, which can represent the order in which the logical addresses increase. Alternatively, the logical addresses of the partitions included in the partition group can be discontinuous. In this case, the partition order can be determined based on the partitions stored in separate memory and information about the logical addresses included in each partition group. In the case of the first partition group 421a, since partitions and logical addresses can be allocated regardless of the partition order, the third partition (partition #3) can be allocated first, and all logical addresses in the third partition can be allocated, so that the first partition (partition #1) can be allocated after the partition becomes a full section, and logical addresses for new data can be allocated. When all logical addresses of the first partition, which is an open section, are allocated to data and the first partition becomes a full partition, the file system 420 can allocate either the zeroth partition (partition #0) or the second partition, which is an empty section, as a new partition, and can allocate the logical addresses included therein to data.

[0068] Figures 8 and 9 are diagrams illustrating the process of allocating a new partition to the second partition group by the file system.

[0069] Referring to Figures 8 and 9, a partition group that allocates new partitions according to the partition order in the partition group can be defined as the second partition group 421b. As shown in Figure 8, in the second partition group, the zeroth partition (partition #0) can be opened first and its logical address can be allocated to data. When the zeroth partition becomes full, the first partition (partition #1), which is the next partition in the order, can be allocated as a new partition to store data. As shown in Figure 9, when all partitions in the second partition group 421b are full, the file system 420 can allocate the zeroth partition (partition #0), which is the first partition in the new second partition group, as a new partition after allocating the new second partition group 421b, and can allocate its logical address to data. At this time, in the case of the second partition group 421b, partitions can be allocated according to the partition order in the partition group. When the third partition (partition #3), which is the last partition, is full, there cannot be empty partitions in the partitions before it. Therefore, in the case of the second partition group 421b, there is no need to search for an empty partition in the partition group. If there is no next-order partition in the second partition group 421b, the file system 420 allocates a new second partition group 421b.

[0070] Figure 10 is a diagram illustrating the reset process through the first partition group of the file system.

[0071] Referring to Figure 10, in the first partition group 421a, 1) when the zeroth partition (partition #0) is reset, 2) by discarding all data corresponding to the logical addresses in the zeroth partition, the zeroth partition becomes an empty partition, thereby completing the reset operation. Additionally, 3) when resetting the first partition (partition #1), 4) by discarding all data corresponding to the logical addresses in the first partition, the first partition becomes an empty partition, thereby completing the reset operation. Additionally, 5) when the second partition (partition #2) is reset, 6) by discarding all data corresponding to the logical addresses in the second partition, the second partition becomes an empty partition, thereby completing the reset operation. That is, when a reset operation is performed on a partition included in the first partition group 421a, in response, the data corresponding to the logical addresses in that partition is discarded, so that the partition can immediately become an empty partition, thus completing the reset operation. At this time, discarding the data corresponding to the logical addresses when performing a reset operation on a partition can represent decoupling the mapping relationship between logical addresses and data. A reset operation is performed when all data corresponding to logical addresses in a specific partition becomes invalid. If valid data exists, it is mapped to logical addresses in another partition. A reset operation can also be performed after invalidating the data corresponding to the relevant logical addresses. The logical addresses included in the reset partition can then be reassigned to new data. Such a reset operation can be performed by the file system.

[0072] Figure 11 is a diagram illustrating the reset process through the second partition group of the file system.

[0073] Referring to Figures 5 and 11, in the second partition group 421b, 1) when the zeroth partition (partition #0) is reset, 2) the data corresponding to the logical addresses in the zeroth partition is not immediately discarded, and information indicating that the zeroth partition is ready to be reset is stored in the bitmap. Additionally, 3) when the first partition (partition #1) is reset, 4) the data corresponding to the logical addresses in the first partition is not immediately discarded, and information indicating that the first partition is ready to be reset is stored in the bitmap. Additionally, 5) when the second partition (partition #2) is reset, 6) the data corresponding to the logical addresses in the second partition is not immediately discarded, and information indicating that the second partition is ready to be reset is stored in the bitmap. Additionally, 7) when the third partition (partition #3) is reset, 8) the data corresponding to the logical addresses in the third partition is not immediately discarded, and information indicating that the third partition is ready to be reset is stored in the bitmap. 9) Therefore, when the information indicating that all partitions in the second partition group 421b are ready to be reset is stored in the bitmap, all data corresponding to all logical addresses in all said partitions is discarded, and all partitions in the second partition group 421b become empty partitions at once, thereby completing the reset operation. That is, in the case of the second partition group 421b, when only a portion of the partitions are reset, the data is not immediately discarded, so the partitions do not become empty partitions. After the reset operation is performed on all partitions in the second partition group 421b, that is, after the information indicating that all partitions are ready to be reset is stored, the data corresponding to the logical addresses of all partitions included in the second partition group 421b is discarded, so all partitions in the second partition group 421b can become empty partitions simultaneously. When the reset operation is completed, the information indicating that all partitions in the second partition group 421b are ready to be reset can be deleted. At this time, the bitmap storing the information indicating that the reset is ready can be included in any location in the storage device. At this time, discarding the data corresponding to the logical address in the partition reset operation can represent decoupling the mapping relationship between the logical address and the data. When all data corresponding to logical addresses in a specific partition becomes invalid, a reset operation is performed. If valid data exists, it is mapped to a logical address in another partition, and a reset operation can be performed after the data corresponding to that logical address is processed as invalid. The logical addresses included in the reset partition can be reallocated to new data. Such a reset operation can be performed by the file system. That is, such a reset operation for the second partition corresponds to the reset operation for the small polycrystalline region 112b in the second superblock 111b of Figure 5. That is, when a reset operation is performed on the second partition 422b, the second partition is in a state ready for reset; therefore, the small polycrystalline region 112b corresponding to the second partition 422b is not immediately erased but is converted to a state ready for reset.Subsequently, when all the second partitions 422b in the second partition group 421b, including the second partition 422b, are converted to a ready-to-reset state, that is, when all the small polycrystalline regions 112b in the second superblock 111b, including the small polycrystalline regions 112b, are converted to a ready-to-reset state, the data corresponding to the logical addresses of all the second partitions 422b in the second partition group 421b is discarded, so that all the partitions in the second partition group 421b simultaneously become empty partitions, and all the small polycrystalline regions 112b in the corresponding second superblock 111b are erased and become empty.

[0074] FIG12 is a diagram illustrating waste recycling of a storage device according to an embodiment of the present invention.

[0075] Referring to Figures 1, 4, and 12, the host 400 includes a host garbage collection control unit 430. The host garbage collection control unit 430 may be included in the file system 420, or may be included in the host 400 as a separate configuration from the file system 420. The host garbage collection control unit 430 may include information about partitions and partition groups allocated by the file system 420, as well as information about corresponding superblocks and zones. Additionally, the host garbage collection control unit 430 may include information about each page included in a zone. For example, it may include information about whether data stored on each page is valid or invalid.

[0076] The host garbage collection control unit 430 may provide a garbage collection execution request to the storage device 50. The garbage collection execution request may include information about each page included in the region. In this embodiment, the garbage collection execution request may include information about the valid pages included in the small multi-chip region. More specifically, the garbage collection execution request may include information about the valid pages included in the small multi-chip region that is in a full state. For example, the garbage collection execution request may include the number of valid pages included in the small multi-chip region that is in a full state, a list of small multi-chip regions that include more than a predetermined number of valid pages, etc.

[0077] The memory controller 200 in the storage device 50 may include a zone management unit 210 and a device garbage collection control unit 220. The zone management unit 210 may allocate and manage zones and superblocks corresponding to partitions and partition groups allocated by the host. Corresponding to the first partition 422a in the first partition group 421a, small single-cell regions 112a in the first superblock 111a may be allocated and mapped; corresponding to the second partition 422b in the second partition group 421b, small multi-cell regions 112b in the second superblock 111b may be allocated and mapped. The device garbage collection control unit 220 may perform garbage collection in response to a garbage collection execution request received by the storage device 50 from the host 400. The device garbage collection control unit 220 may receive information about the allocated superblocks and zones from the zone management unit 210, and select a sacrifice superblock based on the received information. The sacrifice superblock may be selected from the second superblock 111b, which includes the small multi-cell regions 112b. The device garbage collection control unit 220 can select a sacrifice superblock from superblocks consisting only of regions in a full state and a state ready to be reset. The device garbage collection control unit 220 can consider the number of regions in a state ready to be reset when selecting a sacrifice superblock. Information about the number of regions in a state ready to be reset can be received from the region management unit 210 or the host garbage collection control unit 430. For example, a superblock with more regions in a state ready to be reset is more likely to be selected as a sacrifice superblock. Additionally, the device garbage collection control unit 220 can consider information about the valid pages included in regions in a full state when selecting a sacrifice superblock. Information about the valid pages included in regions in a full state can be received from the host garbage collection control unit 430, and this information can be received along with the garbage collection execution request. For example, the more valid pages included in a full state region, the more likely it is to be selected as a sacrifice superblock. The region management unit 210 does not manage information about whether the pages included in a region are valid or invalid; therefore, it can receive related information from the host garbage collection control unit 430. When the device waste collection control unit 220 selects a sacrificial superblock, the zone management unit 210 can copy the data stored in the full zones of the sacrificial superblock and store it in another superblock. When the sacrificial superblock is a second superblock 111b that includes small polycrystalline zones 112b, the other superblock that copies and stores the data of the full zones in the sacrificial superblock can also be the second superblock 111b. Furthermore, at this time, the zone management unit 210 does not need to manage information about whether the pages included in the zone are valid or invalid, so data can be copied and stored on a zone-by-zone basis. Alternatively, data can be copied and stored on a page-by-page basis based on information about valid pages received from the host waste collection control unit 430.That is, it is possible to copy only the data from the valid pages in the full area stored in the sacrificed superblock and store it in another superblock.

[0078] FIG13 is a flowchart illustrating the process of selecting a sacrificial superblock of a storage device according to an embodiment of the present invention.

[0079] Referring to Figures 12 and 13, in step S1301, the storage device 50 can receive a garbage collection execution request from the host 400. In response, in step S1303, the memory controller 200 can select a candidate superblock. The candidate superblock can be a superblock comprising multiple small multi-chip regions. In an embodiment, a superblock consisting only of small multi-chip regions in a full state and a ready-to-reset state can be selected as a candidate superblock.

[0080] In step S1305, the garbage collection cost for each candidate superblock can be calculated. At this time, the number of small polycrystalline regions in the superblock that are in the ready-to-reset state can be considered to calculate the garbage collection cost.

[0081] In step S1307, the cost of each candidate superblock can be modified based on the number of valid pages included in the small multi-chip regions that are in a full state within each candidate superblock. For example, the more valid pages included in the small multi-chip regions that are in a full state, the more weight is assigned to reduce the cost, thereby increasing the likelihood of being selected as a sacrifice superblock. At this time, information about the number of valid pages can be included in the garbage collection execution request. For example, information about valid pages can include the number of valid pages included in the small multi-chip regions that are in a full state and a list of small multi-chip regions that include more than a predetermined number of valid pages. First, it is confirmed whether the regions included in the candidate superblock are in the list of small multi-chip regions that include more than a predetermined number of valid pages. If they are in the list, the cost of the candidate superblock can be reduced by assigning weights based on the number of valid pages.

[0082] In step S1309, the cost of each candidate superblock modified and determined in step S1307 can be compared. Therefore, in step S1311, the candidate superblock with the lowest cost can be selected as the sacrificed superblock.

[0083] Figure 14 is a flowchart illustrating the process of performing garbage collection on a sacrificed superblock according to an embodiment of the present invention.

[0084] Referring to Figures 13 and 14, in step S1401, data stored in a full region of the sacrificial superblock selected according to the process in Figure 13 can be copied and stored in another superblock. When the sacrificial superblock is a second superblock comprising small multi-cell regions, the other superblock for data movement can also be a second superblock. In this case, data can be copied on a region-by-region or page-by-page basis.

[0085] In step S1403, the superblock where the data movement is complete can be erased. Therefore, all areas included in the victim superblock can be converted to an empty state.

[0086] FIG15 is a diagram showing another embodiment of the memory controller of FIG1.

[0087] Referring to FIG15, the memory controller 1000 may include a processor 1010, internal memory 1020, error correction code circuit 1030, host interface 1040, buffer memory interface 1050 and memory interface 1060.

[0088] The processor 1010 can perform various operations for controlling the memory device 100 or generate various commands. When the processor 1010 receives a request from the host 400, the processor 1010 can generate commands according to the received request and transmit the generated commands to the queue controller (not shown). In addition, the processor 1010 can respond to a space allocation request from the host 400, allocate a superblock and the areas included therein in the memory device to store data received from the host, and can manage the allocated superblock and areas. In addition, the processor 1010 can perform garbage collection in response to a garbage collection execution request from the host 400.

[0089] The internal memory 1020 can store various information required for the operation of the memory controller 1000. For example, the internal memory 1020 may include a logical and physical address mapping table. The internal memory 1020 can be configured as at least one of RAM (Random Access Memory), Dynamic RAM (DRAM), Static RAM (SRAM), cache, and tightly coupled memory (TCM).

[0090] The error correction code circuit 1030 is configured to detect and correct errors in data received from the memory device 100 using error correction codes (ECC). The processor 1010 can control the memory device 100 to adjust the read voltage and perform a reread based on the error detection result of the error correction code circuit 1030. In an exemplary embodiment, an error correction block may be provided as an element of the memory controller 1000.

[0091] The host interface 1040 can exchange commands, addresses, and data between the memory controller 1000 and the host 400. For example, the host interface 1040 can receive requests, addresses, data, etc. from the host 400, and can output data read from the memory device 100 to the host 400. The host interface 1040 can use interfaces such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnect), PCIe (PCI express), NVMe (NonVolatile Memory Express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), and LRDIMM. The host interface 1040 communicates with the host 400 using protocols such as Load Reduced DIMM, ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics). The host interface 1040 can receive requests to allocate regions corresponding to partitions allocated to data by the host 400. The host interface 1040 can also receive requests from the host 400 to perform garbage collection, at which time it can simultaneously receive information about the valid pages included in the small polydiode regions of the memory device 100.

[0092] The buffer memory interface 1050 can transfer data between the processor 1010 and the buffer memory. The buffer memory can serve as operational memory or fast buffer memory of the memory controller 1000, and can store data used in the storage device 50. Through the processor 1010, the buffer memory interface 1050 can use the buffer memory as a read buffer, write buffer, mapping buffer, etc. According to embodiments, the buffer memory may include DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), or RDRAM (Memory Bus Dynamic Random Access Memory). When the buffer memory is included inside the memory controller 1000, the buffer memory interface 1050 can be omitted.

[0093] The memory interface 1060 can exchange commands, addresses, and data between the memory controller 1000 and the memory device 100. For example, the memory interface 1060 can transmit commands, addresses, data, etc. to the memory device 100 through a channel, and can also receive data from the memory device 100. The memory interface 1060 can transmit commands, addresses, and data to or receive commands, addresses, and data from the memory device 100 based on superblocks and regions allocated and managed by the processor 1010. In addition, when garbage collection is performed, a portion of the data in a superblock selected as a sacrifice superblock can be moved to another superblock, and an erasure operation can be performed on the sacrifice superblock.

[0094] FIG16 is a block diagram showing a memory card system using a storage device according to an embodiment of the present invention.

[0095] Referring to FIG16, the memory card system 2000 includes a memory controller 2100, a memory device 2200 and a connector 2300.

[0096] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 may be configured to control read, program, erase, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and the host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory controller 2100 may be implemented in the same manner as memory controller 200 described with reference to FIG1. ​​For example, memory controller 2100 may allocate regions and superblocks including those regions in memory device 2200, and may control memory device 2200 on a region and superblock basis.

[0097] For example, the memory controller 2100 may include components such as RAM (random access memory), processing unit, host interface, memory interface, and error correction unit.

[0098] The memory controller 2100 can communicate with an external device via the connector 2300. The memory controller 2100 can communicate with the external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 can be configured to communicate with external devices via at least one of various communication standards such as USB (Universal Serial Bus), MMC (MultiMedia Card), eMMC (embedded MMC), PCI (Peripheral Component Interconnect), PCI-E (PCI express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the aforementioned communication standards.

[0099] For example, the memory device 2200 can be configured as a variety of non-volatile storage devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), and STT-MRAM (Spin Transfer Torque Magnetic RAM).

[0100] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), or a universal flash storage (UFS).

[0101] Figure 17 is a block diagram illustrating a solid state drive (SSD) system using a storage device according to an embodiment of the present invention.

[0102] Referring to Figure 17, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 transmits signals to and receives signals from the host 3100 through a signal connector 3001, and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221-322n, an auxiliary power supply device 3230, and a buffer memory module 3240.

[0103] According to an embodiment of the present invention, the SSD controller 3210 can perform the functions of the memory controller 200 described with reference to FIG1.

[0104] The SSD controller 3210 can control multiple flash memory modules 3221-322n in response to signals received from the host 3100. The SSD controller 3210 can control multiple flash memory modules through multiple channels CH1-CHn. More than one memory chip can be connected to each channel. For example, the signal can be a signal based on the interface between the host 3100 and the SSD 3200. For example, the signal can be a signal defined by at least one of the following interfaces: USB (Universal Serial Bus), MMC (MultiMedia Card), eMMC (embedded MMC), PCI (Peripheral Component Interconnect), PCI-E (PCI express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), Wi-Fi, Bluetooth, and NVMe. The SSD controller 3210 can perform garbage collection based on a garbage collection execution request received from the host 3100.

[0105] The auxiliary power supply unit 3230 is connected to the host 3100 via a power connector 3002. The auxiliary power supply unit 3230 can receive power from the host 3100 and charge it. When the power supply from the host 3100 is unreliable, the auxiliary power supply unit 3230 can supply power to the SSD 3200. For example, the auxiliary power supply unit 3230 can be located inside or outside the SSD 3200. For example, the auxiliary power supply unit 3230 can be located on the motherboard to supply auxiliary power to the SSD 3200.

[0106] Buffer memory 3240 operates as buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221-322n, or buffer memory 3240 may temporarily store metadata (e.g., mapping tables) of flash memories 3221-322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM.

[0107] FIG18 is a block diagram illustrating a user system using a storage device according to an embodiment of the present invention.

[0108] Referring to Figure 18, the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0109] The application processor 4100 can drive components, operating systems (OS), user programs, or file systems included in the user system 4000. For example, the application processor 4100 may include controllers, interfaces, and graphics engines that control components included in the user system 4000. The application processor 4100 may be provided as a system-on-a-chip (SoC). The application processor 4100 can generate records for data requested to be written by the user, allocate partition groups and partitions based on the records, and provide the data allocated to the partitions to the storage module 4400.

[0110] The memory module 4200 can operate as the main memory, operating memory, buffer memory, or fast buffer memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM. For example, the application processor 4100 and the memory module 4200 may be based on POP (Package on Package) packaging and may be provided as a single semiconductor package.

[0111] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communication such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile communication), WCDMA (wideband CDMA), CDMA-2000, TDMA (Time Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0112] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash memory, NOR flash memory, or three-dimensional NAND flash memory. For example, storage module 4400 can be provided as a memory card of user system 4000 or a removable drive of an external drive.

[0113] For example, storage module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as memory device 100 described with reference to FIG1. ​​Storage module 4400 may operate in the same manner as storage device 50 described with reference to FIG1.

[0114] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. For example, user interface 4500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touch screens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 4500 may include user output interfaces such as LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) displays, AMOLED (Active Matrix OLED) displays, LEDs, speakers, and monitors.

[0115] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims. Furthermore, embodiments may be combined to form additional embodiments. [Simplified Explanation of the Diagram]

[0008] FIG1 is a diagram illustrating a storage device according to an embodiment of the present invention. FIG2 is a diagram illustrating the memory device of FIG1. ​​FIG3 is a diagram illustrating the memory cell array of FIG2. FIG4 is a diagram illustrating the superblock allocation process of a storage device according to an embodiment of the present invention. FIG5 is a diagram illustrating superblock management of a storage device according to an embodiment of the present invention. FIG6 is a diagram illustrating the structure of partitions allocated by a file system. FIG7 is a diagram illustrating the process of allocating new partitions of a first partition group by a file system. FIG8 and FIG9 are diagrams illustrating the process of allocating new partitions of a second partition group by a file system. FIG10 is a diagram illustrating the reset process of the first partition group by a file system. FIG11 is a diagram illustrating the reset process of the second partition group by a file system. FIG12 is a diagram illustrating garbage collection in a storage device according to an embodiment of the present invention. FIG13 is a flowchart illustrating the process of selecting a sacrificial superblock of a storage device according to an embodiment of the present invention. FIG14 is a flowchart illustrating the process of performing garbage collection on a sacrificial superblock in a storage device according to an embodiment of the present invention. FIG15 is a diagram illustrating another embodiment of the memory controller of FIG1. Figure 16 is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present invention. Figure 17 is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present invention; and Figure 18 is a block diagram illustrating a user system using a storage device according to an embodiment of the present invention.

Claims

1. A storage device, comprising: Memory device, comprising multiple memory chips; A memory controller is configured to control the memory device on a superblock basis, each superblock comprising two or more memory blocks included in the memory device, wherein at least one superblock in the memory device is a superblock comprising multiple small multi-chip regions, each small multi-chip region comprising a portion of each memory block included in different memory chips in the memory chip, wherein the memory controller is further configured to: receive a garbage collection execution request and information about valid pages included in the small multi-chip regions, and respond to the garbage collection execution request by selecting a sacrifice superblock among the superblocks in the memory device. The sacrificial superblock includes the plurality of small polycrystalline regions, and the plurality of small polycrystalline regions includes one or more small polycrystalline regions in a ready-to-reset state. In the ready-to-reset state, a reset operation is performed on the sacrificial superblock by erasing all the small polycrystalline regions, so that all the small polycrystalline regions in the sacrificial superblock are in an empty state. The reset operation on the sacrificial superblock is not yet completed depending on the state of another small polycrystalline region in the sacrificial superblock.

2. The storage device as claimed in claim 1, wherein, Each of the small polycrystalline regions has any one of the following states: full state, empty state, start-up state, and ready-to-reset state. In the full state, there are no empty areas in the corresponding region. In the empty state, the corresponding region is empty. In the start-up state, data is stored only in a portion of the corresponding region. In the ready-to-reset state, the reset operation is performed on the superblock including the corresponding region by erasing all the small polycrystalline regions in the superblock including the corresponding region, so that all the small polycrystalline regions in the superblock including the corresponding region become empty. The reset operation on the superblock including the corresponding region has not yet been completed depending on the state of another small polycrystalline region in the superblock including the corresponding region.

3. The storage device as claimed in claim 2, wherein, The memory controller selects the sacrifice superblock from among the superblocks within the memory device, which consist only of the small multi-chip regions that are in the full state and the ready-to-reset state.

4. The storage device as claimed in claim 2, wherein, The memory controller is further configured to perform the reset operation on a selected superblock comprising the plurality of small polycrystalline regions by: converting the state of all small polycrystalline regions in the selected superblock to the ready-to-reset state, and erasing all converted small polycrystalline regions, so that the state of all converted small polycrystalline regions becomes the empty state.

5. The storage device as claimed in claim 3, wherein, The information regarding the valid pages included in the small polycrystalline region includes information regarding the valid pages included in the small polycrystalline region that are in the full state in each of the superblocks within the memory device.

6. The storage device as claimed in claim 5, wherein, The memory controller selects the sacrificed superblock based on information about the valid pages included in the small multi-chip region.

7. The storage device as claimed in claim 5, wherein, Information regarding the valid pages included in the small polycrystalline region in the full state includes the number of valid pages included in the small polycrystalline region in the full state and a list of small polycrystalline regions, each of the small polycrystalline regions including a predetermined number or more valid pages.

8. The storage device as claimed in claim 5, wherein, The memory controller selects the sacrificial superblock based on the number of the small multi-chip regions in the ready-to-reset state.

9. The storage device as described in claim 3, wherein, The memory controller is further configured to: copy data stored in the small polycrystalline regions that are in the full state in the sacrificed superblock, and store the data in another superblock comprising a plurality of small polycrystalline regions.

10. The storage device as claimed in claim 1, wherein, At least one of the superblocks within the memory device is a superblock comprising a plurality of small single-cell regions, each of the small single-cell regions comprising one or more memory blocks in a memory cell.

11. A method of operating a storage device, the storage device comprising: Memory device, comprising multiple memory chips; The system includes a memory controller that controls the memory device on a superblock basis, each superblock comprising two or more memory blocks within the memory device. The operation method includes the following steps: receiving a garbage collection execution request and information about valid pages; and selecting a sacrifice superblock among the superblocks in the memory device based on the information about the valid pages; wherein at least one superblock in the memory device is a superblock comprising multiple small multi-chip regions, each small multi-chip region comprising a portion of each memory block included in a different memory chip within the memory chip; and wherein the valid page is included in the small multi-chip region. The sacrificial superblock includes the plurality of small polycrystalline regions, and the plurality of small polycrystalline regions includes one or more small polycrystalline regions in a ready-to-reset state. In the ready-to-reset state, a reset operation is performed on the sacrificial superblock by erasing all the small polycrystalline regions, so that all the small polycrystalline regions in the sacrificial superblock are in an empty state. The reset operation on the sacrificial superblock is not yet completed depending on the state of another small polycrystalline region in the sacrificial superblock.

12. The operating method as described in claim 11, wherein, Each of the small polycrystalline regions has any one of the following states: full state, empty state, start state, and ready-to-reset state. In the full state, there is no empty area in the corresponding region. In the empty state, the corresponding region is empty. In the start state, data is stored only in a portion of the corresponding region. In the ready-to-reset state, the reset operation is performed on the superblock including the corresponding region by erasing all the small polycrystalline regions in the superblock including the corresponding region, so that all the small polycrystalline regions in the superblock including the corresponding region become empty. The reset operation on the superblock including the corresponding region has not yet been completed depending on the state of another small polycrystalline region in the superblock including the corresponding region. The sacrificial superblock is selected from the superblocks in the memory device consisting only of small polycrystalline regions in the full state and the ready-to-reset state.

13. The operating method as described in claim 12, wherein, Selecting the sacrificial superblock includes: selecting candidate superblocks from the superblocks within the memory device, each candidate superblock consisting only of small polycrystalline regions in the full state and the ready-to-reset state; and selecting the sacrificial superblock from the candidate superblocks based on the number of valid pages included in the small polycrystalline regions in the full state in each candidate superblock.

14. The operating method as described in claim 13, wherein, The information regarding the effective pages included in the small polycrystalline region includes information about the number of effective pages included in the small polycrystalline region that is in the full state in each of the superblocks within the memory device.

15. The operating method as described in claim 13, wherein, Selecting the sacrificed superblock from the candidate superblocks includes: calculating the cost based on the number of small polycrystalline regions in the ready-to-reset state in each of the candidate superblocks; modifying the cost based on the number of valid pages included in the small polycrystalline regions in the full state in each of the candidate superblocks; and comparing the modified cost of the candidate superblocks.

16. The operating method as described in claim 13 further includes: Copy the data stored in the small polycrystalline region that is in the full state in the sacrificial superblock; The copied data is stored in another superblock; and the sacrificed superblock is erased.

17. The operating method as described in claim 16, wherein, The other superblock is a superblock that includes multiple of the smaller polycrystalline regions.

18. The operating method as described in claim 11, wherein, At least one of the superblocks within the memory device is a superblock comprising a plurality of small single-cell regions, each of the small single-cell regions comprising one or more memory blocks in a memory cell.

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