Plasma processing apparatus with tunable electrical characteristic

Abstract

A plasma processing apparatus includes: a plasma processing chamber; a source power coupling element configured to generate plasma within the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency; a substrate holder disposed within the plasma processing chamber; a DC coupling element coupled to the DC pulse generator; a DC current path including the DC coupling element, the plasma, and a reference potential node arranged in series, the DC coupling element being configured to bias the substrate holder relative to the reference potential node using the DC pulse train; and a capacitive pre-coating disposed between the DC coupling element and the plasma. The capacitive pre-coating increases the RC time constant of the DC current path according to the DC pulse frequency.

Description

[Technical Field]

[0001] Cross-reference to related patents and applications: This application claims priority to U.S. Nonprovisional Patent Application No. 17 / 337,067, filed June 2, 2021. The entire disclosure of the aforementioned application is incorporated herein by reference.

[0002] The present invention generally relates to plasma processing, and in particular embodiments, to apparatus and method for performing plasma processing using plasma processing equipment having tunable electrical characteristics. [Previous Technology]

[0003] The formation of devices within microelectronic components may involve a range of manufacturing techniques, including the formation, patterning, and removal of multiple material layers on a substrate. To achieve the physical and electrical specifications of current and next-generation semiconductor devices, various patterning processes require workflows that allow for reduction in feature size while maintaining structural integrity.

[0004] Plasma processes are commonly used to form devices in microelectronic workpieces. For example, plasma etching and plasma deposition are common process steps during semiconductor device fabrication. A combination of source power and bias power can be used to generate and direct plasma during plasma processing. During plasma processes, a sequence of direct current (DC) pulses can be applied as a bias voltage. Short DC pulse trains (i.e., sequences) can be used to increase the flux of high-energy ions to the substrate.

[0005] Various parameters such as DC pulse frequency and duty cycle affect the ratio of ions to free radicals and other plasma parameters. DC pulse frequency and duty cycle also affect charge accumulation on biased electrodes. Charging of biased electrodes reduces voltage, which undesirably leads to a decrease in ion flux at the substrate. However, due to the dependence of the ion energy distribution function (IEDF) on DC pulse frequency and duty cycle, it is undesirable to manipulate these parameters to reduce substrate charging. [Summary of the Invention]

[0006] According to an embodiment of the present invention, a plasma processing apparatus includes: a plasma processing chamber; a source power coupling element configured to generate plasma within the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency; a substrate holder disposed within the plasma processing chamber; a DC coupling element coupled to the DC pulse generator; a DC current path including the DC coupling element, the plasma, and a reference potential node arranged in series, the DC coupling element being configured to bias the substrate holder relative to the reference potential node using the DC pulse train; and a capacitive pre-coating disposed between the DC coupling element and the plasma. The capacitive pre-coating increases the RC time constant of the DC current path according to the DC pulse frequency.

[0007] According to another embodiment of the present invention, a plasma processing apparatus includes: a plasma processing chamber; a source power coupling element configured to generate plasma within the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train including a DC pulse frequency; a substrate holder disposed within the plasma processing chamber; a DC coupling element coupled to the DC pulse generator; a DC current path including the DC coupling element, the plasma, and a reference potential node arranged in series; and a tuning circuit coupled between the DC coupling element and the DC pulse generator. The DC coupling element is configured to bias the substrate holder relative to the reference potential node using the DC pulse train. The tuning circuit includes a variable capacitor. The tuning circuit is configured to tune the RC time constant of the DC current path by changing the variable capacitor according to the DC pulse frequency.

[0008] According to yet another embodiment of the present invention, a method for tuning an electrical characteristic of a plasma processing chamber of a plasma processing apparatus, the method comprising: determining a capacitance value from a capacitance value range based on the DC pulse frequency of a DC pulse train generated by a DC pulse generator of the plasma processing apparatus; tuning the electrical characteristic by selecting the determined capacitance value using a tuning circuit coupled between a DC coupling element and the DC pulse generator, the tuning circuit including a variable capacitor tunable within the capacitance value range; and biasing the DC coupling element relative to a reference potential node by generating the DC pulse train at the DC pulse frequency using the DC pulse generator.

Implementation Method

[0023] The various embodiments and their manufacture and use are discussed in detail below. However, it should be understood that the various embodiments described herein are applicable to a variety of specific contexts. The specific embodiments discussed are merely illustrative of particular ways of making and using the various embodiments and should not be construed as limiting the scope.

[0024] DC pulse trains can be used to generate high-flux, high-energy ions at a substrate. For example, a DC pulse train can accelerate ions toward the substrate by creating a voltage difference between the substrate and the plasma. As part of a pulsed plasma process, short DC pulse trains can be applied during the plasma afterglow phase (e.g., applying pulse source power and bias power). DC pulse trains can be used in a variety of applications, such as gate etching, patterning, high aspect ratio contact window (HARC) etching, and memory fabrication.

[0025] However, the flux and energy of the ions depend on the ability to maintain a voltage difference between the plasma and the substrate surface. Charging at the substrate causes this voltage difference to decrease, and thus reduces the effectiveness of the applied voltage over time. Therefore, the effect of each DC pulse must be controlled at the electrodes (e.g., at dielectric-covered electrodes).

[0026] Conventional DC pulse implementations have various drawbacks. Difficulties arise due to the difference between the optimal parameter values ​​for the given process (e.g., pulse length, pulse frequency, duty cycle) and the parameter values ​​required to maintain the plasma sheath. For example, it may be undesirable to change the DC pulse frequency and duty cycle of the given process, even if doing so might reduce charging. Therefore, it may be desirable to have a plasma processing apparatus that can reduce the substrate charging rate without changing the DC pulse frequency or duty cycle.

[0027] The RC electrical characteristics of the plasma processing chamber (i.e., as seen in the DC power supply) significantly affect the charging and discharging of the substrate during the application of a DC bias voltage. Therefore, the period during which the sheath voltage can be maintained largely depends on the RC time constant τ of the chamber. It is generally desirable to maintain the sheath voltage for as long as possible with each DC pulse. By controlling the RC time constant τ, the DC voltage response at the substrate during the application of a DC pulse train can be controlled for any pulse length, pulse frequency, and duty cycle.

[0028] The RC time constant τ can be tuned by changing the resistance and / or capacitance of the DC current path between the DC power supply and a reference potential (e.g., the ground potential of the grounding wall of a plasma processing chamber). Capacitance adjustment can be achieved by adding one or more capacitors between the DC coupling element (e.g., an electrostatic chuck) and the DC power supply. Alternatively or additionally, a capacitive pre-coating can be formed on the DC coupling element, resulting in a significant increase in capacitance. Similarly, resistance can be adjusted by applying a resistive pre-coating to various inner surfaces of the plasma processing chamber or by adding resistors at various points along the DC current path.

[0029] A tuning circuit may be included between the DC pulse generator and the DC coupling element. The tuning circuit may include various capacitors, such as fixed capacitors and variable capacitors. The capacitors may be arranged as a group of capacitors in parallel. One or more switches may be used to select individual capacitors, capacitor groups, or other subsets of capacitors. A short-circuit path between the DC pulse generator and the DC coupling element may also be included and may be selected by one or more switches.

[0030] The plasma processing equipment and method described herein can advantageously provide more margin and efficiency to the DC pulse train process. For example, at low DC pulse frequencies, substrate charging can reduce or eliminate the desired effects of the DC pulse train. The equipment and method described herein can advantageously reduce the effects of substrate charging at lower DC pulse frequencies.

[0031] Reduced substrate charging can also provide the benefit of allowing control over the IEDF. In particular, compared to conventional DC pulse train processes, ion energy distribution can be reduced, average ion energy can be increased, and high-energy ion flux at the substrate can be increased. Control over energy distribution and ion energy flux can be desirable in order to approach the ideal monoenergetic flux for a given process.

[0032] The various embodiments described herein can advantageously allow the electrical characteristics of the plasma processing apparatus to be tuned to different DC pulse frequencies. For example, a tuning circuit including a variable capacitor can be used to select an appropriate capacitor (and / or resistor) in order to tune the electrical characteristics of the plasma processing chamber as seen from the bias power supply according to the desired DC pulse frequency.

[0033] The embodiments provided below describe various apparatuses and methods for plasma processing, and in particular, apparatuses and methods for plasma processing including tunable electrical characteristics. The embodiments are described below. FIG1 is used to describe an example schematic timing diagram of an embodiment plasma processing method. FIG2 is used to describe various qualitative graphs and corresponding qualitative IEDF graphs of the voltage as a function of time corresponding to the embodiment plasma processing method at a given DC pulse frequency. FIG3 is used to describe an embodiment plasma processing apparatus. Some other embodiment plasma processing apparatuses are described using FIG4-6. An embodiment tuning circuit is described using FIG7. Next, three more embodiment tuning circuits are described using FIG8-10. FIG11 describes another embodiment plasma processing apparatus. FIG12 describes an embodiment method.

[0034] FIG1 illustrates a schematic timing diagram of an example plasma treatment method according to an embodiment of the present invention.

[0035] Referring to Figure 1, a schematic timing diagram 100 illustrates the application of source power (SP) and bias power applied in the form of DC voltage in a plasma processing apparatus. SP pulses 111 and a series of DC pulses 115 including a sequence of DC pulses 113 are shown. The SP pulses 111 and the series of DC pulses 115 can be a cycle of a repeating process with an SP pulse period TSP. Each SP pulse 111 has an SP pulse duration tSP, which indicates the length of time the source power is continuously applied in a given period. The SP duty cycle DSP can be defined as tSP / TSP. Similarly, each DC pulse has a DC pulse duration tDC and a DC pulse period TDC, where the DC duty cycle DDC is defined as tDC / TDC. As shown, multiple DC pulses 113 (i.e., multiple periods TDC) are applied in each SP pulse period TSP. A 50% DC duty cycle (DDC = 0.5) is shown, but both DDC and DSP can be any value between 0 and 1.

[0036] The source power can be alternating current (AC) power. For example, the source power can be radio frequency (RF) power having an SP frequency fS. A delay td can be included between the application of the source power and the application of the bias power in the form of a DC pulse train 115. In some cases, a delay can also be included between the DC pulse train 115 and the subsequent SP pulse 111.

[0037] The DC pulse train 115 is applied at a DC pulse frequency fDC corresponding to the rate at which continuous DC pulses 113 are applied (i.e., fDC = 1 / TDC). The DC pulse frequency fDC is less than the SP frequency fSP. In various embodiments, fDC is less than about 1000 kHz. In some embodiments, fDC is less than about 20 kHz and may be on the order of less than 1 kHz. The DC pulse period TDC of fDC is (TDC = 1 µs when fDC = 1000 kHz, TDC = 50 µs when fDC = 20 kHz, and so on).

[0038] Even at higher DC pulse frequencies (e.g., above 100 kHz), the DC pulse train 115 differs from low-frequency RF power applications because the bias power does not oscillate, but rather removes a fraction of 1-DDC from each period. However, when fDC increases to over 1000 kHz (e.g., due to rise and fall rate limitations), the various benefits of applying short DC pulse trains may diminish.

[0039] The SP pulse period TSP is much longer than the DC pulse period TDC. For example, in one embodiment, the SP pulse 111 can be applied at a frequency between approximately 1 kHz and approximately 10 kHz, although it can be much lower. This corresponds to a TSP between approximately 10 µs and approximately 1 ms. Therefore, the range of tSP can be from approximately 5 µs to approximately 25 µs or longer.

[0040] It should be noted that the relative power levels of the source power and bias power are not shown on timing diagram 100. Similarly, the relative pulse length and the number of DC pulses in a single SP cycle are not represented in timing diagram 100 for better understanding. That is, as implied by the example frequencies and pulse lengths above, it is not uncommon for more than 50 DC pulses to occur in a given SP cycle.

[0041] Figure 2 illustrates a time-dependent voltage characterization plot according to an embodiment of the present invention, and a corresponding characterization plot of the ion energy distribution function for several RC time constants at a fixed DC pulse frequency.

[0042] Referring to Figure 2, qualitative graph 200 illustrates the effect of changing the time constant τ while maintaining a DC pulse frequency fDC of 400 kHz and a duty cycle of 50% (DDC = 0.5). Throughout the top row of voltage graphs, the rod electrode response (e.g., for DC-coupled elements) remains constant and is shown as the dashed curve 120. As τ increases from τ = 0.2 µs to τ = 20 µs, the voltage response at the substrate surface is shown as solid curves 121-125. In this example, the voltage at the substrate surface is shown as negative, but it could also be positive, depending on the configuration of the reference potential and the applied bias power.

[0043] As shown in curve 121, at τ = 0.2 µs, the voltage at the substrate surface initially decreases with the rod electrode response, but then increases sharply due to charging, even before reaching the minimum voltage of the rod electrode. This results in a steep return slope, which significantly deviates from the approximate square wave response of the rod electrode. At τ = 1 µs (curve 122), the slope decreases, but the voltage still does not reach the minimum voltage of the rod electrode, and the voltage overshoot at the rising edge of the rod voltage becomes more pronounced. At τ = 5 µs, the slope at the bottom of surface curve 123 begins to approach the flat square wave of the rod voltage. The surface voltage reaches the minimum voltage and increases by only about 15% during the 1.25 µs duration of the DC pulse.

[0044] As τ increases to 10 µs and then to 20 µs, the slope continues to flatten, but with a decreasing return as the slope almost mirrors the rod response. Therefore, the slope at the bottom of curve 124 is very similar to the slope at the bottom of curve 125. On the other hand, the voltage overshoot changes more significantly from τ = 10 µs to τ = 20 µs, as it also begins to approach the rod electrode response.

[0045] IEDF Figures 131-135 show the IEDF generated at the substrate surface and correspond to curves 121-125 respectively. Due to the short time the surface spends under negative voltage, the IEDF shown in Figure 131 at τ = 0.2 µs has low energy (~700 eV) and a large development (indicated by the double-sided arrows). Similarly, at τ = 1 µs (Figure 132), the ion energy increases overall but still only reaches about 950 eV, with a development of ~500 eV. Lower ion energy can be disadvantageous because more voltage is required to achieve the desired ion energy. However, a large energy development may be even more undesirable because many ions reaching the substrate will not have the energy required to produce the desired effect. This can lead to decreased process efficiency and make certain processes impractical.

[0046] In contrast, Figure 133 shows that the ion energy system reaching 1 keV at τ = 5 µs matches the applied voltage of -1 kV. Furthermore, the flattening of the slope results in a much smaller energy expansion of ~200 eV. Figures 134 and 135 illustrate that as τ increases to 10 µs and 20 µs, the energy expansion continues to decrease and the number of high-energy ions increases.

[0047] The period TDC for fDC = 400 kHz is 2.5 µs. From the above analysis, it can be seen that τ = 5 µs has various advantages in terms of surface voltage and the resulting IEDF. Since 5 µs is twice the period of 2.5 µs, a generally favorable objective for τ for a given fDC might be τ ≥ 2 / fDC. In other words, the RC time constant is at least twice the reciprocal of the DC pulse frequency. For example, this objective gives: for fDC = 1000 kHz, τ = 2 µs; and for fDC = 20 kHz, τ = 100 µs.

[0048] However, it should be noted that this objective may or may not accurately describe the desired τ, depending on the specific details of a given application. For example, increasing τ for a given fDC may have a continuous beneficial effect from the outset, not just when a specific objective is achieved. Therefore, some applications may use τ < 2 / fDC (e.g., if 2 / fDC is impractical). Similarly, τ may often be near 2 / fDC, but may also be much greater than this value in applications requiring a near-perfect square wave response at the substrate surface.

[0049] The duty cycle DDC may affect the target τ. For example, the IEDF expansion may increase with increasing DDC (> 0.5) and decrease with decreasing DDC (< 0.5). Therefore, it may be desirable to have a higher τ for a higher DDC and a lower τ for a lower DDC in a given plasma process compared to the target τ at 50% duty cycle.

[0050] Figure 3 shows a schematic diagram of an example plasma processing apparatus including a DC current path between a bias power supply and a reference potential node according to an embodiment of the present invention. The plasma processing apparatus of Figure 3 can be configured to perform the plasma processing method as described herein, for example, according to the timing diagram of Figure 1.

[0051] Referring to FIG. 3, the plasma processing apparatus 300 includes a plasma processing chamber 302 coupled to a source power supply 307 and a bias power supply 309. The source power supply 307 is configured to generate plasma 306 within the interior 303 of the plasma processing chamber 302. The source power supply 307 can generate capacitively coupled plasma (CCP) (e.g., FIG. 11), inductively coupled plasma (ICP), surface wave plasma (SWP), etc. For example, the source power can be coupled to a helical resonator antenna that generates plasma 306 within the plasma processing chamber 302.

[0052] In this illustrative example, the source power supply 307 is coupled to the top of the plasma processing chamber 302, and the bias power supply 309 is coupled to the substrate holder 304 inside the plasma processing chamber 302 303, but other configurations are possible. The substrate holder 304 is configured to support the substrate 305. For example, the substrate holder 304 may be an electrostatic chuck (ESC). Alternatively, the substrate holder may be a vacuum chuck or other suitable support structure.

[0053] The DC pulse generator 308 is coupled between the bias power supply 309 and the substrate holder 304. The DC pulse generator 308 is configured to generate a DC pulse train at a DC pulse frequency. For example, the DC pulse generator 308 and the bias power supply 309 can be combined to apply a DC pulse train to the substrate holder, as shown in the timing diagram 100 of FIG1.

[0054] The reference potential node 345 is coupled to the plasma processing chamber 302. In one embodiment, the reference potential node 345 is coupled to a wall of the plasma processing chamber 302, as shown. In one embodiment, the reference potential node 345 is a ground connection. The reference potential node 345 establishes a DC current path 340 between the bias power supply 309 and the reference potential node 345. The behavior of the DC current path 340 can be modeled as including a resistive component 341 and a capacitive component 343.

[0055] Plasma 306 itself provides a conductive portion of the DC current path 340. It should be noted that, for readability purposes only, the dashed boundary of plasma 306 is drawn to stop before the walls of the plasma processing chamber 302 and the substrate holder 304 / substrate 305. That is, plasma 306 actually extends to and interfaces with the walls of the plasma processing chamber 302, the substrate holder 304, and the substrate 305.

[0056] Furthermore, it should be recognized that this simplified model is conceptual. The actual current paths contributing to resistor 341 and capacitor 343 may be much more complex than depicted. That is, plasma current can travel along all surfaces of the chamber. The chamber surfaces may have inductors, resistors, and capacitors that contribute to the overall behavior of the circuit. There may also be many other sources of contribution for resistor 341 and capacitor 343 (many of which will be discussed below).

[0057] The resistor assembly 341 and capacitor assembly 343 of the DC current path 340 contribute to the electrical characteristics of the plasma processing chamber 302, as seen in the bias power supply 309. In this simplified model, the DC current path 340 is a series RC circuit with a time constant τ equal to RC, where R is the resistance of the resistor assembly 341 and C is the capacitance of the capacitor assembly 343. As previously shown with reference to FIG2, tuning the time constant τ improves the voltage response at the substrate 305 and advantageously results in less ion energy spread, higher ion energy, and increased ion flux at the substrate 305.

[0058] Of course, some physical components may contribute to one or both of the resistor assembly 341 and the capacitor assembly 343. As will become apparent from the following description, although the positions of the resistor assembly 341 and the capacitor assembly 343 may represent the positions of some corresponding physical components, such specific positions are also variable within the plasma processing apparatus.

[0059] FIG4 illustrates a schematic diagram of an example plasma treatment apparatus including a selective capacitive pre-coating and a selective resistive pre-coating according to an embodiment of the present invention. The plasma treatment apparatus of FIG4 may be a specific embodiment of other plasma treatment apparatuses described herein, such as the plasma treatment apparatus of FIG3. Elements with similar markings may be as described above.

[0060] Referring to FIG4, the plasma processing apparatus 400 includes a substrate holder 404 disposed within a plasma processing chamber 402, which is coupled to a source power supply 407 configured to generate plasma 406. A bias power supply 409 is coupled to a DC pulse generator 408, which in turn is coupled to a DC coupling element 453 disposed in the substrate holder 404.

[0061] It should be noted that, for the sake of brevity and clarity, a convention is adopted here and below, wherein the elements according to this pattern [x10] can be related embodiments of the plasma processing chamber in various embodiments. For example, plasma processing chamber 402 can be similar to plasma processing chamber 302, unless otherwise stated. Similar conventions are adopted for other elements, as can be clearly seen by using similar terminology and in conjunction with the three-digit numbering system described above.

[0062] The reference potential node 445 is coupled to one wall of the plasma processing chamber 402. A DC current path is established from the bias power supply 409, through the DC coupling element 453 and the plasma 406, to the reference potential node 445.

[0063] The substrate holder 404 is configured to support a substrate 405. A capacitive pre-coating 444 may be disposed on the upper surface of the substrate holder 404, between the substrate holder 404 and the substrate 405. However, other configurations are also possible. In some embodiments, the capacitive pre-coating 444 may also be omitted (e.g., advantageous alternatives or in embodiments using only additional resistor components).

[0064] The capacitive pre-coating 444 increases the capacitance of the DC current path (used as a capacitor assembly). For example, the capacitance of the capacitive pre-coating 444 can be written as C = εAC / lC, where ε is the permittivity, AC is the area, and lC is the thickness of the capacitive pre-coating 444. While many configurations are possible and depend on the details of a given application, an example set of values ​​might be ε = 6 nF / m, AC = (100 mm)², and lC = 600 µm, which would result in a capacitance C of 100 nF.

[0065] For a given substrate size (e.g., wafer size), A can remain constant, while the permittivity ε (i.e., relative permittivity / dielectric constant) and thickness lC can be varied to achieve the desired capacitance C. For applications involving substrates of different sizes (e.g., larger wafers), A may affect the selection of ε and lC by increasing capacitance. In some cases, materials with higher or lower dielectric constants may be required to ensure an appropriate capacitive pre-coating thickness.

[0066] The capacitive pre-coating 444 includes a dielectric material in various embodiments and is a ceramic material in some embodiments. The capacitive pre-coating 444 may include silicon, and in one embodiment includes silicon dioxide (SiO2). In another embodiment, the capacitive pre-coating 444 includes yttrium oxide (Y2O3).

[0067] However, various dielectric materials may be suitable for use as capacitive pre-coatings 444. As shown in the aforementioned equations, using materials with higher or lower dielectric constants simply requires increasing or decreasing the thickness lC accordingly. Other considerations may also be taken into account, such as process compatibility, potential dielectric breakdown, and other material properties.

[0068] It is well known that the dielectric constant of a given material depends on various factors. For example, those skilled in the art will recognize that the dielectric constant is frequency-dependent. In the context of this disclosure, the dielectric constant (and by extension, permittivity) in the capacitance equation is assumed to be considered under operating conditions at the applied frequency (e.g., DC pulse frequency). Given this description, it is assumed that those skilled in the art will be able to appropriately adjust the thickness of the capacitive pre-coating based on various details of a given application.

[0069] A resistive pre-coating 442 with a thickness of lR may be included on the surface of the interior 403 of the plasma processing chamber 402. Although the resistive pre-coating 442 is included on the surface of the plasma processing chamber 402 here, other configurations are possible (e.g., depending on the location and configuration of the reference potential node 445). In some embodiments, the resistive pre-coating 442 may be omitted (e.g., as an alternative or in embodiments using only additional capacitive components).

[0070] Similar to the capacitive pre-coating 444 discussed above, the resistive characteristics of the resistive pre-coating 442 increase the resistance of the DC current path (acting as a resistive component). The geometry of the plasma processing chamber 402 affects the resistance R of the resistive pre-coating 442. For example, the resistance R = ρl / AR, where ρ is the resistivity, AR is the cross-sectional area perpendicular to the DC current flow direction, and l is the length of the resistive pre-coating 442 in the DC current flow direction. Although the resistive pre-coating 442 is only shown as covering the vertical side of the plasma processing chamber 402, it should be understood that other surfaces, such as the top surface of the plasma processing chamber 402 or the side surfaces of the substrate holder 404, may also be covered.

[0071] Assuming the current travels along the surface of the plasma processing chamber 402, AR can be approximated as 2πr × lR, where r is the radius of the plasma processing chamber 402 (for a cylindrical chamber, but any suitable chamber shape can be used). The length l is the average distance the current must travel to reach the reference potential node. As one would expect, many configurations are possible and depend on various specific factors for a given application. An example set of values ​​could be ρ = 10⁻⁵ Ω·m, AR = 2π(0.15 m)(100 nm) ≈ 10⁻⁷ m², and l = 0.1 m, which would result in a resistance R of approximately 1 kΩ.

[0072] The τ value, which significantly improves the voltage response at the surface of substrate 405 using capacitive pre-coating 444 and resistive pre-coating 442, can be advantageously achieved over a wide frequency range. For example, for C = 100 nF and R = 1 kΩ, τ = 100 µs (= 2 / 20 kHz). Doubling C and R results in τ = 400 µs, corresponding to fDC = 5 kHz. Although there may be some practical limitations regarding the maximum values ​​of C and R, at advantageous low DC pulse frequencies fDC, the effects of charging can be reduced for most of the duration of each DC pulse.

[0073] In various embodiments, the resistive pre-coating 442 comprises a resistive material. In one embodiment, the resistive pre-coating 442 comprises amorphous carbon (aC). In another embodiment, the resistive pre-coating 442 comprises graphitic carbon. The resistive pre-coating 442 may also comprise a graphitic carbon-based material. Furthermore, the resistive pre-coating 442 may also comprise a silicon-like material, or a silicon dioxide-like material, and other materials. Since the resistive pre-coating 442 is exposed to the plasma 406 and the substrate 405, the choice of material may be influenced by process compatibility. For example, a carbon-based resistive pre-coating may be compatible with Si and SiO2 etching processes.

[0074] FIG. 5 illustrates a schematic diagram of an example plasma processing apparatus including a tuning circuit with a variable capacitor according to an embodiment of the present invention. The plasma processing apparatus of FIG. 5 may be a specific embodiment of other plasma processing apparatuses described herein, such as the plasma processing apparatus of FIG. 3. Elements with similar markings may be as described above.

[0075] Referring to FIG5, the plasma processing apparatus 500 includes a substrate holder 504 configured to support a substrate 505 and disposed within a plasma processing chamber 502, which is coupled to a power supply 507 configured to generate plasma 506. A tuning circuit 501 is coupled between a DC pulse generator 508 and a DC coupling element 553 disposed in the substrate holder 504. A bias power supply 509 is coupled to the DC pulse generator 508. A reference potential node 545 is coupled to the plasma processing chamber 502.

[0076] The tuning circuit 501 has a variable capacitance. That is, the capacitance of the tuning circuit 501 can be changed to adjust the electrical characteristics of the plasma processing chamber 502. In one embodiment, the electrical characteristics are the time constant τ of the DC current path between the bias power supply 509 and the reference potential node 545. The capacitance of the tuning circuit 501 can be tuned manually or automatically, and during or between operations of the plasma processing apparatus 500. The capacitance of the tuning circuit 501 can be selected mechanically, electronically, electrically, or by any other suitable selection mechanism.

[0077] The tuning circuit 501 may also include a static or variable resistor component. In some cases, it may be desirable to incorporate such an additional resistor component between the substrate 505 and the reference potential node 545, rather than between the substrate 505 and the bias power supply 509, to prevent unnecessary voltage drops between the substrate 505 and the bias power supply 509.

[0078] FIG. 6 shows a schematic diagram of an example plasma treatment apparatus according to an embodiment of the present invention, including a tuning circuit and optional capacitive pre-coating and optional resistive pre-coating. The plasma treatment apparatus of FIG. 6 may be a specific embodiment of other plasma treatment apparatuses described herein, such as the plasma treatment apparatus of FIG. 3. Components marked similarly may be as described above.

[0079] Referring to FIG6, the plasma processing apparatus 600 includes a substrate holder 604 configured to support a substrate 605 and disposed within the interior 603 of a plasma processing chamber 602. A tuning circuit 601 is coupled between a DC pulse generator 608 and a DC coupling element 653 disposed within the substrate holder 604. A bias power supply 609 is coupled to the DC pulse generator 608. A reference potential node 645 is coupled to the plasma processing chamber 602.

[0080] The source power supply 607 configured to generate plasma 606 is coupled to the source power coupling element 651. In one embodiment, the source power coupling element 651 is an inductive coupling element that couples the source power through an insulator 655 (as shown) to the plasma processing chamber 602, but other configurations are also possible.

[0081] A capacitive pre-coating 644 may be disposed on the upper surface of the substrate holder 604, between the substrate holder 604 and the substrate 605. A resistive pre-coating 642 may be disposed on the surface of the interior 603 of the plasma processing chamber 602. In some embodiments, either the capacitive pre-coating 644 or the resistive pre-coating 642 may be omitted.

[0082] In embodiments that include both the tuning circuit 601 and the capacitive pre-coating 644, the total capacitance C of the DC current path between the bias power supply 609 and the reference potential node 645 is the combination of these two capacitive components. Since the tuning circuit 601 is connected in series with the capacitive pre-coating 644, C = (1 / Cfixed + 1 / Ctuning) - 1.

[0083] Due to the form of the series capacitor equation, C will always be less than Cfixed and will approach Cfixed as Ctuning becomes very large. In some cases, the tuning circuit 601 may include a short-circuit option that, when selected, does not increase the capacitance and allows C to be equal to Cfixed. Since even a value of Ctuning much greater than Cfixed (e.g., 10 times) still only results in C being 91% of Cfixed, if a C equal to Cfixed is required, the short-circuit option can be used to bypass the tuning circuit 601.

[0084] FIG7 illustrates a schematic diagram of an example tuning circuit including a single-pole switch and a plurality of capacitors according to an embodiment of the present invention. The tuning circuit of FIG7 may be a specific implementation of other tuning circuits described herein, such as the tuning circuits of FIG5 and 6. Components with similar markings may be as previously described.

[0085] Referring to FIG. 7, the tuning circuit 701 includes a first tuning input / output 757 (e.g., for coupling to a DC coupling element) and a second tuning input / output 759 (e.g., for coupling to a DC pulse generator). The tuning circuit 701 also includes a plurality of capacitors 760, which may include a fixed capacitor 762 as shown. In various embodiments, the fixed capacitor 762 is a high-reliability capacitor. In some embodiments, some or all of the fixed capacitor 762 are vacuum capacitors. In some embodiments, some or all of the fixed capacitor 762 are ceramic capacitors.

[0086] The first single-pole switch 771 includes a single pole (input) coupled to the first tuning input / output 757 and at least one throw (output) coupled to a subset of the plurality of capacitors 760. An optional second single-pole switch 772 may be coupled between the subset of the plurality of capacitors 760 and the second tuning input / output 759 (e.g., to further isolate current paths not selected from the selected current path). The positions of the first single-pole switch 771 and the optional second single-pole switch 772 may be switched. Optionally, a short-circuit path 764 is also included between the first tuning input / output 757 and the second tuning input / output 759.

[0087] In some embodiments, the first single-pole switch 771 (and optionally the second single-pole switch 772) is a mechanical switch. In one embodiment, this mechanical switch is a motor switch. In other embodiments, other suitable switches, such as electrical switches, may be used. However, it should be noted that care should be taken to avoid dielectric breakdown and parasitic effects caused by the application of high voltage.

[0088] In one embodiment, the first single-pole switch 771 is a single-pole multi-throw switch (as shown), including multiple outputs coupled to multiple subsets of the plurality of capacitors 760. In another embodiment, the first single-pole switch 771 is a single-pole single-throw switch, and the tuning circuit 701 includes an additional single-pole single-throw switch coupled to the plurality of capacitors. Other combinations of single-pole switches are, of course, possible.

[0089] The plurality of capacitors 760 may be arranged as several capacitor banks 763. In one embodiment, the capacitor bank 763 is a physical grouping of individual capacitors. One (or two, if including a selectable switch) single-pole multi-throw switch may be used to select among several capacitor banks that are completely isolated from each other. In another embodiment, the capacitor bank 763 is a logical grouping (e.g., some or all of these capacitors are used in more than one logical group).

[0090] This subset of the plurality of capacitors 760 can be mutually exclusive. However, using the same capacitors in more than one subset can reduce the number of capacitors required to achieve a given range of variable capacitance, but may also increase the complexity of the tuning circuit or allow parasitic currents within the tuning circuit. In a particular example, the first unipolar switch 771 is a rotary switch whose output is coupled to n fixed capacitors 762. The rotary switch has n+1 positions, including positions for coupling the various numbers of capacitors from 1 to n and positions for coupling the zero-coupling capacitor (short-circuit path 764). A variant omits the short-circuit path 764 and includes only n positions.

[0091] In another specific example, the capacitor system is configured in n capacitor banks, each comprising 2m capacitors, where m ranges from 0 to n–1. A number of n single-pole single-throw switches can then be used to select the combination of banks, resulting in 1 to n–1 coupled capacitors. Additional single-pole single-throw switches can allow selection of short-circuit path 764 if short-circuit path 764 is included.

[0092] In fact, a selected subset of this plurality of capacitors 760 forms the previously discussed capacitance Ctuning. Since it is not required that the constituent capacitors of this plurality of capacitors be identical, Ctuning can be customized according to the needs of a given application. However, a simple example of n identical fixed capacitors 762, each having a capacitance C0, is useful for illustrating the function of the tuning circuit 701. Then, Ctuning = nC0. In the absence of other capacitor components, the variable capacitance of the tuning circuit 701 will range from 0 to nC0 in discrete C0 steps.

[0093] However, if another capacitor component (e.g., a capacitive pre-coated capacitor) is included in series, the total capacitance Cn = (1 / Cfixed + 1 / nC0) - 1. Although n cannot be zero in this equation, it should be noted that the case of n = 0 (choosing a short-circuit path) will make C = Cfixed, as previously stated. In the specific example where Cfixed = 100 nF and C0 = 5 nF, Cn = 1, 2, 3... = {4.8 nF, 9.1 nF, 13 nF, …}. Of course, fixed capacitors with capacitance values ​​lower and higher than 5 nF can be used.

[0094] The increase in total capacitance for each added capacitor decreases as n increases. For example, C20 = 50 nF, but C30 = 60 nF. It is worth noting that without Cfixed, C20 = 100 nF and C30 = 150 nF. Therefore, when a high maximum capacitance (e.g., 100 nF) is desired, a combination of a capacitive pre-coating and a tuning circuit may be required, but there is not enough space in the tuning circuit to accommodate a large number of capacitors. A relatively small number of capacitors in the tuning circuit will allow for a lower range of particle capacitance selection, for example, from approximately 5 nF (n = 1) to approximately 33 nF (n = 10).

[0095] FIG8 illustrates a schematic diagram of an example tuning circuit including a single-pole switch and a plurality of variable capacitors according to an embodiment of the present invention. The tuning circuit of FIG8 may be a specific implementation of other tuning circuits described herein, such as the tuning circuit of FIG7. Components with similar markings may be as previously described.

[0096] Referring to FIG8, the tuning circuit 801 includes a first tuning input / output 857, a second tuning input / output 859, and a plurality of capacitors 860, which may include variable capacitors 861 disposed in a plurality of capacitor banks 863, as shown. In various embodiments, the variable capacitors 861 are high-reliability capacitors. In some embodiments, some or all of the variable capacitors 861 are vacuum capacitors. In some embodiments, some or all of the variable capacitors 861 are ceramic capacitors. The tuning circuit 801 also includes a first single-pole switch 871 and may also include an optional second single-pole switch 872. An optional short-circuit path 864 may also be included.

[0097] The difference between tuning circuit 801 and tuning circuit 701 is that a variable capacitor 861 is used instead of a fixed capacitor. This may have the additional advantage of allowing for smooth capacitance switching within the available range of variable capacitors. However, the variable capacitor may have a lower capacitance than the fixed capacitor and may also be larger and more expensive.

[0098] FIG9 illustrates a schematic diagram of an example tuning circuit including a single-pole switch and a plurality of capacitors according to an embodiment of the present invention, wherein the plurality of capacitors includes a fixed capacitor and a variable capacitor. The tuning circuit of FIG9 may be a specific implementation of other tuning circuits described herein, such as the tuning circuit of FIG7. For example, elements marked similarly may be as previously described.

[0099] Referring to FIG. 9, the tuning circuit 901 includes a first tuning input / output 957, a second tuning input / output 959, and a plurality of capacitors 960, which may include variable capacitors 962 and fixed capacitors 961, arranged among a plurality of capacitor banks 963, as shown. The tuning circuit 901 also includes a first single-pole switch 971 and may also include an optional second single-pole switch 972. An optional short-circuit path 964 may also be included.

[0100] The difference between tuning circuit 901 and tuning circuits 701 and 801 is that it uses both a variable capacitor 962 and a fixed capacitor 961. This advantageously allows for an extended range of variable capacitors while also improving fine control of the capacitors.

[0101] FIG10 illustrates a schematic diagram of an example tuning circuit including a single-pole switch and a plurality of capacitors according to an embodiment of the present invention. The tuning circuit of FIG10 may be a specific implementation of other tuning circuits described herein, such as the tuning circuit of FIG7. Components with similar markings may be as previously described.

[0102] Referring to FIG. 10, the tuning circuit 1001 includes a first tuning input / output 1057, a second tuning input / output 1059, and a plurality of capacitors 1060, which may include fixed capacitors 1061 arranged in capacitor bank 1063, as shown. The tuning circuit 1001 also includes a first single-pole switch 1071 and may also include an optional second single-pole switch 1072.

[0103] Tuning circuit 1001 is a specific embodiment of tuning circuit 701 in which short-circuit paths are omitted. This configuration may be useful, for example, when the capacitive pre-coating is omitted. As previously mentioned, a variable capacitor may also be used in addition to or in place of fixed capacitor 1061.

[0104] FIG11 illustrates a schematic diagram of an exemplary plasma treatment apparatus according to an embodiment of the present invention, the plasma treatment apparatus including a capacitive pre-coating covering an upper electrode and a tuning circuit coupled to the upper electrode. The plasma treatment apparatus of FIG11 may be a specific embodiment of other plasma treatment apparatuses described herein, such as the plasma treatment apparatus of FIG3. Components marked similarly may be as described above.

[0105] Referring to FIG11, the plasma processing apparatus 1100 includes a substrate holder 1104 configured to support a substrate 1105 and disposed within the interior 1103 of the plasma processing chamber 1102. A source power supply 1107 configured to generate plasma 1106 is coupled to a source power coupling element 1151. A tuning circuit 1101 is coupled between a DC pulse generator 1108 and a DC coupling element 1153. A bias power supply 1109 is coupled to the DC pulse generator 1108. A reference potential node 1145 is coupled to the substrate holder 1104.

[0106] The plasma processing apparatus 1100 differs from the plasma processing apparatus shown in FIG3 in that the DC coupling element 1153 is implemented as the upper electrode at the top of the interior 1103 of the plasma processing chamber 1102. The voltage applied to the DC coupling element 1153 by the DC pulse generator 1108 can be positive (rather than negative) to generate a potential gradient that accelerates positive ions toward the substrate 1105, which can be at or near the reference potential. Thus, there is a DC current path from the bias power supply 1109 to the reference potential node 1145.

[0107] A selective capacitive pre-coating 1144 may be included on the DC coupling element 1153. Additionally, since the reference potential node 1145 is coupled to the substrate holder 1104 rather than the wall of the plasma processing chamber 1102, a resistive element may be included between the substrate 1105 and the reference potential node 1145. For example, a selective resistive pre-coating (not shown) may be included on the surface of the substrate holder 1104. Alternatively or additionally, a resistor may be included to increase resistance.

[0108] FIG12 illustrates an example method of plasma processing according to an embodiment of the present invention. The method of FIG12 can be combined with other methods and performed using the systems and apparatus described herein. For example, the method of FIG12 can be combined with any of the embodiments of FIG1-11. Although shown in a logical order, the arrangement and numbering of the steps in FIG12 are not intended to be limited thereto. The method steps of FIG12 can be performed in any suitable order or simultaneously with each other, as will be apparent to those skilled in the art.

[0109] Referring to FIG12, step 1201 of the plasma processing method 1200 includes determining a capacitance value from a capacitance value range based on the DC pulse frequency of a DC pulse train generated by a DC pulse generator of the plasma processing equipment. Step 1202 includes tuning an electrical characteristic by selecting the determined capacitance value using a tuning circuit coupled between a DC coupling element and the DC pulse generator, the tuning circuit including a variable capacitor tunable within the capacitance value range.

[0110] In the selective step 1203, plasma is selectively generated in the plasma processing chamber of the plasma processing apparatus by applying source power to the plasma processing chamber. Alternatively, plasma may already be present in the plasma processing chamber. Step 1204 includes biasing a DC coupling element relative to a reference potential node by generating a DC pulse train at a DC pulse frequency using a DC pulse generator. The DC coupling element may be biased during the afterglow phase of the plasma (e.g., after the source power is removed).

[0111] Exemplary embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entire specification and the claims filed herein.

[0112] Example 1. A plasma processing apparatus comprising: a plasma processing chamber; an SP coupling element configured to generate plasma within the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency; a substrate holder disposed within the plasma processing chamber; a DC coupling element coupled to the DC pulse generator; a DC current path including the DC coupling element, the plasma, and a reference potential node arranged in series, the DC coupling element being configured to bias the substrate holder relative to the reference potential node using the DC pulse train; and a capacitive pre-coating disposed between the DC coupling element and the plasma, the capacitive pre-coating increasing the RC time constant of the DC current path according to the DC pulse frequency.

[0113] Example 2. The plasma treatment apparatus of Example 1, wherein the capacitive pre-coating increases the RC time constant to at least twice the reciprocal of the DC pulse frequency.

[0114] Example 3. The plasma treatment apparatus of one of Examples 1 and 2, wherein the capacitance of the capacitive pre-coating is approximately 100 nF.

[0115] Example 4. A plasma processing apparatus of one of Examples 1 to 3, wherein the thickness of the capacitive pre-coating is approximately 600 nm.

[0116] Example 5. A plasma treatment apparatus of one of Examples 1 to 4, wherein the capacitive pre-coating comprises silicon, silicon dioxide, or yttrium oxide.

[0117] Example 6. The plasma processing apparatus of one of Examples 1 to 5 further includes: a resistive pre-coating disposed on an inner surface of the plasma processing chamber; wherein the reference potential node is coupled to the plasma processing chamber; wherein the resistive pre-coating is disposed between the plasma and the reference potential node; and wherein the resistive pre-coating further increases the RC time constant of the DC current path according to the DC pulse frequency.

[0118] Example 7. The plasma treatment apparatus of Example 6, wherein the resistive pre-coating has a resistance of about 1 kΩ.

[0119] Example 8. The plasma processing apparatus of one of Examples 6 and 7, wherein the thickness of the resistive pre-coating is about 100 nm.

[0120] Example 9. The plasma treatment apparatus of one of Examples 6 to 8, wherein the resistive pre-coating comprises amorphous carbon, graphitic carbon, silicon-like material, or silicon dioxide-like material.

[0121] Example 10. The plasma processing apparatus of one of Examples 1 to 9 further includes: a tuning circuit coupled between the DC coupling element and the DC pulse generator, the tuning circuit including a variable capacitor.

[0122] Example 11. A plasma processing apparatus of one of Examples 1 to 10, wherein the substrate holder is an electrostatic chuck (ESC).

[0123] Example 12. A plasma processing apparatus of one of Examples 1 to 11, wherein the DC coupling element is disposed above the substrate holder; and the reference potential node is coupled to the substrate holder.

[0124] Example 13. A plasma processing apparatus includes: a plasma processing chamber; an SP coupling element configured to generate plasma within the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train including a DC pulse frequency; a substrate holder disposed within the plasma processing chamber; a DC coupling element coupled to the DC pulse generator; a DC current path including the DC coupling element, the plasma, and a reference potential node arranged in series, the DC coupling element being configured to bias the substrate holder relative to the reference potential node using the DC pulse train; and a tuning circuit coupled between the DC coupling element and the DC pulse generator, the tuning circuit including a variable capacitor configured to tune the RC time constant of the DC current path by changing the variable capacitor according to the DC pulse frequency.

[0125] Example 14. The plasma processing apparatus of Example 13, wherein the tuning circuit includes a variable capacitor.

[0126] Example 15. A plasma processing apparatus of one of Examples 13 and 14, wherein the tuning circuit includes: a plurality of capacitors; a first unipolar switch including an input coupled to the DC coupling element or the DC pulse generator, and a first output coupled to a first subset of the plurality of capacitors.

[0127] Example 16. The plasma processing apparatus of Example 15, wherein the first single-pole switch is a mechanical switch.

[0128] Example 17. The plasma processing apparatus of Example 16, wherein the first single-pole switch is a motor switch.

[0129] Example 18. A plasma processing apparatus of one of Examples 15 to 17, wherein the tuning circuit further includes: a second unipolar switch having an input coupled to the DC pulse generator and an output coupled to the first subset of the plurality of capacitors, wherein the first unipolar switch is coupled to the DC coupling element.

[0130] Example 19. A plasma processing apparatus of one of Examples 15 to 18, wherein the plurality of capacitors comprises a plurality of capacitor banks coupled in parallel to each other.

[0131] Example 20. A plasma processing apparatus of one of Examples 15 to 19, wherein the first unipolar open-circuit multi-throw switch includes a second output coupled to a second subset of the plurality of capacitors.

[0132] Example 21. Plasma treatment apparatus of Example 20, wherein the first single-pole multi-on / off relationship is a rotary switch.

[0133] Example 22. A plasma processing apparatus of one of Examples 20 and 21, wherein the first subset and the second subset of the capacitors are mutually exclusive.

[0134] Example 23. A plasma processing apparatus of one of Examples 15 to 18, wherein: the first unipolar switch is coupled to a single-throw switch; and the tuning circuit further includes a second unipolar single-throw switch, including an input coupled to the input of the first unipolar single-throw switch and an output coupled to a second subset of the plurality of capacitors.

[0135] Example 24. A plasma processing apparatus of one of Examples 15 to 23, wherein the plurality of capacitors comprises a plurality of fixed capacitors.

[0136] Example 25. The plasma processing apparatus of Example 24, wherein the plurality of capacitors further includes a variable capacitor.

[0137] Example 26. A plasma processing apparatus of one of Examples 15 to 25, wherein the first unipolar switch includes a second output coupled to the DC pulse generator or the DC coupling element such that when the second output is selected, a short-circuit path is formed between the DC coupling element and the DC pulse generator.

[0138] Example 27. The plasma processing apparatus of one of Examples 13 to 26 further includes: a resistive pre-coating disposed on an inner surface of the plasma processing chamber; wherein the reference potential node is coupled to the plasma processing chamber; wherein the resistive pre-coating is disposed between the plasma and the reference potential node; and wherein the resistive pre-coating further increases the RC time constant of the DC current path according to the DC pulse frequency.

[0139] Example 28. The plasma processing apparatus of Example 27 further includes: a capacitive pre-coating layer disposed between the DC coupling element and the plasma, the capacitive pre-coating layer increasing the RC time constant of the DC current path according to the DC pulse frequency.

[0140] Example 29. A method for tuning the electrical characteristics of a plasma processing chamber in a plasma processing apparatus, the method comprising: determining a capacitance value from a capacitance value range based on the DC pulse frequency of a DC pulse train to be generated by a DC pulse generator of the plasma processing apparatus; tuning the electrical characteristics by selecting the determined capacitance value using a tuning circuit coupled between a DC coupling element and the DC pulse generator, the tuning circuit including a variable capacitor tunable within the capacitance value range; and biasing the DC coupling element relative to a reference potential node by generating the DC pulse train at the DC pulse frequency using the DC pulse generator.

[0141] Example 30. The method of Example 29 further includes: generating plasma in the plasma processing chamber by applying source power to the plasma processing chamber before biasing the DC coupling element; and wherein the step of biasing the DC coupling element includes: biasing the DC coupling element during the afterglow phase of the plasma after the source power is removed.

[0142] Example 31. A method of one of Examples 29 and 30, wherein the step of biasing the DC coupling element comprises: generating the DC pulse train at the DC pulse frequency by using the DC pulse generator, and negatively biasing a substrate holder in the plasma processing chamber relative to the reference potential node.

[0143] Example 32. A method of one of Examples 29 to 31, wherein the electrical characteristic includes an RC time constant of a DC current path, the DC current path including the DC coupling element, the plasma in the plasma processing chamber, and the reference potential node.

[0144] Example 33. The method of Example 32, wherein the RC time constant is at least twice the reciprocal of the DC pulse frequency.

[0145] Example 34. The method of Example 33, wherein the DC pulse frequency is below approximately 400 kHz.

[0146] Example 35. The method of Example 34, wherein the DC pulse frequency is below about 20 kHz.

[0147] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of illustrative embodiments and other embodiments of the invention will be apparent to those skilled in the art from this description. Therefore, it is desired that the appended claims cover any such modifications or embodiments. [Simplified Explanation of the Diagram]

[0009] To better understand the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0010] FIG1 illustrates a schematic timing diagram of an example plasma treatment method according to an embodiment of the present invention;

[0011] Figure 2 illustrates a voltage qualitative graph as a function of time according to an embodiment of the present invention, and a corresponding qualitative graph of the ion energy distribution function for several RC time constants at a fixed DC pulse frequency;

[0012] Figure 3 shows a schematic diagram of an example plasma processing apparatus including a DC current path between a bias power supply and a reference potential node according to an embodiment of the present invention;

[0013] FIG4 illustrates a schematic diagram of an example plasma treatment apparatus including a selective capacitive pre-coating and a selective resistive pre-coating according to an embodiment of the present invention;

[0014] FIG5 illustrates a schematic diagram of an example plasma processing apparatus including a tuning circuit with a variable capacitor according to an embodiment of the present invention;

[0015] FIG6 shows a schematic diagram of an example plasma treatment apparatus including a tuning circuit and optional capacitive pre-coating and optional resistive pre-coating according to an embodiment of the present invention;

[0016] FIG7 illustrates a schematic diagram of an example tuning circuit including a single-pole switch and a plurality of capacitors according to an embodiment of the present invention;

[0017] FIG8 illustrates a schematic diagram of an example tuning circuit including a single-pole switch and a plurality of variable capacitors according to an embodiment of the present invention;

[0018] FIG9 illustrates a schematic diagram of an example tuning circuit including a single-pole switch and a plurality of capacitors according to an embodiment of the present invention, wherein the plurality of capacitors include a fixed capacitor and a variable capacitor;

[0019] FIG10 illustrates a schematic diagram of an example tuning circuit including a single-pole switch and a plurality of capacitors according to an embodiment of the present invention;

[0020] FIG11 illustrates a schematic diagram of an exemplary plasma treatment apparatus according to an embodiment of the present invention, the plasma treatment apparatus including a capacitive pre-coating covering an upper electrode and a tuning circuit coupled to the upper electrode; and

[0021] FIG12 illustrates an example method of plasma treatment according to an embodiment of the present invention.

[0022] Unless otherwise stated, the numbers and symbols corresponding to different figures generally refer to the corresponding components. These figures are drawn to clearly illustrate the relevant features of the embodiments and are not necessarily drawn to scale. The edges of the features drawn in the figures do not necessarily indicate the end of the feature range.

Claims

1. A plasma processing apparatus, comprising: a plasma processing chamber; a source power (SP) coupling element configured to generate plasma within the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency; a substrate holder disposed within the plasma processing chamber; a DC coupling element coupled to the DC pulse generator; a DC current path including the DC coupling element, the plasma, and a reference potential node arranged in series, the DC coupling element being configured to bias the substrate holder relative to the reference potential node using the DC pulse train; and a capacitive pre-coating disposed between the DC coupling element and the plasma, the capacitive pre-coating increasing the RC time constant of the DC current path according to the DC pulse frequency.

2. The plasma processing apparatus of claim 1 further comprises: a resistive pre-coating layer disposed on an inner surface of the plasma processing chamber; wherein the reference potential node is coupled to the plasma processing chamber; wherein the resistive pre-coating layer is disposed between the plasma and the reference potential node; and wherein the resistive pre-coating layer further increases the RC time constant of the DC current path according to the DC pulse frequency.

3. The plasma processing apparatus of claim 1 further includes: a tuning circuit coupled between the DC coupling element and the DC pulse generator, the tuning circuit including a variable capacitor.

4. The plasma treatment equipment as described in claim 1, wherein: The DC coupling element is disposed above the substrate holder; and the reference potential node is coupled to the substrate holder.

5. A plasma processing apparatus, comprising: a plasma processing chamber; a source power (SP) coupling element configured to generate plasma within the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train including a DC pulse frequency; a substrate holder disposed within the plasma processing chamber; a DC coupling element coupled to the DC pulse generator; a DC current path including the DC coupling element, the plasma, and a reference potential node arranged in series, the DC coupling element configured to bias the substrate holder relative to the reference potential node using the DC pulse train; and a tuning circuit coupled between the DC coupling element and the DC pulse generator, the tuning circuit including a variable capacitor configured to tune the RC time constant of the DC current path by changing the variable capacitor according to the DC pulse frequency.

6. The plasma processing apparatus of claim 5, wherein the tuning circuit comprises: a plurality of capacitors; a first unipolar switch comprising an input coupled to the DC coupling element or the DC pulse generator, and a first output coupled to a first subset of the plurality of capacitors.

7. The plasma processing apparatus of claim 6, wherein the tuning circuit further comprises: a second unipolar switch having an input coupled to the DC pulse generator and an output coupled to the first subset of the plurality of capacitors, wherein the first unipolar switch is coupled to the DC coupling element.

8. The plasma processing apparatus of claim 6, wherein the plurality of capacitors comprises a plurality of capacitor banks coupled in parallel to each other.

9. The plasma processing apparatus of claim 6, wherein the first single-pole open-circuit multi-throw switch includes a second output coupled to a second subset of the plurality of capacitors.

10. The plasma treatment equipment as claimed in item 6, wherein: The first single-pole switch is a single-throw switch; and the tuning circuit further includes a second single-pole single-throw switch, including an input coupled to the input of the first single-pole single-throw switch and an output coupled to a second subset of the plurality of capacitors.

11. The plasma treatment equipment as claimed in claim 6, wherein, The plurality of capacitors includes a plurality of fixed capacitors.

12. The plasma processing apparatus of claim 6, wherein the first unipolar switch includes a second output coupled to the DC pulse generator or the DC coupling element such that when the second output is selected, a short-circuit path is formed between the DC coupling element and the DC pulse generator.

13. The plasma processing apparatus of claim 5 further comprises: a resistive pre-coating disposed on an inner surface of the plasma processing chamber; wherein the reference potential node is coupled to the plasma processing chamber; wherein the resistive pre-coating is disposed between the plasma and the reference potential node; and wherein the resistive pre-coating further increases the RC time constant of the DC current path according to the DC pulse frequency.

14. The plasma processing apparatus of claim 13 further includes: a capacitive pre-coating layer disposed between the DC coupling element and the plasma, the capacitive pre-coating layer increasing the RC time constant of the DC current path according to the DC pulse frequency.

15. An electrical characteristic tuning method for tuning an electrical characteristic of a plasma processing chamber in a plasma processing apparatus, the method comprising: determining a capacitance value from a capacitance value range based on the DC pulse frequency of a DC pulse train generated by a DC pulse generator of the plasma processing apparatus; tuning the electrical characteristic by selecting the determined capacitance value using a tuning circuit coupled between a DC coupling element and the DC pulse generator, the tuning circuit including a variable capacitor tunable within the capacitance value range; and biasing the DC coupling element relative to a reference potential node by generating the DC pulse train at the DC pulse frequency using the DC pulse generator.

16. The electrical characteristic tuning method of claim 15 further comprises: generating plasma in the plasma processing chamber by applying source power to the plasma processing chamber before biasing the DC coupling element; and wherein, The step of biasing the DC-coupled element includes biasing the DC-coupled element during the afterglow phase of the plasma after the source power is removed.

17. The electrical characteristic tuning method of claim 15, wherein the step of biasing the DC coupling element comprises: generating the DC pulse train at the DC pulse frequency by using the DC pulse generator, and negatively biasing a substrate holder in the plasma processing chamber relative to the reference potential node.

18. The electrical characteristic tuning method of claim 15, wherein the electrical characteristic includes an RC time constant of a DC current path, the DC current path including the DC coupling element, the plasma in the plasma processing chamber, and the reference potential node.

19. The electrical characteristic tuning method of claim 18, wherein the RC time constant is at least twice the reciprocal of the DC pulse frequency.

20. The electrical characteristic tuning method of claim 19, wherein the DC pulse frequency is below about 400 kHz.

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