Clock signal delay path unit and semiconductor memory device including the same

Abstract

A clock signal delay path unit includes: a first delay cell, including a first signal line for delaying and transmitting a clock signal, a first repeater for transmitting the clock signal transmitted via the first signal line without signal attenuation, and a second signal line for delaying and transmitting a clock signal output from the first repeater; a second delay cell, including a first inverter circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal; and a third delay cell, including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater for transmitting the inverted clock signal transmitted via the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

Description

Technical Field

[0001] An embodiment relates to a clock signal delay path unit and a semiconductor memory device including the same. [Cross - reference to related applications]

[0002] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0118258, filed on September 06, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Background Art

[0003] A semiconductor memory device may include a delay lock loop circuit. The delay lock loop circuit may include a delay lock loop and a clock signal delay path unit. The delay lock loop may generate a delayed clock signal that is locked to an external clock signal. The clock signal delay path unit may delay the delayed clock signal by the same delay time through a signal line to generate an internal clock signal and transmit the internal clock signal to a target block (e.g., a data strobe signal driver and a data driver).

Summary of the Invention

[0004] A clock signal delay path unit according to an embodiment may include: at least one first delay cell including a first signal line for delaying and transmitting a clock signal, a first repeater for transmitting the clock signal transmitted through the first signal line without signal attenuation, and a second signal line for delaying and transmitting the clock signal output from the first repeater; a second delay cell including a first inverting circuit for inverting the clock signal provided from the first delay cell to generate an inverted clock signal; and at least one third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater for transmitting the inverted clock signal transmitted through the first branch signal line without signal attenuation, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater, wherein each of the first signal line, the second signal line, the first branch signal line, and the second branch signal line may be a long metal line.

[0005] A semiconductor memory device according to an embodiment may include: a clock signal input buffer configured to buffer an external clock signal externally applied and output a buffered clock signal; a delay locked loop configured to receive the buffered clock signal and generate a delayed clock signal that is delay locked to the external clock signal; a clock signal delay path unit configured to delay and invert the delayed clock signal to generate n internal clock signals, a data strobe signal, and an inverted data strobe signal; a memory cell array including a plurality of memory cells and outputting data stored in the memory cells selected in response to a plurality of word line selection signals and a plurality of row selection signals; a data read path unit configured to receive the data and convert the data into serial data to generate n data; a data output unit configured to drive the n data in response to the n internal clock signals; and a data strobe signal output unit configured to drive the output data strobe signal and the inverted output data strobe signal, wherein the clock signal delay path unit includes n + 2 branch delay units, and the n + 2 branch delay units can generate the n internal clock signals, the output data strobe signal, and the inverted output data strobe signal, each branch delay unit includes: at least one first delay cell including a first signal line for delaying and transmitting the delayed clock signal, a first repeater configured to transmit the delayed clock signal transmitted by the first signal line without signal attenuation, and a second signal line for delaying and transmitting the delayed clock signal output from the first repeater; a second delay cell including a first inverter circuit configured to invert the delayed clock signal provided by the first delay cell to generate an inverted delayed clock signal; and at least one third delay cell including a first branch signal line for delaying and transmitting the inverted delayed clock signal provided by the second delay cell, a second repeater configured to transmit the inverted delayed clock signal transmitted by the first branch signal line without signal attenuation, and a second branch signal line for delaying and transmitting the inverted delayed clock signal output from the second repeater, wherein each of the first signal line, the second signal line, the first branch signal line, and the second branch signal line can be a long metal line.

[0006] The semiconductor memory device according to an embodiment may include: a read enable signal input buffer configured to buffer a read enable signal externally applied and output a buffered read enable signal; an inverted read enable signal input buffer configured to buffer an inverted read enable signal externally applied and output a buffered inverted read enable signal; a read enable signal delay path configured to delay and invert the buffered read enable signal and the buffered inverted read enable signal to generate n internal clock signals, an output data strobe signal, and an inverted output data strobe signal; a memory cell array including a plurality of memory cells and outputting data stored in the memory cells selected in response to a plurality of word line selection signals, a plurality of source line selection signals, a plurality of ground selection signals, and a plurality of row selection signals; a page buffer configured to buffer the data to generate read data; a data read path unit configured to receive the read data and convert the read data into serial data to generate n data; a data output unit configured to drive the n data in response to the n internal clock signals; and a data strobe signal output unit configured to drive the output data strobe signal and the inverted output data strobe signal, wherein the read enable signal delay path includes n + 2 branch delay units, and the n + 2 branch delay units can generate the n internal clock signals, the output data strobe signal, and the inverted output data strobe signal, and each branch delay unit includes: at least one first delay cell including a first pair of signal lines for delaying and transmitting a read enable signal pair including the buffered read enable signal and the buffered inverted read enable signal, a first repeater configured to transmit the read enable signal pair transmitted by the first pair of signal lines without signal attenuation, and a second pair of signal lines for delaying and transmitting the read enable signal pair output from the first repeater; a second delay cell including a first inverter circuit configured to invert the read enable signal pair provided by the first delay cell and output an inverted read enable signal pair; and at least one third delay cell including a first branch pair of signal lines for delaying and transmitting the inverted read enable signal pair provided by the second delay cell, a second repeater configured to transmit the inverted read enable signal pair transmitted by the first branch pair of signal lines without signal attenuation, and a second branch pair of signal lines for delaying and transmitting the inverted read enable signal pair output from the second repeater, wherein each of the first pair of signal lines, the second pair of signal lines, the first branch pair of signal lines, and the second branch pair of signal lines can be a long metal line pair.

Embodiment

[0008] FIG. 1 is a diagram showing a clock signal delay path unit according to an exemplary embodiment. The configuration and operation of the clock signal delay path unit will be described below with reference to FIG. 1.

[0009] The clock signal delay path unit may include a first delay cell DC1, a second delay cell DC2, and a third delay cell DC3.

[0010] The first delay cell DC1 may include: a first root signal line rsl1 that delays and transmits the clock signal CLK; a repeater R that transmits the clock signal transmitted through the first root signal line rsl1 without signal attenuation; and a second root signal line rsl2 that delays and transmits the clock signal output from the repeater R.

[0011] Each of the first root signal line rsl1 and the second root signal line rsl2 may be a long metal line.

[0012] The duty ratio of the clock signal CLK transmitted through the first delay cell DC1 may vary according to changes in process, voltage, and temperature (PVT). For example, although the duty ratio of the clock signal CLK applied to the starting node sn is 50%, when the clock signal CLK passes through the first delay cell DC1, the duty ratio may increase by 5%, and thus the duty ratio of the clock signal CLK generated at the intermediate node mn may reach 55%.

[0013] The second delay cell DC2 may include: a first intermediate signal line msl1 that delays and transmits the clock signal CLK provided from the first delay cell DC1; an inverting repeater IR that inverts the clock signal CLK transmitted through the first intermediate signal line msl1 to generate an inverted clock signal and transmits the inverted clock signal without signal attenuation; and a second intermediate signal line msl2 that delays and transmits the inverted clock signal output from the inverting repeater IR.

[0014] The inverting repeater IR may include an inverting circuit (not shown) and a repeater R (not shown) connected in series.

[0015] In an exemplary embodiment, the second delay cell DC2 may be implemented as an inverting circuit (not shown). For example, the second delay cell DC2 may not include the first intermediate signal line msl1 and the second intermediate signal line msl2 as long metal lines and the repeater R.

[0016] The second delay cell DC2 can invert the phase of the clock signal CLK having a load ratio increased by the first delay cell DC1. Thereby, the load ratio of the inverted clock signal output from the second delay cell DC2 may change. For example, when the phase of the clock signal CLK having a load ratio of 55% is inverted by the second delay cell DC2, the load ratio of the inverted clock signal can become 45%. Thereby, the load ratio of the inverted clock signal can be reduced at the branch node dn.

[0017] The third delay cell DC3 may include: a first branch signal line dsl1 that delays and transmits the inverted clock signal provided from the second delay cell DC2; a repeater R that transmits the inverted clock signal provided by the first branch signal line dsl1 without signal attenuation; and a second branch signal line dsl2 that delays and transmits the inverted clock signal output from the repeater R.

[0018] Each of the first branch signal line dsl1 and the second branch signal line dsl2 may be a long metal line.

[0019] As in the first delay cell DC1, the load ratio of the inverted clock signal transmitted by the third delay cell DC3 may change due to changes in PVT. For example, although the load ratio of the inverted clock signal applied to the branch node dn is 45%, when the inverted clock signal passes through the third delay cell DC3, the load ratio may increase by 5%, and thus the load ratio of the inverted clock signal can reach 50% at the target node.

[0020] In the clock signal delay path unit according to the exemplary embodiment, even if the load ratio of the clock signal CLK increases or decreases due to changes in PVT by the first delay cell DC1 and the second delay cell DC2, the phase of the clock signal CLK is inverted, and thus the load ratio of the clock signal CLK transmitted by the clock signal delay path unit can be kept constant. That is, the load ratio of the clock signal CLK input to the clock signal delay path unit can be substantially the same as the load ratio of the clock signal CLK output from the clock signal delay path unit. For example, when the load ratio of the clock signal CLK input to the clock signal delay path unit is 50%, the load ratio of the clock signal CLK output from the clock signal delay path unit can be 50%. As shown in FIG. 1, even if the load ratio of the clock signal CLK increases by a predetermined percentage (e.g., 5%) by the first delay cell DC1 and the third delay cell DC3, the load ratio of the clock signal CLK can be corrected by inverting the clock signal CLK by the second delay cell DC2 so that the load ratio of the clock signal CLK output from the third delay cell DC3 becomes a desired load ratio (e.g., 50%).

[0021] Although FIG. 1 shows that each of the first delay cell DC1 and the third delay cell DC3 includes a single repeater R, this is merely an example, and for example, each of the first delay cell DC1 and the third delay cell DC3 may include multiple repeaters. In this case, the number of repeaters included in the first delay cell DC1 may be equal to the number of repeaters included in the third delay cell DC3.

[0022] In addition, although FIG. 1 shows that the load ratio is increased by the delay cells of the clock signal delay path portion, even when the load ratio is decreased by the delay cells, the load ratio of the clock signal CLK can be corrected by inverting the clock signal CLK.

[0023] In an exemplary embodiment, each repeater R may include an even number of inverter circuits connected in series.

[0024] In an exemplary embodiment, the long metal wire may be implemented such that the length of the long metal wire is greater than the length of the signal line between the inverter circuits constituting the repeater R.

[0025] In FIG. 1, since the phase of the inverted clock signal generated at the target node tn has the inverted phase of the clock signal CLK, an inverter circuit for inverting the phase of the clock signal CLK may be added to the stage before the start node sn, or an inverter circuit for inverting the phase of the inverted clock signal may be added to the stage after the target node tn to restore the phase of the clock signal CLK.

[0026] FIGS. 2A and 2B are block diagrams of a semiconductor memory device according to an exemplary embodiment.

[0027] Referring to FIGS. 2A and 2B, the semiconductor memory device 100 may include a clock signal terminal 2, command and address terminals 4, a clock signal input buffer 10, a command and address generator 12, a mode setting register 14, a delay controller 16, a delay locked loop circuit 18, a column decoder 20, a row decoder 22, a memory cell array 24, a data read path unit 26, a data write path unit 28, a data output unit 30, a data input unit 32, a data strobe signal output unit 34, a data strobe signal input unit 36, data terminals 38-1 to 38-n, a data strobe signal terminal 40-1, and an inverted data strobe signal terminal 40-2.

[0028] The delay locked loop circuit 18 may include a delay locked loop 18-2 and a clock signal delay path unit 18-4.

[0029] The data output unit 30 may include n data output drivers (DOD) 30-1 to 30-n.

[0030] The data input unit 32 may include n data input drivers (DID) 32-1 to 32-n.

[0031] The data strobe signal output unit 34 may include a data strobe signal output driver (DQSOD) 34-1 and an inverted data strobe signal output driver (DQSBOD) 34-2.

[0032] The data strobe signal input unit 36 may include a data strobe signal input driver (DQSID) 36-1 and an inverted data strobe signal input driver (DQSBID) 36-2.

[0033] The function of each block shown in FIGS. 2A and 2B will be described below.

[0034] The clock signal terminal 2 may receive an external clock signal ECLK. The command and address terminal 4 may receive a command and address CA.

[0035] The clock signal input buffer 10 may buffer the external clock signal ECLK and output a buffered clock signal CLK.

[0036] The command and address generator 12 may decode the command signal included in the command and address CA in response to the external clock signal ECLK to generate an activate command ACT, a write command WR, a read command RD, and a mode setting command MRS. In addition, the command and address generator 12 may receive the address signal included in the command and address CA to generate a column address RADD together with the activate command ACT, a row address CADD together with the write command WR or the read command RD, and a mode setting code OPC together with the mode setting command MRS.

[0037] The mode setting register 14 may store the mode setting code OPC in response to the mode setting command MRS and set a read latency RL and a burst length BL.

[0038] The latency controller 16 may receive the read command RD in response to a latency clock signal LATCLK and generate a latency control signal LA, which is activated after a number of clock cycles corresponding to the read latency RL and deactivated after a number of clock cycles corresponding to the burst length BL.

[0039] The delay locked loop 18-2 can receive a buffered clock signal CLK, generate a delayed clock signal DCLK that is delay locked to an external clock signal ECLK, and additionally generate a delayed clock signal LATCLK.

[0040] The clock signal delay path unit 18-4 can transmit the delayed clock signal DCLK to generate an output data strobe signal dqso, an inverted output data strobe signal dqsob, and n internal clock signals ick1 to ickn that are locked to the external clock signal ECLK. The clock signal delay path unit 18-4 can correct for changes in the load ratio of the delayed clock signal DCLK, which may occur due to PVT changes in the signal line used to transmit the delayed clock signal DCLK. For example, even if the load ratio of the delayed clock signal DCLK increases (or decreases) due to PVT changes in the signal line, the clock signal delay path unit 18-4 can reduce (or increase) the load ratio of the delayed clock signal DCLK by inverting the phase of the delayed clock signal DCLK at the midpoint of the signal line to correct the load ratio. Thereby, the load ratios of the output data strobe signal dqso, the inverted output data strobe signal dqsob, and the n internal clock signals ick1 to ickn generated by the clock signal delay path unit 18-4 can be corrected.

[0041] The column decoder 20 can generate a plurality of word line selection signals wl by decoding a column address RADD.

[0042] The row decoder 22 can generate a plurality of row selection signals csl by decoding a row address CADD.

[0043] The memory cell array 24 can include a plurality of memory cells (not shown), and can output read data DO from the memory cells selected in response to the plurality of word line selection signals wl and the plurality of row selection signals csl, or can store write data DI in the selected memory cells. Each of the plurality of memory cells can be a dynamic memory cell, the memory cell array 24 can be a dynamic memory cell array, and the semiconductor memory device 100 can be a dynamic random access memory (DRAM) device.

[0044] The data read path unit 26 can perform serial conversion on the read data DO to generate n output data do1 to don. The n output data do1 to don can be generated during the active period of the delay control signal LA. For example, when 8n-bit read data DO is input, the n output data do1 to don can be output eight times by 1 bit.

[0045] The data write path unit 28 can perform parallel conversion on n input data di1 to din to generate write data DI. For example, when the n input data di1 to din are input eight times by 1 bit, write data DI of 8n bits can be generated.

[0046] The data output drivers 30-1 to 30-n can be connected to the n data terminals 38-1 to 38-n, and can drive the n output data do1 to don in response to the internal clock signals ick1 to ickn to respectively generate n data DQ1 to DQn.

[0047] The data input drivers 32-1 to 32-n can be connected to the n data terminals 38-1 to 38-n, and can drive the n data DQ1 to DQn to respectively generate n input data di1 to din.

[0048] The data strobe signal output driver 34-1 can be connected to the data strobe signal terminal 40-1, and can drive the output data strobe signal dqso to generate the data strobe signal DQS. The inverted data strobe signal output driver 34-2 can be connected to the inverted data strobe signal terminal 40-2, and can drive the inverted output data strobe signal dqsob to generate the inverted output data strobe signal DQSB.

[0049] The data strobe signal input driver 36-1 can be connected to the data strobe signal terminal 40-1, and can drive the externally applied data strobe signal DQS to generate the input data strobe signal dqsi. The inverted data strobe signal input driver 36-2 can be connected to the inverted data strobe signal terminal 40-2, and can drive the externally applied inverted input data strobe signal DQSB to generate the inverted input data strobe signal dqsib.

[0050] FIG. 3 is a diagram showing the layout of a semiconductor memory device according to an exemplary embodiment. FIG. 4 is a diagram showing the vertical layout of a peripheral circuit area according to an exemplary embodiment.

[0051] Referring to FIG. 3, the semiconductor memory device 100 may include memory cell array areas 24-1 to 24-4 and a peripheral circuit area 50.

[0052] Referring to FIGS. 2A, 2B and 3, the memory cell array 24 may include, for example, four memory banks MBG1 to MBG4. The memory banks MBG1 to MBG4 may be respectively disposed in the memory cell array regions 24-1 to 24-4. In addition, column decoders 20 and row decoders 22 for each of the memory banks MBG1 to MBG4 may be additionally disposed in each of the memory cell array regions 24-1 to 24-4. Peripheral circuits (such as a clock signal input buffer 10, a command and address generator 12, a mode setting register 14, a delay controller 16, a delay locked loop circuit 18, a data read path unit 26, a data write path unit 28, a data output unit 30, a data input unit 32, a data strobe signal output unit 34, a data strobe signal input unit 36, data terminals 38-1 to 38-8, a data strobe signal terminal 40-1 and an inverted data strobe signal terminal 40-2) may be disposed in the peripheral circuit region 50.

[0053] Referring to FIGS. 2A to 4, the peripheral circuit may be disposed in a circuit region 54 on a substrate 52. A signal line region 56 may be disposed on the circuit region 54. A power line region 58 may be disposed on the signal line region 56. A terminal region 60 may be disposed on the power line region 58. Signal lines may be arranged in the signal line region 56. Power lines may be arranged in the power line region 58. The data terminals 38-1 to 38-n, the data strobe signal terminal 40-1 and the inverted data strobe signal terminal 40-2 may be arranged in the terminal region 60. The terminals may be pads.

[0054] The arrangement of the signal lines of the clock signal delay path unit 18-4 shown in FIG. 3 is an arrangement when the data terminals 38-1 to 38-8, the data strobe signal terminal 40-1 and the inverted data strobe signal terminal 40-2 are arranged adjacent to each other, the clock signal terminal CKP to which an external clock signal ECLK is applied is relatively far from the data terminals 38-1 to 38-8 and the data strobe signal terminal 40-1, and the inverted data strobe signal terminal 40-2, the clock signal input buffer 10 and the delay locked loop 18-2 are arranged adjacent to the clock signal terminal CKP, and the data output drivers 30-1 to 30-8, the data strobe signal output driver 34-1 and the inverted data strobe signal output driver 34-2 are respectively arranged adjacent to the data terminals 38-1 to 38-n, the data strobe signal terminal 40-1 and the inverted data strobe signal terminal 40-2.

[0055] The arrangement of the signal lines of the clock signal delay path unit 18-4 will now be further described with reference to FIGS. 2A to 4.

[0056] The first node n1 can be the output node of the delay locked loop 18-2. The second node n2 can be the branch start node. The third node n3 and the fourth node n4 can be the first branch nodes. The fifth node n5 to the eighth node n8 can be the second branch nodes. The ninth node n9 to the thirteenth node n13 can be the third branch nodes. The fourteenth node n14 to the seventeenth node n17 and the twentieth node n20 to the twenty-third node n23 can be the input nodes of the data output drivers 30-1 to 30-8. The eighteenth node n18 and the nineteenth node n19 can be the input nodes of the data strobe signal output driver 34-1 and the inverted data strobe signal output driver 34-2. The twenty-fourth node n24 and the twenty-fifth node n25 can be additional nodes.

[0057] The first node n1 can correspond to the start node sn shown in FIG. 1. The second node n2 can correspond to the branch node dn. The fourteenth node n14 to the twenty-third node n23 can correspond to the target nodes tn.

[0058] The first signal lines sl21 and sl22 from the branch start node (the second node n2) to the first branch nodes (the third node n3 and the fourth node n4) can have the same length and width.

[0059] The second signal lines sl31 and sl32 from the first branch node (the third node n3) to the second branch nodes (the fifth node n5 and the sixth node n6) and the second signal lines sl33 and sl34 from the first branch node (the fourth node n4) to the second branch nodes (the seventh node n7 and the eighth node n8) can have the same length and width.

[0060] The third signal lines (sl41, sl42), sl44, (sl45, sl46), and sl47 from the second branch nodes (the fifth node n5, the sixth node n6, the seventh node n7, and the eighth node n8) to the corresponding third branch nodes ((the ninth node n9, the tenth node n10), the eleventh node n11, (the twelfth node n12, the thirteenth node n13), and the twenty-fourth node n24) can have the same length and width.

[0061] The third signal lines sl43 and sl48 may or may not have the same length as the length of the third signal line sl41.

[0062] The fourth signal lines (sl49, sl50), (sl51, sl52), (sl53, sl54), (sl55, sl56), (sl57, sl58), and sl59 from the third branch nodes (the ninth node n9, the tenth node n10, the eleventh node n11, the twelfth node n12, the thirteenth node n13, and the twenty-fourth node n24) to the corresponding fourth branch nodes ((the fourteenth node n14, the fifteenth node n15), (the sixteenth node n16, the seventeenth node n17), (the eighteenth node n18, the nineteenth node n19), (the twentieth node n20, the twenty-first node n21), (the twenty-second node n22, the twenty-third node n23), and the twenty-fifth node n25) may have the same length and width.

[0063] The root signal line sl1 and the first signal lines sl21 and sl22 to the fourth signal lines sl49 to sl59 may be disposed in the signal line area 56. The signal lines disposed in the horizontal direction and the signal lines disposed in the vertical direction may be disposed on different layers of the signal line area 56. Although in the figure the root signal line sl1 and the first signal lines sl21 and sl22 to the fourth signal lines sl49 to sl59 are successively arranged between the first node n1 and the twenty-fifth node n25, they may be connected by a repeater (not shown) or a component (not shown), and the repeater or the component may be disposed in the circuit area 54.

[0064] As described above, the clock signal delay path unit 18-4 may include two first signal lines sl21 and sl22 and at most 2m fourth signal lines sl49 to sl59, and the at most fourth signal lines sl49 to sl59 connect two first branch nodes (the third node n3 and the fourth node n4) to at most 2m fourth branch nodes (the fourteenth node n14 to the twenty-third node n23 and the twenty-fifth node n25), and the at most 2m fourth branch nodes are successively arranged from the branch starting node n2 in the tree structure for branching m times.

[0065] FIG. 5 is a diagram showing the configuration of a clock signal delay path unit according to an exemplary embodiment.

[0066] Referring to FIGS. 1 and 5, five repeaters R may be disposed on the root signal line sl11 from the first node n1 to the intermediate node mn. Five first delay cells DC1 may be disposed between the first node n1 and the intermediate node mn. The signal lines between the five repeaters R may correspond to the first root signal line rsl1 or the second root signal line rsl2, and may be long metal lines. The repeater R may transmit the delayed clock signal DCLK without signal attenuation.

[0067] The duty cycle corrector DCC, multiplexer MUX, and inverting repeater IR can be disposed between the intermediate signal line sl12 from the intermediate node mn and the second node n2. The configuration between the intermediate node mn and the second node n2 can correspond to the second delay cell DC2.

[0068] The duty cycle corrector DCC can use the internal clock signals ick and ickB to correct the duty ratio of the delayed clock signal DCLK transmitted from the intermediate node mn.

[0069] In response to the select signal sel, the multiplexer MUX can select the delayed clock signal DCLK transmitted from the intermediate node mn, or can select the delayed clock signal DCLK transmitted from the duty cycle corrector DCC. The select signal sel can alternatively be set by the mode setting code OPC applied to the mode setting register 14 shown in FIG. 2A.

[0070] The inverting repeater IR can have a configuration in which an inverting circuit (not shown) is connected in series with a repeater R (not shown). The inverting circuit can invert the phase of the delayed clock signal DCLK transmitted from the multiplexer MUX to generate an inverted delayed clock signal DCLKB, and the repeater R can transmit the inverted delayed clock signal DCLKB without signal attenuation. In an embodiment, a configuration in which the repeater R (not shown) is not provided between the intermediate node mn and the second node n2 can be employed.

[0071] The repeater R can be disposed on each of the first signal lines sl21 and sl22 to the fourth signal lines sl49 to sl59. A branch delay unit including four third delay cells DC3 can be configured in the branch signal line from the second node n2 to the fourth branch node (the fourteenth node n14). Ten branch delay units can be configured from the second node n2 to the fourth branch node (the fourteenth node n14 to the twenty-third node n23). The signal lines between the repeaters R can correspond to the first branch signal line dsl1 or the second branch signal line dsl2, and can be long metal lines. That is, each of the first signal lines sl21 and sl22 to the fourth signal lines sl49 to sl59 can be long metal lines.

[0072] The phase splitter PS and the selector MUX can be additionally arranged between the fourteenth node n14 to the twenty-third node n23 and the data output drivers 30-1 to 30-8, the data strobe signal output driver 34-1, and the inverted data strobe signal output driver 34-2. The phase splitter PS and the selector MUX can invert and split the phases of the internal clock signals ick1 to ick8, the output data strobe signal dqso, and the inverted output data strobe signal dqsob, so as to alternately output pairs of internal clock signals, pairs of output data strobe signals, and pairs of inverted output data strobe signals with a 180-degree phase difference.

[0073] The repeater R can be connected between the twenty-fourth node n24 and the twenty-fifth node n25. The phase splitter PS can be connected to the twenty-fifth node n25, and the phase splitter PS can generate an additional pair of internal clock signals with a 180-degree phase difference by inverting and splitting the phase of the internal clock signal ick9.

[0074] FIG. 6 is a diagram showing the configuration of a clock signal delay path unit according to an exemplary embodiment.

[0075] Except that the inverting repeater IR arranged between the intermediate node mn and the second node n2 in the configuration of FIG. 5 is replaced by the repeater R, and the repeater R connected between the second node n2, the third node n3, and the fourth node n4 in the configuration of FIG. 5 is replaced by the inverting repeater IR in the clock signal delay path unit 18-4', the exemplary embodiment described in conjunction with FIG. 6 can be the same as the exemplary embodiment of the clock signal delay path unit 18-4 in FIG. 5. The inverting repeater IR can have a configuration in which an inverting circuit (not shown) is connected in series with the repeater R (not shown).

[0076] Referring to FIG. 6, the clock signal delay path unit 18-4' can be configured to invert the phase of the delayed clock signal DCLK immediately after the second node n2 (i.e., the branch start node), rather than immediately inverting the phase before the second node n2.

[0077] FIG. 7 is a diagram showing the configuration of a clock signal delay path unit according to an exemplary embodiment.

[0078] Except that the repeater R immediately before the intermediate node mn in the configuration of FIG. 5 is replaced by an inverting repeater IR, and the inverting repeater IR arranged between the intermediate node mn and the second node n2 in the configuration of FIG. 5 is replaced by the repeater R in the clock signal delay path unit 18-4", the exemplary embodiment described in conjunction with FIG. 7 can have the same configuration as the clock signal delay path unit 18-4 in FIG. 5.

[0079] The inverting repeater IR may have an arrangement in which an inverting circuit (not shown) is connected in series with a repeater R (not shown).

[0080] Referring to FIG. 7, the clock signal delay path unit 18-4” may be configured to invert the phase of the delayed clock signal DCLK immediately before the intermediate node mn, rather than immediately before the second node n2 (i.e., the branch start node).

[0081] The phase of the delayed clock signal DCLK is inverted by the inverting repeater IR in the clock signal delay path units 18-4, 18-4', and 18-4” of FIGS. 5 to 7. To restore the phase of the delayed clock signal DCLK, the delay locked loop 18-2 may be configured to pre-invert the delayed clock signal DCLK and apply the inverted delayed clock signal to the first node n1. As another example, the phase splitter PS may be configured to invert the internal clock signals ick1 to ick8, the output data strobe signal dqso, and the inverted output data strobe signal dqsob to perform the above-described phase splitting operation.

[0082] In an exemplary embodiment, the inverting repeater IR may be provided at various positions different from the positions in the clock signal delay path units 18-4, 18-4', and 18-4” (i.e., different from the description with reference to FIGS. 5 to 7 above). For example, a repeater R included in one of a first repeater group including four repeaters R to an m-th repeater group including up to 2m repeaters may be configured as the inverting repeater IR. If, in the clock signal delay path units 18-4, 18-4', and 18-4”, the change in the total load ratio occurring in the signal lines from the first node n1 to the fourth branch node (the fourteenth node n14 to the twenty-third node n23) is 10%, then the inverting repeater IR for inverting the delayed clock signal DCLK may be provided at a position where the change in the load ratio is 5%.

[0083] In an exemplary embodiment, in addition to the load cycle corrector DCC and the multiplexer MUX, each of the clock signal delay path units 18-4, 18-4', and 18-4'' in FIGS. 5 to 7 can be configured. Additionally, in addition to the phase splitter PS and the selector MUX, each of the clock signal delay path units 18-4, 18-4', and 18-4'' in FIGS. 5 to 7 can be configured. For example, if the semiconductor memory device shown in FIGS. 2A and 2B is configured to output data at a single data rate (SDR) instead of a double data rate (DDR), then in addition to the phase splitter PS and the selector MUX, each of the clock signal delay path units 18-4, 18-4', and 18-4'' in FIGS. 5 to 7 can be configured.

[0084] FIGS. 8A and 8B are diagrams showing the configuration of a repeater according to an exemplary embodiment.

[0085] Referring to FIG. 8A, the repeater R may include two inverter circuits INV1 and INV2 connected in series.

[0086] The inverter circuit INV1 may include a single inverter I.

[0087] The inverter circuit INV2 may include two inverters I connected in parallel. The inverter circuit INV2 may have twice the size of the inverter circuit INV1. In another implementation, the inverter circuit INV2 may have three times or more the size of the inverter circuit INV1.

[0088] Referring to FIG. 8B, the repeater R may include four inverter circuits INV1 to INV4 connected in series.

[0089] The inverter circuit INV1 and the inverter circuit INV2 may have the same configuration as that described with reference to FIG. 8A.

[0090] The inverter circuit INV3 may include four inverters I connected in parallel. The inverter circuit INV3 may have four times the size of the inverter circuit INV1.

[0091] The inverter circuit INV4 may include six inverters I connected in parallel. The inverter circuit INV4 may have six times the size of the inverter circuit INV1.

[0092] In another embodiment, different from that shown, the inverter circuit INV1 and the inverter circuit INV2 may have the same size, the inverter circuit INV3 may have a size that is two or more times larger than that of the inverter circuit INV1, and the inverter circuit INV4 may have a size that is three or more times larger than that of the inverter circuit INV1.

[0093] As described with reference to FIGS. 8A and 8B, the repeater R may include an even number of inverter circuits connected in series, and may be configured such that the size of the inverter circuit is equal to or greater than the size of the inverter circuit in the previous stage. The repeater R shown in FIGS. 8A and 8B may drive the delayed clock signal DCLK to generate a delayed clock signal DCLK having the same phase without signal attenuation.

[0094] FIGS. 9A and 9B are diagrams showing the configuration of an inverting repeater according to an exemplary embodiment.

[0095] Referring to FIG. 9A, the inverting repeater IR may have a configuration in which the inverter circuit INV3 is added to the configuration of the repeater R in FIG. 8A.

[0096] Referring to FIG. 9B, the inverting repeater IR may have a configuration in which the inverter circuit INV5 is added to the configuration of the repeater R in FIG. 8B.

[0097] As described with reference to FIGS. 9A and 9B, the inverting repeater IR may include an odd number of inverter circuits connected in series, and may be configured such that the size of the inverter circuit is equal to or greater than the size of the inverter circuit in the previous stage.

[0098] The inverting repeater IR shown in FIGS. 9A and 9B may drive the delayed clock signal DCLK to generate an inverted delayed clock signal DCLKB having an opposite phase.

[0099] According to an exemplary embodiment, the length of the signal line between the inverter circuits of each of the repeaters R and each of the inverting repeaters IR shown in FIGS. 8A to 9B may be smaller than the length of the signal line between the repeaters R shown in FIGS. 5, 6, and 7.

[0100] FIG. 10 is a diagram showing the configuration of an inverter of a repeater according to an exemplary embodiment.

[0101] Referring to FIG. 10, the inverter I may include a P type metal oxide semiconductor (PMOS) transistor P (having a source connected to the power supply voltage VDD, a gate connected to the input node in, and a drain connected to the output node on) and an N type metal oxide semiconductor (NMOS) transistor N (having a source connected to the ground voltage, a gate coupled to the input node in, and a drain coupled to the output node on). The inverter I may invert the signal applied to the input node in and output the inverted signal through the output node on.

[0102] FIG. 11 is a waveform diagram for illustrating the operation of the clock signal delay path unit according to an exemplary embodiment.

[0103] Referring to FIGS. 5 to 11, a delayed clock signal DCLK having a 50% duty ratio may be generated at the first node n1.

[0104] The delayed clock signal DCLK may be transmitted through a root signal line sl1 connected between the first node n1 and an intermediate node mn and a repeater R connected to the root signal line sl1. At this time, due to the change of PVT, the signal transmission rate by the NMOS transistor N of the inverter I constituting the repeater R connected to the root signal line sl1 may become lower than the signal transmission rate by its PMOS transistor P. Thereby, the transition of the delayed clock signal DCLK from the "high" level to the "low" level may be delayed, and thus a delayed clock signal DCLK having a duty ratio greater than 50% may be generated at the intermediate node mn. For example, every time the delayed clock signal DCLK passes through the repeater R, the duty ratio may gradually increase and reach 55% at the intermediate node mn.

[0105] The delayed clock signal DCLK of the intermediate node mn may be transmitted through a multiplexer MUX. When the delayed clock signal DCLK is transmitted from the intermediate node mn through the multiplexer MUX or the duty cycle corrector DCC and the multiplexer MUX, since the signal line is short, the change of the duty ratio caused by the change of PVT may be ignored. Thereby, the phase of the delayed clock signal DCLK transmitted from the intermediate node mn through the multiplexer MUX or the duty cycle corrector DCC and the multiplexer MUX is inverted by the inverting repeater IR, and thus an inverted delayed clock signal DCLKB having a 45% duty ratio may be generated at the second node n2.

[0106] The inverted delay clock signal DCLKB can be transmitted from the second node n2 to the fourth branch nodes (the fourteenth node n14 to the twenty-third node n23) via the repeater R through the branch signal line. At this time, due to the change of PVT, the signal transmission rate through the NMOS transistor N of the inverter I that constitutes the repeater R on the first to fourth signal lines from the second node n2 to the fourth branch nodes (the fourteenth node n14 to the twenty-third node n23) may become lower than the signal transmission rate through its PMOS transistor P. Thereby, the transition of the inverted delay clock signal DCLKB with a 45% load ratio from the "high" level to the "low" level at the second node n2 is delayed, and thus an inverted delay clock signal DCLKB with a 50% load ratio can be generated at each of the fourth branch nodes (the fourteenth node n14 to the twenty-third node n23).

[0107] In addition, the phase splitter PS and the selector MUX can invert the phase of the inverted delay clock signal DCLKB with a 50% load ratio at the fourth branch nodes (the fourteenth node n14 to the twenty-third node n23) to generate internal clock signals ick1 to ick8, an output data strobe signal dqso, and an inverted output data strobe signal dqsob with a 50% load ratio. For example, when the output nodes of the phase splitter PS and the selector MUX connected to the fourteenth node n14 to the twenty-third node n23 are n14' to n23', internal clock signals ick1 to ick8, an output data strobe signal dqso, and an inverted output data strobe signal dqsob with a 50% load ratio can be generated at the output nodes n14' to n23'.

[0108] FIG. 12 is a block diagram showing the configuration of a duty cycle corrector according to an exemplary embodiment. The functions of each block shown in FIG. 12 will be described as follows.

[0109] The duty cycle corrector (DCC) can include a load detector 70 and a load regulator 72.

[0110] The load detector 70 can generate a first pumping voltage and a second pumping voltage (for example, by performing a pumping operation in response to internal clock signals ick and ickB with a 180-degree phase difference), compare the first pumping voltage with the second pumping voltage to generate a comparison output signal, and generate a code CODE (with a predetermined number of bits) and an inverted code CODEB (with a predetermined number of bits) by performing an up-counting or down-counting operation according to the comparison output signal.

[0111] The load regulator 72 can adjust the slopes of the rising transition and the falling transition of the delayed clock signal DCLK at the intermediate node mn in response to the code CODE and the inverted code CODEB, so as to control the load ratio of the delayed clock signal DCLK.

[0112] FIG. 13 is a block diagram showing the configuration of a load detector according to an exemplary embodiment. The functions of each block shown in FIG. 13 will be described as follows.

[0113] The load detector 70 may include a charge pump 70-2, a comparator 70-4, and a counter 70-6.

[0114] The charge pump 70-2 can generate a first pump voltage CP1 by performing a pumping operation in response to the internal clock signal ick, and generate a second pump voltage CP2 by performing a pumping operation in response to the inverted internal clock signal ickB.

[0115] The comparator 70-4 can compare the first pump voltage CP1 with the second pump voltage CP2 to generate a comparison output signal COUT.

[0116] The counter 70-6 can generate a code CODE (having a predetermined number of bits) and an inverted code CODEB (having a predetermined number of bits) by performing an up-counting or down-counting operation in response to the comparison output signal COUT.

[0117] FIG. 14 is a circuit diagram showing the configuration of a load regulator according to an exemplary embodiment.

[0118] Referring to FIG. 14, the load regulator 72 may include a first regulator 72-2 and a second regulator 72-4 connected in series.

[0119] Each of the first regulator 72-2 and the second regulator 72-4 may include i+1 inverters connected in parallel, namely a first inverter I1 and i second inverters I21 to I2i.

[0120] The first inverter I1 may include: a first PMOS transistor P11 connected between the power supply voltage VDD and the first output node on1 or the second output node on2; and a first NMOS transistor N11 connected between the first output node on1 or the second output node on2 and the ground voltage.

[0121] Each of the second inverters I21 to I2i may include: a second PMOS transistor P21, …, or Pi1 and a third PMOS transistor P22, …, or Pi2 connected in series between a power supply voltage VDD and a first output node on1 or a second output node on2; and a third NMOS transistor N22, …, or Ni2 and a second NMOS transistor N21, …, or Ni1 connected in series between the first output node on1 or the second output node on2 and a ground voltage.

[0122] The first inverter I1 of the first regulator 72-2 may invert the delayed clock signal DCLK of the intermediate node mn, and output an inverted clock signal INA having a phase opposite to that of the delayed clock signal DCLK to the first output node on1.

[0123] Each of the second inverters I21 to I2i of the first regulator 72-2 may adjust the slope of the rising transition or the falling transition of the inverted clock signal INA in response to the delayed clock signal DCLK of the intermediate node mn and the corresponding bits c1, …, or ci of the i-bit code CODE, so as to control the duty ratio of the inverted clock signal INA.

[0124] The first inverter I1 of the second regulator 72-4 may invert the inverted clock signal INA, and output a clock signal INB having the same phase as the delayed clock signal DCLK to the second output node on2.

[0125] Each of the second inverters I21 to I2i of the second regulator 72-4 may adjust the slope of the rising transition or the falling transition of the clock signal INB in response to the inverted clock signal INA and the corresponding bits c1B, …, or ciB of the i-bit inverted code CODEB, so as to control the duty ratio of the clock signal INB.

[0126] FIG. 15A and FIG. 15B are diagrams showing the configurations of a phase splitter and a selector according to an exemplary embodiment.

[0127] Referring to FIG. 15A, the phase splitter PS may include a third inverter I3 to a tenth inverter I10.

[0128] The third inverter I3 to the seventh inverter I7 may receive the inverted delayed clock signal DCLKB of the fourteenth node n14, invert it, and output a clock signal CK having a phase opposite to that of the inverted delayed clock signal DCLKB.

[0129] The third inverter I3 to the fifth inverter I5 and the eighth inverter I8 to the tenth inverter I10 can receive the inverted delay clock signal DCLKB and output an inverted clock signal CKB having the same phase as the phase of the inverted delay clock signal DCLKB.

[0130] The selector MUX can receive the clock signal CK and the inverted clock signal CKB, select the clock signal CK in response to the inverted clock signal CKB, and select the inverted clock signal CKB in response to the clock signal CK.

[0131] Referring to FIG. 15B, the phase splitter PS’ may include the third inverter I3 to the ninth inverter I9.

[0132] The third inverter I3 to the sixth inverter I6 can receive the inverted delay clock signal DCLKB of the fourteenth node n14, invert it, and output an inverted clock signal CKB having the same phase as the phase of the inverted delay clock signal DCLKB.

[0133] The third inverter I3, the fourth inverter I4, and the seventh inverter I7 to the ninth inverter I9 can invert the inverted delay clock signal DCLKB and output a clock signal CK having a phase opposite to the phase of the inverted delay clock signal DCLKB.

[0134] The selector MUX can receive the inverted clock signal CKB and the clock signal CK, select the inverted clock signal CKB in response to the clock signal CK, and select the clock signal CK in response to the inverted clock signal CKB.

[0135] FIG. 16 is a diagram showing a clock signal delay path unit according to an exemplary embodiment.

[0136] The clock signal delay path unit may include a first delay cell DC1’, a second delay cell DC2’, and a third delay cell DC3’.

[0137] Except that all nodes (i.e., the start node sn, the middle node mn, the branch node dn, and the target node tn) are provided in pairs (i.e., the start node pair sn1 and sn2, the middle node pair mn1 and mn2, the branch node pair dn1 and dn2, and the target node pair tn1 and tn2), all signal lines (i.e., the first signal line rsl1, the second signal line rsl2, the first intermediate signal line msl1, the second intermediate signal line msl2, the first branch signal line dsl1, and the second branch signal line dsl2) are provided in pairs (i.e., the first signal line pair rslp1, the second signal line pair rslp2, the first intermediate signal line pair mslp1, the second intermediate signal line pair mslp2, the first branch signal line pair dslp1, and the second branch signal line pair dslp2), and the clock signal pair CLK and CLKB is transmitted instead of the clock signal CLK, the clock signal delay path unit shown in FIG. 16 may be the same as the clock signal delay path unit shown in FIG. 1.

[0138] By referring to the operation of the clock signal delay path unit in FIG. 1, the operation of the clock signal delay path unit shown in FIG. 16 can be easily understood.

[0139] FIGS. 17A and 17B are block diagrams showing a semiconductor memory device 200 according to an exemplary embodiment. Each block shown in FIGS. 17A and 17B will be described below.

[0140] The semiconductor memory device 200 may include a control signal terminal 110-2, a read enable signal terminal 110-4, an inverted read enable signal terminal 110-6, a read enable signal buffer (REB) 112-2, an inverted read enable signal buffer (REBB) 112-4, a control logic unit 114, a voltage generator 116, a column decoder 118, a row decoder 120, a memory cell array 122, a read enable signal delay path unit 124, a page buffer 126, a data write path unit 128, a data read path unit 130, a data input unit 132, a data output unit 134, a data strobe signal input unit 136, a data strobe signal output unit 138, data terminals 140-1 to 140-n, a data strobe signal terminal 142-1, and an inverted data strobe signal terminal 142-2.

[0141] The data input unit 132 may include n data input drivers (DID) 132-1 to 132-n.

[0142] The data output unit 134 may include n data output drivers (DOD) 134-1 to 134-n.

[0143] The data strobe signal input unit 136 may include a data strobe signal input driver (DQSID) 136-2 and an inverted data strobe signal input driver (DQSIBD) 136-4.

[0144] The data strobe signal output unit 138 may include a data strobe signal output driver (DQSOD) 138-2 and an inverted data strobe signal output driver (DQSOBD) 138-4.

[0145] The control signal terminal 110-2 may receive a control signal CON (e.g., a command enable signal CE, a write enable signal WE, a command latch enable signal CLE, and an address latch enable signal ALE (not shown)).

[0146] The read enable signal terminal 110-4 may receive a read enable signal RE.

[0147] The inverted read enable signal terminal 110-6 may receive an inverted read enable signal REB.

[0148] The read enable signal buffer (REB) 112-2 may buffer the read enable signal RE and output a buffered read enable signal reb.

[0149] The inverted read enable signal buffer (REBB) 112-4 may buffer the inverted read enable signal REB and output a buffered inverted read enable signal rebb.

[0150] The control logic unit 114 may generate a program command PGM and a read command RD in response to the control signal CON, the buffered read enable signal reb, and the buffered inverted read enable signal rebb. The control logic unit 114 may receive a command COM in response to the command latch enable signal CLE and the write enable signal WE, and may receive an address ADD in response to the address latch enable signal ALE and the write enable signal WE, or may receive an address ADD in response to the address latch enable signal ALE, the buffered read enable signal reb, and the buffered inverted read enable signal rebb.

[0151] The voltage generator 116 may receive a power supply voltage VDD and a ground voltage VSS, generate a drive voltage DV for a program operation in response to the program command PGM, and generate a drive voltage DV for a read operation in response to the read command RD.

[0152] The column decoder 118 can receive a driving voltage DV for a program operation in response to a program command PGM, and decode a column address RADD to drive a plurality of word line selection signals wl, a plurality of source line selection signals ssl, and a plurality of ground selection signals gsl, or can receive a driving voltage DV for a read operation in response to a read command RD, and decode the column address RADD to drive the plurality of word line selection signals wl, the plurality of source line selection signals ssl, and the plurality of ground selection signals gsl.

[0153] The row decoder 120 can receive a row address CADD and decode the row address CADD to generate a plurality of row selection signals csl.

[0154] The memory cell array 122 can include a plurality of memory cells. The memory cell array 122 can program program data pd into the memory cells (the memory cells are selected by a plurality of word line selection signals wl, a plurality of source line selection signals ssl, a plurality of ground selection signals gsl, and a plurality of row selection signals csl) in response to a program command PGM, and can output read data rd from the selected memory cells in response to a read command RD. The plurality of memory cells can be flash memory cells, the memory cell array 122 can be a flash memory cell array, and the semiconductor memory device 200 can be a flash memory device.

[0155] The read enable signal delay path unit 124 can transmit a buffered read enable signal reb and a buffered inverted read enable signal rebb through a signal line pair in response to a read command RD to generate an output data strobe signal dqso, an inverted output data strobe signal dqsob, and n internal clock signals ick1 to ickn.

[0156] The read enable signal delay path unit 124 can correct the load ratios of the buffered read enable signal reb and the buffered inverted read enable signal rebb. The load ratios may change due to changes in PVT in the signal line pair. The buffered read enable signal reb and the buffered inverted read enable signal rebb are transmitted through the signal line pair. For example, even if the load ratios of the buffered read enable signal reb and the buffered inverted read enable signal rebb increase (or decrease) in the signal line pair due to changes in PVT, the read enable signal delay path unit 124 can also decrease (or increase) the load ratios of the buffered read enable signal reb and the buffered inverted read enable signal rebb to correct the load ratios by inverting the phases of the buffered read enable signal reb and the buffered inverted read enable signal rebb at the midpoint of the signal line pair. Thereby, the load ratios of the output data strobe signal dqso, the inverted output data strobe signal dqsob, and the n internal clock signals ick1 to ickn generated from the read enable signal delay path unit 124 can be corrected.

[0157] The page buffer 126 can buffer the write data DI in response to the program command PGM to output the write data DI as the program data pd, and can buffer the read data rd in response to the read command RD to output the read data rd as the read data DO.

[0158] The data write path unit 128 can convert the input data di into parallel data in response to the program command PGM to output the write data DI.

[0159] The data read path unit 130 can convert the read data DO into serial data in response to the read command RD to output the output data do.

[0160] The data input drivers 132-1 to 132-n can be connected to the n data terminals 140-1 to 140-n, and can drive n data DQ1 to DQn to generate n input data di1 to din respectively.

[0161] The data output drivers 134-1 to 134-n can be connected to the n data terminals 140-1 to 140-n, and can drive n output data do1 to don to generate n data DQ1 to DQn respectively.

[0162] The data strobe signal input driver 136-2, the inverted data strobe signal input driver 136-4, the data strobe signal output driver 138-2, and the inverted data strobe signal output driver 138-4 can perform functions identical to those of the data strobe signal input driver 36-1, the inverted data strobe signal input driver 36-2, the data strobe signal output driver 34-1, and the inverted data strobe signal output driver 34-2 described with reference to FIG. 2B.

[0163] The output node of the read enable signal buffer 112-2 and the inverted output node of the inverted read enable signal buffer 112-4 of the semiconductor memory device 200 shown in FIGS. 17A and 17B can correspond to the start node pairs sn1 and sn2 shown in FIG. 16. The read enable signal delay path unit 124 of the semiconductor memory device 200 shown in FIGS. 17A and 17B can be different from the clock signal delay path units 18-4, 18-4', and 18-4" of the semiconductor memory device 100 described with reference to FIGS. 5 to 7 (where each signal line is a single signal line), the difference being that the signal lines can be provided in pairs, as shown in FIG. 16.

[0164] Similarly, the read enable signal delay path unit 124 can be different from the clock signal delay path units 18-4, 18-4', and 18-4" of the semiconductor memory device 100 described with reference to FIGS. 5 to 7 (where each of the first node n1 and the fourth branch nodes (the fourteenth node n14 to the twenty-third node n23) is a single node), the difference being that the nodes can be provided in pairs, as shown in FIG. 15.

[0165] The phases of the buffered read enable signal reb and the buffered inverted read enable signal rebb are inverted by the inverting relay IR, as shown in FIG. 16. In order to restore the phases of the buffered read enable signal reb and the buffered inverted read enable signal rebb, the buffered read enable signal reb and the buffered inverted read enable signal rebb can be applied to the first node pair in a cross manner.

[0166] As another example, a selector can be provided between the fourth branch nodes (the fourteenth node n14 to the twenty-third node n23), the data output drivers 134-1 to 134-n, the data strobe signal output driver 138-2, and the inverted data strobe signal output driver 138-4. The selector can be configured to alternately output a set of inverted internal clock signals, inverted output data strobe signals, and output data strobe signals and a set of internal clock signals, output data strobe signals, and inverted output data strobe signals from among the internal clock signal pair, the output data strobe signal pair, and the inverted output data strobe signal pair.

[0167] Figures 18A and 18B are diagrams showing the configuration of the repeater R according to an exemplary embodiment.

[0168] Figures 18A and 18B correspond to a case where the buffered read enable signal reb and the buffered inverted read enable signal rebb shown in Figures 17A and 17B are transmitted.

[0169] Referring to Figure 18A, the repeater R may include two inverter circuits INV1 and INV2 connected in series.

[0170] The inverter circuit INV1 may include a single inverter amplifier CML.

[0171] The inverter circuit INV2 may include two inverter amplifiers CML connected in parallel.

[0172] The inverter amplifier CML may be an inverter current mode logic differential amplifier.

[0173] The inverter circuit INV2 may have a size twice as large as that of the inverter circuit INV1. In another embodiment, different from that shown, the inverter circuit INV2 may have the same size as the inverter circuit INV1 or a size three times or more times larger than that of the inverter circuit INV1.

[0174] Referring to Figure 18B, the repeater R may include four inverter circuits INV1 to INV4 connected in series.

[0175] The inverter circuit INV1 and the inverter circuit INV2 may have the same configuration as that described with reference to Figure 18A.

[0176] The inverter circuit INV3 may include four inverter amplifiers CML connected in parallel. The inverter circuit INV3 may have a size four times as large as that of the inverter circuit INV1.

[0177] The inverter circuit INV4 may include six inverter amplifiers CML connected in parallel. The inverter circuit INV4 may have a size six times as large as that of the inverter circuit INV1.

[0178] The inverter amplifier CML may be an inverter current mode logic differential amplifier.

[0179] In another embodiment, different from that shown, the inverter circuit INV1 and the inverter circuit INV2 have the same size, the inverter circuit INV3 may have a size two times or more times larger than that of the inverter circuit INV1, and the inverter circuit INV4 may have a size three times or more times larger than that of the inverter circuit INV1.

[0180] As described with reference to FIGS. 18A and 18B, the repeater R may include an even number of inverter circuits connected in series, and may be configured such that the size of the inverter circuit is equal to or greater than the size of the inverter circuit in the previous stage.

[0181] FIGS. 19A and 19B are diagrams showing the configuration of an inverting repeater according to an exemplary embodiment.

[0182] Referring to FIG. 19A, the inverting repeater IR may have the same configuration as the inverting repeater IR shown in FIG. 18A, except that the output signal line pair of the inverter circuit INV1 of the inverting repeater IR in FIG. 18A is cross-coupled to the input signal line pair of the inverter circuit INV2.

[0183] Referring to FIG. 19B, the inverting repeater IR may have the same configuration as the repeater R shown in FIG. 18B, except that the output signal line pair of the inverter circuit INV2 of the inverting repeater IR in FIG. 18B is cross-coupled to the input signal line pair of the inverter circuit INV3.

[0184] In another embodiment, different from that shown, the inverting repeater IR may be configured by cross-coupling the output signal line pair of the inverter circuit INV1 in FIG. 19B to the input signal line pair of the inverter circuit INV2.

[0185] As described with reference to FIGS. 19A and 19B, the inverting repeater IR may include an even number of inverter circuits connected in series, and may be configured by cross-coupling the output signal line pair of the inverter circuit in the previous stage (between two sequentially connected inverter circuits) to the input signal line pair of the inverter circuit in the subsequent stage. Thereby, the inverting repeater IR can invert the phase of the input signal. In addition, the inverting repeater IR may be configured such that the size of the inverter circuit in the subsequent stage is equal to or greater than the size of the inverter circuit in the previous stage.

[0186] FIG. 20 is a diagram showing the configuration of an inverting current-mode logic differential amplifier according to an exemplary embodiment.

[0187] Referring to FIG. 20, the complementary metal-oxide-semiconductor (CMOS) current-mode logic differential amplifier CML may include: a first resistor R1 (connected between a power supply voltage VDD and an inverting output node onb); a second resistor R2 (connected between the power supply voltage VDD and an output node on); a first NMOS transistor N1 (having a drain connected to the inverting output node onb, a gate connected to an input node in, and a source connected to an intermediate node mn); a second NMOS transistor N2 (having a drain connected to the output node on, a gate connected to an inverting input node inb, and a source connected to the intermediate node mn); and a third NMOS transistor N3 (having a drain connected to the intermediate node mn, a gate to which a bias voltage VBIAS is applied, and a source connected to a ground voltage).

[0188] When the third NMOS transistor N3 is turned on in response to the bias voltage VBIAS, the complementary metal-oxide-semiconductor (CMOS) current-mode logic differential amplifier CML can be enabled.

[0189] When the complementary metal-oxide-semiconductor (CMOS) current-mode logic differential amplifier CML is enabled and the voltage level of an input signal applied to the input node in is higher than the voltage level of an inverting input signal applied to the inverting input node inb, the current flowing through the first NMOS transistor N1 is greater than the current flowing through the second NMOS transistor N2, and thus the level of the inverting output node onb becomes lower than the level of the output node on. That is, an inverting output signal can be generated at a "low" level and an output signal can be generated at a "high" level.

[0190] On the other hand, when the complementary metal-oxide-semiconductor (CMOS) current-mode logic differential amplifier CML is enabled and the voltage level of an input signal applied to the input node in is lower than the voltage level of an inverting input signal applied to the inverting input node inb, an output signal can be generated at a "low" level and an inverting output signal can be generated at a "high" level.

[0191] Although not shown, a clock signal delay path unit according to an exemplary embodiment of the embodiment can be used to delay a data strobe signal pair (a data strobe signal DQS and an inverting data strobe signal DQSB) and transmit the data strobe signal pair without signal attenuation.

[0192] As a summary and review, the clock signal delay path unit may include a repeater on a signal line to transmit a delayed clock signal without signal attenuation, and the signal attenuation may be caused by a long signal line length from an output node (i.e., a signal source) of a delay locked loop (generating the delayed clock signal) to a target block.

[0193] As described above, embodiments may provide a clock signal delay path unit and a semiconductor memory device including the clock signal delay path unit, the clock signal delay path unit being configured to correct a change in a load ratio of a clock signal in a signal line (e.g., due to changes in a process, voltage, and temperature).

[0194] Embodiments may provide a clock signal delay path unit, the clock signal delay path unit being configured to correct a load ratio of a clock signal by inverting a phase of the clock signal at a position where a change in a total load ratio that appears in a signal line (e.g., due to changes in a process, voltage, and temperature) is halved. Thereby, an operation reliability of a semiconductor memory device including the clock signal delay path unit may be improved.

[0195] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art at the time of filing this application that, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Thereby, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the following claims.

Brief Description of the Drawings

[0007] The features will become apparent to those skilled in the art by describing the exemplary embodiments in detail with reference to the accompanying drawings, wherein: FIG. 1 is a diagram showing a clock signal delay path unit according to an exemplary embodiment. FIGS. 2A and 2B are block diagrams of a semiconductor memory device according to an exemplary embodiment. FIG. 3 is a diagram showing the layout of a semiconductor memory device according to an exemplary embodiment. FIG. 4 is a diagram showing the vertical layout of a peripheral circuit area according to an exemplary embodiment. FIG. 5 is a diagram showing the configuration of a clock signal delay path unit according to an exemplary embodiment. FIG. 6 is a diagram showing the configuration of a clock signal delay path unit according to an exemplary embodiment. FIG. 7 is a diagram showing the configuration of a clock signal delay path unit according to an exemplary embodiment. FIGS. 8A and 8B are diagrams showing the configuration of a repeater according to an exemplary embodiment. FIGS. 9A and 9B are diagrams showing the configuration of an inverting repeater according to an exemplary embodiment. FIG. 10 is a diagram showing the configuration of an inverter of a repeater according to an exemplary embodiment. FIG. 11 is a waveform diagram for explaining the operation of a clock signal delay path unit according to an exemplary embodiment. FIG. 12 is a block diagram showing the configuration of a duty cycle corrector according to an exemplary embodiment. FIG. 13 is a block diagram showing the configuration of a duty detector according to an exemplary embodiment. FIG. 14 is a circuit diagram showing the configuration of a duty adjustor according to an exemplary embodiment. FIGS. 15A and 15B are diagrams showing the configuration of a phase splitter and a selector according to an exemplary embodiment. FIG. 16 is a diagram showing a clock signal delay path unit according to an exemplary embodiment. FIGS. 17A and 17B are block diagrams of a semiconductor memory device according to an exemplary embodiment. FIGS. 18A and 18B are diagrams showing the configuration of a repeater R according to an exemplary embodiment. FIGS. 19A and 19B are diagrams showing the configuration of an inverting repeater according to an exemplary embodiment. FIG. 20 is a diagram showing the configuration of an inverting current-mode logic differential amplifier according to an exemplary embodiment.

Claims

1. A clock signal delay path unit, comprising: At least one first delay cell includes a first signal line for delaying and transmitting a clock signal, a first repeater for transmitting the clock signal transmitted via the first signal line without signal attenuation, and a second signal line for delaying and transmitting the clock signal output from the first repeater; the second delay cell includes a first inverting circuit for inverting the clock signal provided from the first delay cell to generate an inverted clock signal; And at least one third delay cell, including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater for transmitting the inverted clock signal transmitted via the first branch signal line without signal attenuation, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater, wherein each of the first signal line, the second signal line, the first branch signal line, and the second branch signal line is a long metal wire, wherein: the first repeater includes an even number of third inverting circuits connected in series, the second repeater includes an even number of fourth inverting circuits connected in series, and the length of each of the first signal line and the second signal line is greater than the length of the signal line between the third inverting circuits, or the length of each of the first branch signal line and the second branch signal line is greater than the length of the signal line between the fourth inverting circuits.

2. The clock signal delay path unit as claimed in claim 1, wherein the number of first repeaters included in the at least one first delay cell is equal to the number of second repeaters included in the at least one third delay cell.

3. The clock signal delay path unit as claimed in claim 1, wherein the second delay cell comprises: The first intermediate signal line is used to delay the clock signal provided from the first delay cell and transmit the delayed clock signal to the first inverting circuit. A third repeater is configured to transmit the inverted clock signal output from the first inverting circuit without signal attenuation; and a second intermediate signal line is configured to delay the inverted clock signal output from the third repeater, wherein each of the first intermediate signal line and the second intermediate signal line is a long metal wire.

4. The clock signal delay path unit as described in claim 3, wherein: The third repeater includes an even number of second inverting circuits connected in series, and the length of each of the first intermediate signal line and the second intermediate signal line is greater than the length of the signal line between the first inverting circuit and the third repeater, or greater than the length of the signal line between the even number of second inverting circuits connected in series.

5. The clock signal delay path unit as claimed in claim 4, wherein each of the first inverting circuit and the second inverting circuit is a first inverter.

6. The clock signal delay path unit as claimed in claim 1, wherein each of the third inverting circuit and the fourth inverting circuit is a second inverter.

7. The clock signal delay path unit as described in claim 1 further includes: The fifth inverting circuit is configured to invert and apply the clock signal applied to the first delay cell; Alternatively, a sixth inverting circuit may be configured to invert and output the inverted clock signal provided from the third delay cell.

8. The clock signal delay path unit as described in claim 1, wherein: Each of the first signal line, the second signal line, the first branch signal line, and the second branch signal line is provided in pairs. The first repeater is connected between the first signal line pair and the second signal line pair and is configured to transmit clock signal pairs including the clock signal without signal attenuation. The first inverting circuit is configured to invert the clock signal pairs to generate inverted clock signal pairs including the inverted clock signal. The second repeater is connected between the first branch signal line pair and the second branch signal line pair and is configured to transmit the inverted clock signal pairs without signal attenuation. Each of the first signal line pair, the second signal line pair, the first branch signal line pair, and the second branch signal line pair is a long metal wire pair.

9. The clock signal delay path unit as claimed in claim 8, wherein the number of first repeaters included in the at least one first delay cell is equal to the number of second repeaters included in the second delay cell.

10. The clock signal delay path unit as claimed in claim 8, wherein the second delay cell further comprises: The first intermediate signal line pair is used to delay the clock signal pair provided from the first delay cell and transmit the delayed clock signal pair to the first inverting circuit. A third repeater is configured to transmit the inverted clock signal pair output from the first inverting circuit without signal attenuation; and a second intermediate signal line pair is configured to delay the inverted clock signal pair output from the third repeater, wherein each of the first intermediate signal line pair and the second intermediate signal line pair is a long metal line pair.

11. The clock signal delay path unit as described in claim 10, wherein: The third repeater includes an even number of second inverting circuits connected in series, and the length of each of the first intermediate signal line pair and the second intermediate signal line pair is greater than the length of the signal line pair between the first inverting circuit and the third repeater, or greater than the length of the signal line pair between the even number of second inverting circuits connected in series.

12. The clock signal delay path unit as described in claim 11, wherein: The first inverting circuit includes an even number of first inverting amplifiers, the second inverting circuit includes an even number of second inverting amplifiers, and in the first inverting amplifiers, the output signal line pair of one first inverting amplifier is cross-coupled with the input signal line pair of another first inverting amplifier.

13. The clock signal delay path unit as described in claim 8, wherein: The length of each of the first signal line pair and the second signal line pair is greater than the length of the signal line pair between the third inverting circuit, and the length of each of the first branch signal line and the second branch signal line is greater than the length of the signal line pair between the fourth inverting circuit.

14. The clock signal delay path unit as claimed in claim 13, wherein each of the third inverting circuit and the fourth inverting circuit is a third inverting amplifier.

15. A semiconductor memory device, comprising: A clock signal input buffer is configured to buffer external clock signals applied from the outside and output a buffered clock signal. A delay-locked loop is configured to receive the buffered clock signal and generate a delayed clock signal that is delayed and locked to the external clock signal; a clock signal delay path unit is configured to delay and invert the delayed clock signal to generate n internal clock signals, data selection signals, and inverted data selection signals; a memory cell array includes multiple memory cells and outputs data stored in memory cells selected in response to multiple character line selection signals and multiple row selection signals; a data read path unit is configured to receive the data and convert the data into serial data to generate n data entries; The data output unit is configured to drive the n data lines in response to the n internal clock signals; and a data selection signal output unit, configured to drive the output of a data selection signal and the inverted output of a data selection signal, wherein: the clock signal delay path unit includes n+2 branch delay units, each branch delay unit including: at least one first delay cell, including a first signal line for delaying and transmitting the delayed clock signal, a first repeater configured to transmit the delayed clock signal transmitted via the first signal line without signal attenuation, and a second signal line for delaying and transmitting the delayed clock signal output from the first repeater; The second delay cell includes a first inverting circuit configured to invert the delayed clock signal provided from the first delay cell to generate an inverted delayed clock signal; and at least one third delay cell including a first branch signal line for delaying and transmitting the inverted delayed clock signal provided from the second delay cell, a second repeater configured to transmit the inverted delayed clock signal transmitted via the first branch signal line without signal attenuation, and a second branch signal line for delaying and transmitting the inverted delayed clock signal output from the second repeater, wherein each of the first signal line, the second signal line, the first branch signal line, and the second branch signal line is a long metal line, and the n+2 branch delay units generate the n internal clock signals, the output data selection signal, and the inverted output data selection signal.

16. The semiconductor memory device of claim 15, wherein the number of first repeaters included in the at least one third delay cell is equal to the number of second repeaters included in the second delay cell.

17. The semiconductor memory device of claim 15, wherein the branch signal lines of the first branch signal line and the second branch signal line have the same length in the n+2 branch delay units.

18. The semiconductor memory device of claim 15, wherein the second delay cell further comprises: The first intermediate signal line is used to delay the delayed clock signal provided from the second delay cell and transmit the delayed clock signal to the first inverting circuit; A third repeater is configured to transmit the inverted delayed clock signal output from the first inverting circuit without signal attenuation; and a second intermediate signal line is configured to delay the inverted delayed clock signal output from the third repeater, wherein each of the first intermediate signal line and the second intermediate signal line is a long metal wire.

19. The semiconductor memory device as claimed in claim 15, wherein, The third repeater includes an even number of second inverting circuits connected in series, and the length of each of the first intermediate signal line and the second intermediate signal line is greater than the length of the signal line between the first inverting circuit and the third repeater, or greater than the length of the signal line between the even number of second inverting circuits connected in series.

20. A semiconductor memory device, comprising: The read enable signal input buffer is configured to buffer read enable signals applied from the outside and output a buffered read enable signal. An inverted read enable signal input buffer is configured to buffer an externally applied inverted read enable signal and output a buffered inverted read enable signal; a read enable signal delay path is configured to delay and invert the buffered read enable signal and the buffered inverted read enable signal to generate n internal clock signals, an output data select signal, and an inverted output data select signal; a memory cell array includes multiple memory cells and outputs data stored in memory cells selected in response to multiple character line select signals, multiple source line select signals, multiple ground select signals, and multiple row select signals; a page buffer is configured to buffer the data to generate read data; The data reading path unit is configured to receive the read data and convert the read data into serial data to generate n data items; The data output unit is configured to drive the n data lines in response to the n internal clock signals; and a data selection signal output unit, configured to drive the output data selection signal and the inverted output data selection signal, wherein: the read enable signal delay path includes n+2 branch delay units, each branch delay unit including: at least one first delay cell, including a first signal line pair for delaying and transmitting a read enable signal pair including the buffered read enable signal and the buffered inverted read enable signal; a first repeater configured to transmit the read enable signal pair transmitted via the first signal line pair without signal attenuation; and a second signal line pair for delaying and transmitting the read enable signal pair output from the first repeater; The second delay cell includes a first inverting circuit configured to invert the read enable signal pair provided from the first delay cell and output an inverted read enable signal pair; and at least one third delay cell including a first branch signal line pair for delaying and transmitting the inverted read enable signal pair provided from the second delay cell, a second repeater configured to transmit the inverted read enable signal pair transmitted via the first branch signal line pair without signal attenuation, and a second branch signal line pair for delaying and transmitting the inverted read enable signal pair output from the second repeater, wherein each of the first signal line pair, the second signal line pair, the first branch signal line pair, and the second branch signal line pair is a long metal line pair, and the n+2 branch delay units generate the n internal clock signals, the output data select signal, and the inverted output data select signal.

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