Wafer fabrication methods

Abstract

[Problem] This invention provides a novel technique that prevents the peeling of insulating layers, interlayer peeling between metal layers and insulating layers, and burrs on the metal layers when dicing a wafer by cutting along a dicing track with a metal layer using a cutting blade. [Solution] A wafer processing method in which components 11 are formed in regions divided by a plurality of intersecting dicing tracks 13, and insulating layers 17a, 17b and a metal layer 18 are deposited in at least a portion of the dicing tracks 13, the wafer processing method comprising: a removal step in which the tip of a cutting blade 51a is positioned at a depth reaching the lower end of the metal layer 18, and the cutting blade 51a is used to cut along the dicing track 13 to remove the metal layer 18, the cutting blade 51a having a cutting thickness 51w of at least the width 18w of the metal layer 18 in the width direction (Y-axis direction) of the dicing track 13; and a dicing step in which, after performing the removal step, the wafer 10 is diced along the dicing track 13.

Description

[Technical Field]

[0001] The present invention relates to a wafer processing method, wherein components are formed in each region divided by a plurality of intersecting dicing channels, and an insulating layer and a metal layer are deposited in at least a portion of the dicing channels. [Previous Technology]

[0002] Typically, semiconductor devices are composed of functional layers, which are formed on the front side of a wafer made of semiconductor material. This functional layer includes a wiring layer made of metal and an insulating layer (interlayer insulating film) disposed between the wiring layers. As the material of the insulating layer, a low-dielectric-constant material, such as a Low-k material, can be used.

[0003] As Low-k materials, known materials include: inorganic materials such as SiO2, SiOC, and SiLK; organic materials that are polymers such as polyimide, poly(p-xylene), and polytetrafluoroethylene; and porous silica materials such as polysiloxane containing methyl groups.

[0004] The component portion forming the wiring layer is formed in areas divided by crisscrossing cuts, and the insulating layer is deposited between adjacent components in a manner that spans the cuts. If this insulating layer is cut with a cutting blade, the insulating layer will peel off in a mica-like manner. This peeling will affect the insulating layer inside the component, causing interlayer peeling between the wiring layer and the insulating layer inside the component.

[0005] This interlayer peeling is also known as delamination. Patent Document 1 discloses a method for addressing this peeling problem, in which a laser-processed groove is formed by a laser processing apparatus, and then the laser-processed groove is cut with a cutting blade. [Preferred Art Documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2006-190779 [Summary of the Invention]

[0007] [Problem to be solved by the invention] However, generally speaking, the laser processing apparatus disclosed in Patent Document 1 is expensive, and it is desirable to perform processing while preventing delamination by using a cutting device.

[0008] Furthermore, in cases where there is a metal layer constituting a TEG (Test Element Group) in the dicing path, if an ablation process is performed using a laser processing device, it is confirmed that metal-containing debris adheres to the front side of the wafer, and that this metal-containing debris enlarges over time.

[0009] If enlarged metal debris comes into contact with the terminals of a component or mounting substrate, there is a risk of short circuits in the chip wiring or electrodes. Therefore, this risk exists even when using a laser processing apparatus such as that in Patent Document 1.

[0010] In addition, there are various types of metal layers, such as those used for alignment patterns during TEG manufacturing, metal structures embedded as a dishing countermeasure during grinding. Some of these metal layers are exposed on the front side of the wafer, while others are embedded within the wafer, and all of these types of metal layers need to be considered.

[0011] On the other hand, assuming that the cutting is performed by a cutting device, if there is a metal layer in the cutting path, the metal layer and the insulating layer may peel off, and the metal layer may produce burrs. If burrs are produced, there is a concern that the insulating layer located in the cutting path may be pushed upwards and affect the insulating layer located inside the component, thereby causing the wiring layer and the insulating layer inside the component to peel off.

[0012] In view of the above problems, the present invention proposes a novel technology that can prevent the peeling of insulating layers, the interlayer peeling of metal layers and insulating layers, and the burrs of metal layers when the wafer is divided by cutting along the cutting path of the metal layer with a cutting blade.

[0013] [Technical means for solving the problem] The problem to be solved by the present invention is as described above. The technical means for solving this problem will be described below.

[0014] According to one aspect of the present invention, a wafer processing method is provided, wherein components are formed in each region divided by a plurality of intersecting dicing channels, and an insulating layer and a metal layer are deposited in at least a portion of the dicing channels. The wafer processing method comprises: a removal step in which the tip of a dicing blade is positioned at a depth reaching the lower end of the metal layer, and the dicing blade is used to cut along the dicing channels to remove the metal layer, wherein the dicing blade has a cutting thickness greater than the width of the metal layer in the width direction of the dicing channels; and a dicing step in which, after performing the removal step, the wafer is diced along the dicing channels.

[0015] Furthermore, according to one aspect of the present invention, a blade shape confirmation step is provided, which confirms the front end shape of the cutting blade after the removal step is performed on multiple wafers.

[0016] Furthermore, according to one aspect of the present invention, in the dicing step, the wafer is diced by cutting along the dicing path with a second cutting blade that is thinner than the cutting blade.

[0017] Furthermore, according to one aspect of the present invention, a metal layer confirmation step is further provided, which, prior to the removal step, confirms the cutting path where the metal layer is disposed, the position and width of the metal layer in the width direction of the cutting path, and the position and thickness of the metal layer in the thickness direction of the cutting path, and performs the removal step only on the position where the metal layer is disposed.

[0018] [Effects of the Invention] As an effect of the present invention, it performs the following effects.

[0019] That is, according to one embodiment of the present invention, since the cutting blade thickness of the cutting blade for removing the metal layer is set to be greater than the width of the metal layer, the entire metal layer, including the interface between the metal layer and the insulating layer, can be completely removed. By removing the interface between the metal layer and the insulating layer, which is prone to interlayer peeling, interlayer peeling of the insulating layer within the cutting path can be suppressed, thereby suppressing the occurrence of interlayer peeling (delamination) between the insulating layer and the wiring layer within the component. Furthermore, it can also prevent the occurrence of burrs on the metal layer, the upward push of the insulating layer caused by the metal layer, etc.

[0020] Furthermore, according to one aspect of the present invention, the removal step is performed only on the locations where the metal layer is disposed in all the cutting paths, thereby shortening the overall processing time.

[0021] Furthermore, according to one aspect of the present invention, it is possible to prevent the metal layer from being incompletely removed and forming a residue.

Implementation Method

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG1 is a diagram showing an embodiment of a wafer 10 processed by the processing method of the present invention. On the front side 10a of the wafer 10, elements 11, 11 are formed in areas divided by a plurality of intersecting dicing channels 13. The dicing channels 13 are configured to extend in mutually orthogonal first directions F1 and second directions F2 and to be arranged in a grid pattern.

[0024] As a material for wafer 10, silicon, glass, sapphire, SiC, etc. can be considered, and it is not particularly limited.

[0025] Figure 2 is an enlarged view of a cross-section of the wafer and a partial view of the dicing. A functional layer 14 is deposited on the front side 10a of the wafer 10. A component 11 is formed between the dicings 13 and 13. At the location of the component 11, a plurality of wiring layers made of metal and an insulating layer disposed between the wiring layers are deposited to form an integrated circuit.

[0026] The insulating layer is composed of Low-k materials (low dielectric constant materials) and is also known as a Low-k film. Low-k materials include: inorganic materials such as SiO2, SiOC, and SiLK; organic materials such as polymers such as polyimide, poly(p-xylene), and polytetrafluoroethylene; and porous silica materials such as methyl-containing polysiloxanes.

[0027] At the location of the cut 13, multiple insulating layers 17a, 17b... are laminated. These insulating layers 17a, 17b... are continuous with the insulating layer present in the component 11 portion.

[0028] At the location of the cutting path 13, a metal layer 18 is disposed between the multiple laminated insulating layers 17a, 17b. This metal layer 18 may be, for example, a TEG, an alignment pattern mark during component manufacturing, or a metal structure embedded as a countermeasure for disc-shaped recesses during grinding.

[0029] As shown in the example of Figure 2, the metal layer 18 may be embedded in multiple locations between the multiple insulating layers 17a and 17b that are laminated, or it may be exposed on the front side of the wafer (the front side of the dicing 13).

[0030] The metal layer 18 may be disposed on a portion of the cut channels 13 or on all of the cut channels 13. In addition, the metal layer 18 may be disposed at the intersection of the cut channels 13 or between adjacent components 11 sandwiched between the cut channels 13.

[0031] Figure 3 is a diagram showing an example of a cutting apparatus for dicing wafer 10. The cutting apparatus 50 has two cutting units 51 and 52, and is configured as a dual dicer.

[0032] A holding table 60 is provided on the base 55 of the cutting device 50. The holding table 60 is configured to move back and forth in the processing feed direction, i.e., the X-axis direction, by means of a moving mechanism (not shown). It is also configured to rotate in the horizontal plane by means of a rotating mechanism (not shown).

[0033] The wafer unit U on which the wafer 10 is attached to the adhesive film T is sequentially supplied to the holding stage 60, and the wafer 10 is held by the adhesive film T through the holding surface 61a of the holding stage 60.

[0034] A gate-shaped column 56 is erected on the base 55. Moving mechanisms 57 and 58 are provided on the column 56, supporting the first cutting unit 51 and the second cutting unit 52 in a manner that allows them to move in the Y-axis and Z-axis directions, respectively. Each cutting unit 51 and 52 is equipped with cutting blades 51a and 52a that are driven to rotate by a motor (not shown).

[0035] A plurality of clamps 63 and a waterproof cover 64 are arranged around the holding table 60. A secondary chuck platform 68 is provided on the upper surface of the waterproof cover 64, which exposes and holds the upper surface of the trimming plate 67. The waterproof cover 64 moves together with the holding table 60 in the X-axis direction, and the secondary chuck platform 68 also moves in the X-axis direction as the waterproof cover 64 moves.

[0036] Next, an embodiment of the wafer processing method of the present invention will be described. FIG4 is a flowchart showing one embodiment of the processing method of the present invention. The steps are described below in sequence.

[0037] <Metal Layer Confirmation Step> As shown in Figure 2, the steps are to confirm the cutting track 13 on which the metal layer is disposed, the position and width 18w of the metal layer 18 in the width direction (Y-axis direction) of the cutting track 13, and the position and thickness 18h of the metal layer 18 in the thickness direction (Z-axis direction) of the cutting track 13.

[0038] In cases where design information for the wafer 10, including information such as the placement and dimensions of the metal layer 18 within the wafer, is available, the dicing 13 containing the metal layer 18 is specified based on this design information, along with the position and width 18w (dimension) of the metal layer 18 within the dicing 13 in the width direction (Y-axis direction) and the position and thickness in the thickness direction (Z-axis direction) of the dicing 13. This information is stored in the controller 100 (FIG. 3), which determines the processing position and processing conditions in subsequent removal steps based on this information. Additionally, the operator can input processing conditions (such as the position of the cutting blade in the dicing 18 for complete removal of the metal layer in the Y-axis direction and the cutting depth) based on the design information and store them in the controller.

[0039] In cases where design information for the wafer 10, including the configuration location and dimensions of the metal layer 18 within the wafer, is unavailable, for example, a wafer with the same pattern is pre-cut using a dicing blade. The dicing ridge 13 containing the specific metal layer 18, the position and width 18w of the metal layer 18 within the dicing ridge in the width direction (Y-axis direction), and the position and thickness of the dicing ridge in the thickness direction (Z-axis direction) are stored in the controller 100. The controller 100 determines the processing position and processing conditions in subsequent removal steps based on this information. Additionally, the operator can input processing conditions (the position of the dicing blade in the Y-axis direction for completely removing the metal layer, the cutting depth, etc.) based on this specific information and store it in the controller.

[0040] <Removal Step> As shown in Figures 5 and 6, the step of removing the metal layer 18 by positioning the front end of the cutting blade 51a at a depth reaching the lower end of the metal layer 18 and cutting along the cutting path 13 with the cutting blade 51a, wherein the cutting blade 51a has a cutting thickness 51w of more than the width 18w of the metal layer 18 in the width direction (Y-axis direction) of the cutting path 13.

[0041] Accordingly, in the cutting path 13, within the range corresponding to the cutting blade thickness 51w of the cutting blade 51a, the insulating layers 17a, 17b and the metal layer 18 are removed. The cutting blade thickness 51w of the cutting blade 51a is set to be greater than the width 18w of the metal layer 18, so the entire metal layer 18 is completely removed, including the junction between the metal layer 18 and the insulating layers 17a, 17b.

[0042] Here, by removing the interface between the metal layer 18 and the insulating layers 17a and 17b, which are prone to interlayer peeling, interlayer peeling of the insulating layers 17a and 17b within the cut path 13 can be suppressed, thereby suppressing the occurrence of interlayer peeling (delamination) between the insulating layer and the wiring layer within the component 11. Furthermore, it can also prevent the occurrence of burrs on the metal layer 18 and the upward push of the insulating layer caused by the metal layer 18.

[0043] Furthermore, as shown in FIG6, the cutting blade 51a's blade thickness 51w can also be set to be greater than the width 18w of the widest metal layer 18 in the wafer 10, in a way that can remove all the metal layers 18 present in the wafer 10.

[0044] Alternatively, as shown in the configuration of the cutting device 50 in FIG3, in a configuration having two cutting units 51 and 52, the two cutting units 51 and 52 are used separately according to the width 18w (FIG. 6) of the metal layer 18 to be removed, thereby removing all the metal layer 18. The two cutting units 51 and 52 are equipped with cutting blades 51a and 52a with different blade thicknesses.

[0045] Furthermore, as shown in FIG6, the tip of the cutting blade 51a is preferably configured to cut into the functional layer 14, although it is lower than the lower end of the metal layer 18 in the depth direction (Z-axis direction). That is, cutting into the wafer 10 is avoided.

[0046] Accordingly, the metal layer 18 can be removed reliably, and the burden on the cutting blade 51a during cutting can be reduced. Then, the processing feed rate of the wafer 10 can be increased, thereby shortening the time required for the removal step.

[0047] Furthermore, this removal step is performed only on all the cutting channels where the metal layer 18 is disposed, or only on the location where the metal layer is disposed in each cutting channel, thereby shortening the overall processing time. In addition, all the cutting channels can be cut by the cutting blade 51a, thereby pre-forming a common shallow groove 19 in all the cutting channels (Fig. 7).

[0048] <Segmentation Step> As shown in Figure 7, this is a step of segmenting the wafer 10 along the dicing path 13 after the removal step. The example in Figure 7 is an example of complete cutting with a cutting blade 52a that is thinner than the cutting blade 51a (Figure 6) used in the removal step. In the dual dicing machine shown in Figure 3, a so-called step cut is performed, in which a shallow groove 19 is formed by the removal step performed by the cutting unit 51, and then a complete cut is performed by the other cutting unit 52.

[0049] In addition, in this segmented cutting, in addition to performing the removal step and the segmentation step sequentially for each cutting path 13, the segmentation step can also be performed after the removal step is performed for all cutting paths 13.

[0050] As shown in FIG7, when cutting is performed by cutting blade 52a, the metal layer 18 (FIG. 6) is completely removed. Therefore, the cutting of the metal layer 18 (FIG. 6) by cutting blade 52a is not required, and the remaining insulating layer 17c and wafer 10 are cut along the cutting path.

[0051] In addition, the segmentation step can be performed by complete cutting with cutting blade 52a as shown in FIG7, or by expanding the sheet after forming a modified layer along the cutting path by laser processing equipment, or by laser ablation processing.

[0052] <Blade Shape Confirmation Step> As shown in Figure 8(A), this is the step of confirming the front end shape (blade shape) of the cutting blade 51a at a predetermined time point.

[0053] In the removal step, the metal layer 18 needs to be completely removed (Fig. 6). As shown in Fig. 8(A), if the removal step is repeated, the blade edge of the cutting blade 51a will wear down, the edge of the front end will disappear, and a U-shaped front end profile will be formed. As shown in Fig. 8(B), for example, when performing the removal step on another wafer 10, the bottom surface of the groove will become a U-shaped groove, resulting in the metal layer 18 not being completely removed and a residual portion 18a will be formed.

[0054] Therefore, for example, at a predetermined time point after the removal step for a predetermined number of wafers, the tip shape of the cutting blade 51a is checked, and appropriate and necessary measures are taken. This prevents the metal layer 18 from being incompletely removed, thus preventing the formation of a residue 18a. Furthermore, the predetermined time point can be considered not only after the removal step for a predetermined number of wafers, but also during the processing of one wafer, after the processing of one wafer, etc.

[0055] As necessary measures, such as increasing the cutting depth by removing the metal layer 18 (height adjustment in the Z-axis direction), smoothing the blade edge by plane trimming, and replacing the cutting blade. Planar trimming is performed by cutting the upper surface of the trimming plate 67 shown in FIG3 to flatten the blade edge.

[0056] The shape of the cutting blade 51a is confirmed, for example, by first lowering a rotating cutting blade from above the wafer at the outer periphery of the wafer to cut into the wafer, thereby forming a cutting mark on both ends with the shape of the cutting blade's front end transferred. Alternatively, the outer periphery of the wafer is cut with a cutting blade positioned at a predetermined height, and the cutting blade is withdrawn midway through the cutting process, thereby forming a cutting mark on one end with the shape of the cutting blade's front end transferred. The formed cutting mark can be confirmed by image analysis.

[0057] Alternatively, during the removal process, when the cutting blade reaches the remaining area on the periphery of the wafer where no components are formed, the cutting blade can be withdrawn above the wafer, and the resulting cutting marks can be image analyzed.

[0058] In addition, the test piece can be held by the sub-chuck stage 68 shown in Figure 3, and the cutting marks can be formed on the test piece and confirmed by image analysis of the cutting marks, or the cross-section of the wafer can be directly photographed and confirmed by image analysis.

[0059] As described above, according to the present invention, the cutting blade thickness 51w of the cutting blade 51a for removing the metal layer 18 is set to be greater than the width 18w of the metal layer 18, so that the entire metal layer 18, including the interface between the metal layer 18 and the insulating layers 17a and 17b, can be completely removed. By removing the interface between the metal layer 18 and the insulating layers 17a and 17b, which are prone to interlayer peeling, interlayer peeling of the insulating layers 17a and 17b in the cutting path 13 can be suppressed, thereby suppressing the occurrence of interlayer peeling (delamination) between the insulating layer and the wiring layer present in the component 11. Furthermore, it can also prevent the occurrence of burrs on the metal layer 18 and the upward push of the insulating layer caused by the metal layer 18. [Simplified Explanation of the Diagram]

[0022] Figure 1 is a diagram showing an embodiment of a wafer processed by the processing method of the present invention. Figure 2 is an enlarged view of a cross-section of the wafer and a portion of the dicing path. Figure 3 is a diagram showing an embodiment of a dicing apparatus. Figure 4 is a flowchart showing a process of an embodiment of the processing method of the present invention. Figure 5 is a diagram showing the dicing process performed by a dicing blade. Figure 6 is a diagram illustrating the removal step. Figure 7 is a diagram illustrating the dicing step. Figure 8(A) is a diagram illustrating the wear of the dicing blade, and Figure 8(B) is a cross-sectional view illustrating the groove formed by the worn dicing blade.

Claims

1. A wafer fabrication method comprising: forming components in regions divided by intersecting dicing lines, wherein an insulating layer and a metal layer are deposited in at least a portion of the dicing lines; the wafer fabrication method comprising: a removal step, wherein a cutting edge of a dicing blade is positioned at a depth reaching the lower end of the metal layer, and the dicing blade is used to cut along the dicing lines to remove the metal layer, the dicing blade having a cutting thickness exceeding the width of the metal layer in the width direction of the dicing lines; and a dicing step, wherein, after performing the removal step, the wafer is diced along the dicing lines, wherein... Further comprising: a metal layer confirmation step, which, prior to the removal step, confirms the cutting path where the metal layer is disposed, the position and width of the metal layer in the width direction of the cutting path, and the position and thickness of the metal layer in the thickness direction of the cutting path.

2. The wafer fabrication method as described in claim 1, wherein, This removal step is performed only on the cut surface where the insulating layer and the metal layer are deposited.

3. The wafer processing method as described in claim 1 or 2, wherein, It includes: a blade shape confirmation step, which confirms the tip shape of the cutting blade after the removal step is performed on multiple wafers.

4. The wafer fabrication method as described in claim 1 or 2, wherein, In this dicing step, the wafer is diced by cutting along the dicing path with a second cutting blade that is thinner than the first cutting blade.

5. The wafer processing method as described in claim 1 or 2, wherein, The removal step is performed only at the location where the metal layer is configured.

6. The wafer fabrication method as described in claim 1 or 2, wherein, In this removal step, the metal layer is removed using a cutting blade with a blade thickness greater than the width of the widest metal layer within the wafer.

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