System and method for aging mitigation

Abstract

The various embodiments of this invention control the aging of the signal path in idle mode to mitigate aging. In one example, the input to the signal path is alternately placed at low and high levels during multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In yet another example, based on the aging mode, the input to the signal path is placed at a high or low level during each idle period.

Description

Technical Field

[0001] This patent application claims priority and benefits from non-provisional application No. 17 / 396,046, filed with the U.S. Patent and Trademark Office on August 6, 2021.

[0002] In summary, the subject matter of this case concerns aging, and more specifically, the subject matter of this case concerns aging mitigation. Prior Technology

[0003] Circuits can be affected by aging, such as bias temperature instability (BTI), which can reduce circuit performance over time. For example, BTI stress in the signal path of a circuit during idle mode can cause the duty cycle in the signal path to shift over time, which can lead to timing problems in the circuit (e.g., timing violations). Summary of the Invention

[0004] The following provides a brief overview of one or more implementations to offer a basic understanding of such implementations. This overview is not a generalization of all anticipated implementations, nor is it intended to identify key or essential components of all implementations or to describe the scope of any or all implementations. Its sole purpose is to serve as a prelude to the more detailed descriptions provided later, to provide some concepts of one or more implementations in a simplified form.

[0005] The first embodiment relates to a system. The system includes: a multiplexer having a first input, a second input, a selection input, and an output. The system also includes: a signal path having inputs and outputs, wherein the inputs of the signal path are coupled to the outputs of the multiplexer. The system further includes: a controller coupled to the second input of the multiplexer and the selection input of the multiplexer, wherein the controller has an indicator input. The controller is configured to: receive a mode indicator signal at the indicator input; if the mode indicator signal has a first logic value, instruct the multiplexer to select the first input of the multiplexer; and if the mode indicator signal has a second logic value, instruct the multiplexer to select the second input of the multiplexer, and output a control signal to the second input of the multiplexer, the control signal controlling whether the input of the signal path is at a high level or a low level.

[0006] The second state relates to a system. The system includes: a latch circuit having a signal input, a clock input, a set input, a reset input, and an output. The system also includes: a signal path having inputs and outputs, wherein the inputs of the signal path are coupled to the outputs of the latch circuit. The system further includes: a controller coupled to the set input and reset input of the latch circuit, wherein the controller has an indicator input. The controller is configured to: receive a mode indicator signal at the indicator input; if the mode indicator signal has a first logic value, cancel assertions on the set input and the reset input; and if the mode indicator signal has a second logic value, use the set input and the reset input to control whether the input of the signal path is at a high level or a low level.

[0007] The third-state sample relates to a method for aging control. The method includes: in an active mode, inputting a signal to an input of a signal path; and in an idle mode, controlling the aging of the signal path. Simple Explanation of the Diagram

[0008] Figure 1A illustrates an example of a signal path including a delay circuit, according to certain states of the case.

[0009] Figure 1B illustrates an example of a signal path input being placed at a low level in idle mode, according to certain states of the case.

[0010] Figure 1C illustrates an example of a duty cycle shift in the signal path due to asymmetric aging, according to certain states described in this case.

[0011] Figure 1D illustrates an example of a signal path input being placed at a high level in idle mode, according to certain states of the case.

[0012] Figure 1E illustrates another example of duty cycle shift in the signal path due to asymmetric aging, according to certain states of the case.

[0013] Figure 2 illustrates an example of a system including a multiplexer with aging control, based on certain aspects of the content of this case.

[0014] Figure 3A is a timing diagram illustrating an example of aging control for certain states according to the content of this case.

[0015] Figure 3B is a timing diagram illustrating another example of aging control according to certain conditions in this case.

[0016] Figure 4 illustrates an example of a controller including a circular shift register, based on certain states of the case.

[0017] Figure 5A illustrates another example of a system including a multiplexer with aging control, based on certain aspects of the content of this case.

[0018] Figure 5B illustrates an example of a system including a clock gating circuit from Figure 5A, based on certain aspects of the content of this case.

[0019] Figure 5C illustrates an exemplary implementation of a clock gating circuit of certain states according to the contents of this case.

[0020] Figure 6 illustrates another example of a system including a multiplexer with aging control, based on certain aspects of the content of this case.

[0021] Figure 7 illustrates another example of a system including a multiplexer with aging control, based on certain aspects of the content of this case.

[0022] Figure 8 illustrates another example of a system including a multiplexer with aging control, based on certain aspects of the content of this case.

[0023] Figure 9A illustrates an example of a system with aging control for two signal paths, according to certain aspects of the content of this case.

[0024] Figure 9B illustrates another example of a system with aging control for two signal paths, based on certain aspects of the content of this case.

[0025] Figure 10 illustrates an example of a system including a latching circuit with aging control, according to certain aspects of the content of this case.

[0026] Figure 11A illustrates another example of a system including a latch circuit with aging control, according to certain aspects of the present case.

[0027] Figure 11B illustrates an example of a system including a clock gating circuit in Figure 11A, based on certain aspects of the content of this case.

[0028] Figure 12 illustrates an example of a system including latching circuits and a multiplexer with aging control, based on certain aspects of the content of this case.

[0029] Figure 13 illustrates an example of a single data rate (SDR) to double data rate (DDR) converter system with aging control, according to certain aspects of the present case.

[0030] Figure 14 illustrates an exemplary implementation of a controller in some form according to the content of this case.

[0031] Figure 15 illustrates an example of a multiplexer configured to output aging control signals according to certain states of the case.

[0032] Figure 16 illustrates an example of a memory interface circuit with aging control in certain states according to the content of this case.

[0033] Figure 17 illustrates another example of a memory interface circuit with aging control, based on certain aspects of the content of this case.

[0034] Figure 18 is a flowchart illustrating a method for aging control of certain states according to the content of this case. Implementation

[0035] The embodiments described below with reference to the accompanying drawings are intended as a description of various configurations and are not intended to represent the only configuration in which the concepts described herein can be implemented. Specific details are included in the embodiments to provide a comprehensive understanding of the various concepts. However, it will be apparent to those skilled in the art to which this invention pertains that these concepts can be implemented without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0036] Aging effects such as bias temperature instability (BTI) can degrade circuit performance over time. For example, BTI stress in the signal path of a circuit during idle mode can cause time-varying duty cycles in the signal path, which can lead to timing problems in the circuit (e.g., timing violations).

[0037] Examples of duty cycle shift caused by BTI stress will now be discussed with reference to Figures 1A to 1E. Figure 1A illustrates an example of a signal path 105 including a delay circuit 115 for delaying signals in the signal path 105. The delay circuit 115 can be configured to delay a signal to adjust its timing relative to another signal. The signal can be a clock signal, a data signal, a control signal, an address signal, or another type of signal. In the example where the signal is a clock signal, the delay circuit 115 can be used to adjust the timing of the clock signal to center the clock signal between transitions of the data signal for data retrieval. In the example where the signal is a data signal, the delay circuit 115 can be used to adjust the timing of the data signal to align the data signal with another data signal (e.g., reduce the offset between data signals). For an instance where signal path 105 is located in a memory system, the signal may be a control signal that includes commands for the memory device (e.g., write command, read command, refresh command, etc.) and / or an address signal that includes addresses in the memory device for writing or reading data.

[0038] Delay circuit 115 may include series-coupled delay buffers 120-1 to 120-4, wherein the delay of delay circuit 115 is equal to the sum of the individual delays of delay buffers 120-1 to 120-4. In the example shown in FIG1A, each of delay buffers 120-1 to 120-4 is implemented using a corresponding complementary inverter, which includes a corresponding transistor 125-1 to 125-4 (e.g., an n-type field-effect transistor) and a corresponding transistor 130-1 to 130-4 (e.g., a p-type field-effect transistor). However, it will be appreciated that each of delay buffers 120-1 to 120-4 may be implemented using another type of circuit or logic gate.

[0039] When signal path 105 is in active mode, a signal (e.g., data signal, clock signal, etc.) is received at input 108 of signal path 105 and delayed by delay circuit 115. The resulting delayed signal can be output to another circuit (not shown) coupled to output 110 of signal path 105.

[0040] When signal path 105 is in idle mode, input 108 of signal path 105 can be set to (i.e., maintained at) a high or low level during the idle period. For an instance where the active signal is a clock signal, signal path 105 can be in idle mode when the clock signal is strobed. For an instance where the active signal is a data signal, signal path 105 can be in idle mode when there is no data transmission at input 108 of signal path 105.

[0041] Figure 1B illustrates an example where input 108 is at a low level (i.e., logic 0) in idle mode. Figure 1B also illustrates the logic states at the inputs and outputs of each of delay buffers 120-1 to 120-4. In this example, output 110 of signal path 105 is at a low level (i.e., logic 0) in idle mode. In this example, transistors 130-1, 125-2, 130-3, and 125-4 are turned on in idle mode, and transistors 125-1, 130-2, 125-3, and 130-4 are turned off in idle mode. In Figure 1B, transistors 130-1, 125-2, 130-3, and 125-4 are shown in bold when turned on in idle mode. Transistors 130-1, 125-2, 130-3, and 125-4 that are turned on in idle mode are subjected to stress in idle mode, while transistors 125-1, 130-2, 125-3, and 130-4 that are turned off in idle mode are not subjected to stress in idle mode. This leads to asymmetric aging, where transistors 130-1, 125-2, 130-3, and 125-4 that are subjected to stress in idle mode age faster than transistors 125-1, 130-2, 125-3, and 130-4 that are not subjected to stress in idle mode.

[0042] In this example, asymmetric aging shifts the threshold voltages of transistors 130-1, 125-2, 130-3, and 125-4 under stress in idle mode, resulting in an increase in the falling edge delay at output 110 relative to the rising edge delay at output 110. This increase in falling edge delay relative to rising edge delay causes a duty cycle shift in signal path 105. An example of this duty cycle shift is illustrated in the timing diagram shown in Figure 1C. In the example shown in Figure 1C, clock signal 150 is input to input 108 of signal path 105 in active mode. In this example, clock signal 150 at input 108 has a 50% duty cycle. Figure 1C also illustrates clock signal 160 at output 110 of signal path 105 after clock signal 150 has been delayed by delay circuit 115. Delay circuit 115 delays the rising edge of clock signal 160 by Tr and the falling edge of clock signal 160 by Tf at output 110. As shown in Figure 1C, due to asymmetric aging, the delay Tf of the falling edge is longer than the delay Tre of the rising edge. In this example, the longer delay of the falling edge results in an increase in the duty cycle of the clock signal 160 at output 110 (i.e., the duty cycle at output 110 is greater than 50%).

[0043] In the examples shown in Figures 1B and 1C, input 108 of signal path 105 is at a low level in idle mode. Asymmetric aging also occurs when input 108 of signal path 105 is at a high level in idle mode. Figure 1D also illustrates an example where input 108 is at a high level (i.e., logic 1) in idle mode. Figure 1D also illustrates the logic states at the inputs and outputs of each delay buffer 120-1 to 120-4. In this example, output 110 of signal path 105 is at a high level (i.e., logic 1) in idle mode. In this example, transistors 125-1, 130-2, 125-3, and 130-4 are turned on in idle mode, and transistors 130-1, 125-2, 130-3, and 125-4 are turned off in idle mode. In Figure 1D, transistors 125-1, 130-2, 125-3, and 130-4 are shown in bold as transistors conducting in idle mode. Transistors 125-1, 130-2, 125-3, and 130-4 conducting in idle mode are subjected to stress in idle mode, while transistors 130-1, 125-2, 130-3, and 125-4 turning off in idle mode are not subjected to stress. This leads to asymmetric aging, where transistors 125-1, 130-2, 125-3, and 130-4 subjected to stress in idle mode age faster than transistors 130-1, 125-2, 130-3, and 125-4.

[0044] In this example, asymmetric aging shifts the threshold voltages of transistors 125-1, 130-2, 125-3, and 130-4 under stress in idle mode, resulting in an increase in the rise-edge delay at output 110 relative to the fall-edge delay at output 110. This increase in rise-edge delay relative to fall-edge delay causes a duty cycle shift in signal path 105. An example of this duty cycle shift is illustrated in the timing diagram shown in Figure 1E. In the example shown in Figure 1E, clock signal 150 is input to input 108 of signal path 105 in active mode. In this example, clock signal 150 at input 108 has a 50% duty cycle. Figure 1E also illustrates clock signal 180 at output 110 of signal path 105 after clock signal 150 has been delayed by delay circuit 115. Delay circuit 115 delays the rise-edge of clock signal 180 by TR and the fall-edge of clock signal 180 by Tf at output 110. As shown in Figure 1E, due to asymmetric aging, the rising edge delay Tr is longer than the falling edge delay Tf. In this example, the longer rising edge delay results in a reduced duty cycle of the clock signal 180 at output 110 (i.e., the duty cycle at output 110 is less than 50%).

[0045] Therefore, asymmetric aging in idle mode causes a duty cycle shift (i.e., duty cycle degradation) over time. This duty cycle shift increases or decreases the duty cycle, depending on whether the input 108 of signal path 105 is at a low or high level in idle mode. In duty cycle-sensitive systems, this shift can lead to timing problems. An example of such a system is a double data rate (DDR) system, where data is fetched from a data signal on both the rising and falling edges of the clock signal. In this example, the duty cycle shift due to asymmetric aging can lead to timing violations in the system.

[0046] To address this issue, the various states of this invention control aging in idle mode to mitigate duty cycle shift due to aging. In one example, instead of placing the signal path inputs at the same logic value during every idle period, the inputs are alternately placed at low and high levels across multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path and thus mitigate duty cycle shift due to asymmetric aging. In another example, a clock signal (e.g., a slow clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In yet another example, the signal path inputs can be placed at high or low levels based on an aging mode (e.g., a programmable aging mode) during each idle period. In some states, the aging mode can be programmed to compensate for asymmetric aging of the signal path in active mode. In some states, a multiplexer coupled to the signal path inputs is used to control the aging of the signal path in idle mode. In some configurations, latching circuitry (e.g., flip-flops) coupled to the inputs of the signal path is used to control the aging of the signal path in idle mode. In some configurations, the set inputs and / or reset inputs of the latching circuitry can be used to control the logic values ​​at the inputs of the signal path in idle mode. The above-described exemplary features and other exemplary features of this application will be further discussed below.

[0047] As used herein, "latch circuitry" includes one or more circuits configured to latch / store one or more logic values, such as latches, flip-flops, registers, etc.

[0048] Figure 2 illustrates an example of an aging-mitigation system 205 according to certain aspects of the present invention. In this example, system 205 includes a signal path 210, a multiplexer 220, and a controller 230.

[0049] Signal path 210 has input 212 and output 214. Input 212 can be configured to receive a signal in active mode. This signal can be a clock signal, data signal, control signal, address signal, or another type of signal. Signal path 210 may include delay circuitry (e.g., delay circuit 115) for delaying the signal. For example, the delay circuitry can be configured to delay the signal to adjust the timing of the signal relative to another signal, as further discussed below. It will be appreciated that signal path 210 may include alternative delay circuitry or one or more other circuits besides delay circuitry. One or more other circuits may include one or more logic gates, sequential logic circuits, etc. Output 214 of signal path 210 may be coupled to sequential logic circuitry, a driver, a pad, or another circuit, as further discussed below.

[0050] Multiplexer 220 has a first input 222, a second input 224, a selection input 226, and an output 228. Output 228 of multiplexer 220 is coupled to input 212 of signal path 210. Multiplexer 220 is configured to selectively couple either the first input 222 or the second input 224 to output 228 based on a selection signal received at selection input 226. For example, when the selection signal has a first logic value, multiplexer 220 may couple the first input 222 to output 228 (i.e., select the first input 222), and when the selection signal has a second logic value, couple the second input 224 to output 228 (i.e., select the second input 224). The first logic value can be 1, and the second logic value can be 0, and vice versa. In this example, the first input 222 is configured to receive a signal for the activity mode of signal path 210. As discussed above, the signal can be a clock signal, a data signal, a control signal (also known as a command signal), an address signal, or another type of signal. Although a multiplexer 220 with two inputs (i.e., first input 222 and second input 224) is illustrated in Figure 2, it should be understood that the multiplexer 220 may include more than two inputs.

[0051] Controller 230 has input 232, a first output 234, and a second output 236. Input 232 can be configured to receive an indicator signal that indicates to controller 230 whether signal path 210 is in idle or active mode. In this respect, input 232 can be referred to as an indicator input. In one example, the indicator signal may have a first logic value for indicating idle mode and a second logic value for indicating active mode. The first logic value can be 1, and the second logic value can be 0, or vice versa.

[0052] In an example where the signal input to signal path 210 is a clock signal, the clock signal can be strobed in idle mode. In this example, the indicator signal can be generated by a clock strobing circuit (not shown) in control system 205. In this example, the idle indicator signal can indicate an active mode when the clock signal is not strobed, and an idle mode when the clock signal is strobed. In an example where the signal input to signal path 210 is a data signal, signal path 210 can enter idle mode when there is no incoming data transmission to signal path 210. In this example, the indicator signal can be generated by a data transmission circuit (not shown) in control (e.g., management) system 205. In this example, the indicator signal can indicate an active mode when there is an incoming data transmission, and an idle mode when there is no incoming data transmission. For instances where the signal is a control signal (also known as a command signal), signal path 210 can be idle when no incoming command (e.g., a read / write command) is received. In this instance, the indicator signal can indicate an active mode when an incoming command is received, and an idle mode when no incoming command is received.

[0053] The first output 234 of controller 230 is coupled to the second input 224 of multiplexer 220, and the second output 236 of controller 230 is coupled to the selection input 226 of multiplexer 220. Controller 230 is configured to output an aging control signal at the first output 234. As further discussed below, the aging control signal control is a control signal that controls whether input 212 of control signal path 210 is at a high or low level in idle mode. Controller 230 is configured to output a selection signal at the second output 236 to control the input selection of multiplexer 220.

[0054] In active mode (also known as functional mode), controller 230 instructs overlay 220 to use a selection signal to select first input 222 (e.g., setting the selection signal to a first logic value). As a result, multiplexer 220 passes the signal received at first input 222 to input 212 of signal path 210. In one instance, controller 230 may instruct overlay 220 to select first input 22 when the indicator signal indicates active mode. As discussed above, the signal can be a clock signal, a data signal, a control signal, an address signal, or another type of signal. For instances where the signal is a data signal, signal path 210 may be in active mode when signal path 210 is receiving an incoming data transfer. For instances where the signal is a control signal, signal path 210 may be in active mode when signal path 210 is receiving a command (e.g., a read / write command).

[0055] In idle mode, controller 230 instructs overlay 220 to select second input 224 (e.g., to set the selection signal to a second logic value). For example, when controller 230 receives an indicator signal indicating idle mode, controller 230 may instruct overlay 220 to select second input 224. As a result, multiplexer 220 couples the aging control signal output from first output 234 of controller 230 to input 212 of signal path 210. This allows controller 230 to control the aging of signal path 210 in idle mode by controlling the logic value (i.e., state) set at input 212 of signal path 210 using the aging control signal, as further discussed below.

[0056] Figure 3A is a timing diagram illustrating an example of controller 230 using an aging control signal to control aging in an idle mode according to certain states. Figure 3A illustrates the logic value 305 (i.e., the state) at input 212 of signal path 210 within multiple active periods 310-1 to 310-4 and multiple idle periods 320-1 to 320-4. In this example, the signal input to signal path 210 in active mode is a clock signal. However, it will be understood that this signal can be a data signal, a control signal, an address signal, or another type of signal.

[0057] In the example shown in Figure 3A, the controller 230 alternately sets the input 212 of the signal path 210 to a low level and a high level during idle periods 320-1 to 320-4 to balance the aging of devices (e.g., transistors) in the signal path 210. For example, the controller 230 may alternately set the input 212 of the signal path 210 to a low level and a high level during consecutive idle periods by alternately setting the aging control signal to a low level and a high level during consecutive idle periods. The controller 230 can place the input 212 of the signal path 210 at a low level during odd idle periods 320-1 and 320-3, and at a high level during even idle periods 320-2 and 320-4 (as shown in the example in Figure 3A), or place the input 212 of the signal path 210 at a high level during odd idle periods 320-1 and 320-3, and at a low level during even idle periods 320-2 and 320-4. Therefore, the controller 230 can set the aging control signal to a low level during odd idle periods 320-1 and 320-3 and set it to a high level during even idle periods 320-2 and 320-4, or set the aging control signal to a high level during odd idle periods 320-1 and 320-3 and set it to a low level during even idle periods 320-2 and 320-4.

[0058] Assuming that the cumulative duration of odd-numbered idle periods 320-1 and 320-3 is approximately equal to the cumulative duration of even-numbered idle periods 320-2 and 320-4 over multiple idle periods, then the controller 230 will keep the input 212 of the signal path 210 at the low and high levels for approximately equal durations over time in idle mode. This helps to balance the aging of devices (e.g., transistors) in the signal path 210 and thus reduces duty cycle shift in the signal path 210 caused by asymmetric aging.

[0059] Figure 3B is a timing diagram illustrating another example of how controller 230 uses an aging control signal to control aging in idle mode according to certain states. Figure 3B illustrates the logic value 350 (i.e., state) at input 212 of signal path 210 within multiple active periods 360-1 to 360-4 and multiple idle periods 370-1 to 370-4. In this example, the signal input to signal path 210 in active mode is a clock signal. However, it should be understood that this signal can be a data signal or another type of signal.

[0060] In the example shown in Figure 3B, controller 230 inputs a slow clock signal to signal path 210 in idle mode. The slow clock signal can have a much lower frequency compared to the clock signal used in active mode to reduce power consumption in idle mode. For example, the slow clock signal can have a frequency of 19.2 MHz or lower. The slow clock signal can be generated by a slow clock generator (not shown) coupled to controller 230. The slow clock generator can be implemented using a crystal oscillator or another type of clock generator. In this example, controller 230 can input the slow clock signal to signal path 210 by outputting the slow clock signal in idle mode as an aging control signal (i.e., outputting the slow clock signal at the first output 234). In this example, the slow clock signal illustrates the aging of devices (e.g., transistors) in signal path 210 by alternating input 212 of signal path 210 between high and low levels in idle mode.

[0061] In some states, controller 230 can place input 212 of signal path 210 into an idle mode based on an aging mode, which can be programmable. For example, the aging mode can be repeated for every N consecutive idle periods, where N is an integer. For every N consecutive idle periods, the aging mode can indicate multiple (k) idle periods in which input 212 of signal path 210 is at a high level and multiple (i.e., Nk) idle periods in which input 212 of signal path 210 is at a low level. For example, if N equals 8, the aging mode is repeated for every 8 consecutive idle periods. In this state, controller 230 can control aging by setting the aging control signal to a high level for k idle periods in the N consecutive idle periods and setting the aging control signal to a low level for Nk idle periods in the N consecutive idle periods. N can be an integer greater than 1, k can be an integer equal to or greater than 1, and N can be greater than k. In one instance, k and N can be stored as parameters in register 235 of controller 230. In this instance, k and N can be programmed by writing values ​​of k and N into register 235. It will be understood that register 235 can be omitted in some implementations.

[0062] In some configurations, the aging mode is specified by a sequence of N bits. In these configurations, each bit of the sequence corresponds to one of N consecutive idle periods, and each bit indicates whether the input 212 of signal path 210 is at a high or low level during the corresponding idle period of the N consecutive idle periods. For example, a bit value of 1 can indicate that the input 212 of signal path 210 is at a high level during the corresponding idle period, and a bit value of 0 can indicate that the input 212 of signal path 210 is at a low level during the corresponding idle period, and vice versa. For example, the aging mode provided by the bit sequence 11100000 can indicate that the input 212 is at a high level for 3 out of 8 consecutive idle periods and at a low level for 5 out of 8 consecutive idle periods.

[0063] In some configurations, controller 230 can control aging based on an N-bit sequence by setting the logic state (i.e., logic value) of the aging control signal. Each bit in the sequence corresponds to a specific idle period out of N consecutive idle periods. For each of the N idle periods, if the corresponding bit in the sequence has a first logic value, controller 230 can set the aging control signal to a high level; and if the corresponding bit in the sequence has a second logic value, it can set the aging control signal to a low level. The first logic value can be 1, and the second logic value can be 0, or vice versa.

[0064] Controller 230 can store a sequence of N (e.g., 8) bits of a specified aging mode in register 235. In one instance, register 235 may include a circular shift register configured to output one bit of the sequence at a time. In this regard, Figure 4 illustrates an example of a certain type in which register 235 includes a circular shift register 410. In this example, circular shift register 410 includes storage slots 415-1 to 415-N (also referred to as storage space), where each of storage slots 415-1 to 415-N can hold one bit of the N-bit sequence. Circular shift register 410 has an input 412 and an output 414. Input 412 is used to control the shifting of bits in circular shift register 410, as discussed further below. Output 414 is coupled to a first output 234 of controller 230 and is configured to output bits in storage slots 415-N.

[0065] In this example, controller 230 also includes control circuitry 420. Control circuitry 420 has input 422, a first output 424, and a second output 426. Input 422 is coupled to input 232 of controller 230 and configured to receive the indicator signal discussed above. First output 424 is coupled to input 412 of circular shift register 410 and is used by control circuitry 420 to shift bits in circular shift register 410, as further discussed below. Second output 426 is coupled to second output 236 of controller 230 and is used by control circuitry 420 to control the input selection of multiplexer 220.

[0066] In operation, control circuitry 420 is configured to instruct multiplexer 220 to select second input 224 via second output 426 in idle mode (e.g., when an idle signal indicating an idle period is received at input 422). For an example where multiplexer 220 selects second input 224 when a second logic value is input to selection input 226, control circuitry 420 may instruct multiplexer 220 to select second input 224 by outputting the second logic value to selection input 225 via second output 426. Control circuitry 420 may also be configured to instruct multiplexer 220 to select first input 222 via second output 426 in active mode.

[0067] In idle mode, control circuitry 420 can be configured to shift bits in circular shift register 410 by one bit position each time during each idle period via first output 424, such that circular shift register 410 outputs each bit of the N-bit sequence once every N idle periods. For example, whenever an indicator signal indicates idle mode, control circuitry 420 can shift bits in circular shift register 410 by one bit position. For each shift, bits in each storage slot 415-1 to 415-N can be shifted up to the next storage slot 415-1 to 415-N in circular shift register 410. For example, in one shift, bits in storage slot 415-1 can be shifted up to storage slot 415-2, and bits in storage slot 415-N can be shifted back to storage slot 415-1 (as indicated by the arrows circulating back from storage slot 415-N to storage slot 415-1).

[0068] Therefore, in this example, during each idle period, the bits in the circular shift register 410 are shifted by one bit, such that the circular shift register 410 cycles through the N-bit sequence once every N idle periods. In this example, when the circular shift register 410 outputs the first bit value, the input 212 of the signal path 210 can be set to a high level, and when the circular shift register 410 outputs the second bit value, the input 212 of the signal path 210 can be set to a low level. The first bit value can be 1, and the second bit value can be 0, and vice versa.

[0069] Therefore, the aging control of controller 230 can be configured (e.g., programmed), for example, by programming the bits in the N-bit sequence accordingly. In some use cases, signal path 210 may undergo asymmetric aging in active mode. In these use cases, the aging mode can be programmed to compensate for the asymmetric aging of signal path 210 in active mode, and thus mitigate the duty cycle shift caused by the asymmetric aging in active mode. For example, if the input 212 of signal path 210 is at a high level for a longer duration in active mode (compared to a low level in active mode), the aging mode can be programmed such that controller 230 stores the input 212 of signal path 210 at a low level (compared to a high level) for a longer period of idle time to compensate for the asymmetric aging in active mode. Similarly, if the input 212 of signal path 210 is at a low level for a longer duration in active mode (compared to a high level in active mode), the aging mode can be programmed such that the controller 230 stores the input 212 of signal path 210 at a high level (compared to a low level) for a longer period of idle time to compensate for asymmetric aging in active mode. In this example, the duration for which the input 212 of signal path 210 is at a high or low level in active mode can be determined, for example, by performing a simulation of system 205 in active mode. This information can also be obtained by monitoring the logic state at the input 212 of signal path 210 in active mode and determining the duration for which the input 212 of signal path 210 is at a high or low level in active mode based on the monitored logic state. After obtaining this information, the aging mode can be programmed accordingly to compensate for asymmetric aging in active mode.

[0070] Figure 5A illustrates an example of a system 505 including the signal path 210, multiplexer 220, and controller 230 discussed above. System 505 also includes a driver 510 and pads 520. Driver 510 has an input 512 and an output 514. The input 512 of driver 510 is coupled to the output 214 of signal path 210, and the output 514 of driver 510 is coupled to pads 520. In some configurations, signal path 210, multiplexer 220, driver 510, and pads 520 may be integrated on a wafer (i.e., a die), and pads 520 may be coupled to another wafer via metal lines (e.g., formed on a printed circuit board (PCB)).

[0071] Driver 510 can be configured to receive signals from signal path 210 in active mode and drive pad 520 (and thus metal lines) based on the received signals. For example, driver 510 can be configured to drive pad 520 to a high level when the received signal is high and to drive pad 520 to a low level when the received signal is low. Alternatively, driver 510 can be configured to drive pad 520 to a low level when the received signal is high and vice versa. Driver 510 can be implemented using a pull-up transistor for driving pad 520 to a high level and a pull-down transistor for driving pad 520 to a low level.

[0072] In one example, a metal line (not shown) may be coupled between pad 520 and another die (not shown). In this example, driver 510 may be configured to transmit a signal to the other die via the metal line by driving pad 520 (and thus the metal line) based on a signal. In this example, signal path 210 and driver 510 may be located in the transmit path of system 505. As discussed above, the signal may be a data signal, clock signal, control signal, address signal, or another type of signal.

[0073] In the example in Figure 5A, the logic state at output 214 of signal path 210 can switch between high and low levels during multiple idle periods. This is because controller 230 can alternately place input 212 of signal path 210 at high and low levels to balance aging, as discussed above. In some use cases, it is desirable for input 512 of driver 510 and / or pad 520 to be at a low level (i.e., logic 0) in idle mode. For example, a specification might require pad 520 to be at a low level in idle mode, such that the transmission line (not shown) coupled to pad 520 remains at a low level in idle mode. In these cases, clock gating circuit 540 (also referred to as clock gating unit) can be coupled between output 214 of signal path 210 and input 512 of driver 510 to isolate driver 510 and pad 520 from switching between low and high levels at output 214 of signal path 210 in idle mode, an example of which is illustrated in FIG5B.

[0074] In the example shown in Figure 5B, the clock gating circuit 540 has a signal input 542 coupled to an output 214 of signal path 210, an output 546 coupled to an input 512 of driver 510, and a control input 544 coupled to a third output 530 of controller 230. In this example, controller 230 can be configured to selectively gating or degating clock gating circuit 540 via the third output 530. For example, clock gating circuit 540 can be configured to be gated when a first logic value is input to control input 544 and degated when a second logic value is input to control input 544. In this example, controller 230 can gating clock gating circuit 540 via outputting a first logic value to control input 544 and degating clock gating circuit 540 via outputting a second logic value to control input 544. In this example, the first logic value can be 1, and the second logic value can be 0, and vice versa. In this example, the clock strobe circuit 540 can be configured to set the output 546 to a low level when the clock strobe circuit 540 is selected.

[0075] In this example, controller 230 can be configured to deselect clock strobe circuit 540 in active mode and select clock strobe circuit 540 in idle mode (e.g., when controller 230 receives an indicator signal indicating idle mode at input 232). In this example, clock strobe circuit 540 sets output 546 to a low level in idle mode, which isolates driver 510 and pad 520 from the switching between low and high levels at output 214 of signal path 210 in idle mode.

[0076] It will be understood that the scope of this invention is not limited to the example shown in Figure 5B. For example, in another example, clock gating circuit 540 may be coupled between the output 514 of driver 510 and pad 520 to isolate pad 520 from switching in idle mode. In this example, controller 230 may gating clock gating circuit 540 in idle mode and de-gating clock gating circuit 540 in active mode, as discussed above.

[0077] The clock gating circuit 540 can be implemented using one or more logic gates. For example, Figure 5C illustrates an example where the clock gating circuit 540 includes an AND gate 570. In this example, the first input of the AND gate 570 is coupled to a signal input 542, the second input of the AND gate 570 is coupled to a control input 544, and the output of the AND gate 570 is coupled to an output 546. In this example, when the logic value at the control input 544 is 1, the AND gate 570 de-gating the clock gating circuit 540. When the logic value at the control input 544 is 0, the AND gate 570 gating the clock gating circuit 540 and setting the output 546 to a low level. In one example, the AND gate 570 can be implemented using a NAND gate and an inverter. It will be understood that the clock gating circuit 540 is not limited to the example shown in Figure 5C, and the clock gating circuit 540 can be implemented using another type of logic gate and / or a combination of logic gates. It will also be understood that the clock gating circuit 540 may include additional components not shown in Figure 5C (e.g., latching circuitry or synchronizer to prevent tethering).

[0078] In the above example, clock gating circuit 540 is configured to set output 546 to a low level when clock gating circuit 540 is selected. However, it will be understood that the scope of this application is not limited to this example. For instance, in some use cases, it may be desirable for input 512 and / or pad 520 of driver 510 to be at a high level (i.e., logic 1) in idle mode. In these cases, clock gating circuit 540 is configured to set output 546 to a high level when clock gating circuit 540 is selected. In these cases, clock gating circuit 540 can be implemented using combinations of logic gates or OR gates.

[0079] Figure 6 illustrates an example of a system 605 including the signal path 210, multiplexer 220, and controller 230 discussed above. System 605 also includes a latch circuit 610 (e.g., a flip-flop) having a signal input 612, a clock input 614, and an output 616. The signal input 612 is coupled to the output 214 of the signal path 210. In this example, the signal in active mode can be a data signal, a control signal, or an address signal.

[0080] In active mode, latch circuit 610 is configured to receive a signal from signal path 210 at signal input 612 and a clock signal (labeled "Clk") at clock input 614. Latch circuit 610 is configured to latch (i.e., capture) the logic value of the clock signal on the edge of the clock signal and output the latched logic value at output 616. Output 616 can be coupled to circuitry configured to receive the latched logic value. This circuitry may include another latch circuitry, a processor, a data buffer, etc. The edge of the clock signal used to latch the logic value can be a rising edge or a falling edge.

[0081] Figure 7 illustrates an example of a system 705 including the signal path 210, multiplexer 220, controller 230, and latch circuit 610 discussed above. System 705 also includes pads 720 and a receiver 710. Receiver 710 has an input 712 and an output 714. The input 712 of receiver 710 is coupled to pad 720, and the output 714 of receiver 710 is coupled to a first input 222 of multiplexer 220. In some embodiments, pads 720, receiver 710, multiplexer 220, signal path 210, and latch circuit 610 may be integrated on a wafer (i.e., a die), and pads 720 may be coupled to another wafer via metal lines (e.g., formed on a printed circuit board (PCB)).

[0082] Receiver 710 can be configured to receive signals from another chip (not shown) via pad 720. Receiver 710 can amplify the received signal and / or perform equalization on the received signal (e.g., compensating for signal attenuation in metal lines). Receiver 710 outputs the received signal to the first input 222 of multiplexer 220. In this example, receiver 710 and signal path 210 can be located in the receive path of system 705. In this example, the signal can be a data signal (e.g., sent from another chip to pad 720 via metal lines).

[0083] Figure 8 illustrates an example of a system 805 including the signal path 210, multiplexer 220, and controller 230 discussed above. System 805 also includes a latch circuit 810 (e.g., a flip-flop) having a signal input 812, a clock input 814, and an output 816. The clock input 814 is coupled to the output 214 of signal path 210. In this example, the signal in active mode is a clock signal.

[0084] In active mode, latch circuit 810 is configured to receive a data signal at signal input 812 and a clock signal from signal path 210 at clock input 814. Latch circuit 810 is configured to latch (i.e., capture) the logic value of the data signal on the edge of the clock signal and output the latched logic value at output 816. Output 816 may be coupled to circuitry configured to receive the latched logic value. This circuitry may include another latch circuitry, a processor, a data buffer, etc. The edge of the clock signal used to latch the logic value may be a rising edge or a falling edge. In this example, signal path 210 may be configured to delay the clock signal to adjust the timing of the clock signal (e.g., to center the edge of the clock signal between transitions in the data signal).

[0085] In the example shown in Figure 8, system 805 also includes a clock source 820 configured to output a clock signal at output 822, which is coupled to a first input 222 of multiplexer 220. Clock source 820 may include a phase-locked loop (PLL) or another type of clock generator. Clock source 820 may be integrated on the same chip as multiplexer 220 or may be located on a separate chip.

[0086] Although the signal input 812 to the latch circuit 810 in the example discussed above is a data signal, it will be understood that the signal can also be a control signal or an address signal. For example, the latch circuit 810 can be used to latch command bits or address bits.

[0087] Figure 9A illustrates an example of a system 905 including the signal path 210, multiplexer 220, controller 230, and latch circuit 810 discussed above. System 905 also includes a second multiplexer 920, a second signal path 910, pads 940, and receiver 930. In the following discussion of Figure 9A, signal path 210 is referred to as the first signal path, and multiplexer 220 is referred to as the first multiplexer.

[0088] The second signal path 910 has an input 912 and an output 914, wherein the output 914 is coupled to the signal input 812 of the latch circuit 810. The second signal path 910 can be configured to delay the data signal, control signal, or address signal discussed above with reference to Figure 8.

[0089] The second multiplexer 920 has a first input 922, a second input 924, a selection input 926, and an output 928. The output 928 of the second multiplexer 920 is coupled to input 912 of the second signal path 910. The second multiplexer 920 is configured to selectively couple either the first input 922 or the second input 924 to the output 928 based on a selection signal received at the selection input 926. For example, when the selection signal has a first logic value, the second multiplexer 920 may couple the first input 922 to the output 928 (i.e., select the first input 922), and when the selection signal has a second logic value, couple the second input 924 to the output 928 (i.e., select the second input 924). In the example shown in FIG. 9A, the second input 924 is coupled to the first output 234 of the controller 230 and thus receives the aging control signal output from the controller 230. The selection input 926 is coupled to the second output 236 of the controller 230, and thus receives the selection signal output from the controller 230. Therefore, in this example, the controller 230 controls the aging of the first signal path 210 and the second signal path 910. In this example, the idle periods of the first signal path 210 and the second signal path 910 can be the same. However, it will be understood that, as further discussed below with reference to FIG. 9B, this is not necessary.

[0090] Receiver 930 has input 932 and output 934. Input 932 of receiver 930 is coupled to pad 940, and output 934 of receiver 930 is coupled to first input 922 of second multiplexer 920. In some embodiments, pad 940, receiver 930, first multiplexer 220, second multiplexer 920, first signal path 210, second signal path 910, and latch circuit 810 may be integrated on a chip (i.e., die), and pad 940 may be coupled to another chip via metal lines (e.g., formed on a printed circuit board (PCB)).

[0091] Receiver 930 is configured to receive signals (e.g., data signals, control signals, or address signals) from another chip (not shown) via pad 940. Receiver 930 may amplify the received signal and / or perform equalization on the received signal (e.g., compensating for signal attenuation in metal lines). Receiver 930 outputs the received signal to the first input 922 of the second multiplexer 920. In this example, receiver 930 and signal path 910 may be located in the receive path of system 905.

[0092] As discussed above, in this example, controller 230 controls the aging of the first signal path 210 and the second signal path 910. In active mode, controller 230 instructs first multiplexer 220 to select the corresponding first input 222 and instructs second multiplexer 920 to select the corresponding first input 922. In idle mode, controller 230 instructs first multiplexer 220 to select the corresponding second input 224 and instructs second multiplexer 920 to select the corresponding second input 924. Subsequently, controller 230 uses an aging control signal (e.g., using any of the techniques discussed above with reference to FIG. 2) to control the aging of the first signal path 210 and the second signal path 910. For example, controller 230 may alternately place input 212 of the first signal path 210 at a low level and high level during multiple idle periods, and alternately place input 912 of the second signal path 910 at a low level and high level during multiple idle periods. In another instance, controller 230 may control the aging of the first signal path 210 and the second signal path 910 based on an aging mode (e.g., a sequence of N bits), as discussed above.

[0093] Figure 9B illustrates an example in which controller 230 can independently control the aging of the first signal path 210 and the second signal path 910, depending on certain conditions. In this example, controller 230 has a second input 952, a third output 944, and a fourth output 946 for controlling the aging of the second signal path 910. In the following discussion of Figure 9B, input 232 is referred to as the first input.

[0094] In this example, the third output 944 is coupled to the second input 924 of the second multiplexer 920, and the fourth output 946 is coupled to the selection input 926 of the second multiplexer 920. The first input 232 is configured to receive a first indicator signal indicating an idle period for the first signal path 210, and the second input 942 is configured to receive a second indicator signal indicating an idle period for the second signal path 910. The idle periods of the first signal path 210 and the second signal path 910 may overlap in time. In this example, the controller 230 is configured to output a first aging control signal at the first output 234 to control the aging of the first signal path 210, and to output a second aging control signal at the third output 944 to control the aging of the second signal path 910.

[0095] Exemplary operation of controller 230 will now be discussed according to certain modes. In the active mode of first signal path 210, controller 230 instructs first multiplexer 220 to select first input 222 via second output 236. As a result, first multiplexer 220 will pass the clock signal received at first input 222 to first signal path 210.

[0096] In the idle mode of the first signal path 210, the controller 230 instructs the first multiplexer 220 to select the second input 224. As a result, the multiplexer 220 couples the first aging control signal output from the first output 234 of the controller 230 to the second input 224 of the multiplexer 220. This allows the controller 230 to use the first aging control signal to control the aging of the first signal path 210 in the idle mode, as discussed above with reference to FIG2. In this example, when a first indicator signal indicating that the first signal path 210 is in an idle mode is received at the first input 232, the controller 230 determines that the first signal path 210 is idle.

[0097] In the active mode of the second signal path 910, the controller 230 instructs the second multiplexer 920 to select the first input 922 via the fourth output 946. As a result, the second multiplexer 920 will pass the signal received at the first input 922 (e.g., a data signal, a control signal, or an address signal) to the second signal path 910.

[0098] In the idle mode of the second signal path 910, controller 230 instructs second multiplexer 920 to select second input 924. As a result, second multiplexer 920 couples a second aging control signal output from third output 944 of controller 230 to second input 924 of second signal path 910. This allows controller 230 to control the aging of second signal path 910 in the idle mode of the second signal path using the second aging control signal (e.g., using any of the techniques discussed above with reference to FIG. 2). For example, controller 230 may alternately place input 912 of second signal path 910 at low and high levels during multiple idle periods of second signal path 910. In another instance, controller 230 may control the aging of second signal path 910 based on an aging pattern (e.g., a sequence of N bits), as discussed above. In this example, when a second indicator signal indicating that the second signal path 910 is in an idle mode is received at the second input 942, the controller 230 determines that the second signal path 910 is idle. For example, in the case of a data signal, the second signal path 910 can be in an idle mode when the receiver 930 is not receiving incoming data transmissions.

[0099] Figure 10 illustrates a certain form of aging-mitigation system 1005 according to the present invention. In this example, the system includes a signal path 1040, a latching circuit 1010 (e.g., a trigger), and a controller 1030.

[0100] Signal path 1040 has input 1042 and output 1044. Input 1042 can be configured to receive a signal in active mode. This signal can be a data signal, a control signal, an address signal, or another type of signal. Signal path 1040 may include delay circuitry (e.g., delay circuitry 115) for delaying the signal. For example, the delay circuitry can be configured to delay the signal to adjust its timing relative to another signal, as further discussed below. It will be appreciated that signal path 1040 may include alternative delay circuitry or one or more other circuits besides delay circuitry. The one or more other circuits may include one or more logic gates, sequential logic circuits, etc. As further discussed below, output 1044 of signal path 1040 may be coupled to sequential logic circuitry, a driver, a pad, or another circuit.

[0101] The latch circuit 1010 has a signal input 1012, a clock input 1014, a set input 1016, a reset input 1018, and an output 1020. The output 1020 of the latch circuit 1010 is coupled to input 1042 of signal path 1040. The signal input 1012 is configured to receive a signal (e.g., a data signal, control signal, or address signal), and the clock input 1014 is configured to receive a clock signal (labeled "Clk"). The latch circuit 1010 is configured to latch (i.e., capture) the logic value of the signal on the edge of the clock signal and output the latched logic value at output 1020. For instances where the signal in active mode is a data signal, the signal input 1012 may be referred to as a data log.

[0102] Latch circuit 1010 is configured to set when set input 1016 is asserted (e.g., logic 1 is input to set input 1016). When set input 1016 is asserted, output 1020 of latch circuit 1010 is at a high level (i.e., logic 1). Latch circuit 1010 is configured to reset when reset input 1018 is asserted (e.g., logic 1 is input to reset input 1018). When reset input 1018 is asserted, output 1020 of latch circuit 1010 is at a low level (i.e., logic 0).

[0103] Controller 1030 has input 1032, a first output 1034, and a second output 1036. Input 1032 can be configured to receive an indicator signal that indicates to controller 1030 when signal path 1040 is in an idle mode. For an instance where the signal input to signal path 1040 is a data signal, signal path 1040 can enter an idle mode when there is no incoming data transfer to signal path 1040. In this instance, the indicator signal can be generated by circuitry (not shown) of data transfers in control (e.g., management) system 1005. First output 1034 of controller 1030 is coupled to set input 1016 of latch circuit 1010, and second output 1036 of controller 1030 is coupled to reset input 1018 of latch circuit 1010. As further discussed below, the controller 1030 uses the set input 1016 and reset input 1018 of the latch circuit 1010 to control whether the input 1042 of the signal path 1040 (which is coupled to the output 1020 of the latch circuit 1010) is set to a high level or a low level in idle mode.

[0104] In active mode (also known as functional mode), controller 1030 deasserts the set input 1016 and reset input 1018 of latch circuit 1010 (e.g., inputting logic 0 to both set input 1016 and reset input 1018). In this case, latch circuit 1010 latches the logic value of a signal (e.g., a data signal, control signal, or address signal) on the edge of a clock signal and outputs the latched logic value to signal path 1040.

[0105] In idle mode, controller 1030 uses the set input 1016 and reset input 1018 of latch circuit 1010 to control the aging of signal path 1040. When controller 1030 receives an indicator signal indicating idle mode at input 1032, controller 1030 can determine that signal path 1040 is in idle mode. In this example, controller 1030 can set input 1042 of signal path 1040 to a high level via asserting set input 1016 (e.g., inputting logic 1 to set input 1016). Controller 1030 can set input 1042 of signal path 1040 to a low level via asserting reset input 1018 (e.g., inputting logic 1 to reset input 1018). Note that in this example, one of the set input 1016 and reset input 1018 is asserted each time.

[0106] In idle mode, controller 1030 can use any of the techniques discussed above with reference to FIG2 to control the aging of signal path 1040. For example, controller 1030 can alternately set input 1042 of signal path 1040 to low and high levels during multiple idle periods by alternately asserting the set input 1016 and reset input 1018 of latch circuit 1010 during multiple idle periods. For example, controller 1030 can set input 1042 to low level during odd idle periods and high level during even idle periods, and vice versa. In this example, controller 1030 can assert reset input 1018 during odd idle periods and set input 1016 during even idle periods, or assert set input 1016 during odd idle periods and reset input 1018 during even idle periods.

[0107] In another example, controller 1030 can control the aging of signal path 1040 based on an aging mode, as discussed above. For example, the aging mode can be repeated for every N consecutive idle periods, where N is an integer. For every N consecutive idle periods, the aging mode can indicate multiple (k) idle periods in which input 1042 of signal path 1040 is at a high level, and multiple (i.e., Nk) idle periods in which input 1042 of signal path 1040 is at a low level. For example, if N equals 8, the aging mode is repeated for every 8 consecutive idle periods. In this case, controller 1030 can control aging based on the aging mode by asserting set input 1016 in k idle periods out of N consecutive idle periods and resetting input 1018 in Nk idle periods out of N consecutive idle periods. N can be an integer greater than 1, k can be an integer equal to or greater than 1, and N can be greater than k. In one instance, k and N can be stored as parameters in register 1035 of controller 1030. In this instance, k and N can be programmed by writing values ​​of k and N into register 1035. It will be understood that register 1035 can be omitted in some implementations.

[0108] In some configurations, the aging mode is specified by a sequence of N bits. In these configurations, each bit of the sequence corresponds to one of N consecutive idle periods, and each bit indicates whether the input 1042 of signal path 1040 is at a high or low level during the corresponding idle period of the N consecutive idle periods. For example, a bit value of 1 can indicate that the input 1042 of signal path 1040 is at a high level during the corresponding idle period, and a bit value of 0 can indicate that the input 1042 of signal path 1040 is at a low level during the corresponding idle period, and vice versa. For example, the aging mode provided by the bit sequence 11100000 can indicate that the input 1042 is at a high level for 3 out of 8 consecutive idle periods and at a low level for 5 out of 8 consecutive idle periods.

[0109] In some configurations, controller 1030 can control aging based on a sequence of N bits, namely, a set input 1016 and a reset input 1018, where each bit in the sequence corresponds to a specific idle period in a sequence of N consecutive idle periods. For each of the N idle periods, if the corresponding bit in the sequence has a first logic value, controller 230 can assert that set input 1016 sets input 1042 to a high level, and if the corresponding bit in the sequence has a second logic value, controller 230 can assert that reset input 1018 sets input 1042 to a low level. The first logic value can be 1, and the second logic value can be 0, or vice versa.

[0110] Figure 11A illustrates an example of a system 1105 including the signal path 1040, latch circuit 1010, and controller 1030 discussed above. System 1105 also includes a driver 1110 and a pad 1120. Driver 1110 has an input 1112 and an output 1114. Input 1112 of driver 1110 is coupled to output 1044 of signal path 1040, and output 1114 of driver 1110 is coupled to pad 1120. In some embodiments, signal path 1040, latch circuit 1010, driver 1110, and pad 1120 may be integrated on a chip (i.e., die), and pad 1120 may be coupled to another chip via metal lines (e.g., formed on a printed circuit board (PCB)).

[0111] Driver 1110 can be configured to receive signals from signal path 1040 in active mode and drive pad 1120 (and therefore metalline) based on the received signals. For example, driver 1110 can be configured to drive pad 1120 to a high level when the received signal is high, and to drive pad 1120 to a low level when the received signal is low. Alternatively, driver 1110 can be configured to drive pad 1120 to a low level when the received signal is high, and to drive pad 1120 to a high level when the received signal is low. Driver 1110 can be implemented using a pull-up transistor for driving pad 1120 to a high level and a pull-down transistor for driving pad 1120 to a low level.

[0112] In the example in Figure 11A, the logic state at output 1044 of signal path 1040 can switch between high and low levels during multiple idle periods. This is because controller 1030 can alternately place input 1042 of signal path 1040 at high and low levels to balance aging, as discussed above. In some use cases, it is desirable for input 1112 of driver 1110 and / or pad 1120 to be at a low level (i.e., logic 0) in idle mode. For example, a specification might require pad 1120 to be at a low level in idle mode, such that the transmission line (not shown) coupled to pad 1120 remains at a low level in idle mode. In these cases, clock gating circuit 1140 (also referred to as clock gating unit) can be coupled between output 1044 of signal path 1040 and input 1112 of driver 1110 to isolate driver 1110 and pad 1120 from switching between low and high levels at output 1044 of signal path 1040 in idle mode, an example of which is illustrated in FIG11B.

[0113] In the example shown in Figure 11B, the clock gating circuit 1140 has a signal input 1142 coupled to an output 1044 of signal path 1040, an output 1146 coupled to an input 1112 of driver 1110, and a control input 1144 coupled to a third output 1130 of controller 1030. In this example, controller 1030 can be configured to selectively gating or degating clock gating circuit 1140 via third output 1130. For example, clock gating circuit 1140 can be configured to be gated when a first logic value is input to control input 1144 and degated when a second logic value is input to control input 1144. In this example, controller 1030 can select clock gating circuit 1140 by outputting a first logic value to control input 1144, and deselect clock gating circuit 1140 by outputting a second logic value to control input 1144. In this example, the first logic value can be 1, and the second logic value can be 0, or vice versa. In this example, clock gating circuit 1140 can be configured to set output 1146 to a low level when clock gating circuit 1140 is selected.

[0114] In this example, controller 1030 can be configured to deselect clock strobe circuit 1140 in active mode and select clock strobe circuit 1140 in idle mode (e.g., when controller 1030 receives an indicator signal indicating idle mode at input 1032). In this example, clock strobe circuit 1140 sets output 1146 to a low level in idle mode, which isolates driver 1110 and pad 1120 from the switching between low and high levels at output 1044 of signal path 1040 in idle mode.

[0115] It will be understood that the scope of this invention is not limited to the example shown in Figure 11B. For example, in another example, clock gating circuit 1140 may be coupled between the output 1114 of driver 1110 and pad 1120 to isolate pad 1120 from switching in idle mode. In this example, controller 1030 may gating clock gating circuit 1140 in idle mode and de-gating clock gating circuit 1140 in active mode, as discussed above.

[0116] In the above example, clock strobe circuit 1140 is configured to set output 1146 to a low level when clock strobe circuit 1140 is selected. However, it will be understood that the scope of this invention is not limited to this example. For instance, in some use cases, it may be desirable for input 1112 of driver 1110 and / or pad 1120 to be at a high level (i.e., logic 1) in idle mode. In these cases, clock strobe circuit 1140 is configured to set output 1146 to a high level when clock strobe circuit 1140 is selected.

[0117] Figure 12 illustrates an example of a system 1205 according to certain configurations, wherein the exemplary system 205 shown in Figure 2 is combined with the exemplary system 1005 shown in Figure 10. In the following discussion of Figure 12, signal path 210 is referred to as the first signal path, signal path 1040 is referred to as the second signal path, controller 230 is referred to as the first controller, and controller 1030 is referred to as the second controller.

[0118] In this example, the output 214 of the first signal path 210 is coupled to the clock input 1014 of the latch circuit 1010. Therefore, in this example, the clock signal used to time the latch circuit 1010 propagates via the first signal path 210. As discussed above with reference to FIG2, the first controller 230 controls the aging of the first signal path 210 in its idle mode. As discussed above with reference to FIG10, the second controller 1030 controls the aging of the second signal path 1040 in its idle mode. The output 1044 of the second signal path 1040 may be coupled to a driver (e.g., driver 1110), sequential logic circuitry (e.g., flip-flops), a processor, or another type of circuitry.

[0119] Figure 13 illustrates an example of a system 1305 including the signal path 1040 and controller 1030 discussed above. According to various embodiments of the present invention, system 1305 also includes a single data rate (SDR) to double data rate (DDR) converter 1310. The SDR to DDR converter 1310 includes a first latch circuit 1320, a second latch circuit 1340, and a multiplexer 1360. The SDR to DDR converter 1310 has a first input 1312, a second input 1314, and an output 1316. The first input 1312 is configured to receive a first data signal, and the second input 1314 is configured to receive a second data signal. The first data signal may include an odd number of data bits, and the second data signal may include an even number of data bits, and vice versa. The first data signal and the second data signal may each include one data bit (labeled "Clk") for each period of a clock signal. Therefore, in this example, each of the first and second data signals transmits data at a single data rate (i.e., one bit per period of the clock signal). The output 1316 of the SDR to DDR converter 1310 is coupled to the input 1042 of the signal path 1040.

[0120] The first latch circuit 1320 has a signal input 1322, a clock input 1324, a set input 1326, a reset input 1328, and an output 1330. The signal input 1322 is coupled to a first input 1312 of the SDR-to-DDR converter 1310, and the clock input 1324 is configured to receive a clock signal. The first latch circuit 1320 is configured to latch (i.e., capture) the logic value of a first data signal on the rising edge of the clock signal and output the latched logic value at the output 1330. Therefore, in this example, the first latch circuit 1320 is a rising edge triggered latch circuit (also referred to as a positive edge triggered latch circuit).

[0121] The first latch circuit 1320 is configured to set when the set input 1326 is asserted (e.g., logic 1 is input to the set input 1326). When the set input 1326 is asserted, the output 1330 is at a high level (i.e., logic 1). The first latch circuit 1320 is also configured to reset when the reset input 1328 is asserted (e.g., logic 1 is input to the reset input 1328). When the reset input 1328 is asserted, the output 1330 is at a low level (i.e., logic 0).

[0122] The second latch circuit 1340 has a signal input 1342, a clock input 1344, a set input 1346, a reset input 1348, and an output 1350. The signal input 1342 is coupled to a second input 1314 of the SDR-to-DDR converter 1310, and the clock input 1344 is configured to receive a clock signal. The second latch circuit 1340 is configured to latch (i.e., capture) the logic value of the second data signal on the falling edge of the clock signal and output the latched logic value at output 1350. Therefore, in this example, the second latch circuit 1340 is a falling-edge triggered latch circuit (also referred to as a negative-edge triggered latch circuit).

[0123] The second latch circuit 1340 is configured to set when the set input 1346 is asserted (e.g., logic 1 is input to the set input 1346). When the set input 1346 is asserted, the output 1350 is at a high level (i.e., logic 1). The second latch circuit 1340 is also configured to reset when the reset input 1348 is asserted (e.g., logic 1 is input to the reset input 1348). When the reset input 1348 is asserted, the output 1350 is at a low level (i.e., logic 0).

[0124] The multiplexer 1360 has a first input 1362, a second input 1364, a select input 1366, and an output 1368. The first input 1362 is coupled to the output 1330 of the first latch circuit 1320, the second input 1364 is coupled to the output 1350 of the second latch circuit 1340, the select input 1366 is configured to receive a clock signal, and the output 1368 is coupled to the output 1316 of the SDR to DDR converter 1310.

[0125] Multiplexer 1360 is configured to couple the output 1330 of the first latch circuit 1320 to output 1368 when the clock signal is high-level, and to couple the output 1350 of the second latch circuit 1340 to output 1368 when the clock signal is low-level. Therefore, for each period of the clock signal, multiplexer 1360 outputs latched data bits (e.g., odd-numbered data bits) from output 1330 of the first latch circuit 1320 during a portion of the high-level period and outputs latched data bits (e.g., even-numbered data bits) from output 1350 of the second latch circuit 1340 during a portion of the low-level period. Thus, multiplexer 1360 outputs two data bits of each period of the clock signal at output 1316, and therefore outputs data bits at output 1316 at double the data rate.

[0126] Because the output 1316 of the SDR-to-DDR converter 1310 is coupled to the input 1042 of the signal path 1040, the SDR-to-DDR converter 1310 outputs data bits to the signal path 1040 at double the data rate. The output 1044 of the signal path 1040 can be coupled to a driver (e.g., driver 1110), sequential logic circuitry (e.g., flip-flops), a processor, or another type of circuitry.

[0127] In this example, the first output 1034 of the controller 1030 is coupled to the setting input 1326 of the first latch circuit 1320 and the setting input 1346 of the second latch circuit 1340. The second output 1036 of the controller 1030 is coupled to the reset input 1328 of the first latch circuit 1320 and the reset input 1348 of the second latch circuit 1340.

[0128] In active mode (also known as functional mode), controller 1030 deasserts the set input 1326 and reset input 1328 of the first latch circuit 1320 (e.g., inputting logic 0 to both set input 1326 and reset input 1328), and deasserts the set input 1346 and reset input 1348 of the second latch circuit 1340 (e.g., inputting logic 0 to both set input 1346 and reset input 1348). In this case, the first latch circuit 1320 latches the logic value (i.e., data bits) of the first data signal on the rising edge of the clock signal and outputs the latched logic value to the first input 1362 of the multiplexer 1360, and the second latch circuit 1340 latches the logic value (i.e., data bits) of the second data signal on the falling edge of the clock signal and outputs the latched logic value to the second input 1364 of the multiplexer 1360.

[0129] In idle mode, controller 1030 controls the aging of signal path 1040. When controller 1030 receives an indicator signal indicating idle mode at input 1032, controller 1030 can determine that signal path 1040 is in idle mode. In this example, controller 1030 can set input 1042 of signal path 1040 to a high level by asserting the set input 1326 of the first latch circuit 1320 and the set input 1346 of the second latch circuit 1340 (e.g., by outputting logic 1 at the first output 1034). Controller 1030 can set input 1042 of signal path 1040 to a low level by asserting the reset input 1328 of the first latch circuit 1320 and the reset input 1348 of the second latch circuit 1340 (e.g., by outputting logic 1 at the second output 1036).

[0130] In idle mode, controller 1030 can use any of the techniques discussed above with reference to FIG. 2 to control the aging of signal path 1040. For example, controller 1030 can alternately place input 1042 of signal path 1040 at low and high levels during multiple idle periods. In this example, controller 1030 can place input 1042 at a low level during odd idle periods and at a high level during even idle periods, and vice versa. In another example, controller 1030 can control the aging of signal path 1040 based on an aging mode, as discussed above with reference to FIG. 10.

[0131] Although the SDR to DDR converter 1310 has been discussed above using examples of data signals, it will be understood that the SDR to DDR converter 1310 can also be used for control signals and address signals.

[0132] As discussed above, controller 1030 can control aging based on a sequence of N bits stored in register 1035. In one example, register 1035 may include a circular shift register configured to output one bit of the sequence at a time. In this regard, Figure 14 illustrates an example of a certain type in which register 1035 includes a circular shift register 1410. In this example, circular shift register 1410 includes storage slots 1415-1 to 1415-N, each of which can hold one bit of the sequence of N bits. Circular shift register 1410 has input 1412 and output 1414. Input 1412 is used to control the shifting of bits in circular shift register 1410, as discussed further below. Output 1414 is configured to output bits in storage slots 415-N.

[0133] In this example, controller 1030 also includes a first multiplexer 1450, a second multiplexer 1460, and an inverter 1470. The first multiplexer 1450 has a first input 1452 coupled to the output 1414 of the circular shift register 1410, a second input 1454 configured to receive logic 0, an output 1458 coupled to the first output 1034 of controller 1030, and a selection input 1456. The second multiplexer 1460 has a first input 1462 coupled to the output 1414 of the circular shift register 1410 via inverter 1470, a second input 1464 configured to receive logic 0, an output 1468 coupled to the second output 1036 of controller 1030, and a selection input 1466.

[0134] The controller 1030 also includes control circuitry 1420. Control circuitry 1420 has an input 1422, a first output 1424, and a second output 1426. Input 1422 is coupled to input 1032 of the controller 1030 and is configured to receive the indicator signal discussed above. The first output 1424 is coupled to input 1412 of the circular shift register 1410 and is used by the control circuitry 1420 to shift bits in the circular shift register 1410, as further discussed below. The second output 146 is coupled to selection input 1456 of the first multiplexer 1450 and selection input 1466 of the second multiplexer 1460.

[0135] In operation, control circuit 1420 is configured to instruct each of the first multiplexer 1450 and the second multiplexer 1460 to select the corresponding second inputs 1454 and 1464 via the second output 1426 in active mode. This causes the first multiplexer 1450 and the second multiplexer 1460 to output 0 to the set input 1016 and the reset input 1018 of latch circuit 1010, which will de-assert both the set input 1016 and the reset input 1018.

[0136] In operation, control circuitry 1420 is configured to instruct each of the first multiplexer 1450 and the second multiplexer 1460 to select the corresponding first inputs 1452 and 1462 via the second output 1426 in idle mode. This couples setup input 1016 to output 1414 of circular shift register 1410 and reset input 1018 to output 1414 of circular shift register 1410 via inverter 1470. Thus, in this example, reset input 1018 receives the inverted bit of the bit output by circular shift register 1410.

[0137] In idle mode, control circuit 1420 can be configured to shift bits in circular shift register 410 by one bit position during each idle period via first output 1424, such that circular shift register 410 outputs each bit of an N-bit sequence once every N idle periods. For example, whenever an indicator signal indicates idle mode, control circuit 1420 can shift bits in circular shift register 1410 by one bit position. For each shift, bits in each storage slot 1415-1 to 1415-N can be shifted up to the next storage slot 1415-1 to 1415-N in circular shift register 1410. For example, in a single shift, a bit in storage slot 1415-1 can be shifted up to storage slot 1415-2, and a bit in storage slot 415-N can be shifted back to storage slot 1415-1 (as indicated by the arrows circulating from storage slot 1415-N back to storage slot 1415-1).

[0138] Therefore, in this example, the bits in the circular shift register 1410 are shifted by one bit position during each idle period, such that the circular shift register 1410 cycles through the N-bit sequence once every N idle periods. In this example, when the circular shift register 1410 outputs 1, the output 1020 of the latch circuit 1010 can be set to a high level. This is because the first multiplexer 1450 outputs 1 to the set input 1016 of the latch circuit 1010, which asserts the set input 1016, and the second multiplexer outputs 0 (i.e., the opposite of 1) to the reset input 1018 of the latch circuit 1010, which deasserts the reset input 1018. Furthermore, in this example, when the circular shift register 1410 outputs 0, the output 1020 of the latch circuit 1010 can be set to a low level. This is because the first multiplexer 1450 outputs 0 to the setting input 1016 of the latch circuit 1010, which de-asserts the setting input 1016 of the latch circuit 1010, and the second multiplexer outputs 1 (i.e., the opposite of 0) to the reset input 1018 of the latch circuit 1010, which asserts the reset input 1018.

[0139] In the example shown in Figure 14, inverter 1470 is coupled between the output 1414 of circular shift register 1410 and the first input 1462 of second multiplexer 1460. However, it will be understood that the scope of this invention is not limited to this example. In other implementations, inverter 1470 may be coupled between the output 1414 of circular shift register 1410 and the first input 1452 of first multiplexer 1450. In this example, when circular shift register 1410 outputs 1, output 1020 of latch circuit 1010 may be set to a low level, and when circular shift register 1410 outputs 0, output 1020 of latch circuit 1010 may be set to a high level.

[0140] Figure 15 illustrates another example of an aging-mitigation system 1505 according to certain aspects of the present invention. In this example, system 1505 includes the signal path 210, multiplexer 220, and controller 230 discussed above. System 1505 also includes a second multiplexer 1520. In the following discussion of Figure 15, multiplexer 220 is referred to as first multiplexer 220.

[0141] The second multiplexer 1520 has a first input 1522, a second input 1524, a selection input 1526, and an output 1528. The output 1528 of the second multiplexer 1520 is coupled to the second input 224 of the first multiplexer 220, and the selection input 1526 of the second multiplexer 1520 is coupled to the first output 234 of the controller 230. The first input 1522 of the second multiplexer 1520 is configured to receive logic 0, and the second input 1524 of the second multiplexer 1520 is configured to receive logic 1. For example, the first input 1522 can receive logic 0 by grounding the first input 1522, and the second input 1524 can receive logic 1 by coupling the second input 1524 to a power supply rail.

[0142] In idle mode, the second multiplexer 1520 is configured to receive an aging control signal. As discussed above, in some states, the aging control signal can alternate between 1 (i.e., high level) and 0 (i.e., low level) during multiple idle periods, or switch between 1 (i.e., high level) and 0 (i.e., low level) based on the aging mode. Subsequently, the second multiplexer 1520 can select logic 0 at the first input 1522 or logic 1 at the second input 1524 based on the logic state of the aging control signal, and output the selected one of logic 0 and logic 1 at the output 1528. For example, when the aging control signal is 0, the second multiplexer 1520 can select logic 0 at the first input 1522, and when the aging control signal is 1, the second multiplexer 1520 can select logic 1 at the second input 1524, and vice versa.

[0143] In idle mode, the first multiplexer 220 is configured to receive, at its second input 224, a selected option between logic 0 and logic 1 from the second multiplexer 1520. Since the second input 224 of the first multiplexer 220 is selected in idle mode, as discussed above, the first multiplexer 220 passes the selected option between logic 0 and logic 1 to input 212 of the signal path 210. For example, when logic 0 is selected, input 212 of the signal path is at a low level in idle mode, and when logic 0 is selected, input 212 of the signal path is at a high level in idle mode. Therefore, in this example, the output of the second multiplexer 1520 provides an aging control signal to the second input 224 of the first multiplexer 220.

[0144] As discussed above, signal paths 210, 910, and 1040 may each include a delay circuit. For example, signal paths 210, 910, and 1040 may each include a delay circuit 115, which includes delay buffers 120-1 to 120-4 coupled in series. Although four delay buffers 120-1 to 120-4 are illustrated in the example in Figure 1A, it will be appreciated that signal paths may include different numbers of delay buffers. Although Figure 1A illustrates an example in which delay buffers 120-1 to 120-4 are implemented using inverters, it will be appreciated that delay buffers 120-1 to 120-4 are not limited to this example, and delay buffers 120-1 to 120-4 may be implemented using other types of delay buffers.

[0145] In some configurations, the signal path (e.g., signal path 210, signal path 910, or signal path 1040) may include a delay circuit with an adjustable delay (e.g., to adjust the timing of data signals and / or clock signals). For example, the delay circuit may include delay buffers and switching circuitry configured to control which delay buffers are coupled between the inputs and outputs of the delay circuit. In this example, the delay of the delay circuit can be adjusted by using the switching circuitry to control the number of delay buffers coupled between the inputs and outputs of the delay circuit. The switching circuitry may include switches, logic gates, multiplexers, or any combination thereof.

[0146] Figure 16 illustrates an example of a memory interface circuit 1600 that can use various aging controls according to the present invention. However, it will be understood that the present invention is not limited to the memory interface circuit 1600 and can be used in other types of circuits. The memory interface circuit 1600 can be configured to provide access to a memory device (not shown) to one or more processors (e.g., a central processing unit (CPU) core, a graphics processing unit (GPU), etc.). The memory device can be double data rate (DDR) dynamic random access memory (DRAM) or another type of memory device.

[0147] The memory interface circuit 1600 includes a controller 1690 configured to perform burn-in control operations on the memory interface circuit 1600, as further discussed below. The memory interface circuit 1600 also includes a first pad 1610, a second pad 1612, a third pad 1614, a fourth pad 1616, a first receiver 1620, a second receiver 1624, a first driver 1622, a second driver 1626, a third driver 1627, and a fourth driver 1628. In the example in Figure 16, the first pad 1610 is used for a data signal (labeled "DQ"), the second pad 1612 is used for a data select signal (labeled "DQS"), the third pad 1614 is used for a clock signal (labeled "CK"), and the fourth pad 1616 is used for a command / address signal (labeled "CA"). First pad 1610, second pad 1612, third pad 1614, and fourth pad 1616 are coupled to a memory device (not shown) via corresponding metal lines (unused). Although a single data line corresponding to the first pad 1610 is shown in Figure 16 for ease of illustration, it will be understood that the memory interface circuitry 1600 may include multiple parallel data lines for transmitting and / or receiving multiple data signals in parallel.

[0148] The input of the first receiver 1620 and the output of the first driver 1622 are coupled to the first pad 1610. The input of the second receiver 1624 and the output of the second driver 1626 are coupled to the second pad 1612. The output of the third driver 1627 is coupled to the third pad 1614, and the output of the fourth driver 1628 is coupled to the fourth pad 1616. The first receiver 1620 can be configured to receive data signals from a memory device via the first pad 1610. The first receiver 1620 can be configured to amplify the received data signals. The first driver 1622 can be configured to receive data signals and drive the first pad 1610 using the data signals to send the data signals to the memory device. The second receiver 1624 can be configured to receive data select signals from the memory device via the second pad 1612. The second driver 1626 can be configured to receive data select signals and drive the second pad 1612 using the data select signals to send the data select signals to the memory device. The data selection signal can be a clock signal used to retrieve data bits from a data signal. The third driver 1627 can be configured to receive the clock signal and use it to drive the third pad 1614 to send the clock signal to the memory device. The fourth driver 1628 can be configured to receive a command / address (CA) signal and use it to drive the fourth pad 1616 to send the CA signal to the memory device. In this example, the clock signal sent from the third pad 1614 can be used to retrieve command bits and / or address bits from the CA signal.

[0149] The memory interface circuitry 1600 also includes a first multiplexer 1630, a first signal path 1650, a second multiplexer 1640, a second signal path 1654, a third signal path 1657, a third multiplexer 1675, a fourth signal path 1660, a fourth multiplexer 1680, a fifth signal path 1663, a sixth signal path 1666, a first SDR to DDR converter 1670, and a second SDR to DDR converter 1685. Each of the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, the fifth signal path 1663, and the sixth signal path 1666 may include delay circuitry (e.g., delay circuitry 115) for delaying the corresponding signal.

[0150] The first multiplexer 1630 has a first input 1632 coupled to the output of the first receiver 1620, a second input 1634 coupled to the controller 1690, a selection input 1636 coupled to the controller 1690, and an output 1638. The first signal path 1650 has an input 1651 and an output 1652 coupled to the output 1638 of the first multiplexer 1630.

[0151] The first SDR to DDR converter 1670 has a first signal input 1671-1 and a second signal input 1671-2 coupled to a data source (not shown). The first SDR to DDR converter 1670 also has a setting input 1672 coupled to a controller 1690, a reset input 1673 coupled to the controller 1690, and an output 1674. The second signal path 1654 has an input 1655 coupled to the output 1674 of the first SDR to DDR converter 1670 and an output 1656 coupled to an input of the first driver 1622.

[0152] The second multiplexer 1640 has a first input 1642 coupled to the output of the second receiver 1624, a second input 1644 coupled to the controller 1690, a selection input 1646 coupled to the controller 1690, and an output 1648. The third signal path 1657 has an input 1658 coupled to the output 1648 of the second multiplexer 1640 and an output 1659.

[0153] The third multiplexer 1675 has a first input 1676 coupled to a data gating source (not shown), a second input 1677 coupled to a controller 1690, a selection input 1678 coupled to the controller 1690, and an output 1679. The fourth signal path 1660 has an input 1661 coupled to the output 1679 of the third multiplexer 1675 and an output 1662 coupled to the input of the second driver 1626.

[0154] The fourth multiplexer 1680 has a first input 1681 coupled to a clock source (not shown), a second input 1682 coupled to a controller 1690, a selection input 1683 coupled to the controller 1690, and an output 1684. The fifth signal path 1663 has an input 1664 coupled to the output 1684 of the fourth multiplexer 1680 and an output 1665 coupled to the input of the third driver 1627.

[0155] The second SDR-to-DDR converter 1685 has a first signal input 1686-1 and a second signal input 1686-2 coupled to a command / address source (not shown). The second SDR-to-DDR converter 1685 also has a setting input 1687 coupled to a reset input 1688 coupled to a controller 1690, and an output 1689. The sixth signal path 1666 has an input 1667 coupled to the output 1689 of the second SDR-to-DDR converter 1685 and an output 1668 coupled to the input of the fourth driver 1628.

[0156] Exemplary operation of the memory interface circuit 1600 will now be described in accordance with certain specifications.

[0157] During a write operation, the first SDR-to-DDR converter 1670 can receive data to be written to the memory device. For example, the first SDR-to-DDR converter 1670 can receive data in two or more data signals at a single data rate (SDR), wherein the first data signal may include an odd number of data bits and the second data signal may include an even number of bits. In this example, the first SDR-to-DDR converter 1670 can receive the first data signal via the first signal input 1671-1 and the second data signal via the second signal input 1671-2.

[0158] The first SDR to DDR converter 1670 converts an SDR data signal to a Double Data Rate (DDR) data signal and outputs the DDR data signal at output 1674. In one example, the first SDR to DDR converter 1670 can be implemented using the exemplary SDR to DDR converter 1310. The DDR data signal is propagated to the first driver 1622 via a second signal path 1654, and the first driver 1622 sends the DDR data signal to the memory device via a first pad 1610. In this example, the second signal path 1654 can delay the data signal (e.g., align the data signal with one or more other data signals (not shown) in parallel data lines). As discussed above, other data lines are not shown in FIG. 16 for ease of illustration.

[0159] During a write operation, the third multiplexer 1675 can receive a data select signal at the first input 1676. The controller 1690 instructs the third multiplexer 1675 to select the first input 1676, causing the third multiplexer 1675 to output the data select signal to the fourth signal path 1660. The data select signal can have half the frequency of the data signal in DDR (i.e., the data signal in DDR includes two data bits for each period of the data select signal). The data select signal is propagated to the second driver 1626 via the fourth signal path 1660, and the second driver 1626 sends the data select signal to the memory device via the second pad 1612. In this example, the fourth signal path 1660 can delay the data select signal (e.g., adjust the timing of the data select signal relative to the data signal in DDR).

[0160] During a read operation, the first receiver 1620 can receive a data signal, including read data, from the memory device via the first pad 1610. The controller 1690 can instruct the first multiplexer 1630 to select the first input 1632 to allow the data signal to propagate via the first multiplexer 1630 to the first signal path 1650. The first signal path 1650 can output the read data to the memory controller (not shown), which can buffer the data in the data signal and send the data to the processor requesting data from the memory device.

[0161] During a read operation, the second receiver 1624 can receive a data select signal from the memory device via the second pad 1612 and output the received data select signal to the first input 1642 of the second multiplexer 1640. The controller 1690 instructs the second multiplexer 1640 to select the first input 1642, causing the second multiplexer 1640 to output the data select signal to the third signal path 1657. The data select signal is propagated via the third signal path 1657 to the memory controller (not shown), which can use the data select signal to retrieve read data from the data signals received from the memory device. In this example, the third signal path 1657 can delay the data select signal (e.g., to adjust the timing of the data select signal relative to the received data signal).

[0162] The second SDR-DDR converter 1685 can receive commands and / or address information from a memory device. For example, the second SDR-DDR converter 1685 can receive commands and / or address information in two or more control / address (CA) signals at a single data rate (SDR), wherein the first CA signal may include an odd number of bits, and the second CA signal may include an even number of bits. In this example, the second SDR-DDR converter 1685 can receive the first CA signal via a first signal input 1686-1, and the second CA signal via a second signal input 1686-2.

[0163] The second SDR-DDR converter 1685 converts the CA signal in SDR mode to a CA signal in Double Data Rate (DDR) mode and outputs the CA signal in DDR mode at output 1689. In one example, the second SDR-DDR converter 1685 can be implemented using the exemplary SDR-DDR converter 1310. The CA signal in DDR mode is propagated to the fourth driver 1628 via the sixth signal path 1666, and the fourth driver 1628 sends the CA signal in DDR mode to the memory device via the fourth pad 1616.

[0164] The fourth multiplexer 1680 can receive a clock signal at the first input 1681. The controller 1690 instructs the fourth multiplexer 1680 to select the first input 1681, causing the fourth multiplexer 1680 to output the clock signal to the fifth signal path 1663. The clock signal is propagated via the fifth signal path 1663 to the third driver 1627, and the third driver 1627 sends the clock signal to the memory device via the third pad 1614. The memory device can use the clock signal to fetch command / address bits from the CA signal.

[0165] For write operations, the memory controller (not shown) can receive a request from the processor (not shown) to write data to the memory device. In response, the memory controller generates a CA signal, including a write command and a write address for the data to be written. The second SDR to DDR converter 1685 receives the SDR CA signal via the first signal input 1686-1 and the second signal input 1686-2, converts the SDR CA signal to the DDR CA signal, and outputs the DDR CA signal at output 1689. The CA signal is propagated to the fourth driver 1628 via the sixth signal path 1666, and the fourth driver 1628 sends the CA signal to the memory device via the fourth pad 1616.

[0166] For read operations, the memory controller (not shown) can receive a read request from the processor (not shown). In response, the memory controller generates a CA signal, which includes a read command and a read address for the data to be read from the memory device. The second SDR to DDR converter 1685 receives the SDR CA signal via the first signal input 1686-1 and the second signal input 1686-2, converts the SDR CA signal to the DDR CA signal, and outputs the DDR CA signal at output 1689. The CA signal is propagated to the fourth driver 1628 via the sixth signal path 1666, and the fourth driver 1628 sends the CA signal to the memory device via the fourth pad 1616.

[0167] The memory controller can also generate CA signals, which include commands for performing internal operations (e.g., refresh operations). In this case, the memory controller generates CA signals that include internal commands (e.g., refresh commands) for the memory device. The second SDR to DDR converter 1685 receives the CA signal in SDR via the first signal input 1686-1 and the second signal input 1686-2, converts the CA signal in SDR to the CA signal in DDR, and outputs the CA signal in DDR at output 1689. The CA signal is propagated to the fourth driver 1628 via the sixth signal path 1666, and the fourth driver 1628 sends the CA signal to the memory device via the fourth pad 1616.

[0168] Controller 1690 can be configured to perform aging control operations on memory interface circuit 1600 based on the activity of memory interface circuit 1600, as further discussed below. In some cases, controller 1690 may receive one or more signals at input 1692 instructing the operation of memory interface circuit 1600. Controller 1690 may be implemented using one or more instances of the exemplary controller 230 and / or controller 1030 discussed above.

[0169] During a write operation, the first signal path 1650 and the third signal path 1657 can be idle, while the second signal path 1654, the fourth signal path 1660, the fifth signal path 1663, and the sixth signal path 1666 are active. In other words, during a write operation, the read data path and the read data strobe path (which respectively include the first signal path 1650 and the third signal path 1657) can be in an idle mode. In this case, the controller 1690 can receive a signal indicating a write operation from the memory controller. In response, the controller 1690 can perform an aging control operation for the first signal path 1650 and the third signal path 1657, while the second signal path 1654, the fourth signal path 1660, the fifth signal path 1663, and the sixth signal path 1666 are active.

[0170] In this regard, controller 1690 can instruct first multiplexer 1630 to select second input 1634 via selection input 1636. Subsequently, controller 1690 can input an aging control signal to the second input 1634 of first multiplexer 1630 to control the aging of first signal path 1650 (e.g., using any of the exemplary techniques discussed above). For example, the aging control signal can alternately place input 1651 of first signal path 1650 at high and low levels during multiple idle periods to control the aging of first signal path 1650 based on an aging pattern (e.g., stored in circular shift register 410), etc.

[0171] The controller 1690 can also instruct the second multiplexer 1640 to select the second input 1644 via the selection input 1646. Subsequently, the controller 1690 can input an aging control signal to the second input 1644 of the second multiplexer 1640 to control the aging of the third signal path 1657 (e.g., using any of the exemplary techniques discussed above). For example, the aging control signal can alternately place the input 1658 of the third signal path 1657 at high and low levels during multiple idle periods, controlling the aging of the third signal path 1657 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0172] During a read operation, the second signal path 1654 and the fourth signal path 1660 can be idle, while the first signal path 1650, the third signal path 1657, the fifth signal path 1663, and the sixth signal path 1666 are active. In other words, during a read operation, the write path and the write strobe path (which respectively include the second signal path 1654 and the fourth signal path 1660) can be in an idle mode. In this case, the controller 1690 can receive a signal instructing a read operation from the memory controller. In response, when the first signal path 1650, the third signal path 1657, the fifth signal path 1663, and the sixth signal path 1666 are active, the controller 1690 can perform an aging control operation for the second signal path 1654 and the fourth signal path 1660.

[0173] In this regard, controller 1690 can use the set input 1672 and reset input 1673 of the first SDR-to-DDR converter 1670 (e.g., using any of the exemplary techniques discussed above) to control the aging of the second signal path 1654. For example, controller 1690 can set input 1655 of the second signal path 1654 to a high level via assertion set input 1672 and set input 1655 of the second signal path 1654 to a low level via assertion reset input 1673. In this example, controller 1690 can control aging, for example, by alternately setting input 1655 of the second signal path 1654 to a high level and a low level during multiple idle periods of the second signal path 1654. In another example, controller 1690 can control the aging of the second signal path 1654 based on an aging mode.

[0174] The controller 1690 may also instruct the third multiplexer 1675 to select the second input 1677 via the selection input 1678. Subsequently, the controller 1690 may input an aging control signal to the second input 1677 of the third multiplexer 1675 to control the aging of the fourth signal path 1660 (e.g., using any of the exemplary techniques discussed above). For example, the aging control signal may alternately place the input 1661 of the fourth signal path 1660 at high and low levels during multiple idle periods, controlling the aging of the fourth signal path 1660 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0175] During housekeeping operations (e.g., refresh operations), the first signal path 1650, the second signal path 1654, the third signal path 1657, and the fourth signal path 1660 associated with read and write operations can be idle, while the fifth signal path 1663 and the sixth signal path 1666 can be active to send housekeeping commands (e.g., refresh commands) to the memory device. In other words, during housekeeping operations, the write path, the write strobe path, the read path, and the read strobe path can be idle. In this case, the controller 1690 can receive signals instructing housekeeping operations from the memory controller. In response, the controller 1690 can perform aging control operations for the first signal path 1650, the second signal path 1654, the third signal path 1657, and the fourth signal path 1660. For example, the controller 1690 can perform aging control operations for the first signal path 1650 and the third signal path 1657 in the manner described above for write operations. The controller 1690 can also perform aging control operations on the second signal path 1654 and the fourth signal path 1660 in the manner described above for the read operation.

[0176] During the flow idle mode or clock stop power-down (CSPD) mode, the CA, CK, DQ, and DQS paths are all idle. In this case, the controller 1690 can receive a signal from the memory controller indicating the flow idle mode or CSPD mode. In response, the controller 1690 can perform aging control operations on the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, the fifth signal path 1663, and the sixth signal path 1666. The controller 1690 can perform aging control operations on the first signal path 1650, the second signal path 1654, the third signal path 1657, and the fourth signal path 1660 in the manner described above.

[0177] Controller 1690 can control the aging of the sixth signal path 1666 using the set input 1687 and reset input 1688 of the second SDR-to-DDR converter 1685 (e.g., using any of the exemplary techniques described above). For example, controller 1690 can set input 1667 of the sixth signal path 1666 to a high level via assertion set input 1687 and set input 1667 of the sixth signal path 1666 to a low level via assertion reset input 1688. In this example, controller 1690 can control aging, for example, by alternately setting input 1667 of the sixth signal path 1666 to a high level and a low level during multiple idle periods. In another example, controller 1690 can control the aging of the sixth signal path 1666 based on an aging mode.

[0178] The controller 1690 can also instruct the fourth multiplexer 1680 to select the second input 1682 via the selection input 1683. Subsequently, the controller 1690 can input an aging control signal to the second input 1682 of the fourth multiplexer 1680 to control the aging of the fifth signal path 1663 (e.g., using any of the exemplary techniques discussed above). For example, the aging control signal can alternately place the input 1664 of the fifth signal path 1663 at high and low levels during multiple idle periods, controlling the aging of the fifth signal path 1663 based on an aging pattern (e.g., stored in the circular shift register 410), etc.

[0179] In clockless execution mode, the clock signal may be executed without any command transmission. This can be done, for example, to keep the memory device synchronized with the clock signal. In this mode, the fifth signal path 1663 remains active for the clock signal, while the first signal path 1650, second signal path 1654, third signal path 1657, fourth signal path 1660, and sixth signal path 1666 are idle. In this case, the controller 1690 can receive a signal indicating the clockless execution mode from the memory controller. In response, the controller 1690 can perform aging control operations on the first signal path 1650, second signal path 1654, third signal path 1657, fourth signal path 1660, and sixth signal path 1666 in the manner described above.

[0180] Figure 17 illustrates another example of a memory interface circuit 1900 in which aging control according to various forms of the present invention can be used. The memory interface circuit 1900 includes the first multiplexer 1630, the second multiplexer 1640, the third multiplexer 1675, the fourth multiplexer 1680, the first signal path 1650, the second signal path 1654, the third signal path 1657, the fourth signal path 1660, the fifth signal path 1663, the sixth signal path 1666, the first receiver 1620, the second receiver 1624, the first driver 1622, the second driver 1626, the third driver 1627, the fourth driver 1628, the first pad 1610, the second pad 1612, the third pad 1614, the fourth pad 1616, and the controller 1690. The memory interface circuit 1900 also includes a fifth multiplexer 1710 and a sixth multiplexer 1720.

[0181] The fifth multiplexer 1710 has a first input 1712 configured to receive data signals, a second input 1714 coupled to a controller 1690, a selection input 1716 coupled to the controller 1690, and an output 1718 coupled to an input 1655 of a second signal path 1654. In one example, the first input 1712 can receive data signals from a first SDR to a DDR converter 1670 (not shown in FIG. 17), wherein the first input 1712 of the fifth multiplexer 1710 is coupled to an output 1674 of the first SDR to DDR converter 1670. However, it should be understood that the scope of this invention is not limited to this example.

[0182] The sixth multiplexer 1720 has a first input 1722 configured to receive a CA signal, a second input 1724 coupled to a controller 1690, a selection input 1726 coupled to the controller 1690, and an output 1728 coupled to an input 1667 of a sixth signal path 1666. In one example, the first input 1722 can receive a data signal from a DDR converter 1685 (not shown in Figure 17) from a second SDR, wherein the first input 1722 of the sixth multiplexer 1720 is coupled to an output 1689 of the second SDR to DDR converter 1685. However, it should be understood that the scope of this invention is not limited to this example.

[0183] During a write operation, controller 1690 instructs fifth multiplexer 1710 to select first input 1712 via selection input 1716. This allows fifth multiplexer 1710 to receive a data signal including the data to be written to the memory device, and input 1655 to pass the data signal to second signal path 1654.

[0184] During read operations, housekeeping operations, transfer idle mode, or CSPD mode, controller 1690 may instruct fifth multiplexer 1710 to select second input 1714 via selection input 1716. Subsequently, controller 1690 may input an aging control signal to the second input 1714 of fifth multiplexer 1710 to control the aging of second signal path 1654 (e.g., using any of the exemplary techniques discussed above). For example, the aging control signal may alternately set input 1655 of second signal path 1654 high and low during multiple idle periods, control the aging of second signal path 1654 based on an aging mode (e.g., stored in cyclic shift register 410), etc.

[0185] During read, write, or housekeeping operations, controller 1690 may instruct sixth multiplexer 1720 to select first input 1722 via selection input 1726. This allows sixth multiplexer 1720 to receive CA signals including command and / or address information, and input 1667 to pass the CA signals to sixth signal path 1666.

[0186] During the transfer idle mode, CSPD mode, or no-clock execution mode, controller 1690 may instruct the sixth multiplexer 1720 to select the second input 1724 via selection input 1726. Subsequently, controller 1690 may input an aging control signal to the second input 1724 of the sixth multiplexer 1720 to control the aging of the sixth signal path 1666 (e.g., using any of the exemplary techniques discussed above). For example, the aging control signal may alternately set input 1667 of the sixth signal path 1666 high and low during multiple idle cycles, controlling the aging of the sixth signal path 1666 based on an aging mode (e.g., stored in the circular shift register 410), etc.

[0187] Figure 18 is a flowchart illustrating a method 1800 for aging control based on certain conditions.

[0188] At block 1810, in startup mode, a signal is input to the signal path. For example, the signal may include a data signal, clock signal, control signal, or address signal. The signal path may correspond to any one of signal path 210, signal path 1040, first signal path 1650, second signal path 1654, third signal path 1657, fourth signal path 1660, fifth signal path 1663, or sixth signal path 1666. The signal path may include a delay circuit (e.g., delay circuit 115). In some instances, the signal may be input to the signal path by a multiplexer (e.g., multiplexer 220, multiplexer 920, first multiplexer 1630, second multiplexer 1640, third multiplexer 1675, fourth multiplexer 1680, fifth multiplexer 1710 or sixth multiplexer 1720) or a latching circuit (e.g., latching circuit 1010, first latching circuit 1320 or second latching circuit 1340).

[0189] At block 1820, in idle mode, the aging of the control signal path is performed. Aging can be controlled by a controller (e.g., controller 230, 1030, or 1690).

[0190] In some states, aging of the control signal in idle mode includes alternately setting the signal input to a high level and a low level during multiple consecutive idle periods. In some states, the consecutive idle periods include odd-numbered idle periods and even-numbered idle periods. In these states, alternately setting the signal path input to a high level and a low level may include setting the signal path input to a low level during each odd-numbered idle period and setting the signal path input to a high level during each even-numbered idle period, or may include setting the signal path input to a high level during each odd-numbered idle period and setting the signal path input to a low level during each even-numbered idle period.

[0191] In some states, aging of the signal path in idle mode involves placing the input of the signal path at a high level for k idle periods out of N consecutive idle periods, and placing the input of the signal path at a low level for Nk idle periods out of N consecutive idle periods, where k is an integer equal to or greater than 1, and N is an integer greater than k.

[0192] In some embodiments, method 1800 may also include storing a bit sequence in a register (e.g., register 235 or register 1035), each bit of the bit sequence corresponding to a corresponding idle period in N consecutive idle periods in the idle mode. In these embodiments, aging of the control signal path in the idle mode may include: during each of the N consecutive idle periods, if the corresponding bit in the bit sequence has a first bit value, then placing the input of the signal path at a high level during that idle period, and if the corresponding bit in the bit sequence has a second bit value, then placing the input of the signal path at a low level during that idle period. The first bit value may be 1 and the second bit value may be 0, or the first bit value may be 0 and the second logic bit may be 1.

[0193] In some configurations, aging of the control signal path in idle mode includes inputting a clock signal to the signal path. This clock signal may correspond to the slow clock signal discussed above with reference to Figure 3B.

[0194] Implementation examples are described in the following numbered clauses:

[0195] 1. A system comprising:

[0196] A multiplexer has a first input, a second input, a selection input, and an output;

[0197] A signal path having input and output, wherein the input of the signal path is coupled to the output of the multiplexer; and

[0198] A controller coupled to the second input of the multiplexer and the selection input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to:

[0199] Receive the mode indicator signal at this indicator input;

[0200] If the mode indicator signal has a first logic value, it instructs the multiplexer to select the first input of the multiplexer; and

[0201] If the mode indicator signal has a second logic value, it instructs the multiplexer to select the second input of the multiplexer and outputs a control signal to the second input of the multiplexer. This control signal controls whether the input of the signal path is placed at a high level or a low level.

[0202] 2. The system according to Clause 1, wherein the first input of the multiplexer is configured to receive a data signal, a clock signal, a command signal, or an address signal.

[0203] 3. A system pursuant to Clause 1 or 2, wherein the signal path includes a delay circuit.

[0204] 4. The system according to Clause 3, wherein the delay circuit includes a delay buffer coupled in series.

[0205] 5. The system according to any one of Clauses 1 to 4, wherein the first logic value indicates that the system is in an active mode and the second logic value indicates that the system is in an idle mode.

[0206] 6. The system according to any one of Clauses 1 to 5, wherein when the mode indicator signal has the second logic value, the controller is configured to set the control signal to a high level and a low level during a plurality of consecutive idle periods.

[0207] 7. The system according to Clause 6, wherein the continuous idle period includes odd-numbered idle periods and even-numbered idle periods, and the controller is configured to:

[0208] During each of these odd-numbered idle periods, the control signal is set to a low level; and

[0209] During each of these even-numbered idle periods, the control signal is set to a high level.

[0210] 8. The system pursuant to Clause 6, wherein the continuous idle period includes odd-numbered idle periods and even-numbered idle periods, and the controller is configured to:

[0211] During each of these odd-numbered idle periods, the aging control signal is set to a high level; and

[0212] During each of these even-numbered idle periods, the aging control signal is set to a low level.

[0213] 9. The system according to any one of clauses 1 to 5, wherein the controller is configured to: when the mode indicator signal has the second logic value.

[0214] During k idle periods out of N consecutive idle periods, the control signal is set to a high level; and

[0215] During Nk consecutive idle periods within these N consecutive idle periods, the control signal is set to a low level;

[0216] Where k is an integer equal to or greater than 1, and N is an integer greater than k.

[0217] 10. The system according to any one of clauses 1 to 5, wherein the controller is configured to store a bit sequence in a register, each bit in the bit sequence corresponding to a corresponding idle period in N consecutive idle periods in an idle mode, and wherein within each of the N consecutive idle periods, the controller is configured to:

[0218] If the corresponding bit in the bit sequence has a first bit value, then the control signal is set to a high level during the idle period; and

[0219] If the corresponding bit in the bit sequence has a second bit value, then the control signal is set to the low level during the idle period.

[0220] 11. The system according to any one of Clauses 1 to 5, wherein the control signal includes a clock signal.

[0221] 12. The system according to any one of clauses 1 to 11 also includes:

[0222] solder pads; and

[0223] A receiver having an input and an output, wherein the input of the receiver is coupled to the pad, and the output of the receiver is coupled to the first input of the multiplexer.

[0224] 13. The system according to any one of clauses 1 to 12 also includes:

[0225] solder pads; and

[0226] A driver having inputs and outputs, wherein the input of the driver is coupled to the output of the signal path, and the output of the driver is coupled to the pad.

[0227] 14. The system according to any one of clauses 1 to 12 also includes:

[0228] A latch circuit having a signal input, a clock input, and an output, wherein the signal input is coupled to the output of the signal path.

[0229] 15. The system according to any one of Clauses 1 to 12 also includes:

[0230] A latch circuit having a signal input, a clock input, and an output, wherein the clock input is coupled to the output of the signal path.

[0231] 16. The system according to any one of clauses 1 to 10 and 12 to 15, wherein the controller comprises:

[0232] A circular shift register with inputs and outputs, wherein the output of the circular shift register is coupled to a second input of the multiplexer; and

[0233] A control circuit having an input, a first output, and a second output, wherein the input of the control circuit is coupled to the indicator input, the first output of the control circuit is coupled to the selection input of the multiplexer, and the second output of the control circuit is coupled to the input of the cyclic shift register.

[0234] 17. According to Clause 16, the system in which:

[0235] The circular shift register is configured to store bits and outputs one bit at a time at the output of the circular shift register;

[0236] The control circuit is configured as follows:

[0237] The mode indicator signal is received via the input of the control circuit;

[0238] If the mode indicator signal has the first logic value, then the multiplexer is instructed to select the first input; and

[0239] If the mode indicator signal has the second logic value, the multiplexer is instructed to select the second input via the first output, and the cyclic shift register is instructed to shift the bit in the cyclic shift register via the second output.

[0240] 18. A system comprising:

[0241] A latch circuit has signal input, clock input, setting input, reset input, and output.

[0242] A signal path having input and output, wherein the input of the signal path is coupled to the output of the latch circuit; and

[0243] A controller coupled to the set input and reset input of the latch circuit, wherein the controller has an indicator input, and the controller is configured to:

[0244] Receive the mode indicator signal at this indicator input;

[0245] If the mode indicator signal has a first logic value, then the assertion of the setting input and the reset input is cancelled; and

[0246] If the mode indicator signal has a second logic value, the setting input and the reset input are used to control whether the input of the signal path is set to a high level or a low level.

[0247] 19. The system pursuant to Clause 18, wherein the first logical value indicates that the system is in an active mode and the second logical value indicates that the system is in an idle mode.

[0248] 20. A system pursuant to Clause 18 or 19, wherein the signal input of the latch circuit is configured to receive data signals, command signals, or address signals.

[0249] 21. The system according to any one of Clauses 18 to 20, wherein the signal path includes a delay circuit.

[0250] 22. The system pursuant to Clause 21, wherein the delay circuit includes a delay buffer coupled in series.

[0251] 23. The system according to any one of Clauses 18 to 22, wherein when the mode indicator has the second logic value, the controller is configured to alternately assert the setting input and the reset input during a plurality of consecutive idle periods.

[0252] 24. The system pursuant to Clause 23, wherein the continuous idle period includes odd-numbered idle periods and even-numbered idle periods, and the controller is configured to:

[0253] During each of these odd-numbered idle periods, assert the setting input; and

[0254] During each of these even-numbered idle periods, the reset input is asserted.

[0255] 25. The system pursuant to Clause 23, wherein the continuous idle period includes odd-numbered idle periods and even-numbered idle periods, and the controller is configured to:

[0256] During each of these odd-numbered idle periods, assert the reset input; and

[0257] During each of these even-numbered idle periods, the setting input is asserted.

[0258] 26. The system according to any one of clauses 18 to 22, wherein the controller is configured to: when the mode indicator signal has the second logic value.

[0259] Assert the setting input during k idle periods out of N consecutive idle periods; and

[0260] Assert the reset input during Nk idle periods out of the N consecutive idle periods;

[0261] Where k is an integer equal to or greater than 1, and N is an integer greater than k.

[0262] 27. The system according to any one of clauses 18 to 22, wherein the controller is configured to store a bit sequence in a register, each bit in the bit sequence corresponding to a corresponding idle period in N consecutive idle periods in an idle mode, and wherein within each of the N consecutive idle periods, the controller is configured to:

[0263] If the corresponding bit in the bit sequence has a first bit value, then assert the setting input during the idle period; and

[0264] If the corresponding bit in the bit sequence has a second bit value, then the reset input is asserted during the idle period.

[0265] 28. The system pursuant to any one of Clauses 18 to 27 also includes:

[0266] solder pads; and

[0267] A receiver having an input and an output, wherein the input of the receiver is coupled to the pad and the output of the receiver is coupled to the signal input of the latch circuit.

[0268] 29. The system pursuant to any one of Clauses 18 to 28 also includes:

[0269] solder pads; and

[0270] A driver having inputs and outputs, wherein the input of the driver is coupled to the output of the signal path, and the output of the driver is coupled to the pad.

[0271] 30. A method for aging control, comprising:

[0272] In active mode, the signal is input to the signal path input; and

[0273] In idle mode, the aging of this signal path is controlled.

[0274] 31. The method according to Clause 30, wherein the signal includes a data signal, a clock signal, a control signal, or an address signal.

[0275] 32. The method according to Clause 30 or 31, wherein the signal path includes a delay circuit.

[0276] 33. The method according to Clause 32, wherein the delay circuit includes a delay buffer coupled in series.

[0277] 34. The method according to any one of clauses 30 to 33, wherein controlling the aging of the signal in the idle mode includes alternately placing the input of the signal at a high level and a low level during multiple consecutive idle periods.

[0278] 35. The method according to Clause 34, wherein the continuous idle period includes odd-numbered idle periods and even-numbered idle periods, and wherein the input of the signal path is alternately placed at a high level and a low level includes:

[0279] During each of these odd-numbered idle periods, the input of the signal path is placed at a low level; and

[0280] During each of these even-numbered idle periods, the input of the signal path is set to a high level.

[0281] 36. The method according to Clause 34, wherein the continuous idle period includes odd-numbered idle periods and even-numbered idle periods, and alternatingly placing the input of the signal path at high and low levels includes:

[0282] During each of these odd-numbered idle periods, the input of the signal path is placed at a high level; and

[0283] During each of these even-numbered idle periods, the input of the signal path is set to a low level.

[0284] 37. The method according to any one of clauses 30 to 33, wherein controlling the aging of the signal path in the idle mode includes:

[0285] During k idle periods out of N consecutive idle periods, the input of this signal path is set to a high level; and

[0286] During Nk consecutive idle periods, the input of the signal path is set to the low level.

[0287] Where k is an integer equal to or greater than 1, and N is an integer greater than k.

[0288] 38. The method according to any one of clauses 30 to 33 further includes: storing a bit sequence in a temporary register, each bit in the bit sequence corresponding to a corresponding idle period in N consecutive idle periods in the idle mode, and wherein controlling the aging of the signal path in the idle mode includes: within each of the N consecutive idle periods,

[0289] If the corresponding bit in the bit sequence has a first bit value, then the input of the signal path is placed at a high level during the idle period; and

[0290] If the corresponding bit in the bit sequence has a second bit value, the input of the signal path is set to the low level during the idle period.

[0291] 39. The method according to any one of clauses 30 to 33, wherein controlling the aging of the signal path includes inputting a clock signal to the input of the signal path.

[0292] It should be understood that the content of this case is not limited to the various exemplary terms used above to describe the content of this case. For example, a delay circuit may also be referred to as a delay line, delay chain, delay component, or another term. In another instance, a pad may also be referred to as a pin or another term. It should also be understood that an indicator signal may also be referred to as a mode indicator signal.

[0293] Controllers 230, 1030, and 1690 may each be implemented using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, individual hardware component (e.g., logic gate), or any combination thereof, designed to perform the functions described herein. The processor may perform the functions described herein by executing software comprising code for performing the functions. The software may be stored on a computer-readable storage medium, such as RAM, ROM, EEPROM, optical disc, and / or magnetic disk.

[0294] Within the scope of this document, the term "exemplary" is used to mean "serving as an example, illustration, or explanation." Any implementation or mode described herein as "exemplary" is not necessarily construed as preferred over or superior to other modes within this document. Similarly, the term "mode" does not require that all modes within this document include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect electrical coupling between two structures. It should also be understood that the term "grounding" can refer to DC ground or AC ground, and therefore the term "grounding" encompasses both possibilities.

[0295] The foregoing description of the contents of this application is provided to enable anyone skilled in the art to implement or use the contents of this application. Various modifications to the contents of this application will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the contents. Therefore, the contents of this application are not intended to be limited to the examples and designs described herein, but rather to conform to the broadest scope consistent with the principles and novel features disclosed herein.

[0296] 105: Delayed Signal Path 108: Input 110: Output 115: Delay Circuit 120-1: Delay Buffer 120-2: Delay Buffer 120-3: Delay Buffer 120-4: Delay Buffer 125-1: Transistor 125-2: Transistor 125-3: Transistor 125-4: Transistor 130-1: Transistor 130-2: Transistor 130-3: Transistor 130-4: Transistor 150: Clock signal 160: Clock signal 180: Clock signal 205: System 210: Signal Path 212: Input 214: Output 220: Multiplexer 222: First input 224: Second Input 226: Input 228: Output 230: Controller 232: Input 234: First Output 235: Temporary Register 236: Second Output 305: Logical value 310-1: Activity Period 310-2: Activity Period 310-3: Activity Period 310-4: Activity Period 320-1: Idle Period 320-2: Idle Period 320-3: Idle Period 320-4: Idle Period 350: Logical value 360-1: Activity Period 360-2: Activity Period 360-3: Activity Period 360-4: Activity Period 370-1: Idle Period 370-2: Idle Period 370-3: Idle Period 370-4: Idle Period 410: Circular shift register 412: Input 414: Output 415-(N-1): Storage tank 415-1: Storage tank 415-2: Storage tank 415-N: Storage tank 420: Control Circuit 422: Input 424: First Output 426: Second Output 505: System 510: Drive 512: Input 514: Output 530: Third Output 540: Clock gating circuit 542: Signal Input 544: Control Input 546: Output 570: AND gate 605: System 610: Latch circuit 612: Signal Input 614: Clock Input 616: Output 705: System 710: Receiver 712: Input 714: Output 720: solder pad 805: System 810: Latch circuit 812: Signal Input 814: Clock Input 816: Output 820: Clock Source 822: Output 905: System 910: Second signal path 912: Input 914: Output 920: Second Multiplexer 922: First input 924: Second input 926: Select Input 928: Output 930: Receiver 932: Input 934: Output 940: solder pad 942: Second Input 944: Third Output 946: Fourth Output 1005: System 1010: Latch circuit 1012: Signal Input 1014: Clock Input 1016: Set Input 1018: Reset Input 1020: Output 1030: Controller 1032: Input 1034: First Output 1035: Temporary Register 1036: Second Output 1040: Signal Path 1042: Input 1044: Output 1105: System 1110: Driver 1112: Input 1114: Output 1120: Solder pad 1130: Third Output 1140: Clock gating circuit 1142: Signal Input 1144: Output 1146: Output 1205: System 1305: System 1310: DDR Converter 1312: First input 1314: Second Input 1316: Output 1320: First latch circuit 1322: Signal Input 1324: Clock Input 1326: Set Input 1328: Reset Input 1330: Output 1340: Second latch circuit 1342: Signal Input 1344: Clock Input 1346: Set Input 1348: Reset Input 1350: Output 1360: Multiplexer 1362: First input 1364: Second input 1366: Select Input 1368: Output 1410: Circular shift register 1412: Input 1414: Output 1415-(N-1): Storage tank 1415-1: Storage tank 1415-2: Storage tank 1415-N: Storage tank 1420: Control Circuit 1422: Input 1424: First Output 1426: Second Output 1450: First Multiplexer 1452: First Input 1454: Second Input 1456: Select Input 1458: Output 1460: Second Multiplexer 1462: First Input 1464: Second Input 1466: Select Input 1468: Output 1470: Inverter 1505: System 1520: Second Multiplexer 1522: First input 1524: Second Input 1526: Select Input 1528: Output 1600: Memory Interface Circuit 1610: First pad 1612: Second pad 1614: Third pad 1616: Fourth pad 1620: First Receiver 1622: First Driver 1624: Second Receiver 1626: Second Driver 1627: The Third Drive 1628: The Fourth Drive 1630: First Multiplexer 1632: First input 1634: Second input 1636: Select Input 1638: Output 1640: Second Multiplexer 1642: First Input 1644: Second input 1646: Select Input 1648: Output 1650: First Signal Path 1651: Input 1652: Output 1654: Second Signal Path 1655: Input 1656: Output 1657: Third Signal Path 1658: Input 1659: Output 1660: Fourth Signal Path 1661: Input 1662: Output 1663: Fifth Signal Path 1664: Input 1665: Output 1666: Sixth Signal Path 1667: Input 1668: Output 1670: DDR Converter 1671-1: First Signal Input 1671-2: Second signal input 1672: Setting Input 1673: Reset Input 1674: Output 1675: Third Multiplexer 1676: First input 1677: Second input 1678: Select Input 1679: Output 1680: Fourth Multiplexer 1681: First Input 1682: Second Input 1683: Select Input 1684: Output 1685: DDR Converter 1686-1: First Signal Input 1686-2: Second signal input 1687: Setting Input 1688: Reset Input 1689: Output 1690: Controller 1692: Input 1710: Fifth Multiplexer 1712: First Input 1714: Second Input 1716: Select Input 1718: Output 1720: The Sixth Multiplexer 1722: First Input 1724: Second Input 1726: Select Input 1728: Output 1800: Method 1810: Square 1820: Square CA: Command / Address Signal CK: Clock signal Clk: Clock signal DQ: Data Signal DQS: Data Selection Communication Number T f: Delay T r: Delay

[0297] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A system for aging control, comprising: A multiplexer having a first input, a second input, a selection input, and an output, wherein the first input of the multiplexer is configured to receive a clock signal; a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; and a controller coupled to the second input of the multiplexer and the selection input of the multiplexer, wherein the controller has an indicator input and is configured to: receive a mode indicator signal at the indicator input; If the mode indicator signal has a first logic value, it instructs the multiplexer to select a first input of the multiplexer; and if the mode indicator signal has a second logic value, it instructs the multiplexer to select a second input of the multiplexer, outputs a control signal to the second input of the multiplexer, and alternately sets the control signal to a high level and a low level during multiple consecutive idle periods.

2. The system according to request item 1, wherein the signal path includes a delay circuit.

3. The system according to claim 2, wherein the delay circuit includes a delay buffer coupled in series.

4. The system according to request item 1, wherein the first logical value indicates that the system is in an active mode and the second logical value indicates that the system is in an idle mode.

5. The system according to claim 1, wherein the continuous idle period includes odd idle periods and even idle periods, and the controller is configured to: set the control signal to a low level during each of the odd idle periods; and set the control signal to a high level during each of the even idle periods.

6. The system according to claim 1, wherein the continuous idle period includes odd idle periods and even idle periods, and the controller is configured to: set the control signal to a high level during each of the odd idle periods; and set the control signal to a low level during each of the even idle periods.

7. The system according to request item 1 also includes: One solder pad; and a receiver having an input and an output, wherein the input of the receiver is coupled to the pad and the output of the receiver is coupled to the first input of the multiplexer.

8. The system according to request item 1 also includes: One solder pad; and a driver having an input and an output, wherein the input of the driver is coupled to the output of the signal path, and the output of the driver is coupled to the pad.

9. The system according to request item 1 also includes: A latch circuit having a signal input, a clock input, and an output, wherein the clock input is coupled to the output of the signal path.

10. The system according to request item 1 also includes: One driver; and a clock-gated circuit coupled between the output of the signal path and an input of the driver, wherein the controller is configured to degrate the clock-gated circuit if the mode indicator has the first logic value, and to grapple the clock-gated circuit if the mode indicator has the second logic value.

11. The system according to request 10, wherein the first logical value indicates that the system is in an active mode and the second logical value indicates that the system is in an idle mode.

12. A system for aging control, comprising: A multiplexer having a first input, a second input, a selection input, and an output, wherein the first input of the multiplexer is configured to receive a clock signal; a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; and a controller coupled to the second input of the multiplexer and the selection input of the multiplexer, wherein the controller has an indicator input and is configured to: receive a mode indicator signal at the indicator input; If the mode indicator signal has a first logic value, it instructs the multiplexer to select the first input of the multiplexer; and if the mode indicator signal has a second logic value, it instructs the multiplexer to select the second input of the multiplexer, outputs a control signal to the second input of the multiplexer, sets the control signal to a high level for k idle periods out of N consecutive idle periods, and sets the control signal to a low level for Nk idle periods out of N consecutive idle periods, where k is an integer equal to or greater than 1, and N is an integer greater than k.

13. The system according to claim 12, wherein the controller is configured to store a bit sequence in a register, each bit in the bit sequence corresponding to a corresponding idle period in N consecutive idle periods in an idle mode, and wherein for each of the N consecutive idle periods, the controller is configured to: set the control signal to a high level during the idle period if the corresponding bit in the bit sequence has a first bit value; and set the control signal to a low level during the idle period if the corresponding bit in the bit sequence has a second bit value.

14. The system according to request item 12, wherein the controller includes: A circular shift register having one input and one output, wherein the output of the circular shift register is coupled to a second input of the multiplexer; A control circuit having an input, a first output, and a second output, wherein the input of the control circuit is coupled to the indicator input, the first output of the control circuit is coupled to the selection input of the multiplexer, and the second output of the control circuit is coupled to the input of the cyclic shift register.

15. The system according to request item 14, wherein: The circular shift register is configured to store bits, each of which corresponds to a specific idle period in the N consecutive idle periods, and to output one bit at a time at the output of the circular shift register; the control circuit is configured to receive the mode indicator signal via its input; If the mode indicator signal has the first logic value, the multiplexer is instructed to select the first input; and if the mode indicator signal has the second logic value, the multiplexer is instructed to select the second input via the first output, and the cyclic shift register is instructed to shift the bits in the cyclic shift register via the second output.

16. The system according to request item 12 also includes: One driver; and a clock-gated circuit coupled between the output of the signal path and an input of the driver, wherein the controller is configured to degrate the clock-gated circuit if the mode indicator has the first logic value, and to grapple the clock-gated circuit if the mode indicator has the second logic value.

17. The system according to request item 16, wherein the first logical value indicates that the system is in an active mode and the second logical value indicates that the system is in an idle mode.

18. A system for aging control, comprising: A latch circuit having a signal input, a clock input, a set input, a reset input, and an output, wherein the latch circuit is configured to latch a logic value at a clock input on an edge of a clock signal input to the clock input when the set input and the reset input are de-established, and to output the latched logic value at the output of the latch circuit; a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the latch circuit; and a controller coupled to the set input and the reset input of the latch circuit, wherein the controller has an indicator input and is configured to: receive a mode indicator signal at the indicator input; If the mode indicator signal has a first logic value, the setup input and the reset input are deactivated; and if the mode indicator signal has a second logic value, the setup input and the reset input are alternately activated during multiple consecutive idle periods.

19. The system according to request item 18, wherein the first logical value indicates that the system is in an active mode and the second logical value indicates that the system is in an idle mode.

20. The system according to claim 18, wherein the signal input of the latch circuit is configured to receive a data signal, a command signal, or an address signal.

21. The system according to request item 18, wherein the signal path includes a delay circuit.

22. The system according to claim 21, wherein the delay circuit includes a delay buffer coupled in series.

23. The system according to claim 18, wherein the continuous idle period includes odd idle periods and even idle periods, and the controller is configured to: establish the setting input during each of the odd idle periods; and establish the reset input during each of the even idle periods.

24. The system according to claim 18, wherein the continuous idle period includes odd idle periods and even idle periods, and the controller is configured to: establish the reset input during each of the odd idle periods; and establish the setting input during each of the even idle periods.

25. The system pursuant to request item 18 also includes: One solder pad; and a receiver having an input and an output, wherein the input of the receiver is coupled to the pad and the output of the receiver is coupled to the signal input of the latch circuit.

26. The system pursuant to request item 18 also includes: One solder pad; and a driver having an input and an output, wherein the input of the driver is coupled to the output of the signal path, and the output of the driver is coupled to the pad.

27. The system according to claim 18, wherein the latch circuit is configured to output a logic 1 at the output of the latch circuit when the controller establishes the setting input, and to output a logic 0 at the output of the latch circuit when the controller establishes the reset input.

28. A system for aging control, comprising: A latch circuit having a signal input, a clock input, a set input, a reset input, and an output, wherein the latch circuit is configured to latch a logic value at a clock input on an edge of a clock signal input to the clock input when the set input and the reset input are de-established, and to output the latched logic value at the output of the latch circuit; a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the latch circuit; and a controller coupled to the set input and the reset input of the latch circuit, wherein the controller has an indicator input and is configured to: receive a mode indicator signal at the indicator input; If the mode indicator signal has a first logic value, the setup input and the reset input are cancelled; and if the mode indicator signal has a second logic value, the setup input is established during k idle periods out of N consecutive idle periods, and the reset input is established during Nk idle periods out of N consecutive idle periods, where k is an integer equal to or greater than 1, and N is an integer greater than k.

29. The system according to claim 28, wherein the controller is configured to store a bit sequence in a register, each bit in the bit sequence corresponding to a corresponding idle period in N consecutive idle periods in an idle mode, and wherein for each of the N consecutive idle periods, the controller is configured to: establish the setting input during the idle period if the corresponding bit in the bit sequence has a first bit value; and establish the reset input during the idle period if the corresponding bit in the bit sequence has a second bit value.

30. The system according to claim 28, wherein the latch circuit is configured to output a logic 1 at the output of the latch circuit when the controller establishes the setting input, and to output a logic 0 at the output of the latch circuit when the controller establishes the reset input.

31. A method for aging control in a system including a multiplexer and a signal path coupled to an output of the multiplexer, comprising the steps of: in an active mode, instructing the multiplexer to select a first input of the multiplexer; and inputting a clock signal to the first input of the multiplexer; and in an idle mode, instructing the multiplexer to select a second input of the multiplexer; inputting a control signal to the second input of the multiplexer; and alternately setting the control signal to a high level and a low level during a plurality of consecutive idle periods.

32. The method according to claim 31 also includes the following steps: inputting a data signal, a clock signal, a control signal or an address signal to the first input of the multiplexer in the active mode.

33. The method of claim 31, wherein the signal path includes a delay circuit.

34. The method of claim 33, wherein the delay circuit includes a delay buffer coupled in series.

35. The method of claim 31, wherein the continuous idle period includes odd-numbered idle periods and even-numbered idle periods, and alternately setting the control signal to a high level and a low level includes: During each of these odd-numbered idle periods, the control signal is set to a low level; And during each of the even-numbered idle periods, the control signal is set to a high level.

36. The method of claim 31, wherein the continuous idle period includes odd-numbered idle periods and even-numbered idle periods, and alternately setting the control signal to a high level and a low level includes: During each of these odd-numbered idle periods, the control signal is set to a high level; And during each of the even-numbered idle periods, the control signal is set to a low level.

37. A method for aging control in a system including a multiplexer and a signal path coupled to an output of the multiplexer, comprising the steps of: in an active mode, instructing the multiplexer to select a first input of the multiplexer; and inputting a clock signal to the first input of the multiplexer; and in an idle mode, instructing the multiplexer to select a second input of the multiplexer; inputting a control signal to the second input of the multiplexer; setting the control signal to a high level for k idle periods out of N consecutive idle periods; and setting the control signal to a low level for Nk idle periods out of N consecutive idle periods; wherein k is an integer equal to or greater than 1, and N is an integer greater than k.

38. The method according to claim 37 also includes the steps of: storing a bit sequence in a temporary register, each bit in the bit sequence corresponding to a corresponding idle period in the N consecutive idle periods of the idle mode, and wherein: Setting the control signal to a high level during k idle periods out of N consecutive idle periods includes: for each of the N consecutive idle periods, if the corresponding bit in the bit sequence has a first bit value, then the control signal is set to a high level during that idle period; and setting the control signal to a low level during Nk idle periods out of N consecutive idle periods includes: for each of the N consecutive idle periods, if the corresponding bit in the bit sequence has a second bit value, then the control signal is set to a low level during that idle period.

39. A system for aging control, comprising: A multiplexer having a first input, a second input, a selection input, and an output; a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; a latch circuit having a signal input, a clock input, and an output, wherein the signal input is coupled to the output of the signal path, the clock input of the latch circuit being configured to receive a clock signal, and the latch circuit being configured to latch a logic value at the signal input on an edge of the clock signal, and to output the latched logic value at the output of the latch circuit; and a controller coupled to the second input of the multiplexer and the selection input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to: receive a mode indicator signal at the indicator input; If the mode indicator signal has a first logic value, it instructs the multiplexer to select the first input of the multiplexer; and if the mode indicator signal has a second logic value, it instructs the multiplexer to select the second input of the multiplexer, outputs a control signal to the second input of the multiplexer, and alternately sets the control signal to a high level and a low level during multiple consecutive idle periods.

40. The system according to request item 39, wherein the first input of the multiplexer is configured to receive a data signal, a command signal, or an address signal.

41. A system for aging control, comprising: A multiplexer having a first input, a second input, a selection input, and an output; a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; a latch circuit having a signal input, a clock input, and an output, wherein the signal input is coupled to the output of the signal path, the clock input of the latch circuit being configured to receive a clock signal, and the latch circuit being configured to latch a logic value at the signal input on an edge of the clock signal, and to output the latched logic value at the output of the latch circuit; and a controller coupled to the second input of the multiplexer and the selection input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to: receive a mode indicator signal at the indicator input; If the mode indicator signal has a first logic value, it instructs the multiplexer to select the first input of the multiplexer; and if the mode indicator signal has a second logic value, it instructs the multiplexer to select the second input of the multiplexer, outputs a control signal to the second input of the multiplexer, sets the control signal to a high level for k idle periods out of N consecutive idle periods, and sets the control signal to a low level for Nk idle periods out of N consecutive idle periods, where k is an integer equal to or greater than 1, and N is an integer greater than k.

42. The system according to request 41, wherein the first input of the multiplexer is configured to receive a data signal, a command signal, or an address signal.

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