Hybrid metallic structures in stacked semiconductor devices and associated systems and methods

Abstract

This document discloses a stacked semiconductor device with a hybrid metal structure and related systems and methods. The stacked semiconductor device may include a first semiconductor die and a second semiconductor die. The first semiconductor die may include a top surface, a first bonding site on the top surface, and a second bonding site on the first surface spaced apart from the first bonding site. The second semiconductor die may include a lower surface facing the top surface of the first semiconductor die, a third bonding site on the lower surface, and a fourth bonding site on the lower surface. The third bonding site includes a conductive structure bonded to the first bonding site by a metal-to-metal connector. The fourth bonding site on the lower surface includes a solder ball bonded to the second bonding site.

Description

Technical Field

[0001] This invention generally relates to systems and methods for use in stacked semiconductor devices. Specifically, the invention relates to stacked semiconductor devices having hybrid metal structure bonding grains. Prior Technology

[0002] Microelectronic devices, such as memory devices, microprocessors, and other electronic devices, typically include one or more semiconductor chips mounted on a substrate and encased in a protective cover. Semiconductor chips include functional features such as memory cells, processor circuitry, and interconnect circuitry systems. Semiconductor chip manufacturers face increasing pressure to reduce the volume occupied by semiconductor chips and increase the capacity and / or speed of the resulting semiconductor assembly. To meet these demands, semiconductor chip manufacturers typically stack multiple semiconductor chips vertically to increase the capacity or performance of the microelectronic device within a limited area on the circuit board or other component to which the semiconductor chip and / or assembly is mounted.

[0003] Furthermore, semiconductor die manufacturers have continuously reduced the thickness of bonding wires to decrease the overall height of semiconductor die stacks and / or reduced the pitch between bonding features to decrease the longitudinal area occupied by the die stack. However, reductions can cause bonding problems between dies. For example, conventional solder joints between semiconductor die stacks typically have extruded portions. As height requirements shrink, the dies are compressed together, resulting in more extrusion that can create thermal and / or electrical short circuits between bonding features. Reducing the pitch between bonding features can also cause extruded portions to create short circuits between bonding features. Simple Explanation of the Diagram

[0004] Figure 1 is a cross-sectional view of a stacked semiconductor device having a hybrid metal bonding structure between the grains according to some embodiments of the present invention.

[0005] Figures 2A to 2J illustrate procedures for generating semiconductor dies having a hybrid metal bonding structure for use in stacked semiconductor devices, according to some embodiments of the present invention.

[0006] Figures 3A to 3H illustrate a procedure according to some embodiments of the present invention for generating semiconductor dies having corresponding metal bonding structures for use in stacked semiconductor devices.

[0007] Figures 4A to 4D illustrate procedures for forming a stacked semiconductor device with a hybrid metal bonding structure according to some embodiments of the present invention.

[0008] Figures 5A and 5B illustrate procedures for leveling metal joint structures according to some embodiments of the present invention.

[0009] Figure 6 is a schematic diagram of a system including a semiconductor die assembly configured according to some embodiments of the present invention.

[0010] The drawings are not necessarily drawn to scale. Similarly, for the purpose of illustrating some embodiments of the invention, some components and / or operations may be divided into different blocks or combined into a single block. Furthermore, while the invention is open to various modifications and alternatives, specific embodiments have been shown in the drawings by way of example and are described in detail below. Implementation

[0011] [Overview] []

[0012] This document discloses a stacked semiconductor device with a hybrid metal structure, and associated systems and methods. The stacked semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor die has a top surface and a bottom surface opposite the top surface. One or more first bonding sites are positioned on the top surface. One or more second bonding sites are positioned on the top surface and spaced apart from the first bonding sites. The second semiconductor die includes a lower surface facing the top surface of the first semiconductor die. One or more third bonding sites are positioned on the lower surface corresponding to the first bonding sites. One or more fourth bonding sites are positioned on the lower surface corresponding to the second bonding sites. The third bonding sites include conductive structures bonded to the first bonding sites by metal-to-metal bonding elements. The fourth bonding sites include solder structures (e.g., solder balls, solder pillars, etc.) bonded to the second bonding sites (e.g., using conventional solder bonding techniques). That is, stacked semiconductor devices have a hybrid bonding scheme that includes one or more metal-to-metal connections (e.g., metal-to-metal headers, sometimes referred to herein as "solderless" connections) and one or more solder connections (e.g., solder headers) between bonding sites on the stacked semiconductor die. The hybrid bonding scheme can take advantage of the benefits of solder bonding (e.g., self-alignment, cost, etc.) while minimizing the disadvantages of solder bonding (e.g., short-circuit risk between bonding sites). Furthermore, the hybrid bonding scheme can take advantage of the benefits of metal-to-metal connections (high-quality connections, low short-circuit risk) while addressing the limitations of metal-to-metal connections (e.g., alignment).

[0013] In some embodiments, metal-to-metal bonding forms an electrically charged connection between semiconductor dies, while solder bonding forms a thermal connection between thermal structures within the semiconductor die. In some embodiments, each of the first to fourth bonding sites typically corresponds to a feature in the semiconductor die (e.g., through-substrate vias, redistribution layers, thermal features, and / or any other suitable element). In some embodiments, the first and second bonding sites have substantially similar structures. In some such embodiments, the first and second bonding sites are formed in the same manufacturing process. For example, the first and second bonding sites may be formed using the same copper deposition process. Furthermore, in some embodiments, the metal-to-metal bonding between the first and third bonding sites is a copper-copper bonding.

[0014] For ease of reference, the stacked semiconductor device and its components are sometimes described herein with reference to top and bottom, upper and lower, upward and downward and / or horizontal planes, xy planes, vertical or z-directions relative to the spatial orientation of the embodiments shown in the figures. However, it should be understood that the stacked semiconductor device and its components may be moved to and used in different spatial orientations without altering the structure and / or function of the disclosed embodiments of the invention. [Description of the attached image] []

[0015] Figure 1 is a cross-sectional view of a stacked semiconductor device 100 ("device 100") having a mixed metal structure between semiconductor dies according to some embodiments of the present invention. In the illustrated embodiment, device 100 includes a packaging substrate 102 having a first surface 104 (e.g., an upper surface or die stack surface) and a second surface 106 (e.g., a lower surface) opposite to the first surface 104. Semiconductor dies 110 ("dies 110", individually referred to as first dies 110a to fourth dies 110d) are stacked on the first surface 104 of the packaging substrate 102, and a molding compound is disposed between each of the dies 110 and between the fourth die 110d (e.g., the bottommost die) and the packaging substrate 102.

[0016] As illustrated with reference to a first die 110a (e.g., the uppermost die), each of the dies 110 has a first surface 112 (e.g., an upper surface or top surface) and a second surface 114 (e.g., a lower surface or bottom surface). Each of the dies 110 may include a main semiconductor substrate 116 insulated from a dielectric substrate 118 at the first surface 112 and the second surface 114. The first die 110a includes a first array of bonding sites 120a carried by the first surface 112, an array of through-substrate vias 130 ("TSV 130") extending at least partially through the first die 110a, and a second array of bonding sites 120b carried by the second surface 114. In the illustrated embodiment, TSV 130 extends completely through the first grain 110a; each individual bonding site in the first array of bonding sites 120a is directly coupled to an individual TSV 130; and each individual bonding site in the second array of bonding sites 120b is directly coupled to an individual TSV 130. In various other embodiments, one or more of the TSV 130 may extend only partially through the first grain 110a, one or more bonding sites in the first array of bonding sites 120a may be coupled to another structure on the first surface 112 (e.g., coupled to a trace in a redistribution layer, thermal element, or other suitable structure), and / or one or more bonding sites in the second array of bonding sites 120b may be coupled to another structure on the second surface 114.

[0017] As further illustrated in Figure 1, the first array of bonding sites 120a includes one or more first bonding sites 122 (two shown) and one or more second bonding sites 124 (two shown) spaced apart from the first bonding sites 122. In the illustrated embodiment, the structures of the first bonding sites 122 and the second bonding sites 124 are generally similar. For example, as illustrated, the first bonding sites 122 and the second bonding sites 124 may each have a bonding structure including a conductive pad 121 bonded to the first TSV 132 and the second TSV 134 at a first surface 112, a metal pad 126 supported by the conductive pad 121, and a bonding film 128 supported by the metal pad 126.

[0018] In various embodiments, conductive pad 121 may be formed of a suitable conductive metal, such as copper, gold, silver, aluminum, or any other suitable conductive material. Similarly, in various embodiments, metal pad 126 may be formed of a suitable conductive metal, such as copper, gold, silver, aluminum, or any other suitable conductive material. Similarly, in various embodiments, bonding film 128 may be formed of a suitable conductive metal, such as copper, gold, silver, aluminum, or any other suitable conductive material. In various embodiments, conductive pad 121, metal pad 126, and bonding film 128 may be formed of the same conductive material and / or different conductive materials. For example, in some embodiments, conductive pad 121 and metal pad 126 are formed of copper, while bonding film 128 is formed of gold. The copper construction of conductive pad 121 and metal pad 126 can help reduce manufacturing costs, while the gold construction of bonding film 128 can help improve the bonding capability of the surface of the first bonding site 122.

[0019] The second array of bonding sites 120b includes one or more first bonding sites 142 (two shown) and one or more second bonding sites 144 (two shown) spaced apart from the first bonding sites 142. In the illustrated embodiment, the structure of the first bonding site 142 is substantially different from the structure of the second bonding site 144. As illustrated, the structure of the first bonding site 142 is substantially similar to the structure of the first bonding site 122 discussed above. For example, the first bonding site 142 includes a conductive pad 141 bonded to the first TSV 132 at the second surface 114, a metal pad 146 supported by the conductive pad 141, and a bonding film 148 supported by the metal pad 146. Also as discussed above, in various embodiments, the conductive pad 141, the metal pad 146, and / or the bonding film 148 may be formed of a suitable conductive metal, such as copper, gold, silver, aluminum, or any other suitable conductive material. For example, in some embodiments, conductive pad 141 and metal pad 146 are formed of copper, while bonding film 148 is formed of gold.

[0020] In some embodiments, each of the metal pads 126, 146 is formed of a sufficiently refined metallic material to allow the metal pads 126, 146 to be directly bonded to each other. For example, in some embodiments, each of the metal pads 126, 146 is formed of copper having a relatively defect-free (or defect-free) bonding surface. In such embodiments, the bonding films 128, 148 may be omitted, and the copper in the metal pads 126, 146 may be directly bonded in the form of metal-to-metal joints.

[0021] However, the structure of the second bonding site 144 is substantially different from that of the second bonding site 124. In the illustrated embodiment, the second bonding site 144 includes a conductive pad 141 bonded to the second TSV 134, a metal pad 156 supported by the conductive pad 141, and a solder structure 158 supported by the metal pad 156. The conductive pad 141 and / or the metal pad 156 may be formed of a suitable conductive metal, such as copper, gold, silver, aluminum, or any other suitable conductive material. The solder structure may be a solder ball, a solder material pillar, or any other suitable structure.

[0022] As further illustrated in Figure 1, each of the second grains 110b to the fourth grain 110c includes a first array of bonding sites 120a and a second array of bonding sites 120b. At each bonding interface in the device 100, the first array of bonding sites 120a of the relatively lower grain is bonded to the second array of bonding sites 120b of the relatively higher grain. For example, as illustrated with respect to the first grain 110a and the second grain 110b, the first array of bonding sites 120a on the second grain 110b is bonded to the second array of bonding sites 120b at the first grain 110a. In detail, the first bonding site 122 on the second die 110b is bonded to the first bonding site 142 on the first die 110a by a metal-to-metal bonding member between bonding films 128 and 148, and the second bonding site 124 on the second die 110b is bonded to the second bonding site 144 on the first die 110a by solder bonding between bonding film 128 and solder structure 158.

[0023] During the bonding process, the solder bonding process between the second bonding sites 124, 144 helps align the first die 110a and the second die 110b (e.g., through a solder self-alignment process). However, the bonding process extrudes the solder structure 158, which drifts outward toward the other bonding sites in an xy plane. If every bonding in the device 100 is a solder bonding, the distance between the bonding sites must be at least twice the drift distance to avoid short circuits between the bonding sites. When the height of a device of the type illustrated in FIG1 is required to shrink, the dies 110 in the stack are compressed more tightly together, which can increase the average drift distance of the solder structure 158. In addition, it may be necessary to reduce the distance between bonding sites (e.g., reduce the pitch) to reduce the xy occupancy area of ​​the device 100 and / or provide additional communication lines between the dies 110. Due to the reduction in height and pitch, the solder extruded between the bonding sites can form short circuits between the bonding sites, thereby impairing the performance of the device 100. The metal-to-metal joint between the first engagement sites 122 and 142 does not have the same extrusion problem in forming a short circuit between the engagement sites, and the metal-to-metal joint can provide a high-quality connection between the engagement sites. However, the metal-to-metal joint is not suitable for engagement sites with a pitch greater than 5 micrometers (μm), for example, due to the higher cost of aligning the engagement sites.

[0024] The hybrid configuration of the first bonding site 142 and the second bonding site 144, and the hybrid bonding scheme in the device 100, reduces the likelihood of forming a bridge between the bonding sites while maintaining the many benefits of solder bonding. For example, as discussed in more detail below with reference to Figures 4A to 4D, the second bonding sites 124, 144 can be bonded first to align the first die 110a and the second die 110b, and then a metal-to-metal bond can be formed between the first bonding sites 122, 142. Furthermore, the hybrid bonding scheme can take advantage of the benefits of the metal-to-metal bond between the first bonding sites 122, 142. For example, in some embodiments, the first TSV 132 is an electrical communication channel (e.g., a charged TSV) between the dies 110, while the second TSV 134 forms a thermal communication channel (e.g., a heat dissipation path) between the dies 110. The metal-to-metal bond helps ensure a high-quality electrical connection between the dies 110, while the solder bonding helps ensure accurate alignment of the dies 110.

[0025] The hybrid bonding scheme in device 100 can be particularly advantageous when the column pitch and / or bond line thickness are small enough that pure solder bonding schemes begin to form too many short circuits. In various embodiments, for example, a hybrid metal bonding structure can be used when the column pitch is greater than about 3 μm, between about 60 μm and about 4 μm, or between about 40 μm and about 5 μm. In some embodiments, a hybrid metal bonding structure can be used when the bond line thickness between the grains 110 is between about 1 μm and 30 μm, between about 2 μm and about 25 μm, between about 5 μm and about 20 μm, or between about 10 μm and about 20 μm.

[0026] Figures 2A to 2J illustrate procedures for generating bonding sites on a semiconductor die 110 according to some embodiments of the present invention. The procedures described below with respect to Figures 2A to 2J can, for example, be used to generate a hybrid conductive structure in a second array of bonding sites 120b discussed above with respect to Figure 1. Furthermore, the procedures described below can be started after the dielectric substrate 118 (Figure 1) has been deposited on the second surface 114 and the conductive layer 121' (e.g., a precursor to the conductive pad 121) has been deposited on the dielectric substrate 118.

[0027] Figure 2A illustrates a die 110 after photoresist 220 has been deposited on and patterned onto the second surface 114 of the die 110. As illustrated, patterning the photoresist 220 can form vias 222 in the photoresist 220 that expose a conductive layer 121' above one or more TSVs 130 in the die 110. In some embodiments, the vias 222 expose TSVs 130 corresponding to electrically charged communication channels passing through the die 110.

[0028] Figure 2B illustrates the grain 110 after metal plating of one or more vias 222 to form one or more examples of metal pads 146. As illustrated in Figure 2B, each of the vias 222 can be filled to a level at or near the upper surface 221 of the photoresist material 220 by the metal plating process. As further illustrated in Figure 2B, the metal pads 146 can have dissimilar heights after the metal plating process.

[0029] Figure 2C illustrates the grains 110 after material has been removed from the upper surface 147 of each of the metal pads 146. As discussed in more detail below with respect to Figures 5A and 5B, the removal process ensures that the metal pads 146 have a generally uniform height and / or that the upper surface 147 is relatively free of defects.

[0030] Figure 2D illustrates the grain 110 after a metal plating process is performed on the upper surface 147 of the metal pad 146 to deposit the bonding film 148. In some embodiments, the bonding film 148 may protect the metal pad 146 during further processing of the grain 110, thereby preventing impurities from being reintroduced into the upper surface 147. In some embodiments, the bonding film 148 may be a conductive metal selected at least in part based on its ability to form the metal-to-metal bonding discussed above with respect to Figure 1. For example, in some embodiments, the bonding film 148 is a gold layer.

[0031] As discussed above, in some embodiments, the bonding film 148 is omitted. In such embodiments, the process for generating the first array of bonding sites may omit the second metal plating process of FIG2D. For example, in some embodiments, the metal pad 146 may have a sufficiently uniform upper surface 147 and / or be formed of a suitable metal for forming metal-to-metal joints to omit the second deposition process.

[0032] Furthermore, in some embodiments, the procedure for generating the first array of bonding sites may omit the removal process discussed above with respect to FIG2C. For example, in some embodiments, the deposition process discussed above with respect to FIG2B may produce metal pads 146 with heights within acceptable tolerances, making the removal process unnecessary. In another instance, the second deposition process of FIG2D may take into account differences in height.

[0033] Figure 2E illustrates the grain 110 after the bonding film 148 is deposited onto the metal pad 146 to complete the formation of the conductive structure at the first bonding site 142. Once the conductive structure is complete, the photoresist material 220 can be peeled off from the grain 110.

[0034] Figure 2F illustrates the grain 110 after the second photoresist material 230 has been deposited and patterned on the second surface 114 of the grain 110. As illustrated, the second photoresist material 230 is patterned to form vias 234 that expose the conductive layer 121' above one or more TSVs 130 in the grain 110. In some embodiments, the vias 234 in the photoresist material expose TSVs 130 corresponding to thermal channels passing through the grain 110.

[0035] Figure 2G illustrates the grain 110 after the metal and solder plating process of sequentially depositing metal pads 156 and solder structures 158. As shown, the resulting solder pads may have different heights, but each has a rectangular structure bonded to the metal pad 156.

[0036] Figure 2H illustrates the die 110 after the second photoresist material 230 has been stripped from the die 110. Figure 2I illustrates the die 110 after etching the conductive layer 121' to expose the second surface 114 of the die 110 and isolate the newly formed conductive structure. That is, the stripping process removes material from the conductive layer 121' to isolate the conductive pad 121 of the first bonding site 142 and the second bonding site 144.

[0037] Figure 2J illustrates the die 110 after a solder reflow process that reshapes the solder structure 158. In some embodiments, the solder reflow process can improve the bonding between the metal pad 156 and the solder structure 158. In some embodiments, the solder reflow process can improve the uniformity of the height of the solder structure 158 on the die 110.

[0038] Figures 3A to 3H illustrate procedures for generating a generally similar array of bonding sites on a semiconductor die 110 according to some embodiments of the invention. The procedures described below with respect to Figures 3A to 3H can, for example, be used to generate a first array of bonding sites 120a discussed above with respect to Figure 1. In the illustrated embodiments, the procedures of Figures 3A to 3H occur after the procedures discussed above with respect to Figures 2A to 2J. In other embodiments, the procedures of Figures 3A to 3H occur before forming the hybrid conductive structure of the second array of bonding sites 120b.

[0039] Referring to FIG3A, the process can be initiated by attaching the die 110 to a carrier structure 302, such as a carrier wafer. In some embodiments, the carrier wafer includes a protective material 304 (e.g., a molding material) of the same height as the conductive structures in the second array of bonding sites 120b. Once mounted, the untreated first surface 112' of the die 110 can be treated to expose the TSV 130 within the die 110.

[0040] Figure 3B illustrates the die 110 after a bulk removal and / or thinning process on the first surface 112'', which is performed together with the first surface 112'' at an elevation above the TSV 130. In various embodiments, the bulk thinning process may include a polishing process and / or a chemical mechanical planarization (CMP) process to quickly and / or efficiently remove semiconductor substrate 116 material from the first surface 112''.

[0041] Figure 3C illustrates the die 110 after the second removal and / or thinning process, thereby creating a first surface 112 at an elevation parallel to or just below the TSVs 130. In some embodiments, the second removal process is a dry etching process to carefully remove the semiconductor substrate 116 material while minimizing damage to the TSVs 130 and / or removal from the TSVs.

[0042] Figure 3D illustrates a grain 110 after a dielectric layer 118 (and / or passivation layer) has been deposited on the first surface 112 of the grain 110 by a chemical vapor deposition process. As shown in Figure 3D, the deposition process can produce the most recently exposed end of the dielectric layer 118, TSV 130.

[0043] Figure 3E illustrates the die 110 after a selective removal process of the TSV 130 in the re-exposed die 110 and a deposition process of the conductive layer 121'. In various embodiments, the selective removal process may include a CMP process, a dry etching process, or other suitable removal process to create a completed dielectric layer 118 on the first surface 112 of the die 110.

[0044] As further illustrated in Figure 3E, once TSV 130 is exposed, the deposition process can proceed across the first surface 112 to deposit the conductive layer 121'. In some embodiments, the conductive layer 121' is a metal seed layer. Examples of metals used in the conductive layer 121' include copper, tin, aluminum, gold, silver, and / or any other suitable metal. In some embodiments, the conductive layer 121' is deposited using a physical vapor deposition (PVD) process.

[0045] Figure 3F illustrates a die 110 after the third photoresist material 320 has been deposited and patterned on the conductive layer 121'. As illustrated, the patterning creates vias 322 that expose the conductive layer 121' in locations substantially corresponding to the TSVs 130 in the die 110. In some embodiments, each of the vias 322 has a substantially similar size and shape. In other embodiments, the vias 322 may have different sizes and / or shapes. For example, a first group of vias corresponding to electrically conductive communication channels through the die 110 may have a size configured to engage with conductive structures on the first bonding site 142 (FIG. 1), while a second group of vias corresponding to thermal channels through the die 110 may have a size configured to engage with conductive structures on the second bonding site 144.

[0046] Figure 3G illustrates a die 110 after a plating process, in which a metal pad 126 and a bonding film 128 are deposited in a via 322, thereby forming a first bonding site 122 and a second bonding site 124. As illustrated in Figure 3G, the substantially equivalent width of the via 322 produces a substantially equivalent width between the first bonding site 122 and the second bonding site 124. As discussed above, the first bonding site 122 and the second bonding site 124 may be formed with different widths corresponding to the widths of the first bonding site 142 and the second bonding site 144 (Figure 1) on a second surface 114 of another semiconductor die and / or another suitable substrate. In the illustrated embodiment, the plating process also produces first bonding sites 122 and second bonding sites 124 with substantially uniform heights. In other embodiments, the plating process may be adjusted to produce first bonding sites 122 and second bonding sites 124 with different heights to further facilitate bonding with the corresponding bonding sites. Furthermore, the plating process can omit depositing the bonding film 128 in the metal pad 126 associated with the first bonding site 122.

[0047] Figure 3H illustrates the die 110 after the third photoresist material 320 is stripped from the die 110 to expose the conductive layer 121'. As further illustrated, the process then includes etching the exposed conductive layer 121' to isolate the conductive pad 121 (and thus isolate the first bonding site 122 and the second bonding site 124) and expose the first surface 112 of the die 110.

[0048] Although the procedure described above with respect to Figures 2A through 3H first generates a mixed conductive structure on the semiconductor die, it should be understood that in some embodiments, the die 110 is generated in a different order. For example, in some embodiments, a substantially similar conductive structure on the first surface 112 of the die 110 is generated before the mixed conductive structure on the second surface 114 of the die 110 is generated (e.g., by replacing the procedure described above with respect to Figures 2A through 2J with the procedure described above with respect to Figures 3F through 3H).

[0049] Figures 4A to 4D illustrate procedures for forming a stacked semiconductor device having a hybrid conductive structure according to some embodiments of the present invention. The described procedures may be performed, for example, after the hybrid structure has been formed on die 110 according to the embodiments discussed above with respect to Figures 2A to 3H.

[0050] Referring to Figure 4A, one or more dies 110 (shown as one) can be peeled off from the support structure 302. For example, the die 110 can be debonded from the substrate supporting the wafer and / or peeled off from the molding material. In some embodiments, the process at Figure 4A includes dicing a wafer (not shown) to monomerize the die 110 from the wafer.

[0051] Referring to FIG4B, one or more dies 110 (shown as two) may be stacked on top of the package substrate 102. In the illustrated embodiment, a second die 110b is stacked on the upper surface 104 of the package substrate 102, and a first die 110a is stacked on top of the second die 110b. In some embodiments, the dies may be stacked on various other substrates. For example, in some embodiments, one or more dies 110 may be stacked on a substrate die before or after the substrate die is attached to the package substrate 102 or any other suitable material. As illustrated in FIG4B, stacking the dies 110 may include substantially aligning a second array of bonding sites 120b on the first die 110a with a first array of bonding sites 120a on the second die 110b.

[0052] Figure 4C illustrates the apparatus 100 after a solder reflow process and / or a thermoforming process. The solder reflow process forms a bond between a second bonding site 144 on a first die 110a and a second bonding site 124 on a second die 110b. As illustrated, the solder reflow process includes compressing the die 110, resulting in the extrusion of solder structures 158 onto a horizontal plane. In some embodiments, the solder reflow process establishes a thermal channel 434 through the apparatus 100. In some embodiments, the solder reflow process further aligns the die 110, thereby correcting any minor errors in the alignment from the stack. Self-alignment occurs during the solder reflow process as the solder is adjusted to minimize the surface area of ​​the solder structures 158, and the position of the die 110 can be adjusted accordingly.

[0053] A thermocompression bonding process (sometimes referred to herein as an "annealing process") forms a metal-to-metal bond between a first bonding site 142 on a first die 110a and a first bonding site 122 on a second die 110b. The formed metal-to-metal bond may depend on bonding films 128, 148 deposited on the first bonding sites 122, 142. In some embodiments, the metal-to-metal bond includes a copper-copper bond, a silver-silver bond, a gold-gold bond, and / or any other suitable metal-to-metal bond. In some embodiments, the metal-to-metal bond establishes an electrical path 432 through means 100. In some embodiments, the thermocompression bonding process occurs simultaneously with a solder reflow process. For example, in some embodiments, the thermocompression bonding process introduces sufficient heat to reflow the solder structure 158. In some embodiments, the thermocompression bonding process may be performed after a solder reflow process to improve the alignment between the first bonding sites 122, 142 before forming the metal-to-metal bond.

[0054] Figure 4D illustrates the apparatus 100 after underfill material 160 is deposited between the first die 110a and the second die 110b, and between the second die 110b and the package substrate 102. The underfill material 160 may be a thermosetting epoxide or other suitable material. The underfill material 160 helps reduce thermal stress on the solder structure 158 caused by the mismatch in the coefficients of thermal expansion between the surface of the die 110 and the solder material. In some embodiments, the underfill material 160 increases the rigidity of the apparatus 100 to help reduce debonding between the dies 110. In some embodiments, the underfill material 160 is deposited via a capillary underfill process.

[0055] In some embodiments, one or more additional dies may be stacked on top of the first die 110a to increase the die count in device 100. For example, as illustrated in FIG1, two additional dies 110 may be stacked in device 100. In various embodiments, one, two, five, ten, or any suitable number of additional dies may be added to the stack. In some embodiments, one or more additional dies may be stacked in the initial stacking procedure discussed above with respect to FIG4B. In some embodiments, once the die stacking is complete, an encapsulation (not shown) may flow over device 100 to further insulate and protect the dies 110. In some embodiments, once the die stacking is complete, a cap (not shown) may be attached to encapsulation substrate 102 to further insulate and / or protect the dies 110.

[0056] Figures 5A and 5B illustrate a procedure for leveling bonding structures 522 on grain 110 according to some embodiments of the present invention. As discussed above, in some embodiments, a leveling process is used after the deposition process to improve the uniformity of the bonding structures 522. For example, the leveling process may be performed after the deposition of the metal plating process described above with respect to Figure 2B, thereby producing the first bonding site 122 discussed above with respect to Figure 2C.

[0057] Figure 5A illustrates three bonding structures 522a to 522c after a deposition process in a via of the second photoresist material 230. As illustrated, each of the bonding structures 522a to 522c may include impurity layers 523a to 523c on its respective upper surface. Furthermore, each of the bonding structures 522a to 522c may have a different height. For example, the first bonding structure 522a is higher than the second bonding structure 522b but shorter than the third bonding structure 522c. Without further processing, the different heights of the impurity layers 523a to 523c and the bonding structures 522a and 522c may hinder and / or prevent bonding of the bonding structures 522a to 522c to structures on another grain.

[0058] Figure 5B illustrates the bonding structure 522 after the leveling process. As illustrated, the impurity layer 523 has been removed from each of the bonding structures 522. Furthermore, additional material has been removed from the upper surface of each of the bonding structures 522 to create a generally uniform height across the bonding structure 522. That is, the leveling process includes a material removal process from the bonding structure 522. The removal process can be an electro- and / or chemical process (e.g., a Durendal process, immersing the bonding structure 522 in a chemical bath, or any other suitable process) to avoid mechanical stress on the relatively thin bonding structure. Additionally, the electro- and / or chemical process allows material removal from the bonding structure 522 while the bonding structure 522 is supported by the second photoresist material 230. As discussed above, once the leveling process is complete, the second photoresist material 230 can be peeled off from the die 110.

[0059] Figure 6 is a schematic diagram of a system comprising a semiconductor die assembly configured according to an embodiment of the present invention. Any of the semiconductor devices having the above-described features and / or generated by the processes described above with reference to Figures 1 to 5B can be incorporated into any of numerous larger and / or more complex systems, a representative example being the system 900 schematically shown in Figure 6. System 900 may include memory 990 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), power supply 992, driver 994, processor 996, and / or other subsystems or components 998. Semiconductor devices similar to those described above with reference to Figure 1, or semiconductor devices generated by the processes described above with reference to Figures 2A to 5B, may be included in any of the elements shown in Figure 6. For example, memory 990 may include a stacked semiconductor device having a hybrid metal bonding structure, such as the hybrid metal bonding structure described above with reference to Figure 1. The resulting system 900 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 900 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptops, internet devices, handheld devices (e.g., PDAs, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronic devices, network computers, and microcomputers. Additional representative examples of system 900 include lights, cameras, vehicles, etc. Regarding these and other examples, system 900 can be housed in a single unit or distributed across multiple interconnected units, for example, via a communication network. Therefore, components of system 900 may include local and / or remote memory storage devices and any of a wide variety of suitable computer-readable media. [in conclusion] []

[0060] Based on the foregoing, it should be understood that specific embodiments of the present technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the present technology. In the event of any conflict between any material incorporated herein by reference and the present invention, the present invention shall prevail. Where the context permits, singular or plural terms may also include plural or singular terms respectively. Furthermore, unless the word "or" is expressly limited to meaning only a single item that is exclusive to other items in a list of two or more items, the use of "or" in this list shall be understood to include: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. In addition, as used herein, the phrase "and / or" in "A and / or B" means only A, only B, and both A and B. Furthermore, the terms “comprising,” “including,” “having,” and “with” are used throughout the text to mean that at least one or more of the described features are included, without excluding any larger number of identical features and / or other features of additional types.

[0061] Based on the foregoing, it should also be understood that various modifications can be made without departing from the present invention or the technology thereof. For example, those skilled in the art will understand that the various components of the present technology can be further divided into sub-components, or the various components and functions of the present technology can be combined and integrated. Furthermore, certain aspects of the technology described in the context of a particular embodiment can be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the present invention have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily exhibit such advantages to fall within the scope of the present invention. Therefore, the present invention and related technologies may cover other embodiments not explicitly shown or described herein.

[0062] 100: Stacked semiconductor devices 102: Packaging substrate 104: First Surface 106: Second Surface 110: Semiconductor die 110a: First grain 110b: Second grain 110c: Third grain 110d: Fourth grain 112: First Surface 112': First surface 112'': First surface 114: Second Surface 116: Main semiconductor substrate 118: Dielectric substrate 121: Conductive pad 121': Conductive layer 122: First junctional site 124: Second junctional site 126: Metal Pad 128: Bonding membrane 130: Through-substrate via (TSV) 132: First Through-Substrate Via (TSV) 134: Second Through-Substrate Via (TSV) 141: Conductive pad 142: First junctional site 144: Second junctional site 146: Metal Pad 147: Upper surface 148: Bonding membrane 156: Metal Pad 158: Solder Structure 160: Bottom filling material 220: Photoresist material 221: Upper surface 222: Through hole 230: Second photoresist material 234: Through hole 302: Load-bearing structure 320: Third photoresist material 322: Through hole 432: Electrical Channel 434: Hot Channel 522: Joint structure 522a: Joint structure 522b: Joint structure 522c: Joint structure 900: System 990: Memory 992: Power Supply 994: Driver 996: Processor 998: Other subsystems or components

Claims

1. A stacked semiconductor device comprising: a first semiconductor die having a top surface and a bottom surface opposite to the top surface, the first semiconductor die including a first bonding site at the top surface and a second bonding site at the top surface spaced apart from the first bonding site; and a second semiconductor die having a lower surface facing the top surface of the first semiconductor die and an upper surface opposite to the lower surface, the second semiconductor die including: A third bonding site on the lower surface, wherein the third bonding site includes a solder-free interconnect structure forming a metal-metal bond between the third bonding site and the first bonding site; and a fourth bonding site on the lower surface, wherein the fourth bonding site includes a solder ball bonded to the second bonding site, wherein the second bonding site on the top surface corresponds to a second TSV extending from the top surface toward the bottom surface, and wherein the fourth bonding site on the lower surface corresponds to a fourth TSV extending from the lower surface toward the upper surface.

2. The stacked semiconductor device of claim 1, wherein the conductive structure of the third junction site is a first copper pillar, and wherein the first junction site includes a second copper pillar electrically connected to the first copper pillar via a copper-copper connector.

3. The stacked semiconductor device of claim 1, wherein the fourth bonding site includes a first conductive pad bonded to one of the solder balls, and wherein the second bonding site includes a second conductive pad bonded to the first conductive pad via the solder ball.

4. The stacked semiconductor device of claim 1, wherein the first bonding site at the top surface corresponds to a first through-substrate via (TSV) extending from the top surface toward the bottom surface, and wherein the third bonding site at the lower surface corresponds to a third TSV extending from the lower surface toward the upper surface.

5. The stacked semiconductor device of claim 4, wherein the first TSV and the third TSV form an electrical communication line between the first semiconductor die and the second semiconductor die.

6. The stacked semiconductor device of claim 1, wherein the distance between the first bonding site and the second bonding site is between 5 micrometers and 40 micrometers.

7. The stacked semiconductor device of claim 1, wherein the first semiconductor die and the second semiconductor die have a bonding line thickness between 5 micrometers and 20 micrometers.

8. A stacked semiconductor device comprising: a first semiconductor die having a first bonding surface, a plurality of first bonding sites in a first array on the first bonding surface, and a plurality of second bonding sites in a second array on the first bonding surface; a second semiconductor die having a second bonding surface facing the first bonding surface of the first semiconductor die, a plurality of third bonding sites in the first array on the second bonding surface, and a plurality of fourth bonding sites in the second array at the second bonding surface; a plurality of solder-free interconnect structures between the first semiconductor die and the second semiconductor die, wherein each of the solder-free interconnect structures forms an electrical connection between an individual bonding site in the plurality of first bonding sites and an individual bonding site in the plurality of third bonding sites; and a plurality of solder joints. joints), located between the first semiconductor die and the second semiconductor die, wherein each solder joint is coupled to one of the plurality of second bonding sites and one of the plurality of fourth bonding sites, wherein: The second semiconductor die has a third bonding surface opposite to the second bonding surface, a plurality of fifth bonding sites in the first array on the third bonding surface, and a plurality of sixth bonding sites in the second array on the third bonding surface, wherein: one or more of the plurality of fifth bonding sites are electrically connected to a corresponding bonding site among the plurality of third bonding sites by extending through an interconnect structure of the second semiconductor die, and one or more of the plurality of sixth bonding sites are thermally connected to a corresponding bonding site among the plurality of fourth bonding sites by extending through a thermal structure of the second semiconductor die.

9. The stacked semiconductor device of claim 8, wherein each solderless interconnect structure forms a metal-metal bond between the individual bond site of the plurality of first bond sites and the individual bond site of the plurality of third bond sites.

10. The stacked semiconductor device of claim 8, wherein the electrical connection between the plurality of first bonding sites and the plurality of third bonding sites establishes a plurality of electrical communication channels between the first semiconductor die and the second semiconductor die.

11. The stacked semiconductor device of claim 8, wherein each of the plurality of first bonding sites is bonded to one TSV in the first semiconductor die, and wherein each of the plurality of third bonding sites is bonded to one TSV in the second semiconductor die.

12. The stacked semiconductor device of claim 8, wherein each of the plurality of second bonding sites is bonded to a thermal structure in the first semiconductor die.

13. The stacked semiconductor device of claim 11, wherein the plurality of first bonding sites include a plurality of first bonding pads extending to a height, and wherein the plurality of second bonding sites include a plurality of second bonding pads extending to the height.

14. The stacked semiconductor device of claim 8, wherein the plurality of solder joints between the plurality of second bonding sites and the plurality of fourth bonding sites establish a plurality of thermal channels between the first semiconductor die and the second semiconductor die.

15. The stacked semiconductor device of claim 8, further comprising: a third semiconductor die having a fourth bonding surface facing the third bonding surface of the second semiconductor die, a plurality of seventh bonding sites in the first array on the fourth bonding surface, and a plurality of eighth bonding sites in the second array at the fourth bonding surface, wherein: Each of the plurality of seventh bonding sites includes a conductive structure directly bonded to one of the corresponding conductive structures of the plurality of fifth bonding sites, and each of the plurality of eighth bonding sites includes a solder structure bonded to one of the corresponding conductive structures of the plurality of sixth bonding sites.

16. A method for forming a stacked semiconductor device, comprising: forming a conductive pad at at least one first bonding site of a first semiconductor die; forming a solder structure at at least one second bonding site of the first semiconductor die adjacent to the at least one first bonding site; stacking the first semiconductor die on a second semiconductor die, the second semiconductor die having corresponding conductive pads individually corresponding to each of the at least one first bonding site and the at least one second bonding site; and bonding the at least one first bonding site and the at least one second bonding site to the corresponding conductive pads on the second semiconductor die, wherein the bonding includes: The solder structure is reflowed at at least one second bonding site to bond the at least one second bonding site to the corresponding conductive pads on the second semiconductor die; and the conductive pads are annealed to form a solderless interconnect structure providing a metal-to-metal connection between the at least one first bonding site on the first semiconductor die and the corresponding conductive pad on the second semiconductor die, wherein one of the at least one second bonding site corresponds to a second TSV extending through the first semiconductor die, and wherein one of the corresponding conductive pads on the second semiconductor die corresponding to the at least one second bonding site corresponds to a fourth TSV extending through the second semiconductor die.

17. The method of claim 16, wherein the at least one first bonding site of the first semiconductor die is at least two first bonding sites, and wherein forming the conductive pads on the at least two first bonding sites comprises: A photoresist material is disposed on a bonding surface of one of the first semiconductor die; the photoresist material is patterned to expose the at least two first bonding sites; a conductive material is deposited into the patterned photoresist material at a height exceeding the uniform height of one of the conductive pads; the conductive material is removed until each of the conductive pads is at the uniform height; and the photoresist material is peeled off from the first semiconductor die.

18. The method of claim 17, wherein the at least one second bonding site of the first semiconductor die is at least two second bonding sites, and wherein forming the solder structure on the at least two second bonding sites comprises: A second photoresist material is disposed on the bonding surface of the first semiconductor die, and conductive pads are disposed on the at least two first bonding sites; the second photoresist material is patterned to expose the at least two second bonding sites; solder material is deposited into the second patterned photoresist material; the second photoresist material is peeled off from the first semiconductor die; and the solder material is at least partially reflowed at the at least two second bonding sites.

19. The method of claim 16, wherein the conductive pad on the at least one first junction site of the first semiconductor die and the corresponding conductive pad on the second semiconductor die are both copper pads, and wherein the annealing forms a copper-copper joint between the copper pads.

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