Semiconductor package

Abstract

The present invention provides a semiconductor package comprising a first semiconductor wafer and a second semiconductor wafer bonded together, wherein the first semiconductor wafer comprises: a first semiconductor substrate; a first semiconductor element layer and a first wiring structure, sequentially stacked on a first surface of the first semiconductor substrate; a first connection pad and a first test pad, located on the first wiring structure; and a first front bonding pad connected to the first connection pad, wherein the second semiconductor wafer comprises: a second semiconductor substrate; a second semiconductor element layer and a second wiring structure, sequentially stacked on a third surface of the second semiconductor substrate; and a first back bonding pad bonded to the first front bonding pad, located on a fourth surface of the second semiconductor substrate, and wherein the first test pad is not electrically connected to the second semiconductor wafer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including semiconductor wafers stacked in a die-to-wafer (D2W) manner and a method of manufacturing the semiconductor package.

Background Art

[0002] With the rapid development of the electronics industry and various user requirements, electronic devices have gradually become smaller, lighter, and more functional. It is required that semiconductor packages used in such electronic devices not only have a compact size and light weight but also have versatility. For example, two or more types of semiconductor wafers can be incorporated into a single semiconductor package, so that the size of the semiconductor package can be significantly reduced, while the storage capacity and functionality of the semiconductor package can both be improved.

[0003] To increase the storage capacity of a semiconductor package, semiconductor wafers can be stacked in a Chip-on-Wafer (CoW) method or a die-to-wafer (D2W) method. The CoW method may refer to a method in which semiconductor wafers are stacked on a wafer (or another semiconductor wafer) via a connecting component (e.g., a bump or solder). The D2W method may refer to a method in which semiconductor wafers are stacked on a wafer (or another semiconductor wafer) via pad-to-pad bonding or bonding using an anisotropic conductive film (ACF).

Summary of the Invention

[0004] According to an embodiment of the present disclosure, there is provided a semiconductor package including a first semiconductor wafer and a second semiconductor wafer bonded together, wherein the first semiconductor wafer includes: a first semiconductor substrate having a first surface and a second surface opposite to each other; a first semiconductor element layer and a first wiring structure sequentially stacked on the first surface of the first semiconductor substrate; a first connection pad and a first test pad connected to the first wiring structure and located on the first wiring structure; and a first front-side bonding pad connected to the first connection pad, and the second semiconductor wafer includes: a second semiconductor substrate having a third surface and a fourth surface opposite to the third surface and facing the first surface; a second semiconductor element layer and a second wiring structure sequentially stacked on the third surface of the second semiconductor substrate; and a first back-side bonding pad bonded to the first front-side bonding pad and located on the fourth surface of the second semiconductor substrate, and the first test pad is not electrically connected to the second semiconductor wafer.

[0005] According to an embodiment of the present disclosure, a semiconductor package is provided, including: a semiconductor substrate having a first surface and a second surface opposite to each other; a semiconductor element layer and a wiring structure stacked on the first surface of the semiconductor substrate in sequence; a connection pad connected to the wiring structure and located on the top surface of the wiring structure; a test pad spaced apart from the connection pad and connected to the wiring structure, located on the top surface of the wiring structure; a first liner film and a second liner film stacked on the top surface of the wiring structure in sequence; a connection pad opening exposing the connection pad through the first liner film and the second liner film; a test pad opening exposing the test pad through the first liner film and not penetrating the second liner film; and a front-side bonding pad connected to the connection pad in the connection pad opening.

[0006] According to an embodiment of the present disclosure, a semiconductor package is provided, including: a base substrate; and a plurality of semiconductor wafers stacked on the base substrate in sequence, wherein each of the semiconductor wafers includes: a semiconductor substrate having a first surface facing the top surface of the base substrate and a second surface opposite to the first surface; a semiconductor element layer and a wiring structure stacked on the first surface of the semiconductor substrate in sequence; a connection pad and a test pad connected to the wiring structure and exposed from the wiring structure; a front-side bonding pad connected to the connection pad and not connected to the test pad; a back-side bonding pad located on the second surface of the semiconductor substrate; and a through hole connecting the wiring structure and the back-side bonding pad through the semiconductor substrate.

[0007] According to the foregoing and other embodiments of the present disclosure, a method for manufacturing a semiconductor package is provided, including: providing a first semiconductor substrate having a first surface and a second surface opposite to each other; sequentially forming a first semiconductor element layer and a first wiring structure on the first surface of the first semiconductor substrate; forming a first connection pad and a first test pad, the first connection pad and the first test pad being connected to the first wiring structure and located on the first wiring structure; forming a first liner film on the first wiring structure, the first connection pad, and the first test pad; forming a test pad opening exposing the first test pad through the first liner film; forming a second liner film on the first liner film; and forming a front-side bonding pad, the front-side bonding pad being connected to the first connection pad through the first liner film and the second liner film.

Embodiments

[0009] Some embodiments of the semiconductor package according to the present disclosure will be described hereinafter with reference to FIGS. 1 to 10.

[0010] FIG. 1 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIGS. 2A and 2B are enlarged cross-sectional views of region R1 of FIG. 1. FIGS. 3A and 3B are plan views showing the first connection pad and the first test pad of FIG. 1.

[0011] Referring to FIGS. 1 to 3B, a semiconductor package according to some embodiments of the present disclosure may include a first semiconductor wafer 100 and a second semiconductor wafer 200. Each of the first semiconductor wafer 100 and the second semiconductor wafer 200 may be an integrated circuit (IC) obtained by integrating hundreds to millions of semiconductor elements into a single wafer.

[0012] For example, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be application processors (APs), such as a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, or an application-specific IC (ASIC). In another example, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be volatile memories, such as a dynamic random-access memory (DRAM) or a static random-access memory (SRAM); or non-volatile memories, such as a flash memory, a phase-change random-access memory (RAM), a magnetoresistive random-access memory (SRAM), a ferroelectric random-access memory (SRAM), or a resistive random-access memory (SRAM). In some embodiments, the first semiconductor wafer 100 and the second semiconductor wafer 200 may form a multi-chip semiconductor package, such as a high-bandwidth memory (HBM).

[0013] The first semiconductor wafer 100 may include a first semiconductor substrate 110, a first via 115, a first semiconductor element layer 120, a first wiring structure 130, a first connection pad 142, a first test pad 144, a first passivation film 152, a first interlayer insulating film 154, a first liner film 162, a second interlayer insulating film 156, a second liner film 164, a first front-side bonding pad 172, a first back-side insulating film 190, and a first back-side bonding pad 195.

[0014] The first semiconductor substrate 110 may be, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the first semiconductor substrate 110 may be a silicon substrate or may include, for example, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0015] The first semiconductor substrate 110 may have a first surface 110a and a second surface 110b that face each other. The first surface 110a of the first semiconductor substrate 110 may be the active surface on which the first semiconductor element layer 120 is formed. In the following description, the first surface 110a of the first semiconductor substrate 110 may also be referred to as the front side of the first semiconductor substrate 110, and the second surface 110b of the first semiconductor substrate 110 may also be referred to as the back side of the first semiconductor substrate 110.

[0016] The first semiconductor element layer 120 may be formed on the first surface 110a of the first semiconductor substrate 110. The first semiconductor element layer 120 may include various fine electronic components, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., complementary metal-oxide-semiconductor (CMOS) transistors), large-scale integration (LSI) systems, flash memories, DRAMs, SRAMs, electrically erasable programmable read-only memories (EEPROMs), SRAMs, SRAMs, SRAMs, image sensors (e.g., CMOS imaging sensors), micro-electro-mechanical systems (MEMS), active components, and passive components.

[0017] The first wiring structure 130 may cover the first semiconductor element layer 120. The first wiring structure 130 may be electrically connected to the first semiconductor element layer 120. For example, the first wiring structure 130 may include a first inter-wiring insulating film 132 and a first wiring pattern 134 disposed in the first inter-wiring insulating film 132. The first wiring pattern 134 may form a multi-layer structure and may be electrically connected to the first semiconductor element layer 120. The layout of the first wiring pattern 134, the number of the first wiring patterns 134, and the number of the layers formed by the first wiring patterns 134 are merely illustrative and are not subject to specific limitations.

[0018] For example, the first wiring pattern 134 may include a conductive film and a barrier film disposed between the first inter-wiring insulating film 132 and the conductive film. The conductive film may include at least one of, for example, tungsten (W), aluminum (Al), and copper (Cu). The barrier film may include at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0019] The first through hole 115 may penetrate the first semiconductor substrate 110. The first through hole 115 may be electrically connected to the first wiring structure 130. For example, the first through hole 115 may be connected to the lowermost layer of the first wiring pattern 134 via the first semiconductor substrate 110 and the first semiconductor element layer 120. The first through hole 115 may include at least one of, for example, Cu, Cu alloy (such as, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, or CuW), W, W alloy, nickel (Ni), ruthenium (Ru), and cobalt (Co).

[0020] The first connection pad 142 and the first test pad 144 may be spaced apart from each other and may be formed on the first wiring structure 130. The first connection pad 142 and the first test pad 144 may be electrically connected to the first wiring structure 130. For example, a first wiring trench 142t exposing a portion of the uppermost layer of the first wiring pattern 134 may be formed in the first inter-wiring insulating film 132. At least a portion of the first connection pad 142 may be formed in the first inter-wiring insulating film 132 and may be connected to the first wiring pattern 134. For example, a second wiring trench 144t exposing another portion of the uppermost layer of the first wiring pattern 134 may be formed in the first inter-wiring insulating film 132. At least a portion of the first test pad 144 may be formed in the second wiring trench 144t and may be connected to the first wiring pattern 134.

[0021] The number and layout of the first connection pads 142 and the first test pads 144 are merely illustrative and not subject to specific limitations. For example, as shown in FIG. 3A, the first connection pads 142 may be arranged in a lattice form on the X-Y plane, such as in a two-dimensional matrix pattern along the X direction and the Y direction. A plurality of first test pads 144 may be disposed on both sides of each array of the first connection pads 142. For example, a plurality of first test pads 144 may be located at each of the two opposite ends of the matrix pattern of the first connection pads 142. In another example, as shown in FIG. 3B, four first test pads 144 may be arranged near the four corners of the first semiconductor wafer 100.

[0022] For example, as shown in FIG. 1, the first wiring pattern 134 connected to the first connection pad 142 and the first wiring pattern 134 connected to the first test pad 144 may not be connected to each other. In another example, the first wiring pattern 134 connected to the first connection pad 142 may be electrically connected to the first wiring pattern 134 connected to the first test pad 144.

[0023] The first connection pads 142 and the first test pads 144 may include at least one of, for example, W, Al, and Cu. For example, the first connection pads 142 and the first test pads 144 may include Al.

[0024] For example, as shown in FIG. 2A, the top surface of the first test pad 144 may include a groove 144h. The groove 144h of the first test pad 144 may be formed during the test process of the first semiconductor wafer 100. This will be described later with reference to FIG. 14.

[0025] As shown in FIGS. 1 and 2A, the first connection pads 142 and the first test pads 144 may protrude from the first wiring structure 130, such as above the first wiring structure. For example, the top surface of the first connection pad 142 and the top surface of the first test pad 144 may be formed to be higher than the first wiring structure 130, such as relative to the top surface of the first semiconductor element layer 120. Therefore, the first connection pads 142 and the first test pads 144 may be exposed from the first wiring structure 130.

[0026] Referring to FIG. 2A, the width W11 of the first connection pad 142 and the width W12 of the first test pad 144 can be, for example, about 100 micrometers. For example, the width W11 of the first connection pad 142 and the width W12 of the first test pad 144 can be from about 10 micrometers to about 70 micrometers. The width W11 of the first connection pad 142 can be greater than the width of the first wiring trench 142t, and the width W12 of the first test pad 144 can be greater than the width of the second wiring trench 144t. In some embodiments, the width W12 of the first test pad 144 can be greater than the width W11 of the first connection pad 142. As shown in FIG. 2A, each of the width W11 and the width W12 refers to, for example, the maximum width measured at the widest part between the opposite sidewalls of the corresponding one of the first connection pad 142 and the first test pad 144 along the uppermost surface of the first wiring structure 130.

[0027] The first passivation film 152 can be formed on the first wiring structure 130, the first connection pad 142, and the first test pad 144. For example, the first passivation film 152 can be conformally formed along the contours of the first wiring structure 130, the first connection pad 142, and the first test pad 144. The first passivation film 152 can protect the first connection pad 142 and the first test pad 144 from external impacts or moisture. The first passivation film 152 can include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0028] The first interlayer insulating film 154 can be formed on the first passivation film 152. The first interlayer insulating film 154 can cover the top surface of the first passivation film 152. In some embodiments, the first interlayer insulating film 154 can have a planarized top surface. For example, the top surface of the first interlayer insulating film 154 can extend parallel to the uppermost top surface of the first wiring structure 130. The first interlayer insulating film 154 can include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first interlayer insulating film 154 can include tetraethyl orthosilicate (TEOS).

[0029] The first liner film 162 can be formed on the first interlayer insulating film 154. The first liner film 162 can cover the top surface of the first interlayer insulating film 154. In some embodiments, the first liner film 162 can conformally extend along the planarized top surface of the first interlayer insulating film 154. The first liner film 162 can include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0030] In some embodiments, the first liner film 162 can include a material different from that of the first interlayer insulating film 154. For example, the first interlayer insulating film 154 can include a silicon oxide film, and the first liner film 162 can include a silicon nitride film.

[0031] The first passivation film 152, the first interlayer insulating film 154, and the first liner film 162 may expose the first test pad 144. For example, a test pad opening 174t may be formed to expose at least a portion of the top surface of the first test pad 144 through the first passivation film 152, the first interlayer insulating film 154, and the first liner film 162. As shown in FIGS. 3A and 3B, the test pad opening 174t (e.g., the elliptical dashed line) may overlap at least a portion of the first test pad 144 in the plan view (e.g., the shaded rectangle overlapping the dashed elliptical line).

[0032] The second interlayer insulating film 156 may be formed on the first liner film 162. The second interlayer insulating film 156 may cover the top surface of the first liner film 162. In some embodiments, the second interlayer insulating film 156 may have a planarized top surface. For example, the top surface of the second interlayer insulating film 156 may extend parallel to the uppermost top surface of the first wiring structure 130. The second interlayer insulating film 156 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. For example, the second interlayer insulating film 156 may include TEOS.

[0033] In some embodiments, a portion of the second interlayer insulating film 156 may be in contact with the first test pad 144 through the first passivation film 152, the first interlayer insulating film 154, and the first liner film 162. For example, as shown in FIGS. 2A and 2B, a portion of the second interlayer insulating film 156 may fill the test pad opening 174t.

[0034] The second liner film 164 may be formed on the second interlayer insulating film 156. The second liner film 164 may cover the top surface of the second interlayer insulating film 156. In some embodiments, the second liner film 164 may conformally extend along the planarized top surface of the second interlayer insulating film 156. The second liner film 164 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0035] In some embodiments, the second liner film 164 may include a material different from that of the second interlayer insulating film 156. For example, the second interlayer insulating film 156 may include a silicon oxide film, and the second liner film 164 may include a silicon nitride film.

[0036] In some embodiments, the first liner film 162 and the second liner film 164 may include different materials. For example, the first liner film 162 may include a SiN film, and the second liner film 164 may include a SiCN film.

[0037] The first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, and the second liner film 164 may expose the first connection pad 142. For example, a connection pad opening 172t may be formed to expose at least a portion of the top surface of the first connection pad 142 through the first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, and the second liner film 164. As shown in FIGS. 3A and 3B, the connection pad opening 172t (e.g., the solid curve) may overlap at least a portion of the first connection pad 142 in the plan view (e.g., the shaded rectangle overlapping the solid curve).

[0038] In some embodiments, different from the connection pad opening 172t, the test pad opening 174t may not penetrate the second interlayer insulating film 156 and the second liner film 164. That is, the test pad opening 174t may be formed in the first passivation film 152, the first interlayer insulating film 154, and the first liner film 162, but not in the second interlayer insulating film 156 and the second liner film 164.

[0039] The first front-side bonding pad 172 may be formed on the first connection pad 142. The first front-side bonding pad 172 may be connected to the first connection pad 142 through the first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, and the second liner film 164. For example, the first front-side bonding pad 172 may be formed in the connection pad opening 172t and may be connected to the first connection pad 142. The first front-side bonding pad 172 may be exposed from the second liner film 164. For example, the top surface of the first front-side bonding pad 172 may be disposed in the same plane as the top surface of the second liner film 164. For example, the top surfaces of the first front-side bonding pad 172 and the second liner film 164 may face the same direction and may be coplanar.

[0040] The first front-side bonding pad 172 may be connected to the first test pad 144. For example, as mentioned above, a portion of the second interlayer insulating film 156 may fill the test pad opening 174t.

[0041] The first front-side bonding pad 172 may include at least one of, for example, W, Al, and Cu. Preferably, the first front-side bonding pad 172 may include Cu.

[0042] For example, the width W21 of the first front-side bonding pad 172 can be about 10 micrometers or less than 10 micrometers, such as about 5 micrometers to about 10 micrometers. In some embodiments, the width W22 of the test pad opening 174t can be greater than the width W21 of the first front-side bonding pad 172. As shown in FIG. 2A, each of the width W21 and the width W22 refers to the maximum width measured at the widest part between the opposing sidewalls of the corresponding one of the first front-side bonding pad 172 and the test pad opening 174t.

[0043] For example, the height H11 of the first front-side bonding pad 172 can be about 5 micrometers or less than 5 micrometers, such as about 3 micrometers to about 5 micrometers. Since the first front-side bonding pad 172 penetrates the second interlayer insulating film 156 and the second liner film 164 other than the first liner film 162, the height H11 of the first front-side bonding pad 172 can be greater than the height H12 of the first dummy pad 174.

[0044] The first back-side insulating film 190 can be formed on the second surface 110b of the first semiconductor substrate 110. The first back-side insulating film 190 can cover the second surface 110b of the first semiconductor substrate 110. The first back-side insulating film 190 can include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the first back-side insulating film 190 can include a silicon oxide film.

[0045] The first back-side bonding pad 195 can be formed on the second surface 110b of the first semiconductor substrate 110. The first back-side bonding pad 195 can be exposed from (e.g., via) the first back-side insulating film 190. For example, the bottom surface of the first back-side bonding pad 195 can be disposed in the same plane as the bottom surface of the first back-side insulating film 190. For example, the first back-side bonding pad 195 can penetrate the entire thickness of the first back-side insulating film 190 to have the same thickness as the first back-side insulating film 190 and have a bottom surface coplanar with the bottom surface of the first back-side insulating film 190.

[0046] The first back-side bonding pad 195 can be electrically connected to the first through hole 115. For example, the first through hole 115 can be connected to (e.g., directly) the top surface of the first back-side bonding pad 195 via the first semiconductor substrate 110. The first back-side bonding pad 195 can be electrically connected to the first wiring structure 130 and / or the first semiconductor element layer 120 via the first through hole 115.

[0047] The first back-side bonding pad 195 can include at least one of, for example, W, Al, and Cu. For example, the first back-side bonding pad 195 can include Cu.

[0048] The second semiconductor wafer 200 may include a second semiconductor substrate 210, a second through hole 215, a second semiconductor element layer 220, a second wiring structure 230, a second connection pad 242, a second test pad 244, a second passivation film 252, a third interlayer insulating film 254, a third liner film 262, a fourth interlayer insulating film 256, a fourth liner film 264, a second front side bonding pad 272, a second back side insulating film 290, and a second back side bonding pad 295. The second semiconductor substrate 210, the second through hole 215, the second semiconductor element layer 220, the second wiring structure 230, the second connection pad 242, the second test pad 244, the second passivation film 252, the third interlayer insulating film 254, the third liner film 262, the fourth interlayer insulating film 256, the fourth liner film 264, the second front side bonding pad 272, the second back side insulating film 290, and the second back side bonding pad 295 may respectively correspond to the first semiconductor substrate 110, the first through hole 115, the first semiconductor element layer 120, the first wiring structure 130, the first connection pad 142, the first test pad 144, the first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, the second liner film 164, the first front side bonding pad 172, the first back side insulating film 190, and the first back side bonding pad 195

[0049] The first semiconductor wafer 100 and the second semiconductor wafer 200 may be bonded together by a die-to-wafer (D2W) method. For example, the first front side bonding pad 172 of the first semiconductor wafer 100 and the second back side bonding pad 295 of the second semiconductor wafer 200 may be bonded together. For example, the first front side bonding pad 172 and the second back side bonding pad 295 may be directly connected to each other through direct surface contact between their opposing surfaces. Accordingly, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be electrically connected. Specifically, the first semiconductor element layer 120 and / or the first wiring structure 130 of the first semiconductor wafer 100 may be electrically connected to the second semiconductor element layer 220 and / or the second wiring structure 230 of the second semiconductor wafer 200 through the first connection pad 142, the first front side bonding pad 172, the second back side bonding pad 295, and the second through hole 215.

[0050] For example, as shown in FIG. 2A, the width of the second back side bonding pad 295 (e.g., the maximum width along the surface contacting the first front side bonding pad 172) may be the same as the width W21 of the first front side bonding pad 172. In another example, the width of the second back side bonding pad 295 may be smaller than or larger than the width W21 of the first front side bonding pad 172.

[0051] The first test pad 144 of the first semiconductor wafer 100 may not be electrically connected to the second semiconductor wafer 200. For example, the first test pad 144 may be electrically isolated from the second semiconductor wafer 200. For example, as already mentioned above, a portion of the second interlayer insulating film 156 may be formed in the test pad opening 174t (e.g., completely filling the test pad opening 174t) and the second backside bonding pad 295 may not be connected to the first test pad 144.

[0052] In some embodiments, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be bonded via hybrid bonding. Hybrid bonding refers to a method of bonding metal and an insulating film (e.g., an oxide film) or metal and a polymer. For example, as shown in FIG. 2A, the first frontside bonding pad 172 may be attached to the second backside bonding pad 295, and the second liner film 164 may be attached to the second backside insulating film 290. For example, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be bonded via Cu-oxide hybrid bonding.

[0053] In other embodiments, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be bonded via metal bonding. For example, as shown in FIG. 2B, the first frontside bonding pad 172 may be attached to the second backside bonding pad 295, and the second liner film 164 may be spaced apart from the second backside insulating film 290. For example, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be bonded via Cu-Cu bonding.

[0054] As the demand for the compactness, light weight, and multifunctionality of semiconductor packages increases, stacking semiconductor wafers only via the chip-on-wafer (CoW) method may have limitations. For example, due to the limitation of smoothly releasing heat, it may be difficult to ensure appropriate thermal characteristics of the connection components (e.g., bumps or solders).

[0055] In contrast, according to an exemplary embodiment, the semiconductor wafers (e.g., the first semiconductor wafer 100 and the second semiconductor wafer 200) of a semiconductor package may be bonded together by the D2W method, thereby having improved thermal characteristics. For example, as already mentioned above, the first frontside bonding pad 172 of the first semiconductor wafer 100 and the second backside bonding pad 295 of the second semiconductor wafer 200 may be (e.g., directly) bonded together and may contain Cu. For example, each of the first frontside bonding pad 172 and the second backside bonding pad 295 may contain Cu and may be bonded to each other via Cu-Cu bonding, and the Cu-Cu bonding has lower heat resistance than the connection components (e.g., bumps or solders). Therefore, a semiconductor package having improved thermal characteristics can be provided.

[0056] In addition, a semiconductor package according to some embodiments of the present disclosure may include test pads (e.g., the first test pad 144) capable of providing a test function for a semiconductor wafer (e.g., the first semiconductor wafer 100). Therefore, a semiconductor package that can facilitate the test process can be provided.

[0057] FIG. 4 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIG. 5 is an enlarged cross-sectional view of region R2 of FIG. 4. FIG. 6 is a plan view showing the first connection pad and the first test pad of FIG. 4. For convenience, descriptions of elements or features that have been described above with reference to FIGS. 1 to 3B will be omitted or simplified.

[0058] Referring to FIGS. 4 to 6, the first semiconductor wafer 100 may further include a first dummy pad 174, and the second semiconductor wafer 200 may further include a second dummy pad 274. The first dummy pad 174 may be formed on the first test pad 144, and the second dummy pad 274 may be formed on the second test pad 244. The structure of the second dummy pad 274 may be the same as the structure of the first dummy pad 174.

[0059] Specifically, the first dummy pad 174 may be formed on the first test pad 144 and may be connected to the first test pad 144 via the first passivation film 152, the first interlayer insulating film 154, and the first liner film 162. For example, the first dummy pad 174 may be formed in the test pad opening 174t, for example, completely filling the test pad opening 174t, and may be connected to the first test pad 144. The first dummy pad 174 may be exposed from the first liner film 162. For example, the top surface of the first dummy pad 174 may be disposed in the same plane as the top surface of the first liner film 162 (e.g., coplanar with the top surface of the first liner film 162). The first dummy pad 174 may include at least one of, for example, W, Al, and Cu. For example, the first dummy pad 174 may include Cu.

[0060] For example, the width W22 of the first dummy pad 174 may be about 10 microns or less than 10 microns, for example, about 5 microns to about 10 microns. In some embodiments, the width W22 of the first dummy pad 174 may be greater than the width W21 of the first front-side bonding pad 172.

[0061] For example, the height H12 of the first dummy pad 174 may be about 5 microns or less than 5 microns, for example, about 3 microns to about 5 microns. Since the first front-side bonding pad 172 penetrates the second interlayer insulating film 156 and the second liner film 164 other than the first liner film 162, the height H11 of the first front-side bonding pad 172 may be greater than the height H12 of the first dummy pad 174.

[0062] The first dummy pad 174 may not be electrically connected to the second semiconductor wafer 200. For example, the second interlayer insulating film 156 may be formed on the first liner film 162 and the first dummy pad 174. The second interlayer insulating film 156 may cover the top surface of the first liner film 162 and the top surface of the first dummy pad 174. Accordingly, the second backside bonding pad 295 may not be connected to the first test pad 144.

[0063] FIGS. 7 to 10 are cross-sectional views of a semiconductor package according to some embodiments of the present disclosure. For convenience, descriptions of elements or features that have been described above with reference to FIGS. 1 to 6 will be omitted or simplified.

[0064] Referring to FIG. 7 or FIG. 8, a semiconductor package according to some embodiments of the present disclosure may include a base substrate 500 and a semiconductor wafer stack (100, 200, 300, and 400).

[0065] The base substrate 500 may be a packaging substrate for forming a semiconductor package. For example, the base substrate 500 may be a printed circuit board (PCB), a ceramic substrate, or an interposer. In another example, the base substrate 500 may be a wafer level package (WLP) substrate manufactured at the wafer level. In another example, the base substrate 500 may be a semiconductor wafer including semiconductor components. The base substrate 500 will be described hereinafter as a semiconductor wafer including a base semiconductor substrate 510.

[0066] The semiconductor wafer stack (100, 200, 300, and 400) may include a plurality of stacked semiconductor wafers, that is, a first semiconductor wafer 100, a second semiconductor wafer 200, a third semiconductor wafer 300, and a fourth semiconductor wafer 400. For example, the second semiconductor wafer 200 may be stacked on the fourth semiconductor wafer 400, the first semiconductor wafer 100 may be stacked on the second semiconductor wafer 200, and the third semiconductor wafer 300 may be stacked on the first semiconductor wafer 100. The semiconductor wafer stack (100, 200, 300, and 400) may form a multi-chip semiconductor package, such as HBM.

[0067] Each of the first semiconductor wafer 100, the second semiconductor wafer 200, the third semiconductor wafer 300, and the fourth semiconductor wafer 400 may include a semiconductor substrate 110, a semiconductor substrate 210, a semiconductor substrate 310, or a semiconductor substrate 410, a through hole 115, a through hole 215, or a through hole 415, a semiconductor element layer 120, a semiconductor element layer 220, a semiconductor element layer 320, or a semiconductor element layer 420, a wiring structure 130, a wiring structure 230, a wiring structure 330, or a wiring structure 430, a connection pad 142, a connection pad 242, a connection pad 342, or a connection pad 442, a test pad 144, a test pad 244, a test pad 344, or a test pad 444, a front-side bonding pad 172, a front-side bonding pad 272, a front-side bonding pad 372, or a front-side bonding pad 472, and a back-side bonding pad 195, a back-side bonding pad 295, or a back-side bonding pad 495. The semiconductor substrate 110, the semiconductor substrate 210, the semiconductor substrate 310, or the semiconductor substrate 410, the through hole 115, the through hole 215, or the through hole 415, the semiconductor element layer 120, the semiconductor element layer 220, the semiconductor element layer 320, or the semiconductor element layer 420, the wiring structure 130, the wiring structure 230, the wiring structure 330, or the wiring structure 430, the connection pad 142, the connection pad 242, the connection pad 342, or the connection pad 442, the test pad 144, the test pad 244, the test pad 344, or the test pad 444, the front-side bonding pad 172, the front-side bonding pad 272, the front-side bonding pad 372, or the front-side bonding pad 472, and the back-side bonding pad 195, the back-side bonding pad 295, or the back-side bonding pad 495 may respectively correspond to the first semiconductor substrate 110, the first through hole 115, the first semiconductor element layer 120, the first wiring structure 130, the first connection pad 142, the first test pad 144, the first front-side bonding pad 172, and the first back-side bonding pad 195 of FIG. 1, and thus their detailed descriptions will be omitted.

[0068] The semiconductor wafer stacks (100, 200, 300, and 400) may be stacked on the base substrate 500. For example, a first base pad 595 may be formed on the top surface of the base semiconductor substrate 510. The fourth semiconductor wafer 400 may be electrically connected to the base substrate 500 via the first base pad 595. For example, the front-side bonding pad 472 of the fourth semiconductor wafer 400 may be (e.g., directly) connected to the first base pad 595 of the base substrate 500.

[0069] In some embodiments, the base substrate 500 may further include a base via 515, a second base pad 540, and a base connection component 545. The second base pad 540 may be formed on the bottom surface of the base semiconductor substrate 510. The base via 515 may connect the first base pad 595 and the second base pad 540 via the base semiconductor substrate 510. The base connection component 545 may be connected to the second base pad 540. The semiconductor package according to some embodiments of the present disclosure may be electrically connected to an external device (e.g., a set of electronic devices) via the base connection component 545. The base connection component 545 may include at least one of, for example, solder balls, bumps, under bump metallurgy (UBM), and combinations thereof. For example, the base connection component 545 may include a metal such as tin (Sn).

[0070] The test pad 144, the test pad 244, the test pad 344, and the test pad 444 may not be respectively connected to the first semiconductor wafer 100, the second semiconductor wafer 200, the third semiconductor wafer 300, and the fourth semiconductor wafer 400, and vice versa. For example, as shown in FIG. 7, due to the insulating material (e.g., the second interlayer insulating film 156 in FIG. 1), the test pad 144, the test pad 244, the test pad 344, and the test pad 444 may not be respectively electrically connected to the backside bonding pads 195, 295, and 495.

[0071] Referring to FIG. 8, in some embodiments, each of the first semiconductor wafer 100, the second semiconductor wafer 200, the third semiconductor wafer 300, and the fourth semiconductor wafer 400 may further include a dummy pad 174, a dummy pad 274, a dummy pad 374, or a dummy pad 474. The dummy pad 174, the dummy pad 274, the dummy pad 374, or the dummy pad 474 may correspond to the first dummy pad 174 in FIGS. 4 to 6, and thus the detailed description thereof will be omitted.

[0072] Referring to FIGS. 9 or 10, a semiconductor package according to some embodiments of the present disclosure may include a PCB 10, an interposer 20, a logic semiconductor wafer 30, and a molding component 50.

[0073] The interposer 20 may be stacked on the PCB 10. The interposer 20 may be electrically connected to the PCB 10. For example, a base pad 14 may be formed on the top surface of the PCB 10, and a first interposer pad 22 may be formed on the bottom surface of the interposer 20. The base pad 14 and the first interposer pad 22 may be connected to each other via a first connection component 25. The first connection component 25 may include at least one of, for example, solder balls, bumps, UBM, and combinations thereof. For example, the first connection component 25 may include a metal such as Sn.

[0074] The interposer 20 can be inserted between the PCB 10 and the semiconductor chip stacks (100, 200, 300, and 400). The semiconductor chip stacks (100, 200, 300, and 400) can be stacked on the top surface of the interposer 20. The interposer 20 can be a silicon interposer or an organic interposer. In some embodiments, the interposer 20 can include a silicon interposer. The interposer 20 can facilitate the connection between the logic semiconductor chip 30 and the semiconductor chip stacks (100, 200, 300, and 400), and can be used to reduce the bending of the semiconductor package according to some embodiments of the present disclosure.

[0075] The logic semiconductor chip 30 can be an integrated circuit (IC) obtained by integrating hundreds to millions of semiconductor elements into a single chip. The logic semiconductor chip 30 can be an AP, such as a CPU, GPU, FPGA, DSP, cryptographic processor, microprocessor, microcontroller, or ASIC.

[0076] The logic semiconductor chip 30 can be mounted on the top surface of the interposer 20. For example, the second interposer pad 24 can be formed on the top surface of the interposer 20, and the first chip pad 32 can be formed on the bottom surface of the logic semiconductor chip 30. The second interposer pad 24 and the first chip pad 32 can be connected to each other via the second connection component 35. The second connection component 35 can include at least one of, for example, microbumps, UBMs, and combinations thereof. For example, the second connection component 35 can include a metal, such as Sn.

[0077] In some embodiments, the first underfill 52 can be formed between the interposer 20 and the logic semiconductor chip 30. The first underfill 52 can fill the space between the interposer 20 and the logic semiconductor chip 30. In addition, the first underfill 52 can cover the second connection component 35. The first underfill 52 can prevent the breakage of the logic semiconductor chip 30 by fixing the logic semiconductor chip 30 on the interposer 20. For example, the first underfill 52 can include an insulating polymer material, such as an epoxy molding compound (EMC).

[0078] Semiconductor wafer stacks (100, 200, 300, and 400) can form a multi-chip semiconductor package, such as HBM. In some embodiments, a buffer semiconductor wafer 40 can be inserted between the interposer 20 and the semiconductor wafer stack (100, 200, 300, and 400). The buffer semiconductor wafer 40 can facilitate the connection between the interposer 20 and the semiconductor wafer stack (100, 200, 300, and 400) and the connection between the logic semiconductor wafer 30 and the semiconductor wafer stack (100, 200, 300, and 400). For example, the buffer semiconductor wafer 40 can be an AP, such as a CPU, GPU, FPGA, DSP, cryptographic processor, microprocessor, microcontroller, or ASIC.

[0079] The buffer semiconductor wafer 40 can be mounted on the top surface of the interposer 20 to be spaced apart from the logic semiconductor wafer 30. For example, a second chip pad 42 can be formed on the bottom surface of the buffer semiconductor wafer 40. The second interposer pad 24 and the second chip pad 42 can be connected to each other via a third connection component 45. The third connection component 45 can include at least one of, for example, micro-bumps, UBMs, and combinations thereof. For example, the third connection component 45 can include a metal, such as Sn.

[0080] In some embodiments, a second underfill 54 can be formed between the interposer 20 and the buffer semiconductor wafer 40. The second underfill 54 can fill the space between the interposer 20 and the buffer semiconductor wafer 40. In addition, the second underfill 54 can cover the third connection component 45. The second underfill 54 can prevent the buffer semiconductor wafer 40 from breaking by fixing the buffer semiconductor wafer 40 to the interposer 20. For example, the second underfill 54 can include an insulating polymer material, such as EMC.

[0081] A molding component 50 can be formed on the top surface of the interposer 20. The molding component 50 can cover at least a portion of the logic semiconductor wafer 30 and at least a portion of the semiconductor wafer stack (100, 200, 300, and 400). For example, the molding component 50 can cover the side surfaces of the logic semiconductor wafer 30 and the semiconductor wafer stack (100, 200, 300, and 400). The molding component 50 is shown as only exposing the top surfaces of the logic semiconductor wafer 30 and the semiconductor wafer stack (100, 200, 300, and 400). Alternatively, the molding component 50 can also cover the top surfaces of the logic semiconductor wafer 30 and the semiconductor wafer stack (100, 200, 300, and 400).

[0082] For example, the molded component 50 may include an insulating polymer material, such as EMC. In some embodiments, the first underfill 52 and the second underfill 54 may include a material different from the molded component 50. For example, the first underfill 52 and the second underfill 54 may include an insulating material having a greater fluidity than the molded component 50. Accordingly, the first underfill 52 and the second underfill 54 may effectively fill the narrow spaces between the interposer 20 and the logic semiconductor wafer 30 and / or between the interposer 20 and the semiconductor wafer stacks (100, 200, 300, and 400).

[0083] A method of manufacturing a semiconductor package according to some embodiments of the present disclosure will be described hereinafter with reference to FIGS. 1 to 23.

[0084] FIGS. 11 to 20 are cross-sectional views of stages in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. For convenience, descriptions of elements or features that have been described above with reference to FIGS. 1 to 10 will be omitted or simplified.

[0085] Referring to FIG. 11, a first via 115, a first semiconductor element layer 120, a first wiring structure 130, a first connection pad 142, a first test pad 144, and a first passivation film 152 may be formed on a first semiconductor substrate 110.

[0086] For example, a first semiconductor substrate 110 having a first surface 110a and a second surface 110b may be provided. The first semiconductor element layer 120 may be formed on the first surface 110a of the first semiconductor substrate 110. The first via 115 may be formed in the first semiconductor substrate 110 and the first semiconductor element layer 120 (e.g., through the first semiconductor substrate 110 and the first semiconductor element layer 120). The first wiring structure 130 may be formed on the first semiconductor element layer 120. The first connection pad 142 and the first test pad 144 may be spaced apart from each other and may be formed on the first wiring structure 130.

[0087] Thereafter, the first passivation film 152 may be formed on the first wiring structure 130, the first connection pad 142, and the first test pad 144. The first passivation film 152 may conformally extend along the contours of the first wiring structure 130, the first connection pad 142, and the first test pad 144. The first passivation film 152 may be formed by high-density plasma chemical vapor deposition (HDPCVD).

[0088] Referring to FIG. 12, the first interlayer insulating film 154 and the first liner film 162 can be sequentially formed on the first passivation film 152.

[0089] For example, the first interlayer insulating film 154 covering the first passivation film 152 can be formed. The first interlayer insulating film 154 can be formed by, for example, plasma-enhanced chemical vapor deposition (PECVD), low-temperature chemical vapor deposition (LTCVD), or atomic layer deposition (ALD). The first interlayer insulating film 154 can include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. For example, the first interlayer insulating film 154 can include TEOS.

[0090] Thereafter, the first liner thin film 162 covering the first interlayer insulating film 154 can be formed. In some embodiments, the first interlayer insulating film 154 can be planarized before forming the first liner film 162. The first interlayer insulating film 154 can be planarized by, for example, chemical mechanical polishing (CMP). The first interlayer insulating film 154 can extend along the planarized top surface of the first interlayer insulating film 154. The first liner film 162 can include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. For example, the first liner film 162 can include a SiN film.

[0091] Referring to FIG. 13, the test pad opening 174t is formed in the first interlayer insulating film 154 and the first liner film 162.

[0092] For example, an etching process can be performed to expose at least a portion of the top surface of the first test pad 144. The etching process can include a dry etching process for the first interlayer insulating film 154 and the first liner film 162. Thus, the test pad opening 174t exposing at least a portion of the top surface of the first test pad 144 through the first interlayer insulating film 154 and the first liner film 162 can be formed.

[0093] Referring to FIG. 14, the test process of the first test pad 144 can be performed using the test pad opening 174t. The test process can be performed to test the functions and electrical connections of the first semiconductor wafer 100.

[0094] For example, a test device including a probe TP may be provided. The test device may perform a test process by physically contacting the probe TP with the first test pad 144. This type of contact test process may have higher performance than a non-contact test process.

[0095] In some embodiments, a groove 144h may be formed in the first test pad 144. For example, since the probe TP physically contacts the first test pad 144 during the test process, the groove 144h may be formed on the top surface of the first test pad 144.

[0096] Referring to FIG. 15, the second interlayer insulating film 156 and the second liner film 164 may be sequentially formed on the first liner film 162.

[0097] For example, the second interlayer insulating film 156 covering the first liner film 162 may be formed. The second interlayer insulating film 156 may be formed by PECVD, LTCVD, or ALD.

[0098] The second interlayer insulating film 156 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. For example, the second interlayer insulating film 156 may include TEOS.

[0099] In some embodiments, the second interlayer insulating film 156 may fill the test pad opening 174t of FIG. 14. Accordingly, a portion of the second interlayer insulating film 156 may contact the first test pad 144.

[0100] Thereafter, the second liner film 164 covering the second interlayer insulating film 156 may be formed. In some embodiments, the second interlayer insulating film 156 may be planarized before forming the second liner film 164. The second interlayer insulating film 156 may be planarized by CMP. The second liner film 164 may extend along the planarized top surface of the second interlayer insulating film 156.

[0101] The second liner film 164 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. For example, the second liner film 164 may include a SiCN film.

[0102] Referring to FIG. 16, a first front-side bonding pad 172 connected to the first connection pad 142 is formed.

[0103] For example, an opening (e.g., the connection pad opening 172t in FIGS. 2A and 2B) may be formed that exposes at least a portion of the top surface of the first connection pad 142 through the first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, and the second liner film 164. Thereafter, a conductive film may be formed on the second liner film 164 to fill the opening. The conductive film may be formed by, for example, a metal damascene process.

[0104] Thereafter, the conductive film may be planarized. The conductive film may be planarized by, for example, CMP. In some embodiments, the second liner film 164 may be used as an etch stopper during the planarization of the conductive film. Thus, a first front-side bonding pad 172 may be formed whose top surface is disposed in the same plane as the top surface of the second liner film 164.

[0105] The first front-side bonding pad 172 may include at least one of, for example, W, Al, and Cu. For example, the first front-side bonding pad 172 may include Cu.

[0106] Referring to FIG. 17, a recess process is performed on the second surface 110b of the first semiconductor substrate 110.

[0107] For example, a back grinding process may be performed on the second surface 110b of the first semiconductor substrate 110. Due to the recess process, a portion of the first through hole 115 may be exposed. For example, the recess process may be performed until the second surface 110b of the first semiconductor substrate 110 becomes lower than the top surface of the first through hole 115. In this example, a first through hole 115 that protrudes beyond (e.g., is higher than) the second surface 110b of the first semiconductor substrate 110 may be formed.

[0108] Referring to FIG. 18, a first back-side insulating film 190 is formed on the second surface 110b of the first semiconductor substrate 110.

[0109] For example, the first through hole 115 may be planarized. The first through hole 115 may be planarized by, for example, CMP. Thus, the protruding portion of the first through hole 115 may be removed. Thereafter, a first back-side insulating film 190 covering the second surface 110b of the first semiconductor substrate 110 and the first through hole 115 may be formed. The first back-side insulating film 190 may be formed by, for example, CVD.

[0110] Referring to FIG. 19, a first back-side bonding pad 195 connected to the first through hole 115 is formed.

[0111] For example, an opening may be formed that exposes at least a portion of the top surface of the first via hole 115 through the first backside insulating film 190. Thereafter, a conductive film may be formed to fill the opening. The conductive film may be formed by, for example, a metal damascene process.

[0112] Thereafter, the conductive film may be planarized. The conductive film may be planarized by, for example, CMP. Thus, a first backside bonding pad 195 may be formed whose top surface is disposed on the same plane as the top surface of the first backside insulating film 190.

[0113] The first backside bonding pad 195 may include at least one of, for example, W, Al, and Cu. For example, the first backside bonding pad 195 may include Cu.

[0114] In this way, the first semiconductor wafer 100 of FIG. 1 may be obtained.

[0115] Referring to FIG. 20, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be bonded together. The second semiconductor wafer 200 may be manufactured in a manner similar to the first semiconductor wafer 100, and thus a detailed description of how to manufacture the second semiconductor wafer 200 will be omitted.

[0116] The first semiconductor wafer 100 and the second semiconductor wafer 200 may be bonded together by a D2W method. For example, the first frontside bonding pad 172 of the first semiconductor wafer 100 and the second backside bonding pad 295 of the second semiconductor wafer 200 may be bonded. Thus, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be electrically connected.

[0117] FIGS. 21 to 23 are cross-sectional views of stages in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. For convenience, descriptions of elements or features that have been described above with reference to FIGS. 1 to 20 will be omitted or simplified. FIG. 21 shows steps of a method of manufacturing a semiconductor package after FIG. 14 according to some embodiments of the present disclosure.

[0118] Referring to FIG. 21, a first dummy pad 174 connected to the first test pad 144 is formed. For example, a conductive film may be formed to fill the test pad opening 174t. The conductive film may be formed by, for example, a metal damascene process.

[0119] Thereafter, the conductive film may be planarized. The conductive film may be planarized by, for example, CMP. In some embodiments, the first liner film 162 may be used as an etching stopper during the planarization of the conductive film. Thus, a first dummy pad 174 may be formed whose top surface is disposed on the same plane as the top surface of the first liner film 162.

[0120] The first dummy pad 174 may include at least one of, for example, W, Al, and Cu. For example, the first dummy pad 174 may include Cu.

[0121] Referring to FIG. 22, the second interlayer insulating film 156 and the second liner film 164 are sequentially formed on the first liner film 162 and the first dummy pad 174. The formation of the second interlayer insulating film 156 and the second liner film 164 is similar to the formation of the second interlayer insulating film 156 and the second liner film 164 in FIG. 15, and thus the detailed description thereof will be omitted.

[0122] Referring to FIG. 23, a first front-side bonding pad 172 connected to the first connection pad 142 is formed. The formation of the first front-side bonding pad 172 is similar to the formation of the first front-side bonding pad 172 in FIG. 15, and thus the detailed description thereof will be omitted.

[0123] Thereafter, the steps of FIGS. 17 to 20 can be executed. In this way, the semiconductor packages of FIGS. 4 to 6 can be obtained.

[0124] By way of summary and overview, embodiments of the present disclosure provide semiconductor packages with improved thermal characteristics. Embodiments of the present disclosure also provide a method of manufacturing a semiconductor package with improved thermal characteristics.

[0125] Example embodiments have been disclosed herein, and although specific terms are used, these terms are used only in a general and descriptive sense and not for purposes of limitation, and should be construed only in a general and descriptive sense and not for purposes of limitation. In some cases, as will be apparent to those of ordinary skill in the art as of the filing date of this application, unless otherwise specifically indicated, the features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those of skill in the art should understand that various forms and details changes can be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Brief Description of the Drawings

[0008] By describing exemplary embodiments in detail with reference to the accompanying drawings, the features will become apparent to those of ordinary skill in the art, wherein: FIG. 1 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIGS. 2A and 2B are enlarged cross-sectional views of region R1 of FIG. 1. FIGS. 3A and 3B are plan views of the first connection pad and the first test pad of FIG. 1. FIG. 4 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIG. 5 is an enlarged cross-sectional view of region R2 of FIG. 4. FIG. 6 is a plan view of the first connection pad and the first test pad of FIG. 4. FIGS. 7 to 10 are cross-sectional views of a semiconductor package according to some embodiments of the present disclosure. FIGS. 11 to 20 are cross-sectional views of stages in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIGS. 21 to 23 are cross-sectional views of stages in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

Claims

1. A semiconductor package, comprising: A first semiconductor wafer includes: a first semiconductor substrate having a first surface and a second surface opposite to each other; a first semiconductor element layer and a first wiring structure sequentially stacked on the first surface of the first semiconductor substrate; a first connection pad and a first test pad connected to the first wiring structure; and a first front bonding pad connected to the first connection pad; and a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer including: a second semiconductor substrate having a third surface and a fourth surface opposite to each other, the third surface facing the first surface of the first semiconductor substrate; a second semiconductor element layer and a second wiring structure sequentially stacked on the third surface of the second semiconductor substrate; and a first back bonding pad bonded to the first front bonding pad of the first semiconductor wafer on the fourth surface of the second semiconductor substrate, wherein the first test pad of the first semiconductor wafer is not electrically connected to the second semiconductor wafer.

2. The semiconductor package as described in claim 1, wherein: The first semiconductor wafer further includes a first interlayer insulating film, a first liner, a second interlayer insulating film and a second liner stacked sequentially on the first wiring structure, and the first front bonding pad is connected to the first bonding pad via the first interlayer insulating film, the first liner, the second interlayer insulating film and the second liner.

3. The semiconductor package as claimed in claim 2, wherein the second semiconductor wafer further includes a back-side insulating film, the back-side insulating film being on the fourth surface of the second semiconductor substrate and bonded to the second liner.

4. The semiconductor package as described in claim 2, wherein: The first interlayer insulating film and the second interlayer insulating film comprise silicon oxide film, and the first liner film and the second liner film comprise silicon nitride film.

5. The semiconductor package as claimed in claim 2, wherein a portion of the second interlayer insulating film contacts the first test pad via the first interlayer insulating film and the first liner.

6. The semiconductor package as claimed in claim 1, wherein: The first semiconductor wafer further includes a dummy pad connected to the first test pad, and the height of the first front bonding pad is greater than the height of the top surface of the dummy pad.

7. The semiconductor package of claim 1, wherein the first semiconductor wafer further comprises: a second back-side bonding pad on the second surface of the first semiconductor substrate, and a via connecting the first wiring structure and the second back-side bonding pad via the first semiconductor substrate.

8. The semiconductor package of claim 1, wherein the second semiconductor wafer further includes a through-hole connecting the second wiring structure and the first back-side bonding pad via the second semiconductor substrate.

9. The semiconductor package of claim 8, wherein the second semiconductor wafer further comprises: a second connection pad and a second test pad connected to the second wiring structure, on the second wiring structure, and a second front bonding pad connected to the second connection pad but not connected to the second test pad.

10. A semiconductor package, comprising: A semiconductor substrate having a first surface and a second surface opposite to each other; Semiconductor element layers and wiring structures are sequentially stacked on the first surface of the semiconductor substrate; A connecting pad, connected to the wiring structure, on the top surface of the wiring structure; a test pad, spaced apart from the connecting pad and connected to the wiring structure, on the top surface of the wiring structure; a first liner and a second liner, sequentially stacked on the top surface of the wiring structure; The connecting pad opening exposes the connecting pad via the first liner and the second liner; The test pad opening exposes the test pad through the first liner and does not penetrate the second liner; And a front engagement pad, connected to the connection pad in the opening of the connection pad.

11. The semiconductor package as described in claim 10, further comprising: A first interlayer insulating film is located between the wiring structure and the first liner film; And a second interlayer insulating film, between the first liner and the second liner, wherein the first interlayer insulating film and the second interlayer insulating film comprise silicon oxide films, and wherein the first liner and the second liner comprise silicon nitride films.

12. The semiconductor package of claim 11, wherein the first liner comprises a SiN film and the second liner comprises a SiCN film.

13. The semiconductor package of claim 10, wherein the connection pad and the test pad comprise aluminum (Al), and the front bonding pad comprises copper (Cu).

14. The semiconductor package of claim 10, wherein the top surface of the front bonding pad is in the same plane as the top surface of the second liner.

15. The semiconductor package of claim 10 further includes a dummy pad connected to the test pad in the test pad opening, the top surface of the dummy pad being in the same plane as the top surface of the first liner.

16. The semiconductor package as described in claim 10, further comprising: A back-side insulating film covers the second surface of the semiconductor substrate; A back-side bonding pad, exposed from the back-side insulating film, is on the second surface of the semiconductor substrate; And vias, connecting the wiring structure and the back-side bonding pad via the semiconductor substrate.

17. The semiconductor package of claim 10, wherein the width of the test pad is greater than the width of the connection pad.

18. The semiconductor package of claim 10, wherein the top surface of the test pad includes a groove.

19. A semiconductor package, comprising: Basic base; And semiconductor wafers, sequentially stacked on the base substrate, each of the semiconductor wafers comprising: a semiconductor substrate having a first surface facing a top surface of the base substrate and a second surface opposite to the first surface; a semiconductor element layer and a wiring structure, sequentially stacked on the first surface of the semiconductor substrate; a connection pad and a test pad connected to and exposed from the wiring structure; a front bonding pad connected to the connection pad and not connected to the test pad; a back bonding pad on the second surface of the semiconductor substrate; and a via connecting the wiring structure and the back bonding pad via the semiconductor substrate.

20. The semiconductor package as claimed in claim 19, wherein: Each of the semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer bonded together, the front bonding pad of the first semiconductor wafer and the back bonding pad of the second semiconductor wafer being bonded together, and the test pad of the first semiconductor wafer not being electrically connected to the second semiconductor wafer.

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