Method for fabricating semiconductor device

Abstract

This invention discloses a method for fabricating a semiconductor device. First, a magnetic tunneling junction (MTJ) stack structure is formed on a substrate. Then, a first spin orbit torque (SOT) layer is formed on the MTJ stack structure. A first hard mask is formed on the first SOT layer. Finally, a second hard mask is used to pattern the first hard mask, the first SOT layer, and the MTJ stack structure to form an MTJ.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Prior Technology

[0002] The magnetoresistance (MR) effect is known to be the change in the resistance of a material with respect to an applied magnetic field. Its physical quantity is defined as the resistance difference under and without a magnetic field divided by the original resistance, representing the rate of change of resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial application value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, the disadvantages of these prior technologies typically include: larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a magnetic tunneling junction (MTJ) stack structure is formed on a substrate. Then, a first spin orbit torque (SOT) layer is formed on the MTJ stack structure. A first hard mask is formed on the first SOT layer. Finally, a second hard mask is used to pattern the first hard mask, the first SOT layer, and the MTJ stack structure to form an MTJ.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, a first spin orbit torque (SOT) layer disposed on the MTJ, a second SOT layer disposed on the first SOT layer, and a hard mask disposed between the first SOT layer and the second SOT layer. Simple Explanation of the Diagram

[0006] Figures 1 to 7 are schematic diagrams illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Implementation

[0007] Please refer to Figures 1 to 7, which are schematic diagrams illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. As shown in Figure 1, a substrate 12 is first provided, for example, a substrate 12 made of semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and preferably an MRAM region 14 and a logic region 16 are defined on the substrate 12.

[0008] The substrate 12 may contain active components such as metal-oxide-semiconductor (MOS) transistors, passive components, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor elements, wherein the MOS transistor may include a gate structure (such as a metal gate) and source / drain regions, sidewalls, epitaxial layers, contact hole etch stop layers, etc. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistor, and the interlayer dielectric layer 18 may have a plurality of contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistor. Since the related processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0009] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0010] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each metal interconnect 26 and 32 may more specifically include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene processes are well-known techniques in the art, they will not be described in detail here. In addition, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethyl orthosilicate (TES), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0011] Next, a lower electrode 38, an MTJ stack structure 40, an upper electrode 42, a first spin orbit torque (SOT) layer 44, a hard mask 68, and another hard mask 46 are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 40 can be formed by first sequentially forming a pinned layer, a barrier layer, and a free layer on the lower electrode 38. In this embodiment, the lower electrode 38 and the upper electrode 42 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixed layer can also be made of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer can be made of insulating materials containing oxides, such as aluminum oxide (AlOx) or magnesium oxide (MgO), but is not limited to these. The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field. In this embodiment, the first SOT layer 44 is preferably a channel for a spin orbit torque (SOT) MRAM, therefore its material can include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi xSe 1-x), or combinations thereof. Additionally, hard mask 68 preferably contains conductive or metallic materials such as ruthenium (Ru), while hard mask 46 may contain conductive or dielectric materials such as, but not limited to, titanium nitride.

[0012] Then, as shown in Figure 2, an etching process, or more specifically a lithography and etching process, is performed to pattern the hard mask 46 and expose the surface of the underlying hard mask 68. In detail, the lithography and etching process performed in this stage preferably first forms a patterned mask (not shown), such as a patterned photoresist, on the hard mask 46. Then, using the patterned mask as a mask, an etching process is performed to remove a portion of the hard mask 46, forming a patterned hard mask 46 and exposing the surface of the underlying hard mask 68. The etching process performed in this stage preferably includes a reactive ion etching (RIE) process. It should be noted that the hard mask 68 in this embodiment preferably serves as an etch stop layer. Therefore, when removing a portion of the hard mask 46 using the reactive ion etching process in this stage, the etching formulation used can stop on the surface of the hard mask 68 without affecting the magnetic material in the underlying MTJ stack structure 40.

[0013] Subsequently, as shown in Figure 3, one or more etching processes are performed using the patterned hard mask 46 as a mask to remove a portion of the hard mask 68, a portion of the first SOT layer 44, a portion of the upper electrode 42, a portion of the MTJ stack structure 40, a portion of the lower electrode 38, and a portion of the intermetallic dielectric layer 30 to form at least one MTJ 48 in the MRAM region 14, and then the patterned mask 46 is removed. It is worth noting that in this embodiment, the etching process performed on the patterned upper electrode 42, MTJ stack structure 40, lower electrode 38, and intermetallic dielectric layer 30 preferably does not include reactive ion etching processes but only uses, for example, ion beam etching (IBE). Due to the characteristics of ion beam etching processes, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. Additionally, it should be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, part of the metal interconnects 32 can be removed simultaneously, so that the metal interconnects 32 form sloping sidewalls near the junction of MTJ 48. Secondly, during this stage of the etching process, in addition to removing the aforementioned material layers, it is preferable to remove all the hard masks 46 simultaneously, so that only the hard mask 68 is provided above the first SOT layer 44.

[0014] A masking layer 50 is then formed on the MTJ 48 and covers the surface of the intermetallic dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 50 preferably contains silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to process requirements.

[0015] Next, as shown in Figure 4, without using any patterned masking, such as patterned photoresist, an etching process is directly performed to remove part of the masking layer 50 to form a sidewall 66 surrounding or disposed on the MTJ 48, the first SOT layer 44, and the hard mask sidewall. The sidewall 66 formed preferably presents an approximately L-shape in cross-sectional angle. Then, a deposition process, such as atomic layer deposition (ALD), is performed to form an intermetallic dielectric layer 52 on the hard mask 68, the sidewall 66, and the intermetallic dielectric layer 30. Then, a planarization process, such as chemical mechanical polishing (CMP) or an etch-back process, is performed to remove part of the intermetallic dielectric layer 52, so that the top surface of the remaining intermetallic dielectric layer 52 is approximately flush with the top surface of the sidewall 66 and the hard mask 68.

[0016] Subsequently, as shown in Figure 5, a second SOT layer 54 is first formed on the first SOT layer 44 and the intermetallic dielectric layer 52. Then, a pattern transfer process is performed, for example, using a patterned mask (not shown) to remove part of the second SOT layer 54 located on the intermetallic dielectric layer 52, so that the remaining second SOT layer 54, in addition to being disposed on the hard mask 68 and the sidewall 66, is still disposed on the intermetallic dielectric layer 52 on both sides of the sidewall 66. In this embodiment, the second SOT layer 54 and the first SOT layer 44 preferably contain the same material, wherein the second SOT layer 54 also serves as a channel for a spin orbit torque (SOT) MRAM, therefore its material may contain tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi xSe 1-x) or a combination thereof.

[0017] As shown in Figure 6, another intermetallic dielectric layer 56 is then formed on the second SOT layer 54 and the intermetallic dielectric layers 52 on both sides. The intermetallic dielectric layer 56 is preferably conformally disposed on the second SOT layer 54, and the intermetallic dielectric layers 52 and 56 may contain an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon hydrogen carbide (SiOCH). Next, a planarization process is performed, for example, by using a chemical mechanical polishing (CMP) process or an etch-back process to remove part of the intermetallic dielectric layer 56, but the top surface of the remaining intermetallic dielectric layer 56 is still higher than the top surface of the second SOT layer 54.

[0018] A pattern transfer process is then performed, for example, by using a patterned mask (not shown) to remove part of the inter-metal dielectric layer 56, part of the inter-metal dielectric layer 52, part of the inter-metal dielectric layer 30, and part of the stop layer 28 between MRAM region 14 and logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. The contact holes are then filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and low-resistance metal layers selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, for example, by chemical mechanical polishing to remove part of the metal material to form contact plugs or metal interconnects 58 electrically connecting the metal interconnects 26 within the contact holes.

[0019] Next, as shown in Figure 7, a stop layer 60 is first formed in the MRAM region 14 and the logic region 16, covering the intermetallic dielectric layer 56 and the metal interconnects 58. An intermetallic dielectric layer 62 is then formed on the stop layer 60. One or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 62 and part of the stop layer 60 in the MRAM region 14 and the logic region 16, forming contact holes (not shown). Then, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 64 in the MRAM region 14 and the logic region 16, respectively, electrically connecting the underlying MTJ 48 and the metal interconnects 58. Preferably, the metal interconnects 64 in the MRAM region 14 directly contact the underlying second SOT layer 54, while the metal interconnects 64 in the logic region 16 contact the underlying metal interconnects 58.

[0020] In this embodiment, stop layer 60 and stop layer 28 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 64 disposed within the intermetallic dielectric layer 62 can be embedded within the intermetallic dielectric layer 62 according to a single damascene process or a double damascene process. For example, the metal interconnects 64 may more specifically include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene processes are well-known techniques in the art, they will not be described in detail here. This completes the fabrication of a semiconductor device according to an embodiment of the present invention. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0021] 12: Base 14: MRAM region 16: Logical Area 18: Interlayer dielectric layer 20: Metal interconnect structure 22: Metal interconnect structure 24: Intermetallic dielectric layer 26: Metal interconnects 28: Stop Layer 30: Intermetallic dielectric layer 32: Metal interconnects 34: Barrier Layer 36: Metal layer 38: Lower electrode 40: MTJ stacked structure 42: Upper electrode 44: First SOT layer 46: Hard mask 48:MTJ 50: Covering layer 52: Intermetallic dielectric layer 54: Second SOT layer 56: Intermetallic dielectric layer 58: Metal interconnects 60: Stop Layer 62: Intermetallic dielectric layer 64: Metal interconnects 66: Sidewall 68: Hard Mask

Claims

1. A method for fabricating a semiconductor device, characterized in that it comprises: forming a magnetic tunneling junction (MTJ) stack structure on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack structure; forming a first hard mask on the first SOT layer; patterning the first hard mask, the first SOT layer, and the MTJ stack structure using a second hard mask to form an MTJ; removing the second hard mask after forming the MTJ; and forming a second SOT layer on the first hard mask.

2. The method as described in claim 1, wherein the substrate includes an MRAM region and a logic region, the method comprising: forming a first inter-metal dielectric layer on the substrate; forming a first metal interconnect within the first inter-metal dielectric layer of the MRAM region; forming the MTJ stack structure on the first inter-metal dielectric layer and the first metal interconnect; forming a first SOT layer on the MTJ stack structure; forming a first hard mask on the first SOT layer; forming a second hard mask on the first hard mask; performing a first etch process to pattern the second hard mask and expose the first hard mask; and performing a second etch process to pattern the first hard mask, the first SOT layer, and the MTJ stack structure to form the MTJ on the first metal interconnect.

3. The method as described in claim 2, wherein the first etching process includes a reactive ion etching process.

4. The method as described in claim 2, wherein the second etching process includes an ion beam etching process.

5. The method as described in claim 2 further includes performing the second etching process to completely remove the second hard mask.

6. The method as described in claim 2, further comprising: forming a masking layer on the first hard mask and the first intermetallic dielectric layer; removing the masking layer to form a sidewall surrounding the MTJ; forming a second intermetallic dielectric layer surrounding the sidewall; forming the second SOT layer on the first hard mask and the second intermetallic dielectric layer; patterning the second SOT layer; forming a third intermetallic dielectric layer on the second SOT layer; and forming a second metal interconnect in the logic region.

7. The method as described in claim 6, wherein the top surface of the second intermetallic dielectric layer is flush with the top surface of the first hard mask.

8. The method as described in claim 6, wherein the top surface of the second intermetallic dielectric layer is flush with the top surface of the sidewall sub-layer.

9. The method as described in claim 6 further comprises: forming a stop layer on the third inter-metal dielectric layer; forming a fourth inter-metal dielectric layer on the stop layer; forming a third metal interconnect in the MRAM region and connecting it to the second SOT layer; and forming a fourth metal interconnect in the logic region and connecting it to the second metal interconnect.

10. The method as described in claim 1, wherein the first hard mask comprises ruthenium.

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