Semiconductor device

Abstract

This disclosure relates to a semiconductor device. A wiring substrate includes: a first insulating layer; a ground plane formed on the first insulating layer; a second insulating layer formed on the first insulating layer such that the ground plane is covered by the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer formed on the second insulating layer such that the first signal wiring is covered by the third insulating layer; and a second signal wiring formed on the third insulating layer and electrically connected to the first signal wiring. The first signal wiring is disposed in a region that partially overlaps with a heat sink. The second signal wiring is not disposed in this region. The ground plane has an opening located at the position overlapping with the first signal wiring. The opening is formed to extend along the first signal wiring.

Description

[Previous Technology]

[0001] This invention relates to a semiconductor device.

[0002] The following technologies are disclosed here.

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2010-245439

[0004] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2020-4821

[0005] In a semiconductor device in which a semiconductor wafer is mounted on a wiring substrate, there exists a semiconductor device in which a heat sink (stiffener ring) covering the semiconductor wafer is bonded to the wiring substrate (see, for example, Patent Document 1). Furthermore, Patent Document 2 discloses a semiconductor device in which a cover is bonded to the wiring substrate via a conductive adhesive layer and a reference potential is supplied to the cover. [Summary of the Invention]

[0006] Performance evaluation indicators for semiconductor devices include signal transmission reliability, improved signal transmission rate, miniaturization of product size, and simplification of the wiring substrate structure. For example, from the viewpoint of reducing the number of wiring layers on the wiring substrate, it is preferable to use the uppermost wiring layer as the space for signal wiring. However, in the case of a semiconductor device where a heat sink is bonded to the wiring substrate, from the viewpoint of avoiding the risk of wiring breakage due to temperature cycle load, it is preferable not to place the signal wiring directly below the area where the heat sink is bonded. In this case, it is necessary to lay the signal wiring through multiple wiring layers. However, in the case of a structure where a single signal wiring is formed in different wiring layers, the impedance of the signal transmission path may be discontinuous due to the different wiring structures.

[0007] Other objects and novel features will become clear from the description in this specification and the accompanying drawings.

[0008] According to one embodiment, a semiconductor device includes: a semiconductor wafer having a first surface, a first electrode disposed on the first surface, the first electrode being a transmission path for a first signal; a wiring substrate having a second surface facing the first surface of the semiconductor wafer; and a heat sink disposed on the wiring substrate such that the semiconductor wafer is covered by the heat sink. Here, the heat sink has: a first portion including a portion overlapping with the semiconductor wafer; and a second portion disposed around the first portion and bonded to the wiring substrate via an adhesive layer. Furthermore, the wiring substrate includes: a first insulating layer; a first conductive pattern formed on the first insulating layer and supplied with a first potential; a second insulating layer contacting the first conductive pattern and formed on the first insulating layer such that the first conductive pattern is covered by the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer contacting the first signal wiring and formed on the second insulating layer such that the first signal wiring is covered by the third insulating layer; a second signal wiring formed on the third insulating layer and electrically connected to each of the first signal wiring and the first electrode; and an organic insulating film contacting the second signal wiring and formed on the third insulating layer such that the second signal wiring is covered by the organic insulating film. The first signal wiring is arranged in the area overlapping with the second portion of the heat sink, while the second signal wiring is not arranged in the area overlapping with the second portion of the heat sink. The first conductive pattern has a first opening portion located at the position overlapping with the first signal wiring. Furthermore, the first opening portion is formed to extend along the first signal wiring.

[0009] According to one of the above embodiments, the performance of the semiconductor device can be improved.

Implementation Method

[0011] (Forms, basic terms and instructions for use in this application)

[0012] In this application, for convenience, the description of embodiments will be divided into multiple parts as needed, etc., but unless otherwise expressly stated, these parts are not independent of each other, and each part of a single example (where one part is a partial detail or part or all of another part, whether before or after the description, etc.) is a modifying example, etc. Descriptions of similar parts are omitted in principle. Furthermore, each element in an embodiment is not essential unless otherwise expressly stated, theoretically limited to that number, or clearly not so from the context.

[0013] Similarly, in the description of embodiments, etc., the phrase "X is composed of A" or similar terms related to materials, components, etc., does not exclude elements other than A, unless explicitly stated otherwise and it is obvious from the context that this is not the case. For example, regarding composition, it means "X includes A as a major component," etc. For example, the term "silicon component," etc., is not limited to pure silicon; it goes without saying that it also includes components containing SiGe (silicon-germanium) alloys, multi-component alloys containing silicon as their major component, other additives, etc. Furthermore, the terms gold plating, Cu layer, nickel plating, etc., include not only pure components but also components containing gold, Cu, nickel, etc., as major components, unless explicitly stated otherwise.

[0014] Furthermore, references to a particular value or quantity may be greater than or less than that particular value, unless otherwise expressly stated, theoretically limited to that number, or clearly not from the context.

[0015] In the accompanying drawings of the embodiments, the same or similar parts are indicated by the same or similar reference numerals or reference numerals, and will not be described again in principle.

[0016] Furthermore, in the accompanying drawings, even in cross-sections, shading may be omitted when the cross-section becomes complex or when the cross-section and gap are clearly distinguished. In this regard, even if the hole is closed in a plane, the outline of the background may be omitted when it is clear from the description, etc. In addition, shading lines or dot patterns may be added to indicate that the area is not a gap (even if it is not a cross-section), or to indicate the boundary of the area.

[0017] In the following description, the terms ground plane or power plane may be used. Ground plane and power plane are large-area conductor patterns that differ from so-called wiring patterns. In a large-area conductor pattern, the area supplied with a reference potential is called the ground plane, and the area supplied with a power potential is called the power plane. <Electronic Equipment>

[0018] First, referring to FIGS. 1 and 2, the use of the semiconductor device of this embodiment described below will be explained. FIG. 1 is an illustrative view showing a configuration example of an electronic device including the semiconductor device of this embodiment. Furthermore, FIG. 2 is an illustrative view showing a circuit configuration example of the electronic device shown in FIG. 1. Incidentally, in order to clearly show that semiconductor devices PKG1 and PKG2 are electrically connected, FIG. 1 schematically shows the signal transmission path SGP shown in FIG. 2 with solid lines.

[0019] The electronic device (electronic device) EDV1 shown in FIG1 has a wiring board (mainboard, mounting board) MB1 and semiconductor devices PKG1 and PKG2 mounted on the wiring board MB1. Semiconductor devices PKG1 and PKG2 are electrically connected to each other via a signal transmission path SGP formed in the wiring board MB1. The signals transmitted through the signal transmission path SGP include a signal SGT output from semiconductor device PKG1 and a signal SGR input to semiconductor device PKG1. In addition, the signal transmission path SGP includes a signal transmission path SGPT to which the signal SGT is transmitted and a signal transmission path SGPR to which the signal SGR is transmitted.

[0020] In the example shown in Figure 1, signal SGT is output from semiconductor device PKG1 and input to semiconductor device PKG2. Furthermore, signal SGR is output from semiconductor device PKG2 and input to semiconductor device PKG1. However, the output destination of signal SGT and the output source of signal SGR are not limited to the example shown in Figure 1, and various modified examples exist. Since semiconductor devices PKG1 and PKG2 shown in Figure 1 have similar structures, semiconductor device PKG1 will be described below as a typical example.

[0021] As shown in Figure 2, the electronic device EDV1 has multiple signal transmission paths SGPs. A signal transmission path SGP is, for example, a high-speed transmission path (high-speed signal transmission path) that transmits signals at a transmission rate of 15 Gbps (gigabits per second) or higher. Incidentally, when achieving a transmission rate of 15 Gbps through a single signal transmission path, for example, the frequency of the electrical signal flowing through the signal transmission path SGP needs to be 30 GHz (gigahertz) or higher. Furthermore, in this embodiment, a high-speed transmission path, as an example of a signal transmission path SGP, will be described using a so-called single-ended transmission path structure, in which different signals are transmitted to each of the multiple signal transmission paths SGPs. However, the technique described below, which transmits a signal via a pair of signal transmission paths constituting a differential pair, can also be applied to the transmission paths of differential systems. An embodiment corresponding to a differential transmission path will be described later as a modified example.

[0022] As shown in Figure 2, the semiconductor wafer (semiconductor element, electronic component) CHP1 of the semiconductor device PKG1 includes multiple electrodes (electrode terminals). The multiple electrodes of the semiconductor wafer CHP1 include signal electrodes (signal electrode terminals) Tx, to which the output signal SGT (see Figure 1) will be transmitted as a transmission signal. Furthermore, the multiple electrodes of the semiconductor wafer CHP1 include signal electrodes (signal electrode terminals) Rx, to which the input signal SGR (see Figure 1) will be transmitted as a reception signal. In the following description, the signal electrode Sx will sometimes be referred to as either the signal electrode Tx or the signal electrode Rx collectively.

[0023] In Figure 2, among the multiple signal transmission paths SGP provided in the semiconductor device PKG1, two output signal transmission paths SGPT and two input signal transmission paths SGPR are typically shown. However, the number of signal transmission paths SGP included in the semiconductor device PKG1 is greater than the number of signal transmission paths shown in Figure 2.

[0024] Furthermore, the plurality of electrodes of the semiconductor wafer CHP1 include an electrode (reference potential electrode, first potential electrode) Vs to be supplied with a reference potential (first potential) VSS, and an electrode (power supply potential electrode, second potential electrode) Vd to be supplied with a power supply potential (second potential) VDD. Electrode Vs forms part of the reference potential supply path VSP. Electrode Vd forms part of the power supply potential supply path VDP. The power supply potential VDD is supplied to the semiconductor wafer CHP1 (specifically, the circuit disposed in the semiconductor wafer CHP1) via electrode Vd. Furthermore, the reference potential VSS is supplied to the semiconductor wafer CHP1 (specifically, the circuit disposed in the semiconductor wafer CHP1) via electrode Vs. At least a portion of the plurality of circuits disposed in the semiconductor wafer CHP1 is driven by a driving voltage generated by the potential difference between the power supply potential VDD and the reference potential VSS. The reference potential VSS is, for example, ground potential. Furthermore, the power supply potential VDD is higher than the reference potential VSS. <Semiconductor Device>

[0025] Figure 3 is a top surface view of one of the two semiconductor devices shown in Figure 1. Figure 4 is a bottom surface view of the semiconductor device shown in Figure 3. Figure 5 is a plan view with the heat sink constituting the semiconductor device shown in Figure 3 removed. Furthermore, Figure 6 is a cross-sectional view along line AA shown in Figure 3.

[0026] The semiconductor device PKG1 of this embodiment includes a wiring substrate SUB1 and a semiconductor wafer CHP1 mounted on the wiring substrate SUB1 (see FIG5). In addition, the semiconductor device PKG1 includes a heat dissipation adhesive sheet TIM disposed on the semiconductor wafer CHP1 and a heat sink LID covering the entire semiconductor wafer CHP1, the entire heat dissipation adhesive sheet TIM and a portion of the wiring substrate SUB1.

[0027] In the case of a semiconductor package that performs signal transmission at high speed, such as the semiconductor device PKG1, the heat value of the semiconductor wafer CHP1 tends to increase with increasing power consumption. On the other hand, from the viewpoint of stabilizing the operation of the semiconductor wafer CHP1, it is preferable that the temperature of the semiconductor wafer CHP1 does not rise excessively. Therefore, it is preferable to effectively dissipate the heat generated in the semiconductor wafer CHP1 to the outside. In the case of the semiconductor device PKG1, since the semiconductor wafer CHP1 is thermally connected to the heat sink LID via the thermal adhesive TIM, the heat emission characteristics of the heat generated in the semiconductor wafer CHP1 can be improved.

[0028] As shown in FIG. 6, the heat sink LID is bonded (fixed, bonded) to the wiring substrate SUB1 via the adhesive layer BND1. The heat sink LID includes a portion (central portion) LIDp1 that overlaps with the semiconductor wafer CHP1, and a portion (peripheral portion) LIDp2 disposed around the portion LIDp1 and bonded to the wiring substrate SUB1 via the adhesive layer BND1. By bonding the heat sink LID not only to the semiconductor wafer CHP1 but also to the wiring substrate SUB1, the heat sink LID can be securely fixed. The portion (peripheral portion) LIDp2 is defined as the portion that overlaps with the adhesive layer BND1 in the thickness direction (Z direction shown in FIG. 6) of the wiring substrate SUB1. The portion LIDp2 includes an adhesive surface LIDb that adheres to the adhesive layer BND1.

[0029] The wiring substrate SUB1 has an upper surface (surface, main surface, wafer mounting surface) 2t on which a semiconductor wafer CHP1 is mounted, and a lower surface (surface, main surface, mounting surface) 2b opposite to the upper surface 2t. Furthermore, the wiring substrate SUB1 has a plurality of side surfaces 2s continuous with the corresponding outer edges of the upper surface 2t (see FIG. 3) and the lower surface 2b (see FIG. 4). In this embodiment, each surface of the wiring substrate SUB1, including the upper surface 2t (see FIG. 3) and the lower surface 2b (see FIG. 4), is composed of a square (rectangular) shape. The upper surface 2t is the wafer mounting surface facing the front surface 3t of the semiconductor wafer CHP1.

[0030] The wiring substrate SUB1 has multiple wiring layers (six layers in the example shown in FIG. 6) WL1, WL2, WL3, WL4, WL5, and WL6, which are used to electrically connect terminals (pads 2PD) on the upper surface 2t (which is a wafer mounting surface) and terminals (pads 2LD) on the lower surface 2b (which is a mounting surface). Each wiring layer is located between the upper surface 2t and the lower surface 2b. Each wiring layer has a conductor pattern, such as wiring, which is a path for providing electronic signals or power. In addition, an insulating layer 2e is disposed between the wiring layers. The wiring layers are electrically connected to each other via via wiring 2v, which serves as an interlayer conductive path through the insulating layer 2e, or via through-hole wiring 2THW. In this embodiment, a wiring substrate having six wiring layers is exemplified as an example of wiring substrate SUB1, but the number of wiring layers disposed in wiring substrate SUB1 is not limited to six layers. For example, wiring substrates having five or fewer wiring layers or seven or more wiring layers can be used as modified examples.

[0031] Furthermore, among the multiple wiring layers, the uppermost wiring layer WL1 is covered by an organic insulating film SR1. An opening is provided in the organic insulating film SR1, and multiple pads WL1 disposed in the wiring layer 2PD are exposed from the organic insulating film SR1 at this opening. Furthermore, among the multiple wiring layers, multiple pads 2LD are disposed in the lowermost wiring layer WL6. The wiring layer WL6 is covered by an organic insulating film SR2. Each of the organic insulating films SR1 and SR2 is a solder resist film. The multiple pads 2PD disposed in the wiring layer WL1 and the multiple pads 2LD disposed in the wiring layer WL6 are electrically connected to each other via conductor patterns (wiring 2d or large-area conductor pattern 2CP) formed on the respective wiring layers, which are respectively disposed in the wiring substrate SUB1, via wiring 2v, and through-hole wiring 2THW.

[0032] Each of the following is made of, for example, copper or a metallic material comprising copper as a major component: wiring 2d, pad 2PD, via wiring 2v, via pad 2vL (see Figure 7 described later), through-hole pad THL (see Figure 7 described later), through-hole wiring 2THW, pad 2LD and conductor pattern 2CP.

[0033] Furthermore, for example, by using a build-up method, multiple wiring layers are stacked (layered) on each of the upper surface 2Ct and lower surface 2Cb of an insulating layer (core material, core insulation layer) 2CR made of resin-impregnated glass fiber prepreg to form a wiring underlay SUB1. Additionally, wiring layer WL3 on the upper surface 2Ct of wiring layer 2CR and wiring layer WL4 on the lower surface 2Cb of wiring layer 2CR are electrically connected to each other via multiple via wiring 2THWs embedded in multiple vias configured to penetrate the insulating layer 2CR from one of the upper surface 2Ct and the lower surface 2Cb to the other.

[0034] In the example shown in FIG. 6, wiring substrate SUB1 represents a wiring substrate in which multiple wiring layers are stacked on both sides of the upper surface 2Ct and the lower surface 2Cb of the insulating layer 2CR, which serves as the core material. However, as a modified example with respect to FIG. 6, a so-called coreless substrate can be used, which does not have an insulating layer 2CR made of a rigid material such as a prepreg material, and is formed by sequentially stacking (laminating) an insulating layer 2e and a conductive pattern such as wiring 2d. When using a coreless substrate, through-hole wiring 2THW is not formed, and each wiring layer is electrically connected to each other via through-hole wiring 2v.

[0035] Furthermore, in the example shown in Figure 6, the solder ball (solder material, external terminal, electrode, external electrode) SB is connected to each of the multiple pads 2LD. The solder ball SB is a conductive component used to electrically connect multiple terminals of the motherboard (not shown) to the multiple pads 2LD when the semiconductor device PKG1 is mounted on the motherboard (not shown). Each solder ball SB is, for example, a Sn-Pb solder material containing lead (Pb), or a solder material that does not substantially contain lead (Pb), i.e., a so-called lead-free solder (Pb-free solder). Examples of lead-free solders include tin-only (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), etc. Here, lead-free solder refers to solder in which the lead (Pb) content is less than 0.1 wt%, and this content is determined to meet the standards of the RoHS (Restriction of Hazardous Substances) directive.

[0036] Furthermore, as shown in FIG4, multiple solder balls SB are arranged in a matrix (array, matrix). Although not shown in FIG4, multiple pads 2LD (see FIG6) to which the multiple solder balls SB are connected are also arranged in a matrix. Therefore, a semiconductor device in which multiple external terminals (solder balls SB, pads 2LD) are arranged in a matrix on the mounting surface of the wiring substrate SUB1 is called a planar array type semiconductor device. In the case of a planar array type semiconductor device, since the mounting surface (lower surface 2b) of the wiring substrate SUB1 can be used as the arrangement space for external terminals, the increase in the mounting surface area of ​​the semiconductor device can be suppressed, even if the number of external terminals increases. In other words, a semiconductor device in which the number of external terminals increases according to the increase in function and high integration can be mounted without increasing the mounting space.

[0037] Furthermore, the semiconductor device PKG1 includes a semiconductor wafer CHP1 mounted on a wiring substrate SUB1. As shown in FIG6, the semiconductor wafer CHP1 has a front surface (main surface, upper surface) 3t on which a plurality of protruding electrodes 3BP are arranged, and a rear surface (main surface, lower surface) 3b opposite to the front surface 3t. The semiconductor wafer CHP1 has a plurality of side surfaces 3s intersect with each of the front surface 3t and the rear surface 3b. As shown in FIG5, the semiconductor wafer CHP1 has a square (rectangular) shape with a smaller planar area than the wiring substrate SUB1 in a plan view. In the example shown in FIG5, the semiconductor wafer CHP1 is mounted in the central portion of the upper surface 2t of the wiring substrate SUB1, and the four side surfaces 3s of the semiconductor wafer CHP1 extend along the four side surfaces 2s of the wiring substrate SUB1, respectively.

[0038] Furthermore, multiple electrodes (pads, electrode pads, bonding pads) 3PD are formed on the front surface 3t of the semiconductor wafer CHP1. In the example shown in FIG6, the semiconductor wafer CHP1 is mounted on the wiring substrate SUB1 in such a state that the front surface 3t faces the upper surface 2t of the wiring substrate SUB1. This mounting method is called the face-down mounting method or the flip-chip bonding method.

[0039] Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor wafer CHP1 (specifically, a semiconductor element formation region disposed on the element formation surface of the semiconductor substrate, which serves as the base material of the semiconductor wafer CHP1). A plurality of electrodes 3PD are electrically connected to the plurality of semiconductor elements via wiring (not shown) formed in a wiring layer disposed inside the semiconductor wafer CHP1 (specifically, between the front surface 3t and the semiconductor element formation region not shown).

[0040] The semiconductor wafer CHP1 (specifically, the substrate material of the semiconductor wafer CHP1) is made of silicon (Si), for example. Additionally, an insulating film covering the substrate material and wiring of the semiconductor wafer CHP1 is formed on the front surface 3t, and a portion of each of the plurality of electrodes 3PDs is exposed from the passivation film through an opening formed in the passivation film. Furthermore, each of the plurality of electrodes 3PDs is made of metal, and in this embodiment, for example, of aluminum (Al).

[0041] Furthermore, as shown in FIG6, the protruding electrode 3BP is connected to each of the plurality of electrodes 3PD, and the plurality of electrodes 3PD of the semiconductor wafer CHP1 and the plurality of pads 2PD of the wiring substrate SUB1 are electrically connected respectively through the plurality of protruding electrodes 3BP. The protruding electrode (bump electrode) 3BP is a metal part formed to protrude on the front surface 3t of the semiconductor wafer CHP1 (conductive component). In this embodiment, the protruding electrode 3BP has a structure in which a columnar electrode made of, for example, copper is formed on the electrode 3PD, and solder material is stacked on the front end of the columnar electrode. As the solder material stacked on the front end of the columnar electrode, similar to the solder ball SB described above, a lead-containing solder material or a lead-free solder can be used.

[0042] When the semiconductor wafer CHP1 is mounted onto the wiring substrate SUB1, a bonding material (e.g., a base metal film or solder paste) with good solder adhesion is pre-formed on multiple pads 2PD. By performing heat treatment (reflow process) while bringing the solder material at the tip of the columnar electrode into contact with the bonding material on the pad 2PD, the solder is integrated, and the protruding electrode 3BP is formed. Alternatively, as a modified example of this embodiment, a columnar electrode or micro solder ball made of nickel (Ni) can be formed on the electrode 3PD by forming a lower metal film, or a so-called solder bump can be used as the protruding electrode 3BP.

[0043] Furthermore, as shown in FIG6, an underfill resin (insulating resin) UF is provided between the semiconductor wafer CHP1 and the wiring substrate SUB1. The underfill resin UF is configured to close the space between the upper surface 2t of the front surface 3t and the wiring substrate SUB1 of the semiconductor wafer CHP1. Each of the plurality of protruding electrodes 3BP is sealed by the underfill resin UF. Furthermore, the underfill resin UF is made of an insulating (non-conductive) material (e.g., resin material) and is configured to seal the electrical connection portion (the junction of the plurality of protruding electrodes 3BP) between the semiconductor wafer CHP1 and the wiring substrate SUB1. Therefore, by covering the junction between the plurality of protruding electrodes 3BP and the plurality of pads 2PD with the underfill resin UF, the stress occurring in the electrical connection portion between the semiconductor wafer CHP1 and the wiring substrate SUB1 can be reduced. In addition, the stress occurring at the junction between the plurality of electrodes 3PD and the plurality of protruding electrodes 3BP of the semiconductor wafer CHP1 can be reduced. Furthermore, the main surface of the semiconductor device on which the semiconductor wafer CHP1 (circuit element) is formed can also be protected.

[0044] Furthermore, a heat sink (cover, heat sink, heat dissipation component) LID is provided on the rear surface 3b of the semiconductor wafer CHP1. The heat sink LID is, for example, a metal plate with a higher thermal conductivity than the wiring substrate SUB1 and the function of dissipating heat generated in the semiconductor wafer CHP1 to the outside. Furthermore, the heat sink LID is thermally connected to the semiconductor wafer CHP1 via a thermally conductive adhesive sheet (TIM). The thermally conductive adhesive sheet (TIM) contacts both the semiconductor wafer CHP1 and the heat sink LID. <Signal Wiring Layout>

[0045] Next, the layout of the signal wiring on the wiring substrate SUB1 of the semiconductor device PKG1 of this embodiment will be described. The semiconductor device PKG1 includes multiple signal transmission paths, and one of the multiple signal transmission paths will be used in the following description. FIG7 is a perspective plan view showing an example of the layout of the signal wiring provided in the wiring substrate shown in FIG6. FIG8 is an enlarged cross-sectional view along the BB line shown in FIG7. FIG9 is an enlarged cross-sectional view along the CC line shown in FIG7. FIG10 is an enlarged cross-sectional view showing an experimental example with respect to FIG9. In FIG7, in order to facilitate observation of the corresponding planar positional relationship between the signal wiring SGW1 formed in the wiring layer WL1, the signal wiring SGW2 formed in the wiring layer WL2, and the ground plane GP1 formed in the wiring layer WL3, this is a perspective plan view that does not show the pattern and insulating layer, but shows the aforementioned signal lines SGW1, SGW2, the through-hole pad THL formed in the wiring layer WL3, and the ground plane GP1. In the perspective plan view, the area R1 shown by the double-dotted line in Figure 7 is the area that overlaps with a portion of LIDp2 of the heat sink LID shown in Figure 6. Incidentally, referring to Figure 11, which is described later, and also to Figure 14, the area R1 in Figure 18 is shown; these also represent areas that overlap with a portion of LIDp2 of the heat sink LID in the perspective plan view.

[0046] In the description of this embodiment, the expression "A" and "B" overlap in a transparent plan view can be used. This means that "A" and "B" overlap in the Z direction shown in FIG. 6. Therefore, the expression "A" and "B" overlap in the perspective plan view can be replaced with the expression "A" and "B" overlap in the thickness direction of the wiring substrate SUB1. In this case, the thickness direction of the wiring substrate SUB1 refers to the direction from one of the upper surface 2t and the lower surface 2b shown in FIG. 6 toward the other (i.e., the Z direction shown in FIG. 6).

[0047] For the wiring substrate SUB1, a portion of the signal wiring SGW (signal wiring SGW1) is wired in the wiring layer WL1. However, in the wiring layer WL1, the area overlapping with a portion of the heat sink LID (region R1 in FIG. 7) is not provided with the signal wiring SGW. One reason for this is as follows. As shown in FIG. 6, the portion of the heat sink LID (LIDp2) overlaps with the adhesive layer BND1. In the wiring layer WL1, the organic insulating film SR1 is inserted between the adhesive layer BND1 and the wiring layer WL1. When a repetitive thermal loop load is provided by using the semiconductor device PKG1, the stress caused by this load may cause cracks to form in the portion of the organic insulating film SR1 inserted between the adhesive layer BND1 and the wiring layer WL1. If an elongated wiring pattern is arranged at the crack initiation point of the organic insulating film SR1, there is a possibility that a portion of the wiring pattern will be destroyed. On the other hand, if a large area of ​​conductor pattern, such as a ground plane, is placed at the crack initiation point of the organic insulating film SR1, the large area of ​​conductor pattern will hardly be damaged by the crack. Therefore, as in this embodiment, even if a crack occurs in the organic insulating film SR1, damage to the signal wiring SGW1 can be prevented, even if no signal wiring SGW1 is provided in the region R1 that overlaps with a portion of the heat sink LID p2.

[0048] It is preferable not to place the signal wiring SGW1 in an area overlapping with a portion of the heat sink LID p2. However, from the perspective of preventing damage to the signal wiring SGW1 due to cracks, in order to increase the number of signal transmission paths provided by a semiconductor device PKG1, the signal wiring SGW needs to be routed to an area close to the periphery of the wiring substrate SUB1. As shown in FIG4, the solder balls SB, which are external terminals of the semiconductor device PKG1, are arranged closer to the periphery. Therefore, in this embodiment, by placing the signal wiring SGW2 in the wiring layer WL2 and electrically connecting the signal wiring SGW1 of the wiring layer WL1 and the signal wiring SGW2 of the wiring layer WL2, a structure in which the signal transmission path leads to the vicinity of the periphery of the wiring substrate SUB1 is achieved.

[0049] Here, the wiring structures of the signal wiring SGW1 provided on the wiring layer WL1 and the signal wiring SGW2 provided on the wiring layer WL2 are different from each other. For example, as shown in FIG8, the signal wiring SGW1 is provided on the wiring layer WL1 in the thickness direction of the wiring substrate SUB1, and the ground plane is provided on one side of the signal wiring SGW1, which is composed of a so-called microstrip line structure. On the other hand, like the wiring substrate SUBc shown in FIG10 as an example of research, the signal wiring SGW2 provided in the wiring layer WL2 can also be a so-called stripline structure, wherein the ground plane GP1 or the ground plane GP3 is provided on both sides of the signal wiring SGW2 in the thickness direction of the wiring substrate SUBc. When comparing the microstrip line structure and the stripline structure, since more capacitive coupling occurs in the stripline structure, the characteristic impedance of the signal transmission path is likely to be lower. For example, if the characteristic impedance of the signal wiring SGW1 formed in the wiring layer WL1 is 100Ω, the characteristic impedance of the signal wiring SGW2 formed in the wiring layer WL2 shown in FIG10 becomes approximately 80Ω. When the characteristic impedance has different parts in the same signal transmission path, the signal transmission efficiency will be reduced because reflection occurs at the discontinuity of the characteristic impedance.

[0050] As described above, in order to suppress signal reflection, it is necessary to reduce the characteristic impedance difference between the signal trace SGW1 of wiring layer WL1 and the signal trace SGW2 of wiring layer WL2. As shown in FIG9, in this embodiment, in the conductive pattern (e.g., ground plane GP1) of wiring layer WL3 provided near the signal trace SGW of wiring layer WL2, an opening GPH1 is formed along the extending direction of the signal trace SGW2 of wiring layer WL2. By forming the opening GPH1, the capacitive coupling with respect to wiring layer WL2 can be reduced, and therefore, the characteristic impedance difference between the signal trace SGW1 of wiring layer WL1 and the signal trace SGW2 of wiring layer WL2 can be reduced.

[0051] Although not shown, for example, the ground plane GP3 formed on the wiring layer WL1 shown in FIG10 can reduce the characteristic impedance of the signal wiring SGW2 of the wiring layer WL2, even in the case of an opening in the extending direction of the signal wiring SGW2 forming the wiring layer WL2. However, with this method, as the number of signal wiring SGWs increases, a portion of the ground plane GP3 formed on the wiring layer WL1 may become an elongated pattern, thus causing cracks as described above in the organic insulating film SR1, and the elongated portion of the ground plane GP3 may be damaged. This embodiment is also preferably characterized by preventing damage to the ground plane GP3 formed in the region R1 of the interconnect layer WL1.

[0052] The wiring structure of the wiring substrate SUB1 shown in Figures 7 to 9 can be represented as follows. The wiring substrate SUB1 includes an insulating layer 2e1 (see Figures 8 and 9), a ground plane (conductor pattern) GP1 formed on the insulating layer 2e1 and supplied with a first potential (reference potential VSS in this embodiment). In addition, the wiring substrate SUB1 is in contact with the ground plane GP1 and includes an insulating layer 2e2 (see Figures 8 and 9) and a signal wiring SGW2. The insulating layer 2e2 is formed on the insulating layer 2e1 to cover the ground plane GP1, and the signal wiring SGW2 is formed on the insulating layer 2e2. Furthermore, the wiring substrate SUB1 contacts the signal wiring SGW2 and includes an insulating layer 2e3 (see Figures 8 and 9) and an organic insulating film SR1 (see Figures 8 and 9). The insulating layer 2e3 is formed on the insulating layer 2e2 to cover the signal wiring SGW2. The signal wiring SGW1 is electrically connected to each of the signal wiring SGW2 and the signal electrode Sx1 (see Figure 7). The organic insulating film SR1 contacts the signal wiring SGW1 and is formed on the insulating layer 2e3 to cover the signal wiring SGW1. As schematically shown in Figure 7, the signal SG1 will be transmitted to the signal electrode Sx1. Each signal wiring in the signal wiring SGW1 and the signal wiring SGW2 constitutes the transmission path of the signal SG1. The signal wiring SGW2 is arranged in a region (area) R1 that overlaps with a portion of the LIDp2 (see Figure 6) of the heat sink LID (see Figure 6), while the signal wiring SGW1 is not arranged in a region (area) R1 that overlaps with a portion of the LIDp2 of the heat sink LID. In the perspective plan view, the ground plane GP1 has an opening GPH1 located at a position overlapping with the signal trace SGW2. The opening GPH1 is formed to extend along the extension direction of the signal trace SGW2. That is, the opening GPH1 is formed to extend along the signal trace SGW2.

[0053] Incidentally, Figure 7 shows an example where the signal trace SGW2 and the entire via pad 2vL connected to the signal trace SGW2 overlap with the opening portion GPH1. In other words, in the example shown in Figure 7, in the perspective plan view, the entire signal trace path SGW2 is located within the opening portion GPH1. As a modified example of Figure 7, a portion of the signal trace SGW2 may not overlap with the opening portion GPH1. For example, most of the signal trace SGW2 overlaps with the opening portion GPH1, but sometimes a portion of the signal trace SGW2 does not overlap with the opening portion GPH1 due to the convenience of the wiring layout in the wiring layer WL3. However, from the viewpoint of matching the characteristic impedance of the entire signal trace SGW2, as shown in Figure 7, preferably, the entire signal trace SGW2 overlaps with the opening portion GPH1. <Preferred Embodiment of Wiring Structure>

[0054] Hereinafter, preferred embodiments of the signal wiring SGW shown in Figures 7 to 9 will be described. First, in the example shown in Figure 7, the wiring width LW2 of signal wiring SGW2 is narrower than the wiring width LW1 of signal wiring SGW1. From the viewpoint of improving the reliability of signal transmission by reducing the risk of breakage of the signal wiring SGW, the wiring width LW2 of signal wiring SGW2 and the wiring width LW1 of signal wiring SGW1 are preferably 30 μm or greater. However, the characteristic impedance of the signal wiring SGW2 disposed in the wiring layer WL2 is likely to be low as described above. Therefore, the wiring width LW2 of signal wiring SGW2 is preferably as narrow as possible within the range that can ensure the reliability of signal transmission. Thus, for example, in the example shown in Figure 7, the wiring width LW2 is 30 μm. On the other hand, if the wiring width LW1 of signal wiring SGW1 is wider than 30 μm, the risk of breakage is further reduced. Furthermore, when the wiring width LW1 is greater than the wiring width LW2, the difference between the characteristic impedance of signal wiring SGW1 and the characteristic impedance of signal wiring SGW2 decreases.

[0055] However, the wiring width LW1 of the signal wiring SGW1 is determined to match the value of the design characteristic impedance of the signal transmission path. For example, if the designed characteristic impedance is 100Ω, the wiring width LW1 of the signal wiring SGW1 is determined to a value that makes the characteristic impedance 100Ω. If the above value is 30μm, then the wiring width LW1 and wiring width LW2 are set to 30μm. On the other hand, if the value of the wiring width LW1 that makes the characteristic impedance 100Ω is greater than 30μm (e.g., 31μm or 32μm), by setting the value of the wiring width LW2 to 30μm (less than the wiring width LW1), the characteristic impedance of the signal wiring SGW2 can be made close to 100Ω.

[0056] Incidentally, from the viewpoint of improving the reliability of signal transmission by reducing the risk of wire breakage, the preferred lower limit of the wiring width is 30 μm. However, the lower limit of the wiring width can vary depending on the configuration material and size of the wiring substrate SUB1. Therefore, the value of the wiring width LW2 is not limited to 30 μm.

[0057] Furthermore, in the example shown in FIG. 7, the wiring length LL2 of signal wiring SGW2 is less than the wiring length LL1 of signal wiring SGW1. As described above, from the viewpoint of preventing damage to signal wiring SGW1, it is impossible to place signal wiring SGW1 in region R1. Therefore, signal wiring SGW2 is at least provided in region R1. On the other hand, even if signal wiring SGW2 is provided outside region R1, there is no risk of wire breakage, etc., so as a modified example, the wiring length LL2 of signal wiring SGW1 can also be longer than the wiring length LL1 of signal wiring SGW2.

[0058] However, as the length of the signal wiring SGW2 increases, the arrangement space (see FIG. 9) for the conductor patterns (e.g., ground plane and power plane) disposed in the wiring layer WL2 becomes narrower. Therefore, from the viewpoint of effectively utilizing the wiring layer WL1, it is preferable that the wiring length LL1 of the signal wiring SGW1 is greater than the wiring length LL2 of the signal wiring SGW2.

[0059] The routing length LL2 is defined as follows. That is, both ends of the signal routing SGW2 are connected to via pads 2vL respectively. The routing length LL2 is the path distance from the boundary between one end of the signal routing SGW2 and one of the via pads 2vL to the boundary between the other end of the signal routing SGW2 and the other of the via pads 2vL. For example, if the signal routing SGW2 is not straight but curved, the routing length LL2, defined as the path distance, will be longer than that of a straight line.

[0060] Similarly, the routing length LL1 is defined as follows. That is, one end of the signal routing SGW1 is connected to the via pad 2vL, and the other end of the signal routing SGW1 is connected to the pad 2PD shown in FIG. 6. The routing length LL1 is the path distance from the boundary between one end of the signal routing SGW1 and the via pad 2vL to the boundary between the other end of the signal routing SGW1 and the pad 2PD. For example, if the signal routing SGW1 is not straight but curved, the routing length LL1, defined as the path distance, will be longer than that of a straight line.

[0061] Furthermore, in the example shown in FIG9, the wiring substrate SUB1 is formed on the insulating layer 2e3, and also includes a ground plane (conductor pattern) GP3 electrically connected to the ground plane (conductor pattern) GP1. The ground plane GP3 is arranged in the region R1 (see FIG7) that overlaps with a portion of the LIDp2 of the heat sink LID (see FIG6). The signal wiring SGW2 overlaps with the ground plane GP1. By providing the ground plane GP3 on the top of the signal wiring SGW2, it is possible to suppress electromagnetic waves generated when the signal current flowing in the signal wiring SGW2 diffuses above the wiring substrate SUB1.

[0062] Furthermore, in the example shown in FIG9, the wiring substrate SUB1 is formed on the insulating layer 2e2, and also includes a ground plane (conductor pattern) GP2 electrically connected to the ground plane (conductor pattern) GP1. In the wiring layer WL2, the ground plane GP2 is spaced apart from the signal wiring SGW2 and is configured to sandwich the signal wiring SGW2. For example, by placing the ground plane GP2 in such a way that it sandwiches the signal wiring SGW2, even if multiple signal transmission paths in the wiring layer WL2 are densely arranged, the generation of crosstalk noise between signal transmission paths can be suppressed.

[0063] Similarly, in the example shown in FIG8, the wiring substrate SUB1 is formed on the insulating layer 2e3, and also includes a ground plane (conductor pattern) GP3 electrically connected to the ground plane (conductor pattern) GP1. In the wiring layer WL1, the ground plane GP3 is spaced apart from the signal wiring SGW1 and is configured to sandwich the signal wiring SGW1. For example, by placing the ground plane GP3 in a manner that sandwiches the signal wiring SGW1, even if multiple signal transmission paths in the wiring layer WL1 are densely arranged, the generation of crosstalk noise between signal transmission paths can be suppressed. <Relationship between adjacent signal wirings>

[0064] Next, an example of multiple signal traces arranged in the same wiring layer will be described with reference to Figures 11 to 13. Figure 11 is a perspective plan view showing a modified example with respect to Figure 7. Figure 12 is an enlarged cross-section along the DD line shown in Figure 11. Figure 13 is an enlarged cross-sectional view along the EE line shown in Figure 11. In Figure 11, similar to Figure 7, the signal trace SGW, the ground plane GP1 formed on the wiring layer WL3, and the through-hole pad THL formed on the wiring layer WL3 are shown; other conductor patterns and insulating layers are not shown.

[0065] The plurality of electrodes 3PD arranged on the front surface 3t of the semiconductor wafer CHP1 shown in FIG. 6 also include signal electrodes Sx2, which are the transmission paths for signal SG2 as shown in FIG. 11. As shown in FIG. 11-13, the wiring substrate SUB1 also includes signal wiring SGW3 formed on the insulating layer 2e2 and arranged adjacent to signal wiring SGW2, and signal wiring SGW4 formed on the insulating layer 2e3 and electrically connected to each of signal wiring SGW3 and signal electrode Sx2. Each of signal wiring SGW3 and signal wiring SGW4 constitutes the transmission path for signal SG2. Signal wiring SGW3 is arranged in region R1 (see FIG. 6) overlapping a portion of LIDp2 of the heat sink LID (see FIG. 6), while signal wiring SGW4 is not arranged in region R1 overlapping a portion of LIDp2 of the heat sink LID. The ground plane GP1 has an opening portion GPH2, which is located at a position overlapping with signal wiring SGW3 in the perspective plan view. The opening portion GPH2 is formed to extend along the extension direction of the signal wiring SGW3. In other words, the opening portion GPH2 is formed to extend along the signal wiring SGW3.

[0066] In the embodiment shown in FIG11, signals SG1 and SG2 are independent and different signals. Therefore, in the signal transmission path including signal wiring SGW2, it is necessary to reduce crosstalk noise between the signal transmission paths including signal wiring SGW3. To reduce crosstalk noise between signal wiring SGW2 and signal wiring SGW3, as shown in FIG11, preferably, a portion of ground plane GP1 is inserted between opening portion GPH1 and opening portion GPH2. Furthermore, as shown in FIG13, in wiring layer WL2, preferably, a portion of ground plane GP2 is inserted between signal wiring SGW2 and signal wiring SGW3. Each ground plane in ground plane GP1 and ground plane GP2 serves as a shield to suppress the spread of electromagnetic waves.

[0067] Similarly, in order to reduce crosstalk noise between signal wiring SGW1 and signal wiring SGW4 in wiring layer WL1, as shown in FIG12, preferably, a portion of ground plane GP3 is inserted between signal wiring SGW1 and signal wiring SGW4. Each ground plane in ground plane GP3 and ground plane GP2 acts as a shield to suppress the spread of electromagnetic waves.

[0068] Although not shown, as a modified example with respect to FIG11, the openings GPH1 and GPH2 may be connected to each other at a location away from the signal wiring SGW. However, from the viewpoint of preventing crosstalk noise, ideally, as shown in FIG11, and particularly preferably, the openings GPH1 and GPH2 are separated from each other via a portion of the ground plane GP1.

[0069] Furthermore, similar to the positional relationship between signal routing SGW2 and opening GPH1 described with reference to FIG. 7, as a modified example of FIG. 11, a portion of signal routing SGW3 may not overlap with opening GPH2. However, from the viewpoint of matching the characteristic impedance of the entire signal routing SGW1 and the entire signal routing SGW3, as shown in FIG. 11, preferably, the entire signal routing SGW2 overlaps with opening GPH1, and the entire signal routing SGW3 overlaps with opening GPH2. That is, preferably, the entire signal routing SGW2 is located within opening GPH1 in the top perspective view, and the entire signal routing SGW3 is located within opening GPH2 in the top perspective view. <Example of signal routing constituting a differential pair>

[0070] Next, an example of signal routing applied to form a differential pair will be described with reference to Figures 14 to 16. Figure 14 is a perspective plan view showing another modified example with respect to Figure 7. Figure 15 is an enlarged cross-sectional view along the FF line shown in Figure 14. Figure 16 is an enlarged cross-sectional view along the GG line shown in Figure 14. In Figure 14, similar to Figure 7, the signal routing SGW, the ground plane GP1 formed on the routing layer WL3, and the through-hole pad THL formed on the routing layer WL3 are shown, except for other conductor patterns and insulating layers. Except for the differences described below, the semiconductor device PKG2 shown in Figure 14 is the same as the semiconductor device PKG1 shown in Figure 7.

[0071] The plurality of electrodes 3PD arranged on the front surface 3t of the semiconductor wafer CHP1 shown in FIG. 6 also include a signal electrode Sx3, which is the transmission path of the signal SG3 as shown in FIG. 14. The transmission paths of the signal SG1 and the signal SG3 constitute a differential pair. In other words, the signal SG1 and the signal SG3 constitute a differential signal.

[0072] As shown in Figures 14 to 16, a wiring substrate SUB1 is formed on an insulating layer 2e2, and further includes a signal wiring SGW5 arranged adjacent to the signal wiring SGW2, and a signal wiring SGW6 formed on the insulating layer 2e3 and electrically connected to each of the signal wiring SGW5 and the signal electrode Sx3. Each of the signal wirings SGW5 and SGW6 constitutes a transmission path for the signal SG3. The signal wiring SGW5 is arranged in a region R1 (see Figure 6) that overlaps with a portion of the LIDp2 of the heat sink LID (see Figure 6), while the signal wiring SGW6 is not arranged in the region R1 that overlaps with a portion of the LIDp2 of the heat sink LID. In a perspective plan view, the opening portion GPH1 of the ground plane GP1 is formed at the location where it overlaps with each of the signal wirings SGW2 and SGW5, and is formed to extend along the extending direction of the signal wirings SGW2 and SGW5. Incidentally, since signal routing SGW2 and signal routing SGW5 form a differential pair, they extend in the same direction adjacent to each other.

[0073] As shown in Figure 15, when signal routing SGW1 and signal routing SGW6 form a differential pair, the ground plane GP3 is not arranged between signal routing SGW1 and signal routing SGW6. Similarly, as shown in Figure 16, when signal routing SGW2 and signal routing SGW5 form a differential pair, the ground plane GP2 is not arranged between signal routing SGW2 and signal routing SGW5. In this case, in routing layer WL3, it is not necessary to provide a separate opening at each of the locations overlapping with signal routing SGW2 in the perspective view and the locations overlapping with signal routing SGW5 in the perspective view. That is, preferably, an opening portion GPH1 is formed to overlap with each of the signal routings in signal routing SGW2 and signal routing SGW5.

[0074] Although not shown, when multiple differential pairs are provided as signal transmission paths, similar to the example described with reference to Figures 11 to 13, portions of ground plane GP3 (see Figure 12) and ground plane GP2 (see Figure 13) are inserted between adjacent differential pairs. Preferably, each differential pair forms an opening portion GPH1 as shown in Figure 14.

[0075] Furthermore, similar to the positional relationship between the signal wiring SGW2 and the opening GPH1 illustrated with reference to FIG. 7, as a modified example of FIG. 14, a portion of the signal wiring SGW5 may not overlap with the opening GPH1. However, from the viewpoint of matching the characteristic impedance of the entire signal wiring SGW1 and the signal wiring SGW5, as shown in FIG. 14, it is preferable that the signal wiring SGW1 and the entire signal wiring SGW5 preferably overlap with the opening GPH1. In other words, in the perspective plan view, the entire signal wiring SGW5 is preferably located within the opening GPH1. <Modified example using a heat sink as a shielding element>

[0076] Next, as a modified example of the semiconductor devices PKG1 and PKG2 shown in FIG. 6, a modified example of using a heat sink LID as an electromagnetic wave shielding component will be described below. FIG. 17 is an illustrative view showing the modified example with respect to FIG. 6. FIG. 18 is an enlarged cross-sectional view of the connection between the ground plane and the heat sink shown in FIG. 17.

[0077] The wiring substrate SUB3 constituting the semiconductor device PKG3 shown in FIG. 17 includes the wiring substrate SUB1 shown in FIG. 9 and FIG. 13, and is similar to the wiring substrate SUB2 shown in FIG. 16, having a ground plane GP3 formed on the insulating layer 2e3 and electrically connected to the ground plane GP1. The ground plane GP3 is arranged in the region R1 that overlaps with a portion of the heat sink LID p2 (see FIG. 18). The signal wiring SGW2 overlaps with the ground plane GP3. This is similar to the wiring substrate SUB1 described with reference to FIG. 9.

[0078] In the case of the wiring substrate SUB3, the heat sink LID is made of metal, and the heat sink LID is electrically connected to the ground plane (conductor pattern) GP3 via a conductive adhesive layer BND2. Specifically, as shown in FIG18, in the region R1 overlapping with a portion of LIDp2 of the heat sink LID, an opening SRH1 is formed in the organic insulating film SR1. The adhesive layer BND2 is, for example, a so-called conductive resin in which a large number of conductive particles are mixed in solder or thermosetting resin. In the opening SRH1 formed in the organic insulating layer SR1, the adhesive layer BND2 is bonded to the ground plane GP3. In addition, the adhesive layer BND2 is bonded to a portion of LIDp2 of the heat sink LID.

[0079] In the case of the semiconductor device PKG3, a fixed potential (e.g., a reference potential) is supplied to the heat sink LID by electrically connecting the heat sink LID and the ground plane GP3 to each other. In this case, the heat sink LID acts as an electromagnetic wave shielding member to suppress electromagnetic waves generated in the wiring path of the wiring substrate SUB3 to prevent them from spreading above the semiconductor device PKG3.

[0080] This modified example is particularly useful for semiconductor devices incorporated into electronic devices that require high performance and reduced electromagnetic noise, such as radio communication modules.

[0081] The opening portion SRH1 shown in FIG. 18 can be formed in at least one location in region R1 shown in FIG. 5. However, from the viewpoint of stabilizing the potential supplied to the heat sink LID, it is preferable that the opening portion SRH1 is formed at multiple locations in region R1. Particularly preferably, the opening portion SRH1 has a frame shape along the shape of region R1.

[0082] Apart from the differences described above, the semiconductor device PKG3 shown in Figures 17 and 18 is the same as the semiconductor devices PKG1 and PKG2 described above. Therefore, repeated descriptions are omitted.

[0083] In the description of the above embodiments and the above modified examples, ground plane GP1, ground plane GP2, and ground plane GP3 can be large-area conductor patterns to which a fixed potential will be supplied. Therefore, for example, each plane can be a power plane to be supplied with a power potential other than a reference potential. As a concept including ground planes and power planes, it can also be understood as a conductor pattern to which a fixed potential is supplied.

[0084] Furthermore, the above description primarily focuses on methods for controlling impedance in the signal routing SGW. However, as a modified example, it can also be applied in conjunction with methods for controlling impedance at other locations, such as the via pad THL shown in FIG7. For example, as a method for reducing capacitive coupling to the via pad THL in the example shown in FIG7, an opening is sometimes formed in the routing layer WL1 (see FIG6) at a location where the conductor pattern 2CP (see FIG6) overlaps with the via pad THL.

[0085] Although the invention made by the inventors has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its spirit.

[0086] The disclosure (including the specification, drawings and abstract) of Japanese Patent Application No. 2021-140945, filed on August 31, 2021, is incorporated herein by reference in its entirety. [Simplified Explanation of the Diagram]

[0010] FIG1 is an illustrative view showing an example configuration of an electronic device including a semiconductor device according to one embodiment; FIG2 is an illustrative view showing an example configuration of the circuit of the electronic device shown in FIG1; FIG3 is a top surface view of one of the two semiconductor devices shown in FIG1; FIG4 is a bottom surface view of the semiconductor device shown in FIG3; FIG5 is a plan view with the heat sink constituting the semiconductor device shown in FIG3 removed; FIG6 is a cross-sectional view along line AA shown in FIG3; FIG7 is a perspective plan view showing an example of the layout of signal wiring provided in the wiring substrate shown in FIG6; FIG8 is an enlarged cross-sectional view along line BB shown in FIG7; FIG9 is an enlarged cross-sectional view along line CC shown in FIG7; FIG10 is an enlarged cross-sectional view showing an experimental example with respect to FIG9; FIG11 is a perspective plan view showing a modified example with respect to FIG7; FIG12 is an enlarged cross-sectional view along line DD shown in FIG11; FIG13 is an enlarged cross-sectional view along line EE shown in FIG11; FIG14 is a perspective plan view showing another modified example with respect to FIG7; FIG15 is an enlarged cross-sectional view along line FF shown in FIG14; Figure 16 is an enlarged cross-sectional view along the GG line shown in Figure 14; Figure 17 is an illustrative view showing a modified example with respect to Figure 6; and Figure 18 is an enlarged cross-sectional view at the connection between the ground plane and the heat sink shown in Figure 17.

Claims

1. A semiconductor device, comprising: A semiconductor wafer has a first surface, on which a first electrode is disposed, and the first electrode is a transmission path for a first signal. A wiring substrate has a second surface facing the first surface of a semiconductor wafer; and a heat sink is disposed on the wiring substrate such that the semiconductor wafer is covered by the heat sink, wherein the heat sink has: a first portion including a portion overlapping the semiconductor wafer; and a second portion disposed around the first portion and bonded to the wiring substrate via an adhesive layer, wherein the wiring substrate includes: a first insulating layer; a first conductive pattern formed on the first insulating layer and supplied with a first potential; a second insulating layer in contact with the first conductive pattern and formed on the first insulating layer such that the first conductive pattern is covered by the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer in contact with the first signal wiring and formed on the second insulating layer such that the first signal wiring is covered by the third insulating layer; a second signal wiring formed on the third insulating layer and electrically connected to each of the first signal wiring and the first electrode; and an organic insulating film in contact with the second signal wiring and formed on the third insulating layer such that the second signal wiring is covered by the organic insulating film. The first signal wiring is arranged in the area overlapping with the second part of the heat sink, the second signal wiring is not arranged in the area overlapping with the second part of the heat sink, the first conductive pattern has a first opening portion located at the position overlapping with the first signal wiring, and the first opening portion is formed to extend along the first signal wiring.

2. The semiconductor device of claim 1, wherein the width of the first signal wiring is smaller than the width of the second signal wiring.

3. The semiconductor device of claim 1, wherein the wiring length of the first signal wiring is less than the wiring length of the second signal wiring.

4. The semiconductor device of claim 1, wherein the semiconductor wafer further comprises a second electrode disposed on the first surface, the second electrode being a transmission path for a second signal, wherein the wiring substrate further comprises: The third signal wiring is formed on the second insulating layer and is formed adjacent to the first signal wiring. A fourth signal wiring is formed on the third insulating layer and electrically connected to each of the third signal wiring and the second electrode, wherein the third signal wiring is arranged in the region overlapping with the second portion of the heat sink, wherein the fourth signal wiring is not arranged in the region overlapping with the second portion of the heat sink, wherein the first conductive pattern has a second opening portion located at a position overlapping with the third signal wiring, and wherein the second opening portion is formed to extend along the third signal wiring.

5. The semiconductor device of claim 4, wherein a portion of the first conductive pattern is located between the first opening portion and the second opening portion.

6. The semiconductor device of claim 5, wherein the first opening portion and the second opening portion are separated from each other via the portion of the first conductive pattern.

7. The semiconductor device of claim 1, wherein the semiconductor wafer further comprises a second electrode disposed on the first surface, the second electrode being a transmission path for a third signal, wherein the transmission path of the first signal and the transmission path of the third signal constitute a differential pair, wherein the wiring substrate further comprises: The fifth signal wiring is formed on the second insulating layer and is formed adjacent to the first signal wiring. A sixth signal wiring is formed on the third insulating layer and electrically connected to each of the fifth signal wiring and the second electrode, wherein the fifth signal wiring is arranged in the region overlapping with the second portion of the heat sink, wherein the sixth signal wiring is not arranged in the region overlapping with the second portion of the heat sink, wherein the first opening portion of the first conductive pattern is located at the position overlapping with both the first signal wiring and the fifth signal wiring, and wherein the first opening portion is formed to extend along both the first signal wiring and the fifth signal wiring.

8. The semiconductor device of claim 1, wherein the wiring substrate further comprises: A second conductive pattern is formed on the third insulating layer and electrically connected to the first conductive pattern, wherein the second conductive pattern is arranged in the region that overlaps with the second portion of the heat sink, and wherein, in a plan view, the first signal wiring overlaps with the second conductive pattern.

9. The semiconductor device of claim 8, wherein the heat sink is made of metal, and wherein the heat sink is electrically connected to the second conductive pattern via the conductive adhesive layer.

10. The semiconductor device of claim 1, wherein the entire first signal wiring overlaps with the first opening portion.

Images