Electroplating method and integrated circuit device structure

Abstract

Several exemplary methods for electroplating a metal having a nano-bicrystalline structure are described. These electroplating methods may include electroplating a metal material into at least one opening on a patterned substrate, wherein at least a portion of the metal material is characterized by a nano-bicrystalline structure. These methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to at least or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nano-bicrystalline structure. In other embodiments, the nano-bicrystalline metal may be nano-bicrystalline copper.

Description

[Technical Field]

[0001] This technology relates to several electrochemical deposition operations in semiconductor processing. More particularly, this technology relates to several systems and methods for performing electrochemical deposition of nano-bicrystalline copper materials on semiconductor structures and in semiconductor packages. [Previous Technology]

[0002] Integrated circuits can be manufactured by forming an interlaced patterned material layer on the surface of a substrate. After formation, etching, and other processes on the substrate, metals or other conductive materials are often deposited or formed to provide electrical connections between components. Because this metallization can be performed after many manufacturing operations, problems that occur during metallization can result in costly discarded substrates or wafers.

[0003] Electroplating is performed in an electroplating chamber, where the target side of the wafer is in a liquid electrolyte bath, and electrical contacts on a contact ring contact a conductive layer, such as a seed layer, on the substrate material. Current flows from a power supply through the electrolyte and the conductive layer. Metal ions in the electrolyte are plated out onto the substrate material, forming a metal layer. When the substrate material is patterned, and non-planar features are defined on the surface, metal ions in the electrolyte may not deposit at all points on the non-planar features at the same rate. These differences can make the electroplating operation challenging and result in deposited material with other defects, including voids and uneven thickness.

[0004] Therefore, there is currently a need for improved systems and methods that can be used to produce high-quality devices and structures. This technology can address these and other needs. [Summary of the Invention]

[0005] Several embodiments of this technology include several electroplating methods, including electroplating a metallic material into at least one opening on a patterned substrate. At least a portion of the metallic material is characterized by a nano-bicrystalline structure. These methods may also include polishing an exposed surface of the metallic material in the opening to reduce an average surface roughness of the exposed surface to at least or about 1 nm. The polished exposed surface includes at least a portion of the metallic material characterized by a nano-bicrystalline structure.

[0006] In other embodiments, the metallic material characterized by the nano-bicrystalline structure is nano-bicrystalline phase copper. In a further embodiment, the metallic material may include at least one second metal layer selected from the group consisting of gallium, silver, gold, and platinum. In a still further embodiment, the metallic material is polished using chemical mechanical polishing. In yet another embodiment, the metallic material is polished using electrolytic polishing. In many more embodiments, the polishing of the exposed surface of the metallic material is performed in an oxygen-free environment, wherein the polishing removes one or more metal oxides from the exposed surface of the metallic material. In still many more embodiments, the metallic material includes a first portion and a second portion, the first portion contacting a bottom surface of an opening without the nano-bicrystalline structure, and the second portion contacting a polished exposed surface including the nano-bicrystalline structure. In yet another embodiment, the patterned substrate further includes a barrier layer located between the first portion and the second portion of the metallic material in the opening.

[0007] Several embodiments of this technology also include several electroplating methods, including electroplating a first portion of a metal material onto a bottom of at least one opening on a patterned substrate, wherein the first portion of the metal material is substantially without a nano-bicrystalline structure. These methods further include forming a barrier layer on the first portion of the metal material. The method additionally includes electroplating a second portion of the metal material onto the barrier layer, wherein the second portion of the metal material is characterized by a nano-bicrystalline structure.

[0008] In other embodiments, the first portion of the metallic material is greater than or approximately 50 wt.% of the total amount of metallic material in the opening. In a further embodiment, the metallic material is copper. In a still further embodiment, the second portion of the metallic material includes at least one second metal selected from the group consisting of gallium, silver, gold, and platinum. In yet another embodiment, the barrier layer includes a metal not included in the second portion of the metallic material. In many more embodiments, the method further includes polishing an exposed surface of the second portion of the metallic material in the opening to reduce an average surface roughness of the exposed surface to less than or approximately 1 nm.

[0009] Several embodiments of the present technology further include several circuit device structures, including a patterned substrate. The patterned substrate includes at least one opening, and has a top surface and a bottom surface. The top of at least the opening is filled with a metal-containing material, wherein the metal-containing material includes an exposed surface characterized by an average surface roughness of less than or about 1 nm, and wherein the metal-containing material is characterized by a nano-bicrystalline structure.

[0010] In other embodiments, the patterned substrate further includes a barrier layer located between a second portion of the metal-containing material filling the top of the opening and a second portion of the metal-containing material contacting the bottom surface of the opening. In a further embodiment, the second portion of the metal-containing material does not have a nano-bicrystalline structure. In a still further embodiment, the metal-containing material includes copper. In yet another embodiment, the metal-containing material in the top of the opening includes at least one second metal selected from the group consisting of gallium, silver, gold, and platinum. In many more embodiments, the opening is characterized by a depth-to-width ratio greater than or approximately 1:1.

[0011] Several embodiments of this technology allow for the formation and finishing of nano-bicrystalline metals, such as nano-bicrystalline copper, in openings on a patterned substrate. These embodiments involve forming metal lines, vias, pillars, and other metal-containing components of integrated circuit devices, wherein the bonding surfaces on the components include metals having a nano-bicrystalline structure. In many examples, metals with nano-bicrystalline structures are less susceptible to oxide formation and are easier to bond to similar metal surfaces at lower bonding temperatures and pressures. Furthermore, several embodiments of this technology can be performed in an electroplating chamber, where lines and pillar systems containing nano-bicrystalline metals are formed in high-volume quantities in openings on a patterned substrate. These and other embodiments, as well as many of their advantages and features, are described in more detail below in conjunction with the accompanying drawings. To provide a better understanding of the above and other aspects of the invention, specific embodiments are described below in detail with reference to the accompanying drawings:

Implementation Method

[0013] The form of many electronic devices using semiconductor-based integrated circuits has progressed from single-chip (i.e., bare die) packages to multiple chips arranged in a single package in a stacked or otherwise manner. Single chips are electrically interconnected via circuit boards. These multi-die packages may include bare dies for memory, logic, micro-electro-mechanical systems (MEMS), and sensors, and may include system-on-chip (SoC) and system-in-package (SiP) packages. As these multi-die packages add more further miniaturized chips, the density of electrical interconnects between them (i.e., interconnect density) increases. This has led to a reduction in the size of these interconnects. These dimensions, typically measured as the pitch between conductive lines or vias, have decreased from hundreds of micrometers to 10 µm or less. Conductive lines or vias form interconnects between input / output pads on adjacent semiconductor dies.

[0014] Reducing the spacing between interconnects has changed how interconnects are formed. For the increasing number of miniaturized multi-die packages, conventional solder bumps with diameters of several hundred micrometers are too large to form high-density interconnects with spacing of 50 µm or less. In many examples, these high-density interconnects eliminate solder bumps and form direct metal-to-metal connections between the opposing lines, vias, and pads of the interconnects.

[0015] In most conventional high interconnect density integrated circuit devices, direct metal-to-metal connections are made of polycrystalline copper, whose grains are randomly oriented. Unfortunately, the limitations of polycrystalline copper become more pronounced as the spacing dimensions of copper wires, vias, and pillars continue to decrease. In many cases, the oxidation and diffusion properties of polycrystalline copper, among other characteristics, necessitate copper-to-copper bonding under high temperature and pressure. The bonding conditions can lead to more cracks and other defects in the smaller and thinner copper wires surrounding the bonding site. The number of defects increases further due to the increased density of bonding sites in high interconnect density integrated circuits. As the spacing and other dimensions of interconnects continue to decrease and the density of bonding sites continues to increase, the problems associated with high-temperature, high-pressure bonding on polycrystalline copper surfaces continue to increase.

[0016] Several embodiments of this technology address the problem of bonding polycrystalline copper in high interconnect density integrated circuit devices by replacing polycrystalline copper with nanonotwin copper (NTCu) having a <1,1,1> crystal orientation. In other embodiments, a significant proportion of NTCu grains on the metal bonding surface are oriented in the same <1,1,1> orientation. Compared to polycrystalline copper, NTCu is significantly less prone to oxidation and less likely to form copper oxide. NTCu also has a diffusion rate that is typically higher than that of polycrystalline copper by x10³ to x10⁴. Due to these and other characteristics, the bonding temperature and pressure of NTCu are significantly lower than those of polycrystalline copper. Unfortunately, NTCu is not as stable as other crystalline phases of copper, and it has proven challenging to form metal contact surfaces with most of the surface made of NTCu. Contact surfaces formed by electroplating NTCu may also have a high average surface roughness. Rough contact surfaces may reduce the contact area between opposite ends of interconnects and require higher bonding temperatures and pressures to form a sufficient bond between these ends.

[0017] Several embodiments of this technology address the low NTCu coverage and high roughness of the contact surfaces of electroplated NTCu in narrow-pitch, high-aspect-ratio openings formed on a patterned substrate. Several embodiments of this technology include methods for filling and finishing copper-containing materials in narrow-pitch, high-aspect-ratio openings to provide contact surfaces in these materials with a wide range of NTCu and low average surface roughness. These embodiments include electroplating NTCu from the bottom surface of the opening upwards, such that the top of the opening forming the contact surface includes a high proportion of NTCu. These embodiments further include polishing the exposed contact surfaces to reduce their average surface roughness and remove contaminants, such as metal oxides. These embodiments also include forming a barrier layer between the bottom and top of the metal-containing material filling the opening. The barrier layer prevents dilution of non-nano-bicrystalline metal in the bottom and conversion of nano-bicrystalline metal in the top of the opening into other crystalline phases. These embodiments further include forming a second metal layer on the electroplated NTCu contact surface. A second metal layer system is chosen to increase the low-temperature, low-pressure bonding of the opposite ends of the metal interconnects. These and other embodiments of this technology are further described below.

[0018] Figure 1 illustrates a perspective view of an electroplating system 100 capable of performing an NTCu electroplating method according to several embodiments of the present technology. The electroplating system 100 illustrates an exemplary electroplating system including a system head 110 and a bowl 115. During electroplating operations, a wafer can be clamped into the system head 110, flipped, and extended into the bowl 115 to perform the electroplating operation. The electroplating system 100 may include a head lifting member 120, which can be fitted to lift and rotate the system head 110, or otherwise position the system head in the system, including tilting operations. The system head and bowl may be attached to a platform plate 125 or other structure, which may be part of a larger system incorporating multiple electroplating systems 100 and may share electrolytes and other materials. A rotor can provide for the rotation of a substrate clamped in the system head within or outside the bowl during different operations. The rotor may include a contact ring providing conductive contact with the substrate. Further illustrated below, a seal 130 may be connected to the system head. Seal 130 may include a chucked wafer to be processed. Figure 1 illustrates an electroplating system 100, which may include components to be cleaned directly on the platform. In several embodiments, the electroplating system 100 further includes an in-situ rinsing system 135 for component cleaning. In other embodiments (not shown), the electroplating system may be mounted with a platform on which the system head can be moved to an additional module to perform cleaning of seals or other components.

[0019] Figure 2 illustrates a partial cross-sectional view of an electroplating chamber including an electroplating apparatus 200 according to some embodiments of the present technology. The electroplating apparatus 200 can be combined with an electroplating system, including the electroplating system 100 described above. As shown in Figure 2, the electroplating bath container 205 of the electroplating system is illustrated together with a head 210. The head 210 has a substrate 215 coupled to the head. In the illustrated embodiment, the substrate can be coupled to a seal 212 coupled to the head 210. A rinsing frame 220 can be coupled above the electroplating bath container 205 and can be assembled to accommodate the head 210 into the electroplating bath container during electroplating. The rinsing frame 220 may include an rim 225 extending circumferentially around the upper surface of the electroplating bath container 205. A rinsing channel 227 may be defined between the rim 225 and the upper surface of the electroplating bath container 205. For example, edge 225 may include an inner sidewall 230 characterized by a sloping profile. As previously described, rinsing fluid ejected from the substrate may contact the inner sidewall 230 and may be contained in a plenum 235. The plenum 235 extends around the edge for collecting rinsing fluid from the electroplating apparatus 200.

[0020] In several embodiments, the electroplating apparatus 200 may additionally include one or more cleaning elements. These cleaning elements may include one or more nozzles for delivering fluid to or toward the substrate 215 or head 210. Figure 2 illustrates one of several embodiments in which an improved rinsing assembly may be used to protect the plating bath and substrate during rinsing operations. In other embodiments, a side cleaning nozzle 250 may extend through the edge 225 of the rinsing frame 220 and be directed to rinse multiple aspects of the seal 212 and the substrate 215.

[0021] Several embodiments of the above-described system and chamber can be used to perform several embodiments of the present NTCu electroplating method. Figure 3 illustrates a schematic diagram of exemplary operations in method 300 for electroplating and finishing NTCu-containing materials according to several embodiments of the present technology. One or more operations may also be included before the start of method 300, including pretreatment, deposition, gate formation, etching, polishing, cleaning, or any other operations that may be performed prior to said operations. This method may further include several selected operations, which may be particularly related to or not related to some embodiments of the method according to the present technology. For example, many operations are illustrated to provide a broader scope of the process performed, but are not critical to the present technology or can be performed by alternative methods, as will be further explained below. Method 300 may illustrate several operations illustrated in Figures 4A-4B, the diagrams of which will be used to illustrate the operations of method 300. It will be understood that the diagrams are only partial schematic diagrams, and the substrate may contain any number of additional materials and features with a variety of properties and aspects, as shown in the diagrams. Several embodiments of method 300 may include or may not include selected operations to develop a semiconductor structure as a specific manufacturing operation.

[0022] Several embodiments of method 300 include providing a patterned substrate 400 in operation 305. Figure 4A illustrates a portion of the patterned substrate 400, which may, for example, be included in an intermediate packaging region of a single-die or multi-die (e.g., 3D-IC) integrated circuit package. This portion of the patterned substrate 400 may include at least one opening 404. In several embodiments, the opening 404 may include a bottom surface 406 and one or more sidewall surfaces 408. In a further embodiment, the opening 404 may be a trench, forming part of an NTCu-containing conductive line, such as a redistribution line in the intermediate packaging region. In other embodiments, the opening 404 may be a via, forming an NTCu-containing conductive via or pillar. In still other embodiments, the opening 404 may include one or more grooves, steps, or other types of structures such as isolation structures.

[0023] In several embodiments, the patterned substrate 400 may include a dielectric layer 402, in which openings 404 may be formed. In the embodiment illustrated in Figure 4A, the opening 404 terminates in the dielectric layer 402 to leave a bottom surface 406 of the opening. The bottom surface 406 is formed by the exposed surface of the dielectric layer 402. These openings may include trenches forming part of a conductive line containing NTCu, such as a redistribution line. In other embodiments (not shown), one or more openings may extend through the dielectric layer and terminate in an underlying conductive layer, such as a pad. In these embodiments, the bottom surface forming the opening replaces the dielectric layer. These openings may include columnar vias and pillars electrically connected to metal lines and layers in a vertically separating plane.

[0024] In several embodiments, the opening 404 may be characterized by a distance of less than or about 100 µm, less than or about 75 µm, less than or about 50 µm, less than or about 40 µm, less than or about 30 µm, less than or about 20 µm, less than or about 10 µm, less than or about 5 µm, less than or about 4 µm, less than or about 3 µm, less than or about 2 µm, less than or about 1 µm, or less. In other embodiments, the opening 404 may be characterized by an aspect ratio greater than or approximately 0.25:1, greater than or approximately 0.5:1, greater than or approximately 0.75:1, greater than or approximately 1:1, greater than or approximately 2:1, greater than or approximately 3:1, greater than or approximately 4:1, greater than or approximately 5:1, greater than or approximately 6:1, greater than or approximately 7:1, greater than or approximately 8:1, greater than or approximately 9:1, greater than or approximately 10:1, or more.

[0025] In other embodiments, the patterned substrate 400 may be formed by depositing and patterning photoresist on at least one dielectric material layer, and etching the at least one opening into the dielectric material layer via the patterned photoresist. In other embodiments, the patterned substrate 400 may be formed in at least one semiconductor material layer. In further embodiments, the at least one dielectric material layer may include silicon oxide, silicon nitride, silicon-carbon-nitride, or other dielectric materials such as organic polymers (e.g., benzocycloalkane). In still further embodiments, the at least one semiconductor material layer may include other semiconductor materials such as silicon, germanium, or gallium arsenide.

[0026] In other embodiments, the patterned substrate 400 may include a barrier layer 410 to limit the diffusion of the filler material or its interaction with the underlying substrate. In several embodiments, the barrier layer 410 may include one or more of other barrier layer materials such as refractory metal, metal oxide, or metal nitride. In other embodiments, the barrier layer 410 may include one or more of tantalum, titanium, or tantalum nitride. In still other embodiments, the barrier layer 410 may facilitate the deposition of the seed layer 415 and may also be an adhesive layer or include an adhesive layer to facilitate the formation of the seed layer.

[0027] Several embodiments of method 300 also include forming a seed layer 415 in operation 310. In several embodiments, the seed layer 415 may be deposited at the same rate on all inner surfaces of the opening 404, including the bottom surface 406 and the sidewall surface 408. In a further embodiment, the seed layer 415 may be a conformal layer having the same thickness on both the bottom surface 406 and the sidewall surface 408. In several embodiments, the seed layer 415 may be formed by other deposition techniques such as physical vapor deposition or atomic layer deposition. In other embodiments, the seed layer 415 may include the same material as electroplated into the opening 404. In a further embodiment, the seed layer 415 may include NTCu.

[0028] In other embodiments, the seed layer 415 may be formed to a thickness of less than or about 100 nm, less than or about 50 nm, less than or about 25 nm, less than or about 10 nm, less than or about 5 nm, or less. In a further embodiment, the seed layer 415 may be formed in a manner that covers a specific area of ​​the opening 404, such as a bottom corner or a sidewall surface 408 near the bottom surface 406 of the opening. In a further embodiment, the seed layer 415 is thin enough to avoid pinching-off at the top of the opening. Pinching-off at the top of the opening may hinder or impede the electrodeposition of NTCu-containing material into the opening by slowing or blocking the NTCu-containing electrochemical plating solution from reaching the bottom of the opening 404. It will be understood that the structural features of the opening 404, including other structural features such as the aspect ratio of the opening spacing dimension, are not intended to be considered limiting, and any other type of patterned substrate 400 including the seed layer material is included in a similar manner. Other examples of patterned substrates may include two-dimensional and three-dimensional patterned substrates commonly used in semiconductor manufacturing, and openings or other features may be formed in the patterned substrate, and a seed layer may be deposited along the patterned substrate. Furthermore, while patterned substrates including openings with high aspect ratios can benefit from this technology, this technology can also be applied to openings with lower aspect ratios and other structures.

[0029] Several embodiments of method 300 may further include removing one or more contaminants from the as-deposited seed layer 415 in operation 315. In other embodiments, the one or more contaminants may include metal oxides formed on the surface of the seed layer 415 exposed to oxygen in an aqueous electrochemical plating solution or directly exposed to air. In further embodiments, these metal oxides may include copper oxide, such as copper dioxide (CuO 2), which may be formed at least partially by oxidation of copper metal in the seed layer 415. In more embodiments, contaminants may be removed by contacting the as-deposited seed layer 415 with an etchant bath. In several embodiments, the etchant bath may include an aqueous solution of an inorganic acid, such as hydrochloric acid or sulfuric acid. In other embodiments, the etchant bath may include a corrosion inhibitor, such as benzotriazole. In a further embodiment, contaminants can be removed by plasma, such as oxygen-containing etching plasma for removing organic materials, argon- and / or nitrogen-containing plasma for exposing the pristine surface, or hydrogen-containing plasma for reducing surface oxides on metal surfaces, and other types of plasma.

[0030] Several embodiments of method 300 may further include, in operation 320, electroplating an NTCu-containing material (e.g., a first portion 420 of a copper-containing material) into at least one opening 404 of the patterned substrate 400. In some embodiments, the electroplating operation may more preferably include, in operation 325, interrupting the electroplating operation to form a barrier layer 425 on the first portion of the electroplated material. In these embodiments, method 300 includes electroplating the first portion 420 of the copper-containing material in the bottom of the opening 404, forming the barrier layer 425 on the first portion of the copper-containing material, and electroplating the second portion 430 of the copper-containing material in the top of the opening. In other embodiments, the barrier layer 425 prevents the dilution of the first portion 420 of the copper-containing material and the conversion of the NTCu in the second portion 430 of the copper-containing material into a non-nano bicrystalline phase of copper. By integrating the barrier layer 425 into the copper-containing filler of the opening 404, the first portion 420 of the copper-containing material electroplated at the bottom of the opening can be completed quickly, and the first portion 420 of the copper-containing material can have more polycrystalline copper and less NTCu than the second portion 430 of the copper-containing material. The barrier layer 425 also provides a new bottom surface for the opening 404, which is higher than the original bottom surface 406 in the opening. The second portion 430 of the copper-containing material is electroplated in a shallower opening with a lower aspect ratio than the original opening 404. This allows the electroplating of the second portion 430 of the copper-containing material to have more bottom-up characteristics, reducing the influence of polycrystalline copper from the sidewall surface 408 on NTCu.

[0031] In other embodiments, the barrier layer 425 may be made of a conductive material that does not substantially increase the resistance of the copper-containing material filling the opening 404, such as a metal other than copper. In further embodiments, the barrier layer may be made of one or more metals, such as gallium, silver, gold, or other metals such as platinum. In more embodiments, the barrier layer 425 may be a thinner layer deposited by other deposition techniques such as physical vapor deposition or atomic layer deposition. The barrier layer 425 may have a thickness of less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or about 10 nm, less than or about 5 nm, or less.

[0032] In other embodiments, the first portion 420 of the copper-containing material can be electroplated at a first deposition rate faster than the second deposition rate for electroplating the second portion 430 of the copper-containing material. In a further embodiment, the first deposition rate for the first portion 420 of the copper-containing material can be greater than or about 10% faster than the second deposition rate for the second portion 430 of the copper-containing material. In still other embodiments, the percentage difference between the first and second deposition rates can be greater than or about 15%, greater than or about 20%, greater than or about 25%, greater than or about 30%, greater than or about 35%, greater than or about 40%, greater than or about 45%, greater than or about 50%, or more. In more embodiments, the electroplating rate for the first portion 420 of the copper-containing material can be greater than or about 0.5 µm / min, greater than or about 0.75 µm / min, greater than or about 1 µm / min, greater than or about 1.25 µm / min, greater than or about 1.5 µm / min, or higher. In further embodiments, the electroplating of the first portion 420 of the copper-containing material may continue until the aspect ratio of the partially filled opening reaches less than or about 2:1, less than or about 1.5:1, less than or about 1:1, less than or about 0.5:1, or less. In still other embodiments, the electroplating operation during the first period may include delivering a continuous positive current from a DC power supply to the patterned substrate 400. In still other embodiments, the initially plated first portion 420 of the copper-containing material may include less than or about 25 wt.% NTCu, less than or about 20 wt.% NTCu, less than or about 15 wt.% NTCu, less than or about 10 wt.% NTCu, less than or about 5 wt.% NTCu, less than or about 1 wt.% NTCu, or less.

[0033] In other embodiments, the second portion 430 of the copper-containing material formed in the top of the opening 404 may be electroplated at a second deposition rate of less than or about 1 µm / min, 0.9 µm / min, less than or about 0.8 µm / min, less than or about 0.7 µm / min, less than or about 0.6 µm / min, less than or about 0.5 µm / min, or less. In still other embodiments, the second portion 430 of the copper-containing material may include greater than or about 50 wt.% NTCu, greater than or about 55 wt.% NTCu, greater than or about 60 wt.% NTCu, greater than or about 65 wt.% NTCu, greater than or about 70 wt.% NTCu, greater than or about 75 wt.% NTCu, greater than or about 80 wt.% NTCu, greater than or about 85 wt.% NTCu, greater than or about 90 wt.% NTCu, or more.

[0034] In other embodiments, the electroplating operation 320 may include pulse-transmitting the surface of the electroplating substrate and removing the positive and reverse currents of the electroplating from the surface of the substrate to the patterned substrate. In some embodiments of the electroplating operation 320, which further includes forming a barrier layer 425 in operation 325, the pulse-transmitting of the positive and reverse currents may be limited to the electroplating of the second portion 430 containing copper material. In other embodiments where the barrier layer 425 is not formed, the pulse-transmitting of the positive and reverse currents may be used in all portions of the electroplating operation 320. In the following description of pulse-transmitting the positive and reverse currents to the patterned substrate, the bottom surface may refer to the bottom surface 406 where the opening 404 of the barrier layer 425 is not formed, or the bottom surface formed when the barrier layer 425 is formed.

[0035] In several embodiments, the pulsed delivery of forward and reverse currents to the patterned substrate may include a reverse current that removes copper plating from the sidewall surface 408 faster than it removes copper plating from the bottom surface of the opening 404. The continuous cycles of the forward and reverse currents plating more NTCu-containing material on the bottom surface than on the polycrystalline copper on the sidewall surface 408. When the filling has reached the top of the opening 404, most of the copper on the contact surface of the filling has already achieved nano-bicrystalline orientation. In a further embodiment, the contact surface includes NTCu with a surface area greater than or about 50%, greater than or about 55%, greater than or about 60%, greater than or about 65%, greater than or about 70%, greater than or about 75%, greater than or about 80%, greater than or about 85%, greater than or about 90%, or more.

[0036] In several embodiments, a pulsed DC power supply provides a forward current to the patterned substrate 400 of the electrochemical plating solution in the contact plating chamber. In other embodiments, the pulse of the forward current may be characterized by a duty cycle of less than or approximately 50%, less than or approximately 45%, less than or approximately 40%, less than or approximately 35%, less than or approximately 30%, less than or approximately 25%, less than or approximately 20%, or less. In further embodiments, the on-time of the duty cycle may be greater than or approximately 0.5 seconds, greater than or approximately 1 second, greater than or approximately 1.5 seconds, greater than or approximately 2 seconds, greater than or approximately 2.5 seconds, greater than or approximately 3 seconds, greater than or approximately 3.5 seconds, greater than or approximately 4 seconds, greater than or approximately 4.5 seconds, greater than or approximately 5 seconds, or more. In a further embodiment, the forward current may be characterized by an average current density of less than or about 2.0 mA / cm², less than or about 1.5 mA / cm², less than or about 1.0 mA / cm², less than or about 0.5 mA / cm², or less. In more embodiments, the forward current may be characterized by a peak current during the operating time greater than or about 0.5 A, and may be greater than or about 1.0 A, greater than or about 1.5 A, greater than or about 2.0 A, greater than or about 2.5 A, greater than or about 3.0 A, greater than or about 3.5 A, greater than or about 4.0 A, greater than or about 4.5 A, greater than or about 5.0 A, or higher. In still more embodiments, the peak current may be characterized by a peak current density greater than or about 2 mA / cm², and may be greater than or about 5 mA / cm², greater than or about 10 mA / cm², greater than or about 20 mA / cm², greater than or about 50 mA / cm², or higher.

[0037] In other embodiments, after the forward current is transmitted, a reverse current is transmitted to the patterned substrate 400. In several embodiments, the reverse current may be transmitted via the same pulsed DC power supply that transmitted the forward current or via a different power supply. The reverse current removes a portion of the copper plated on the patterned substrate 400 during the transmission of the forward current. In more embodiments, the reverse current removes less than or about 50 wt.% of the copper plated during the aforementioned transmission of the forward current. In still more embodiments, the reverse current removes less than or about 45 wt.%, less than or about 40 wt.%, less than or about 35 wt.%, less than or about 30 wt.%, less than or about 25 wt.%, less than or about 20 wt.%, less than or about 15 wt.%, less than or about 10 wt.%, less than or about 5 wt.%, or less of the previously plated copper. As described above, the copper plated that is removed from the sidewall surface 408 by the reverse current is greater than the copper plated that is removed from the bottom surface of the opening 404. In several embodiments, the difference in the total amount of copper plated that is removed from the sidewall surface and the bottom surface may be greater than or about 5%, greater than or about 10%, greater than or about 15%, greater than or about 20%, greater than or about 25%, greater than or about 30%, greater than or about 35%, greater than or about 40%, greater than or about 45%, greater than or about 50%, or more.

[0038] In some embodiments, the reverse current may be a pulsed current having the same or similar average and peak current densities as the forward current, and a shorter operating time during its duty cycle. In other embodiments, the reverse current may be a pulsed current having lower average and peak current densities than the forward current, and the same or similar operating time during a comparable duty cycle. In a further embodiment, the pulse of the reverse current may be characterized by a duty cycle of less than or about 50%, less than or about 45%, less than or about 40%, less than or about 35%, less than or about 30%, less than or about 25%, less than or about 20%, or less. In a further embodiment, the operating time of the duty cycle may be less than or about 100 milliseconds, less than or about 90 milliseconds, less than or about 80 milliseconds, less than or about 70 milliseconds, less than or about 60 milliseconds, less than or about 50 milliseconds, less than or about 40 milliseconds, less than or about 30 milliseconds, less than or about 20 milliseconds, less than or about 10 milliseconds, or less. In further embodiments, the reverse current may be characterized by an average current density of less than or about 2.0 mA / cm², less than or about 1.5 mA / cm², less than or about 1.0 mA / cm², less than or about 0.5 mA / cm², or lower. In still more embodiments, the reverse current may be characterized by a peak current density greater than or about 2 mA / cm², and may be greater than or about 5 mA / cm², greater than or about 10 mA / cm², greater than or about 20 mA / cm², greater than or about 50 mA / cm², or higher.

[0039] In further embodiments, the number of cycles of forward and reverse currents transmitted to the patterned substrate 400 of the electrochemical plating solution in the contact plating chamber is determined by the total amount of pure NTCu plated after each cycle and the copper-containing material filling the opening 404. In several embodiments, the number of cycles may be greater than or approximately 1 cycle, greater than or approximately 2 cycles, greater than or approximately 3 cycles, greater than or approximately 4 cycles, greater than or approximately 5 cycles, greater than or approximately 6 cycles, greater than or approximately 7 cycles, greater than or approximately 8 cycles, greater than or approximately 9 cycles, greater than or approximately 10 cycles, greater than or approximately 15 cycles, greater than or approximately 20 cycles, or more. In further embodiments, the overall electroplating rate of the NTCu-containing material may be characterized by a deposition rate greater than or about 0.1 µm / min, greater than or about 0.2 µm / min, greater than or about 0.3 µm / min, greater than or about 0.4 µm / min, greater than or about 0.5 µm / min, greater than or about 0.6 µm / min, greater than or about 0.7 µm / min, greater than or about 0.8 µm / min, greater than or about 0.9 µm / min, greater than or about 1 µm / min, or more.

[0040] In several embodiments, during the electroplating operation, the electrochemical plating solution contacting the patterned substrate 400 may be an aqueous solution including copper ions. In further embodiments, the concentration of copper ions may be greater than or about 0.1 M, greater than or about 0.2 M, greater than or about 0.3 M, greater than or about 0.4 M, greater than or about 0.5 M, greater than or about 0.6 M, greater than or about 0.7 M, greater than or about 0.8 M, greater than or about 0.9 M, greater than or about 1 M, or more. In more embodiments, copper ions may be provided by water-soluble copper-containing salts, such as copper sulfate and copper chloride, or other copper-containing salts. In other embodiments, the electrochemical plating solution may have a pH greater than or about 2, greater than or about 3, greater than or about 4, greater than or about 5, greater than or about 6, greater than or about 7, greater than or about 8, greater than or about 9, greater than or about 10, greater than or about 11, greater than or about 12, or more. In other embodiments, the pH of the electrochemical plating solution can be adjusted by an acid, such as sulfuric acid or hydrochloric acid. In a further embodiment, the electrochemical plating solution may include one or more other compounds to facilitate the plating of NTCu-containing materials, such as one or more thickening agents, one or more surfactants, one or more accelerators, one or more levelers, one or more suppressors, and one or more polarizers.

[0041] Several embodiments of method 300 may further include polishing the contact surface of the NTCu-containing material in operation 330. In several embodiments, polishing the contact surface may include chemical-mechanical-polishing (CMP) to reduce average surface roughness and remove surface contaminants. In other embodiments, polishing the contact surface may include electropolishing the surface by oxidizing and dissolving serrated portions of the surface in an electropolishing medium. In a further embodiment, polishing operation 330 may include a combination of CMP and electropolishing. In a still further embodiment, polishing operation 330 may reduce the average surface roughness of the initially plated NTCu-containing material contact surface by more than or about 10%, more than or about 20%, more than or about 30%, more than or about 40%, more than or about 50%, or more. In a further embodiment, the polishing operation 330 can reduce the average surface roughness of the contact surface by at least or about 10 nm, less than or about 7.5 nm, less than or about 5 nm, less than or about 2.5 nm, less than or about 1 nm, or less.

[0042] In several embodiments, CMP operations that smooth the surface roughness to the aforementioned level often leave concave or dish-shaped surfaces where the center height of the polished surface is lower than the surrounding height. In direct copper-to-copper binding operations, the concave surface may leave a gap in the middle of the interconnect ends. The gap may create a smaller contact area between the opposite ends of the interconnect and reduce conductivity through the interconnect structure. On the other hand, the large amount of NTCu present in the polished surface at room temperature can transform the concave profile into a flatter profile during temperature-increasing bonding operations. The transformation from a concave profile to a flat profile occurs due to the thermal expansion of the NTCu-containing material, which is more limited around the contact surface than at the center. In other embodiments, during temperature-increasing bonding operations, the thermal expansion of the center of the polished NTCu-containing material, which is greater than the surrounding area, can reduce the difference between the center and the surrounding area of ​​the polished surface to less than or about 100 nm, less than or about 50 nm, less than or about 25 nm, less than or about 10 nm, less than or about 5 nm, less than or about 1 nm, or less.

[0043] In several embodiments, the CMP operation for polishing the contact surface of the NTCu-containing material may include contacting the surface with a CMP pad containing an abrasive slurry. In further embodiments, the abrasive slurry may include chemical additives and specific abrasives. In other embodiments, the chemical additives may include oxidants (e.g., hydrogen peroxide, potassium ferricyanide, and other oxidants such as ferric chloride) to form a removable oxide film on the contact surface. In further embodiments, the chemical additives may include inhibitors and complexing agents (e.g., benzotriazole and ammonia) to affect the formation and removal rates of the oxide film from the contact surface.

[0044] In some embodiments, method 300 may also optionally include forming a second metal layer on the contact surface containing the NTCu material at operation 335. The second metal layer may include one or more copper-free metals that may further enhance the bonding formation of copper-to-copper joints on the NTCu-containing contact surface. In several embodiments, the second metal layer may include increasing the diffusion rate of NTCu in the contact surface by greater than or about 10%, greater than or about 25%, greater than or about 50%, greater than or about 75%, greater than or about 100%, or more. In more embodiments, the second metal layer may include one or more non-copper metals, such as gallium, silver, gold, or other metals such as platinum. In further embodiments, the second metal layer may have a thickness of less than or about 100 nm, less than or about 50 nm, less than or about 25 nm, less than or about 10 nm, or less. In still further embodiments, the second metal layer may be formed on the contact surface by other deposition techniques such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0045] The completed surface contact system containing NTCu material is characterized by increasing copper-to-copper bonding properties, for example, by bonding temperature and bonding pressure. In several embodiments, the bonding temperature of the copper-to-copper contact may be less than or about 200°C, less than or about 190°C, less than or about 180°C, less than or about 170°C, less than or about 160°C, less than or about 150°C, less than or about 140°C, less than or about 130°C, less than or about 120°C, less than or about 110°C, less than or about 100°C, or less. In a further embodiment, when the opposing contact surfaces are pressed together, the bonding pressure may be less than or about 10 MPa, less than or about 7.5 MPa, less than or about 5 MPa, less than or about 2.5 MPa, less than or about 1 MPa, or less.

[0046] Several embodiments of this technology provide contact surfaces comprising nanowin-phase copper (NTCu) for use in many types of integrated circuit structures, including high-density interconnects, vias, and other types of metal-containing IC structures such as pillars. These embodiments address the problems of forming and stabilizing contact surfaces by using a high proportion of the contact area made of NTCu. These embodiments include several methods that facilitate the electroplating of nanowin-phase copper onto the top of openings in a patterned substrate and slow the transformation of NTCu into other crystalline phases, such as polycrystalline copper. Several embodiments of this technology also include polishing the contact surface containing NTCu material to reduce surface roughness and remove oxides and other contaminants that reduce the bonding efficiency of the contact surface. Several embodiments of this technology further include forming a second, non-copper metal layer on the contact surface to further increase the surface bonding efficiency. These and other embodiments of this technology provide NTCu-containing contact surfaces with significantly improved bonding efficiency compared to conventional copper contact surfaces that primarily comprise polycrystalline copper.

[0047] In the foregoing description, numerous details have been set forth for illustrative purposes to provide an understanding of several embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without certain details or with the need for additional details. For example, other substrates that may be advantageous for the described wet processing techniques may be used with the present technology.

[0048] Given that several embodiments have been disclosed, those skilled in the art will understand that several modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some known processes and components have not been described to avoid unnecessarily obscuring the scope of the art. Therefore, the above description should not be construed as limiting the scope of the art.

[0049] It will be understood that, unless the context explicitly specifies otherwise, when a numerical range is provided, the smallest fraction of each intermediate value between the upper and lower limits of that range to the lower limit unit is also explicitly disclosed. Any narrower range between any stated or unstated intermediate values ​​within the stated range, and any other stated or intermediate values ​​within this stated range, are included. The upper and lower limits of these smaller ranges may be independently included or excluded from the range, and ranges that include any one restriction, have no restrictions, or have both restrictions are also included in this technique, but are still subject to any explicitly excluded restrictions within the range. Where a stated range includes one or two restrictions, ranges that do not include any one or both of those restrictions are also included. Where multiple values ​​are provided in a list, any ranges that include or are based on those values ​​are similarly specifically disclosed.

[0050] As used herein and in the appended claims, unless otherwise expressly provided, the singular forms of "a," "an," and "the" include the plural forms. Thus, for example, reference to "a material" includes several such materials, and reference to "the period of time" includes one or more periods of time known to those skilled in the art and their equivalents.

[0051] Furthermore, when used in this specification and in the claims below, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including" are intended to refer to the presence of the stated features, integers, elements, or operations, but they do not exclude the presence or addition of one or more other features, integers, elements, operations, actions, or groups. In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0012] Further understanding of the nature and advantages of the disclosed embodiments can be achieved by referring to the remainder of the specification and the drawings. Figure 1 illustrates a perspective view of an electroplating system according to some embodiments of the present technology. Figure 2 illustrates a partial cross-sectional view of an electroplating system according to some embodiments of the present technology. Figure 3 illustrates an exemplary operation in an electroplating method according to some embodiments of the present technology. Figures 4A-4B illustrate cross-sectional views of a patterned substrate performing electroplating of a nano-bicrystalline copper material according to some embodiments of the present technology. Several figures are included for illustrative purposes. It will be understood that the figures are for illustrative purposes and should not be considered to be to scale unless specifically stated otherwise. In addition, the figures are provided for illustrative purposes and may not include all aspects or information compared to actual representations, and may include exaggerated material for illustrative purposes. In the figures, similar elements and / or features may have the same element reference symbols. Furthermore, elements of the same kind may be distinguished by adding letters after the reference symbol to distinguish similar elements and / or features. If only the preceding numerical reference symbol is used in the specification, the specification applies to any similar element and / or feature having the same preceding numerical reference symbol, regardless of the letter in the suffix.

Claims

1. An electroplating method, comprising: Electroplating a metal material into at least one opening in a patterned substrate, wherein at least a portion of the metal material is characterized by a nanotwin crystal structure; and polishing an exposed surface of the metal material in the at least one opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm, wherein the polished exposed surface includes at least a portion of the metal material characterized by the nanotwin crystal structure; wherein the metal material includes a first portion and a second portion, the first portion contacting a bottom surface of the at least one opening that does not contain the nanotwin crystal structure, and the second portion contacting the polished exposed surface that includes the nanotwin crystal structure; the patterned substrate further includes a barrier layer located between the first portion and the second portion of the metal material in the at least one opening.

2. The electroplating method as described in claim 1, wherein the metal material characterized by the nano-bicrystalline structure is nano-bicrystalline copper.

3. The electroplating method as described in claim 2, wherein the metal material comprises at least one second metal selected from the group consisting of gallium, silver, gold, and platinum.

4. The electroplating method as described in claim 1, wherein the exposed surface of the metal material is polished using chemical mechanical polishing.

5. The electroplating method as described in claim 1, wherein the exposed surface of the metal material is further polished using electropolishing.

6. The electroplating method as claimed in claim 1, wherein the polishing of the exposed surface of the metal material is performed in an oxygen-free environment, and wherein the polishing removes one or more metal oxides from the exposed surface of the metal material.

7. An electroplating method, comprising: Electroplating a first portion of a metallic material on the bottom of at least one opening in a patterned substrate, wherein the first portion of the metallic material is substantially without a nano-bicrystalline structure; forming a barrier layer on the first portion of the metallic material; and electroplating a second portion of the metallic material on the barrier layer, wherein the second portion of the metallic material is characterized by a nano-bicrystalline structure.

8. The electroplating method as claimed in claim 7, wherein the first portion of the metal material is greater than or approximately 50 wt. of the total amount of the metal material in the at least one opening.

9. The electroplating method as described in claim 7, wherein the metal material is copper.

10. The electroplating method as claimed in claim 9, wherein the second portion of the metallic material comprises at least one second metal selected from the group consisting of gallium, silver, gold, and platinum.

11. The electroplating method as claimed in claim 7, wherein the barrier layer comprises a metal that is not included in the second portion of the metal material.

12. The electroplating method as claimed in claim 7, wherein the electroplating method further comprises polishing an exposed surface of the second portion of the metal material in the at least one opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm.

13. An integrated circuit device structure, comprising: A patterned substrate includes at least one opening, wherein the at least one opening includes a top surface and a bottom surface; The patterned substrate further includes a metal-containing material filling the top of at least one opening, wherein the metal-containing material includes an exposed surface having an average surface roughness of less than or about 1 nm, and wherein the metal-containing material is characterized by a nano-bicrystalline structure; wherein the patterned substrate further includes a barrier layer located between a second portion of the metal-containing material filling the top of the at least one opening and the metal-containing material contacting the bottom surface of the at least one opening.

14. The integrated circuit device structure as described in claim 13, wherein the second portion containing the metallic material does not have the nano-bicrystalline structure.

15. The integrated circuit device structure as described in claim 13, wherein the metallic material includes copper.

16. The integrated circuit device structure as claimed in claim 15, wherein the metal-containing material in the top of the at least one opening includes at least one second metal selected from the group consisting of gallium, silver, gold, and platinum.

17. The integrated circuit device structure as claimed in claim 13, wherein the at least one opening is characterized by a depth-to-width ratio greater than or approximately 1:1.

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