High electron mobility transistor and method for fabricating the same

Abstract

This invention discloses a method for fabricating a high electron mobility transistor (HEMT). The method mainly involves first forming a buffer layer on a substrate, then forming a barrier layer on the buffer layer, forming a P-type semiconductor layer on the barrier layer, forming a gate electrode layer on the P-type semiconductor layer, and then patterning the gate electrode layer to form a gate electrode, wherein the gate electrode includes an inclined sidewall.

Description

Technical Field

[0001] The present invention relates to a high electron mobility transistor and a manufacturing method thereof. Prior Art

[0002] High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) materials offer numerous advantages in electronic, mechanical, and chemical properties, including wide bandgap, high breakdown voltage, high electron mobility, large elastic modulus, high piezoelectric and piezoresistive coefficients, and chemical passivity. These advantages make GaN-based materials suitable for the fabrication of devices such as high-brightness light-emitting diodes, power switches, regulators, battery protectors, panel display drivers, and communications components. Summary of the Invention

[0003] One embodiment of the present invention discloses a method for fabricating a high electron mobility transistor (HEMT), which primarily comprises forming a buffer layer on a substrate, then forming a barrier layer on the buffer layer, forming a P-type semiconductor layer on the barrier layer, forming a gate electrode layer on the P-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode, wherein the gate electrode includes a sloped sidewall. Simple diagram description

[0004] FIG1 to FIG4 are schematic diagrams of a method for manufacturing a high electron mobility transistor according to an embodiment of the present invention. Implementation Method

[0005] Please refer to Figures 1 to 4, which are schematic diagrams of a method for fabricating a high electron mobility transistor according to one embodiment of the present invention. As shown in Figure 1, a substrate 12 is first provided, such as a substrate composed of silicon, silicon carbide, or aluminum oxide (or sapphire). Substrate 12 can be a single-layer substrate, a multi-layer substrate, a gradient substrate, or a combination thereof. According to other embodiments of the present invention, substrate 12 can also include a silicon-on-insulator (SOI) substrate.

[0006] Then, a selective nucleation layer (not shown) and a buffer layer 14 are formed on the surface of the substrate 12. In one embodiment, the nucleation layer preferably comprises aluminum nitride, and the buffer layer 14 comprises a Group III-V semiconductor such as gallium nitride. The thickness of the buffer layer 14 may be between 0.5 microns and 10 microns. In one embodiment, the buffer layer 14 may be formed on the substrate 12 using a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0007] An unintentionally doped buffer layer (not shown) can then be optionally formed on the surface of the buffer layer 14. In this embodiment, the unintentionally doped buffer layer preferably comprises a Group III-V semiconductor, such as gallium nitride, or more specifically, unintentionally doped gallium nitride. In one embodiment, the unintentionally doped buffer layer can be formed on the buffer layer 14 using a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0008] Subsequently, a barrier layer 16 is formed on the surface of the unintentionally doped buffer layer or buffer layer 14. In this embodiment, the barrier layer 16 preferably comprises a III-V semiconductor such as N-type aluminum gallium nitride (AlxGa1-xN), where 0 < x < 1. The barrier layer 16 preferably comprises an epitaxial layer formed by an epitaxial growth process, and the barrier layer 16 may comprise dopants of silicon or germanium. Similar to the manner of forming the buffer layer 14 described above, a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination of the above may be used to form the barrier layer 16 on the buffer layer 14.

[0009] Next, a P-type semiconductor layer 18, a gate electrode layer 20, a hard mask 22, and a patterned mask 24 such as a patterned photoresist are sequentially formed on the barrier layer 16. In one embodiment, the P-type semiconductor layer 18 preferably comprises P-type gallium nitride, and a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination of the above may be used to form the P-type semiconductor layer 18 on the surface of the barrier layer 16.

[0010] According to an embodiment of the present invention, the gate electrode layer 20 preferably consists of Schottky metal, and the gate electrode layer 20 may comprise gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, an electroplating process, a sputtering process, a resistance heating evaporation process, an electron beam evaporation process, a physical vapor deposition (PVD) process, a chemical vapor deposition process (CVD), or a combination of the above may be used to form a conductive material as the gate electrode layer 20 on the P-type semiconductor layer 18. Additionally, the hard mask 22 preferably comprises a dielectric material such as, but not limited to, silicon nitride.

[0011] Continuing with Figures 2 to 4, Figures 2 to 4 illustrate schematic diagrams of a method for patterning the gate electrode layer 20 using photolithography and etching to form the gate electrode 26 according to one embodiment of the present invention. As shown in Figures 2 to 3, an etching process is first performed using the patterned mask 24 as a mask to remove portions of the hard mask 22 and the gate electrode layer 20, thereby patterning the gate electrode layer 20 to form the gate electrode 26. The etching process performed in this stage preferably utilizes a fluorine-containing gas, such as carbon tetrafluoride (CF4) or sulfur hexafluoride (SF6), to sequentially remove portions of the hard mask 22 and the gate electrode layer 20. The fluorine-containing gas preferably reacts with the P-type semiconductor layer 18 to form a byproduct 28 on the surface of the P-type semiconductor layer 18. Since the byproduct 28 is preferably formed by the reaction of the fluorine-containing gas with the P-type semiconductor layer 18, its composition is preferably composed primarily of gallium (Ga).

[0012] As shown in FIG3 , as the fluorine-containing gas in the etching process removes a portion of the P-type semiconductor layer 18 downward, byproducts 28 cover the top surface and sidewalls of the patterned P-type semiconductor layer 18, such as the top surface of the P-type semiconductor layer 18 on both sides of the gate electrode 26 and the sidewalls of the P-type semiconductor layer 18 directly below the gate electrode 26. Notably, as the byproducts 28 continue to accumulate, the byproducts 28 originally covering the sidewalls of the P-type semiconductor layer 18 directly below the gate electrode 26 accumulate upward and erode the sidewalls of the gate electrode 26 directly above the P-type semiconductor layer 28 in the direction indicated by the arrows, causing the sidewalls of the gate electrode 26 to slightly retract and form inclined sidewalls 30.

[0013] From a structural perspective, the entire gate electrode 26 preferably exhibits a trapezoidal or, more specifically, inverted trapezoidal cross-section at this stage, and the bottom surface or bottom surface width of the gate electrode 26 is preferably smaller than the top surface or top surface width of the gate electrode 26. Furthermore, the angle between the inclined sidewall 30 and the top surface of the P-type semiconductor layer 18 can be preferably between 30 and 70 degrees, or preferably between 40 and 60 degrees. It should also be noted that as the byproducts 28 erode the sidewalls of the gate electrode 26 to form the inclined sidewall 30, the byproducts 28 that were originally accumulated and advanced onto the sidewalls of the gate electrode 26 are preferably consumed simultaneously with the formation of the inclined sidewall 30. In other words, after the byproducts 28 erode the gate electrode 26 to form the inclined sidewall 30, preferably no byproducts 28 remain on the sidewall surface of the gate electrode 26.

[0014] As shown in FIG. 4 , after the fluorine-containing gas has completely patterned the P-type semiconductor layer 18 and exposed the barrier layer 16 on both sides, another etching process can be performed to completely remove the remaining byproducts 28, the patterned mask 24, and the hard mask 22, exposing the top surface of the gate electrode 26. A protective layer 32 can then be optionally formed on the barrier layer 16. Portions of the protective layer 32 on both sides of the gate electrode 26 are removed to form two recesses (not shown). A source electrode 34 and a drain electrode 36 are then formed on either side of the gate electrode 26.

[0015] While the protective layer 32 in this embodiment is illustrated as a single-layer structure, it is not limited thereto. Depending on product requirements, the protective layer 32 may be formed as a single layer or more, such as a double or triple layer. The protective layer 32 may comprise a dielectric material such as silicon oxide, silicon nitride, or aluminum oxide. Furthermore, in this embodiment, the source electrode 34 and the drain electrode 36 are preferably formed of metal. Compared to the gate electrode 26, which is formed of a Schottky metal, the source electrode 34 and the drain electrode 36 are preferably formed of an ohmic contact metal. According to one embodiment of the present invention, the gate electrode 26, the source electrode 34, and the drain electrode 36 may each comprise gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, a conductive material may be formed in the grooves using electroplating, sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof. The electrode material is then patterned using a single or multiple etching steps to form the source electrode 34 and the drain electrode 36. This completes the fabrication of a high electron mobility transistor according to one embodiment of the present invention.

[0016] Generally speaking, in current high-electron-mobility transistors, a potential difference often arises between the Schottky metal of the gate electrode and the underlying P-type semiconductor layer under high forward gate bias operation. Furthermore, the fringing field effect easily forms a reverse channel on the sidewalls of the P-type semiconductor layer, leading to leakage current. To address this issue, the present invention primarily utilizes a fluorine-containing gas to pattern the gate electrode and the P-type semiconductor layer, and uses the accumulation of byproducts on the sidewalls of the P-type semiconductor layer to erode the gate electrode to form a sloped sidewall. According to a preferred embodiment of the present invention, using this method to trim the gate electrode into a roughly inverted trapezoidal shape effectively suppresses leakage current from the gate electrode sidewalls and improves the condition of high-temperature gate bias. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0017] 12: Base 14: Buffer layer 16: Barrier layer 18: P-type semiconductor layer 20: Gate electrode layer 22: Hard Mask 24: Patterned Mask 26: Gate electrode 28: Byproducts 30: inclined side wall 32: Protective layer 34: Source electrode 36: Drain electrode

Claims

1. A method for fabricating a high electron mobility transistor (HEMT), characterized in that it comprises: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a P-type semiconductor layer on the barrier layer, wherein the P-type semiconductor layer comprises P-type gallium nitride; forming a gate electrode layer on the P-type semiconductor layer, wherein the gate electrode layer comprises a rectangular cross-sectional profile; and removing a portion of the gate electrode layer using a gas etching process, patterning the gate electrode layer to form a gate electrode, wherein the gate electrode directly contacts the P-type semiconductor layer, the gate electrode comprises an inclined sidewall, and the gate electrode comprises an inverted trapezoidal cross-section, and the bottom surface area of ​​the gate electrode is smaller than the top surface area of ​​the gate electrode.

2. The method as described in claim 1, wherein the gas etching process is performed to remove a portion of the gate electrode layer to form a byproduct on the surface of the P-type semiconductor layer and to form the inclined sidewall, and the method further includes: removing the byproduct; and forming a source electrode and a drain electrode on both sides of the gate electrode.

3. The method as described in claim 2, wherein the gas etching process comprises fluorine.

4. The method as described in claim 1, wherein the buffer layer comprises gallium nitride (GaN).

5. The method as described in claim 1, wherein the barrier layer comprises aluminum gallium nitride (AlxGa1-xN).

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