Laterally diffused metal-oxide- semiconductor structure

Abstract

The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) structure, comprising a substrate, a plurality of fin structures located on the substrate, a gate structure located on the substrate and spanning the plurality of fin structures, and a gate contact layer located on the gate structure, wherein the gate contact layer is electrically connected to a dummy contact structure.

Description

Technical Field

[0001] This invention relates to semiconductor transistor devices, and more particularly to a laterally diffused metal oxide semiconductor (LDMOS) transistor device having an extended field plate. Prior Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are a common type of power semiconductor. Due to their horizontal structure, LDMOS devices are easy to manufacture and integrate with existing semiconductor technologies, thus reducing manufacturing costs. Furthermore, they can withstand high breakdown voltages and deliver high output power, making them widely used in power converters, power amplifiers, switches, rectifiers, and other components.

[0003] However, traditional LDMOS still has some drawbacks that need improvement, such as high on-resistance (Ron), excessively high turn-off current (Ioff), and insufficient hot carrier injection lifetime. Therefore, more advanced LDMOS structures are needed to address these shortcomings. Summary of the Invention

[0004] The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) structure, comprising a substrate, a plurality of fin structures located on the substrate, a gate structure located on the substrate and spanning the plurality of fin structures, and a gate contact layer located on the gate structure, wherein the gate contact layer is electrically connected to a dummy contact structure.

[0005] The present invention is characterized by forming a gate contact layer on the gate of an LDMOS structure. This gate contact layer acts as a field plate for the LDMOS, effectively dispersing the electric field and suppressing the Kirk effect. Furthermore, the gate contact layer of the present invention is directly connected to a dummy contact structure located on a shallow trench isolation layer. Without adding process steps, the field plate can be further extended, resulting in more dispersed current and improved LDMOS quality. According to the applicant's experimental results, the structure of the present invention contributes to reducing turn-off current (Ioff), reducing on-resistance (Ron), improving hot carrier injection lifetime, and increasing breakdown voltage (Vbd). Simple Explanation of the Diagram

[0006] Figure 1 illustrates a top view of a laterally diffused metal-oxide-semiconductor (LDMOS) according to a first preferred embodiment of the present invention. Figure 2 shows a cross-sectional view obtained from the section line A-A' in Figure 1. Figure 3 shows a cross-sectional view obtained from the section line B-B' in Figure 1. Figure 4 illustrates a top view of a laterally diffused metal-oxide-semiconductor (LDMOS) according to a second preferred embodiment of the present invention. Figure 5 shows a cross-sectional view obtained from the section line C-C' in Figure 4. Implementation

[0007] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0008] For ease of explanation, the various drawings of this invention are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The description of the vertical relationships between relative elements in the drawings should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0009] Figure 1 shows a top view of a laterally diffused metal-oxide-semiconductor (LDMOS) according to a first preferred embodiment of the present invention; Figure 2 shows a cross-sectional view obtained according to section line A-A' in Figure 1; and Figure 3 shows a cross-sectional view obtained according to section line B-B' in Figure 1. As shown in Figures 1, 2, and 3, the LDMOS structure of the first embodiment of the present invention includes a substrate 100, the substrate 100 being made of, for example, a silicon substrate or a silicon on insulation (SOI) substrate. In this embodiment, the substrate 100 has a first conductivity type (e.g., P-type), and multiple fin structures F are formed on the substrate 100 by means of etching or the like. The material of the fin structures F is preferably the same as that of the substrate 100 (e.g., microsilicon), and the multiple fin structures F are arranged parallel to each other along the same direction, for example, parallel to each other along the X-axis in Figure 1. Furthermore, as shown in Figure 2, a first well region W1 and a second well region W2 are formed in the substrate 100 by ion implantation or other methods. The first well region W1 contains, for example, a first conductivity type (e.g., P-type), while the second well region W2 contains a second conductivity type (e.g., N-type). The first well region W1 and the second well region W2 are not in direct contact. As shown in Figure 2, a portion of the substrate 100 remains undoped between the first well region W1 and the second well region W2, serving as a channel region for the subsequent LDMOS. The first well region W1 also contains a source region SR, and the second well region W2 also contains a drain region DR. Both the source region SR and the drain region DR contain a second conductivity type (e.g., N-type), and the doping concentration of the source region SR and the drain region DR is higher than the ion doping concentration of the second well region W2. It is worth noting that the LDMOS in this embodiment is an N-type LDMOS, therefore the substrate 100 and the first well region W1 are P-type, and the second well region W2, the source region SR, and the drain region DR are N-type. However, the present invention is not limited to this. The present invention also includes P-type LDMOS, that is to say, the conduction type of the above-mentioned components is not limited to this embodiment.

[0010] Next, please refer to Figures 1 and 2. The substrate 100 includes a shallow trench isolation (STI), where the STI material is an insulating material such as silicon oxide or silicon nitride, and the fin structure F is exposed. It is worth noting that within the second well region W2, a portion of the fin structure F is truncated and a groove is formed, for example, by etching, before the shallow trench isolation (STI) is formed and filled into the groove. Therefore, as shown in Figure 2, the shallow trench isolation (STI) is also formed within the second well region W2 and extends into a portion of it. This shallow trench isolation (STI) within the second well region W2 allows current (not shown) to flow from the source region SR through the bottom of the shallow trench isolation (STI) to the drain region DR when the LDMOS switch is turned on, extending the current path and thus increasing the LDMOS breakdown voltage (Vbd) and the stability of the LDMOS structure.

[0011] Additionally, the substrate 100 includes an interlayer dielectric layer 101. Multiple gate structures G, dummy gate structures DG, and multiple contact CTs are located within the interlayer dielectric layer 101. The gate structures G and dummy gate structures DG extend across multiple fin structures F along the Y-axis. The material of the gate structures G and dummy gate structures DG is, for example, polycrystalline silicon, but is not limited to this; in other embodiments, it may also be a metallic material. The gate structure G is located on the substrate 100 and extends across the first well region W1 and the second well region W2 along the X-axis, while the dummy gate structure DG is located on the second well region W2. Furthermore, multiple contact structures CTs are formed to electrically connect the source region SR and the drain region DR, respectively, and at least one contact structure is located on the shallow trench isolation STI. For ease of representation, the contact structure CT electrically connected to the source region SR is defined as source contact CT1, the contact structure CT electrically connected to the drain region DR is defined as drain contact CT2, and the contact structure CT located on the shallow trench isolation STI is defined as dummy contact structure CT3, wherein the dummy contact structure CT3 is not actually connected to the electronic component. In this embodiment, the contact structure CT and the dummy contact structure are made of the same material and are preferably fabricated in the same step. In this embodiment, the purpose of forming the dummy contact structure CT3 and the dummy gate structure DG is to improve the uniformity of the pattern during the fabrication process and avoid large differences in pattern density that would affect the quality of pattern generation.

[0012] Next, as shown in Figure 3, a gate contact layer 102 is formed above the gate structure G. The gate contact layer 102 is used for electrical connection to other subsequent contact structures (not shown). It is worth noting that in this embodiment, the gate contact layer 102 is arranged in the same direction as the fin structure F, but the gate contact layer 102 is not located directly above the fin structure F. In other words, the location of the fin structure F can be defined as the active area AA, and the gate contact layer 102 is located outside the active area AA. However, it is worth noting that in other embodiments of the present invention, the gate contact layer 102 may also be located within the active area AA, and this structure is also within the scope of the present invention.

[0013] It is worth noting that in this embodiment, the gate contact layer 102 is also directly connected to the adjacent dummy contact structure CT3. In the actual manufacturing process, after forming the gate structure G and the dummy gate structure DG, grooves for the contact structures CT (including source contact CT1, drain contact CT2, and dummy contact structure CT3) and the gate contact layer 102 can be formed in the interlayer dielectric layer 101, and then a conductive layer is simultaneously filled into these grooves to simultaneously form source contact CT1, source contact CT2, dummy contact structure CT3, and gate contact layer 102. That is, the gate contact layer 102 and the dummy contact structure CT3 can be integrally formed (made of the same material and manufactured in the same step). Furthermore, since both are formed simultaneously, it is preferable that the top surface of the gate contact layer 102 and the top surface of the dummy contact structure CT3 are flush with each other.

[0014] In this embodiment, the gate contact layer 102 can not only be used as a layer for electrically connecting other subsequent contact structures, but also, located on the gate structure G, can form a field plate structure. Here, "field plate" refers to a structure where the gate structure G spans the insulating layer to disperse the electric field. More specifically, when the LDMOS is turned on, the surface electric field at the channel end is concentrated, making it prone to punch-through. After the gate structure G is covered with the gate contact layer 102, the gate contact layer 102 extends the gate structure G, forming a field plate structure, which disperses the electric field and prevents excessive concentration at the channel end, thus avoiding the aforementioned punch-through phenomenon. Furthermore, in this invention, the gate contact layer 102 is directly connected to the dummy contact structure CT3, further extending the field plate and further dispersing the electric field, thereby improving the quality of the LDMOS.

[0015] In this invention, the gate contact layer 102 is directly connected to the dummy contact structure CT3. Compared to embodiments that simply form the gate contact layer 102 and the dummy contact structure CT3 without connecting them, this invention significantly improves the overall performance of the LDMOS. According to the applicant's experimental results, compared to embodiments that do not connect the gate contact layer to the dummy contact structure, this embodiment, by connecting the two, can reduce the turn-off current (Ioff) by approximately 40%, reduce the on-resistance (Ron) by approximately 6%, increase the hot carrier injection lifetime by approximately 20%, and increase the breakdown voltage (Vbd) by approximately 1%. All of these parameters contribute to improving the quality of the LDMOS. In addition, the method used in this embodiment is compatible with existing processes and does not add any additional process steps.

[0016] Figure 4 shows a top view of a laterally diffused metal-oxide-semiconductor (LDMOS) according to a second preferred embodiment of the present invention, and Figure 5 shows a cross-sectional view obtained according to the section line C-C' in Figure 4. This embodiment also proposes an LDMOS structure, and most of the components are the same as those described in the above embodiments, including the substrate 100, fin structure F, first well region W1, second well region W2, shallow trench isolation STI, source region SR, drain region DR, interlayer dielectric layer 101, gate structure G, dummy gate structure DG, source contact CT1, drain contact CT2, dummy contact structure CT3, etc., all of which are the same as those described in the above embodiments and will not be repeated. The difference between this embodiment and the above embodiments is that in this embodiment, the gate contact layer 102 is located directly above the region where the fin structure F is located, that is, directly above the active region AA. Similarly, in this embodiment, the gate contact layer 102 is also directly connected to the adjacent dummy contact structure CT3. As shown in Figure 5, after the gate contact layer 102 is connected to the adjacent dummy contact structure CT3, it presents a cross-sectional structure similar to a right angle, that is, it has two parts: the laterally extending gate contact layer 102 and the longitudinally extending dummy contact structure CT3, and the two are integrally formed. Similar to the above embodiments, the structure of this embodiment also has an extended field plate structure, which can improve the quality of LDMOS. Apart from the above features, the remaining features are the same as those in the above embodiments, and will not be repeated here.

[0017] Based on the above description and figures, the present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) structure, comprising a substrate 100, a plurality of fin structures F located on the substrate 100, a gate structure G located on the substrate 100 and spanning the plurality of fin structures F, and a gate contact layer 102 located on the gate structure G and electrically connected to the gate structure G, wherein the gate contact layer 102 is electrically connected to a dummy contact structure CT3.

[0018] In some embodiments of the present invention, a first well region W1 and a second well region W2 are located in the substrate 100, and a shallow trench isolation STI is located in the second well region W2.

[0019] In some embodiments of the present invention, the dummy contact structure CT3 is located on and in direct contact with the shallow trench isolation STI.

[0020] In some embodiments of the present invention, a source contact (contact structure CT1) is located on a first well region W1, and a drain contact (contact structure CT2) is located on a second well region W2.

[0021] In some embodiments of the present invention, the first well region is P-type and the second well region is N-type.

[0022] In some embodiments of the present invention, the first well region W1 further includes a source region SR, and the second well region W2 further includes a drain region DR.

[0023] In some embodiments of the present invention, the source contact CT1 is electrically connected to the source region SR, and the drain contact CT2 is electrically connected to the drain region DR.

[0024] In some embodiments of the present invention, a dummy gate structure DG is further included, located between the dummy contact structure CT3 and the drain contact CT2.

[0025] In some embodiments of the present invention, the gate structure G spans a portion of the first well region W1 and a portion of the second well region W2, and the dummy contact structure CT3 is located next to the gate structure G.

[0026] In some embodiments of the present invention, the gate contact layer 102 is flush with a top surface of the dummy contact structure CT3.

[0027] In some embodiments of the present invention, the gate contact layer 102 and the plurality of fin structures F both extend along a first direction (e.g., arranged parallel to each other along the X-axis in Figure 1).

[0028] In some embodiments of the invention, the dummy contact structure CT3 extends along a second direction (e.g., the Y-axis in Figure 1), and the first direction is different from the second direction.

[0029] In some embodiments of the present invention, the region where the plurality of fin structures F are located is defined as an active region AA, and the gate contact layer 102 is located outside the active region AA.

[0030] In some embodiments of the present invention, the region where the plurality of fin structures F are located is defined as an active region AA, and the gate contact layer 102 is located within the active region AA.

[0031] In some embodiments of the present invention, the gate contact layer 102 is made of the same material as the dummy contact structure CT3.

[0032] In some embodiments of the present invention, a bottom surface of the dummy contact structure CT3 is lower than a bottom surface of the gate contact layer 102 (as shown in Figure 3 or Figure 5) or a bottom surface of the dummy gate structure DG (as shown in Figure 2).

[0033] The present invention is characterized by forming a gate contact layer on the gate of an LDMOS structure. This gate contact layer acts as a field plate for the LDMOS, effectively dispersing the electric field and suppressing the Kirk effect. Furthermore, the gate contact layer of the present invention is directly connected to a dummy contact structure located on a shallow trench isolation layer. Without adding process steps, the field plate can be further extended, resulting in more dispersed current and improved LDMOS quality. According to the applicant's experimental results, the structure of the present invention contributes to reducing turn-off current (Ioff), reducing on-resistance (Ron), improving hot carrier injection lifetime, and increasing breakdown voltage (Vbd). The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0034] 100: Base 101: Interlayer dielectric layer 102: Gate contact layer AA: Active Zone CT: Contact Structure CT1: Source Contact CT2: Drain Contact CT3: Virtual Contact Structure DG: Virtual gate structure DR: Drainage Zone F: Fin-like structure G: Gate structure SR: Source Region STI: Shallow Trench Isolation W1: First pit region W2: Second trap region

Claims

1. A laterally diffused metal-oxide-semiconductor (LDMOS) structure, comprising: a substrate; a plurality of fin structures located on the substrate; a gate structure located on the substrate and spanning the plurality of fin structures; and a gate contact layer located on the gate structure and electrically connected to the gate structure, wherein the gate contact layer is electrically connected to a dummy contact structure, wherein the dummy contact structure is located on a shallow trench isolation and directly contacts the shallow trench isolation.

2. The laterally diffused metal-oxide-semiconductor structure as described in claim 1, further comprising a first well region and a second well region located in the substrate, and the shallow trench isolation located within the second well region.

3. The laterally diffused metal-oxide-semiconductor structure as described in claim 2, further comprising a source contact located on the first well region and a drain contact located on the second well region.

4. The laterally diffused metal-oxide-semiconductor structure as described in claim 3, wherein the first well region is P-type and the second well region is N-type.

5. The laterally diffused metal-oxide-semiconductor structure as described in claim 3, wherein the first well region further includes a source region and the second well region further includes a drain region.

6. The laterally diffused metal-oxide-semiconductor structure as described in claim 5, wherein the source contact is electrically connected to the source region and the drain contact is electrically connected to the drain region.

7. The laterally diffused metal-oxide-semiconductor structure as described in claim 3, further comprising a dummy gate structure located between the dummy contact structure and the drain contact.

8. The laterally diffused metal-oxide-semiconductor structure as described in claim 2, wherein the gate structure spans a portion of the first well region and a portion of the second well region, and the dummy contact structure is located next to the gate structure.

9. The laterally diffused metal-oxide-semiconductor structure as described in claim 1, wherein the gate contact layer is flush with a top surface of the dummy contact structure.

10. The laterally diffused metal-oxide-semiconductor structure as described in claim 1, wherein the gate contact layer and the plurality of fin structures both extend along a first direction.

11. The laterally diffused metal-oxide-semiconductor structure as described in claim 10, wherein the dummy contact structure extends along a second direction, the first direction being different from the second direction.

12. The laterally diffused metal-oxide-semiconductor structure as described in claim 1, wherein the region where the plurality of fin structures are located is defined as an active region, and the gate contact layer is located outside the active region.

13. The laterally diffused metal-oxide-semiconductor structure as described in claim 1, wherein the region where the plurality of fin structures are located is defined as an active region, and the gate contact layer is located within the active region.

14. The laterally diffused metal-oxide-semiconductor structure as described in claim 1, wherein the gate contact layer is made of the same material as the dummy contact.

15. The laterally diffused metal-oxide-semiconductor structure as described in claim 1, wherein one bottom surface of the dummy contact is lower than one bottom surface of the gate contact layer.

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