Method of forming 3-dimensional spacer

Abstract

A method for processing a substrate includes: loading a substrate having a raised feature and at least two exposed sidewalls in a processing chamber; depositing a first layer over the substrate to cover a first portion of the sidewalls; depositing a second layer over the first layer to cover a second portion of the sidewalls; depositing a third layer over the second layer and the raised feature to cover a third portion of the sidewalls and the top surface of the raised feature; performing an anisotropic dry etching that removes multiple portions of the second and third layers, the remaining portion of the second layer forming a second sidewall spacer, and the remaining portion of the third layer forming a third sidewall spacer; and performing an isotropic etching that selectively removes the second sidewall spacer to expose multiple portions of the sidewalls of the raised feature.

Description

Technical Field

[0001] This invention relates generally to a method for manufacturing semiconductors, and in a particular embodiment, to a method for forming three-dimensional spacers. [Cross-reference to related applications]

[0002] This application asserts the rights of U.S. Provisional Application No. 63 / 239,837, filed on September 1, 2021, which is incorporated herein by reference. Prior Technology

[0003] The semiconductor industry is characterized by a trend toward fabricating larger and more complex circuits on a given semiconductor wafer. These larger and more complex circuits are achieved by shrinking the size of individual components within the circuit and spacing them more closely. Improved electrical performance can be obtained by shrinking the size of individual components within devices such as metal-oxide-semiconductor (MOS) or bipolar transistors and making the device components more compact. However, attention must be paid to the formation of doped regions in the substrate to ensure that harmful electric field conditions are not generated. Summary of the Invention

[0004] According to an embodiment of the present invention, a method for processing a substrate includes: loading a substrate having a raised feature portion and at least two sidewalls exposed on the surface of the raised feature portion in a processing chamber; depositing a first layer over the substrate and adjacent to the raised feature portion, the first layer covering a first portion of the sidewalls; depositing a second layer over the first layer and adjacent to the raised feature portion, the second layer covering a second portion of the sidewalls, wherein the first layer and the second layer comprise different materials; depositing a third layer over the second layer and the raised feature portion, the third layer covering a third portion of the sidewalls and the top surface of the raised feature portion, wherein the second layer and the third layer comprise different materials; performing anisotropic dry etching to remove multiple portions of the second layer and the third layer, the remaining portion of the second layer forming a second sidewall spacer and the remaining portion of the third layer forming a third sidewall spacer; and performing isotropic etching to selectively remove the second sidewall spacers to expose multiple portions of the sidewalls of the raised feature portion.

[0005] According to an embodiment of the present invention, a method for forming a 3D spacer for a semiconductor device includes: loading a substrate having raised features in a processing chamber, the raised features including exposed sidewalls; depositing a first dielectric material on the substrate adjacent to the raised features to cover a first portion of the sidewalls; depositing a second dielectric material on the first dielectric material adjacent to the raised features to cover a second portion of the sidewalls; depositing a third dielectric material on the second dielectric material adjacent to the raised features to cover a third portion of the sidewalls; and repeatedly depositing the second dielectric material and the raised features... The process involves: depositing a third dielectric material to form a layer stack; performing anisotropic dry etching of multiple portions of the layer stack to form a second sidewall spacer containing a first dielectric material and a third sidewall spacer containing a third dielectric material; selectively removing the second sidewall spacer to expose multiple portions of the sidewalls of the raised feature; conformally depositing a dopant layer on the raised feature, with the dopant layer in solid contact with the exposed portions of the sidewalls of the raised feature; and heating the substrate to form a doped region in the raised feature by diffusion of the dopant from the dopant layer into the raised feature.

[0006] According to an embodiment of the present invention, a method of processing a substrate includes: loading a substrate having a raised feature portion and at least two sidewalls exposed on the surface of the raised feature portion in a processing chamber; depositing a first layer over the substrate and adjacent to the raised feature portion, the first layer covering a first portion of the sidewalls; depositing a second layer over the first layer and adjacent to the raised feature portion, the second layer covering a second portion of the sidewalls, wherein the first layer and the second layer comprise different materials; depositing a third layer over the second layer using atomic layer deposition (ALD), the third layer covering a third portion of the sidewalls, the third layer having a chemical composition that varies in a direction perpendicular to the main surface of the substrate; performing an anisotropic dry etching that removes a plurality of portions of the second layer and the third layer, the remaining portion of the second layer forming a second sidewall spacer and the remaining portion of the third layer forming a third sidewall spacer; and performing an isotropic etching that removes a portion of the second sidewall spacer and the third sidewall spacer to expose a plurality of portions of the sidewalls of the raised feature portion. Simple Explanation of the Diagram

[0007] To more fully understand the invention and its advantages, it is now described with reference to the following description in conjunction with the accompanying drawings, wherein:

[0008] Figures 1-8 schematically illustrate the formation of 3D spacers and ultra-shallow doped regions according to embodiments through cross-sectional views. Figure 1 shows an input substrate with raised features; Figure 2 shows a substrate after two layers are deposited around the raised features; Figure 3 shows a substrate after a third layer is deposited to cover the raised features; Figure 4 shows a substrate after an anisotropic dry etching process; Figure 5 shows a substrate after isotropic etching; Figure 6 shows a substrate after a dopant layer is deposited; Figure 7 shows a substrate after heat treatment for solid-state diffusion; and Figure 8 shows a substrate after the remaining portion of the dopant layer is removed.

[0009] Figures 9-14 schematically illustrate, through cross-sectional views, the formation of a plurality of 3D spacers and ultra-shallow doped regions according to another embodiment, wherein Figure 9 shows an input substrate with protruding features covered by alternating layers, Figure 10 shows a substrate after an anisotropic dry etching process, Figure 11 shows a substrate after isotropic etching, Figure 12 shows a substrate after depositing a dopant layer, Figure 13 shows a substrate after heat treatment for solid-state diffusion, and Figure 14 shows a substrate after removing the remaining portion of the dopant layer;

[0010] Figure 15 schematically illustrates, through a cross-sectional view, the subsequent lateral etching of the raised feature portion, which uses the sidewall spacers as an etching mask, following the steps of Figures 9-11 according to an alternative embodiment;

[0011] Figures 16-18 schematically illustrate the formation of a plurality of 3D spacers according to yet another embodiment through cross-sectional views, wherein Figure 16 shows an input substrate having some stacked layers with a gradient in chemical composition, Figure 17 shows a substrate after the formation of 3D spacers with varying thicknesses, and Figure 18 shows a substrate after a subsequent etching process;

[0012] Figures 19A-19F schematically illustrate examples of chemical composition gradients for 3D spacers according to various embodiments through cross-sectional views, wherein Figure 19A shows an initial layer deposited according to one embodiment, Figure 19B shows the shape of the 3D spacer obtained from Figure 19A, Figure 19C shows an initial layer deposited according to another embodiment, Figure 19D shows the shape of the 3D spacer obtained from Figure 19C, Figure 19E shows an initial layer deposited according to yet another embodiment, and Figure 19F shows the shape of the 3D spacer obtained from Figure 19E; and

[0013] Figures 20A-20C show process flow diagrams of methods for forming 3D spacers according to various embodiments, wherein Figure 20A shows one embodiment, Figure 20B shows another embodiment, and Figure 20C shows an alternative embodiment. Implementation

[0014] This application relates to a method for processing substrates, particularly to forming 3D spacers. As the size of device elements, such as transistor gates in MOS devices and emitter regions in bipolar devices, shrinks, the junction depth of doped regions formed in semiconductor substrates must also shrink. It has been shown that forming shallow junctions with uniform doping profiles and high surface concentrations is extremely difficult. A common technique is to use ion implantation equipment to implant dopant atoms into the substrate. Enabling dopant atoms are bombarded at high speeds and driven into the substrate using ion implantation. While this method has proven effective for forming doped regions with moderate junction depths, forming ultra-shallow junctions using ion implantation is extremely difficult. Both the path of the enabling dopant atoms within the substrate and the implantation uniformity are difficult to control at the low energies necessary for forming shallow junctions. The implantation of enabling dopant atoms damages the lattice in the substrate, making repair difficult. Dislocations caused by lattice damage can easily form spikes within the shallow junction area, leading to leakage current within the junction area. Furthermore, the implantation of p-type dopants, such as boron, that rapidly diffuse in silicon leads to over-dispersion of the dopant atoms after they are introduced into the substrate. Consequently, it becomes difficult to form a highly confined concentration of p-type dopant atoms in a specific region of the substrate, particularly on the substrate surface.

[0015] Furthermore, novel device structures utilizing doped three-dimensional transistors and memory devices are being implemented. Examples of such devices include, but are not limited to, FinFETs, three-gate FETs, recessed channel transistors (RCATs), and embedded dynamic random access memory (EDRAM) trenches. To uniformly dope these structures, conformal doping methods are desired. Ion implantation processes effectively act as positioning lines, thus requiring special substrate orientation to uniformly dope fin and trench structures. Moreover, at high device densities, the masking effect makes uniform doping of fin structures extremely difficult or even impossible using ion implantation techniques. Conventional plasma doping and atomic layer doping are known conformal doping techniques that have revealed 3D semiconductor structures, but each of these is limited to the range of dopant densities and depths achievable under ideal conditions.

[0016] Embodiments of the present invention provide a method for forming doped vertical spacers on a 3D structure of a semiconductor device. This method can overcome some of the aforementioned difficulties, for example, through ultra-shallow doped regions in vertical recessed features. Methods for forming ultra-shallow doped regions in a semiconductor device by solid-state diffusion from a dopant layer to raised features on a substrate are disclosed in numerous embodiments. The doped regions may, for example, include ultra-shallow doped regions for FinFETs and three-gate FETs. This method provides vertical spacers on a 3D structure and allows for etching and doping of specific areas of raised features, such as fins, pillars, or trenches defined by vertical or near-vertical sidewalls. While the method is primarily described for embodiments of ultra-shallow doped regions formed by solid-state diffusion, in other embodiments, the method for forming 3D spacers can be used for many other applications.

[0017] In the following description, a method for forming 3D spacers and ultra-shallow doped regions according to one embodiment is described with reference to Figures 1-8. Another embodiment for forming a plurality of 3D spacers is described with reference to Figures 9-14. Another embodiment for a method of using 3D spacers as an etching mask in a subsequent etching process is described with reference to Figures 15-18. Example process flow diagrams are shown in Figures 19A-19C. All figures in this disclosure are for illustrative purposes only and are not drawn to scale (including aspect ratios of features).

[0018] Figures 1-8 schematically show, through cross-sectional views, the formation of 3D spacers and ultra-shallow doped regions according to the embodiments.

[0019] Figure 1 shows a schematic cross-sectional view of an input structure 1 including a substrate 100 and a raised feature 110. In many embodiments, the substrate 100 may be part of or include a semiconductor device and may undergo processing steps following, for example, conventional processes. Therefore, the substrate 100 may include a semiconductor stack that facilitates various microelectronic devices. For example, a semiconductor structure may include a substrate 100 in which various device regions are formed. The substrate 100 may have any size, such as a 200 mm substrate, a 300 mm substrate, or even a larger substrate. According to one embodiment, the substrate 100 and the raised feature 110 may contain Si, such as crystalline Si, polycrystalline Si, or amorphous Si. In one example, the substrate 100 may be a tensile strained Si layer. According to another embodiment, the substrate 100 may contain Ge or a Si xGe 1-x compound, where x is the atomic fraction of Si, 1-x is the atomic fraction of Ge, and 0 < x < 1. Example Si xGe 1-x compounds include Si 0.1Ge 0.9, Si 0.2Ge 0.8, Si 0.3Ge 0.7, Si 0.4Ge 0.6, Si 0.5Ge 0.5, Si 0.6Ge 0.4, Si 0.7Ge 0.3, Si 0.8Ge 0.2, and Si 0.9Ge 0.1. In one example, substrate 100 may be a compressive strain Ge layer or a tensile strain Si xGe 1-x layer (x > 0.5) deposited on a relaxed Si 0.5Ge 0.5 buffer layer. According to some embodiments, substrate 100 may include silicon-on-insulator (SOI). Additionally, substrate 100 may include compound semiconductors such as GaAs, GaN, InP, InSb, InAs, InGaAs, and InGaSb. In many embodiments, the substrate 100 may be patterned or embedded in other elements of the semiconductor device.

[0020] Referring again to FIG. 1, the raised feature 110 may comprise a fin-like structure having a height between 50 nm and 60 nm and a width between 3 nm and 8 nm, but other dimensions may be used in other embodiments. In several embodiments shown in FIG. 1, a selective cap layer 108 may be located on top of the raised feature 110. The cap layer 108 may be, for example, an oxide layer, a nitride layer, or an oxide oxynitride layer. In several embodiments, the selective cap layer 108 may be a hard mask that has been used to fabricate the raised feature 110 and / or will be used in anisotropic etching processes during the formation of 3D spacers. In one or more embodiments, the cap layer 108 may be 10-40 nm thick, but various thicknesses may be selected depending on the specific integration process. Additionally, in many embodiments, the raised feature 110 has at least two exposed sidewalls 117, wherein one or more 3D spacers may be formed by the steps described below.

[0021] Figure 2 shows the substrate 100 after two layers are deposited around the protruding feature 110.

[0022] In Figure 2, a first layer 102 may be deposited on a substrate 100 adjacent to the raised feature 110. In many embodiments, the first layer 102 may cover a portion of the sidewalls 117 near the bottom as shown in Figure 2. The first layer 102 may be 10-50 nm thick, but in some embodiments, the first layer 102 may be thicker (e.g., 100 nm) when the raised feature 110 has a height greater than that of the first layer 102. According to some embodiments, the first layer 102 may include a dielectric layer. The dielectric layer may include silicon oxide, silicon nitride, silicon carbide, spin-coated carbon, or spin-coated polymer. For example, the first layer 102 may be deposited by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD), sputtering, or a wet process such as spin coating.

[0023] PECVD or PEALD can, for example, utilize plasma generated by a low-energy slotted planar antenna array, which reduces or prevents damage to the underlying stack and provides directional deposition of the first layer 102 (and subsequent stacks) on the substrate 100 adjacent to the raised feature 110.

[0024] The deposition or growth of the first layer 102 on the substrate 100 relative to the sidewall 117 of the protruding feature 110 can be highly selective or directional. Therefore, the first layer 102 can grow from the surface of the substrate 100 and only a portion of the sidewall 117 at the bottom can be covered by the first layer 102.

[0025] Figure 2 further shows a second layer 104 deposited on substrate 100 adjacent to the raised feature 110. In some embodiments, the second layer 104 may be 10-50 nm thick. The first layer 102 and the second layer 104 contain different materials to achieve etch selectivity in subsequent etch steps. According to some embodiments, the second layer 104 may contain a dielectric layer. This dielectric layer may contain silicon oxide, silicon nitride, silicon carbide, spin-coated carbon, or spin-coated polymer. In one example, an aluminum oxide-doped polymer may be used. For example, the second layer 104 may be deposited by a wet process such as CVD, PECVD, ALD, PEALD, PVD, sputtering, or spin coating. The deposition or growth of the second layer 104 on substrate 100 relative to the sidewall 117 of the raised feature 110 can be highly selective. Therefore, only a portion of the sidewall 117 can be covered by the second layer 104.

[0026] Figure 3 shows the substrate 100 after the third layer 106 is deposited to cover the raised feature 110.

[0027] In Figure 3, a third layer 106 may be deposited on the second layer 104 and the raised feature 110. In some embodiments, the third layer 106 may be 5-10 nm thick. The third layer 106 and the second layer 104 contain different materials to achieve etch selectivity in subsequent etching steps. In one example, the third layer 106 and the first layer 102 may contain the same or similar materials. According to some embodiments, the third layer 106 may contain a dielectric layer. This dielectric layer may contain silicon oxide, silicon nitride, silicon carbide, spin-coated amorphous carbon, or spin-coated polymer. For example, the third layer 106 may be deposited by CVD or ALD. Compared to the first layer 102 and the second layer 104, in some embodiments, the deposition of the third layer 106 can be highly conformal on the raised feature 110. Therefore, any remaining sidewalls 117 and optional capping 108 can be completely covered by the third layer 106, even if the height of the remaining sidewalls 117 and optional capping 108 is greater than the thickness of the third layer 106.

[0028] According to one embodiment, the first layer 102 comprises silicon nitride and the second layer 104 comprises silicon oxide. In one embodiment, the first layer 102 comprises silicon nitride, the second layer 104 comprises silicon oxide, and the third layer comprises silicon nitride. In one example, as further described later with reference to Figures 9-14, one or more of the first layer 102, the second layer 104, and the third layer 106 can be epitaxially deposited or grown.

[0029] Figure 4 shows the substrate 100 after an anisotropic dry etching process.

[0030] In Figure 4, an anisotropic dry etching process can be performed to etch the second layer 104 and the third layer 106. Due to the anisotropy of the etching process, a major portion of the stack positioned above the top surface of the substrate 100 can be removed, leaving a portion of the stack attached to the sidewalls 117. Therefore, a second sidewall spacer 114 can be formed from the second layer 104 and a third sidewall spacer 116 can be formed from the third layer 106. In some embodiments, a selective cap layer 108 can be used as an etching mask. In the embodiment illustrated in Figure 4, the anisotropic dry etching process terminates on the first layer 102. In another embodiment, although not shown, the anisotropic dry etching process can further etch the first layer 102 and terminate on the substrate 100. In one example, the anisotropic dry etching process may include plasma-excited fluorocarbon gas and oxygen. In order to effectively remove both the second layer 104 and the third layer 106, the anisotropic dry etching process can be a multi-step plasma etching process involving multiple etching gas compositions.

[0031] Figure 5 shows the substrate 100 after isotropic etching.

[0032] In Figure 5, isotropic etching can be performed to selectively remove the second sidewall spacer 114 from structure 1. This results in the exposure of some portions of the sidewall 117 of the raised feature 110 below the third sidewall spacer 116 and above the first layer 102. In one example, a wet etching process containing an HF solution can be used. In another embodiment, a dry etching process can be used. The remaining third sidewall spacer 116 after isotropic etching is a 3D spacer that can be used in subsequent steps, such as the formation of ultra-shallow doped regions (Figures 6-8).

[0033] Figure 6 shows the substrate 100 after the deposition of the dopant layer 118.

[0034] In Figure 6, conformal deposition of the dopant layer 118 can be performed on structure 1, on multiple exposed portions of the sidewall 117 of the protruding feature 110. As illustrated in Figure 6, the dopant layer 118 can be in direct physical contact with the exposed sidewall 117. In some embodiments, the conformal dopant layer 118 can be deposited by CVD or ALD. The dopant layer 118 may comprise an oxide layer (e.g., SiO2), a nitride layer (e.g., SiN), or an oxide-oxygen nitride layer (e.g., SiON), or a combination of two or more thereof. The dopant layer 118 may comprise one or more dopants from Group IIIA of the periodic table: boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl); and Group VA: nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). According to some embodiments, the dopant layer 118 may comprise low dopant levels, for example, dopants between about 0.5 and about 5 atomic percent. According to other embodiments, the dopant layer 118 may contain a medium dopant level, such as between about 5 and about 20 atomic percent dopant. According to yet another embodiment, the dopant layer 118 may contain a high dopant level, such as greater than 20 atomic percent dopant. In some examples, the thickness of the dopant layer 118 may be less than 4 nanometers (nm), for example, between 1 nm and 4 nm, between 2 nm and 4 nm, or between 3 nm and 4 nm. However, other thicknesses may be used.

[0035] According to other embodiments, the dopant layer 118 may comprise or consist of a doped high-k dielectric material in the following forms: an oxide layer, a nitride layer, or an oxide oxynitride layer. The dopant in the high-k dielectric material may be selected from the list of dopants above. The high-k dielectric material may comprise one or more metallic elements selected from alkaline earth elements, rare earth elements, Group IIIA elements, Group IVA elements, and Group IVB elements of the periodic table. Alkaline earth metallic elements include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba). Example oxides include magnesium oxides, calcium oxides, and barium oxides, and combinations thereof. Rare earth metal elements may be selected from the group consisting of: scandium (Sc), yttrium (Y), argonium (Lu), lanthanum (La), cerium (Ce), pium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), thorium (Gd), tbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thionium (Tm), and ytterbium (Yb). Group IVB elements include titanium (Ti), hafnium (Hf), and zirconium (Zr). According to some embodiments of the present invention, high-k dielectric materials may comprise HfO₂, HfON, HfSiON, ZrO₂, ZrON, ZrSiON, TiO₂, TiON, Al₂O₃, La₂O₃, W₂O₃, CeO₂, Y₂O₃, or Ta₂O₅, or combinations of two or more thereof. However, other dielectric materials can be considered and used.

[0036] Figure 7 shows the substrate 100 after heat treatment for solid-state diffusion.

[0037] Subsequently, structure 1 in FIG. 6 can be heat-treated to allow dopant (e.g., B, Al, Ga, In, Tl, N, P, As, Sb, or Bi) to diffuse from dopant layer 118 into raised feature 110 via sidewall 117 to form dopant region 120. This is schematically shown in FIG. 7. In FIG. 7, two dopant regions 120 are shown on each side of raised feature 110. The heat treatment may involve heating structure 1 to a temperature between 100°C and 1000°C for 10 seconds to 10 minutes in an inert atmosphere (e.g., argon (Ar) or nitrogen (N2)) or in an oxidizing atmosphere (e.g., oxygen (O2) or water vapor (H2O)). In many embodiments, the temperature and gas environment of the heat treatment can be selected to optimize dopant diffusion. In some examples, heat treatment may include rapid thermal annealing (RTA), surge annealing, or laser spike annealing.

[0038] In some examples, the thickness of the dopant region 120 may be between 1 nm and 10 nm or between 2 nm and 5 nm. However, those skilled in the art will readily understand that the lower boundary of the dopant region 120 may not be abrupt, but rather has a gradually decreasing doping concentration.

[0039] Figure 8 shows the substrate 100 after the remaining portion of the dopant layer 118 has been removed.

[0040] After heat treatment, any remaining portion of the dopant layer 118 can be removed using a dry etching process or a wet etching process. The resulting structure 1 is illustrated in Figure 8. Furthermore, a dry or wet cleaning process can be performed after heat treatment to remove any etching residues from structure 1.

[0041] In the above embodiments (Figures 1-8), only one set of two 3D spacers is described (i.e., the third sidewall spacers 116 on both sides of the sidewall 117). In other embodiments, the method can enable more than one set of 3D spacers to be formed along the sidewall 117.

[0042] Figure 9-14 schematically illustrates, through cross-sectional views, the formation of a plurality of 3D spacers and ultra-shallow doped regions according to another embodiment. Many of the steps can be followed as described in the preceding embodiments above, and therefore some details of the structure and process will not be repeated.

[0043] Figure 9 shows a schematic cross-sectional view of structure 2.

[0044] In Figure 9, structure 2 is similar to structure 1 described in Figure 1 and includes a substrate 100, a raised feature 110, an optional cap layer 108 located on top of the raised feature 110, and a first layer 102 deposited on the substrate 100 adjacent to the raised feature 110.

[0045] Figure 9 further shows additional stacks 122, 124, 126, 128, 130, and 135 deposited on the first layer 102. In many embodiments, each of these additional stacks 122, 124, 126, 128, 130, and 135 may be 5-20 nm thick, but each of the stacks 102, 122, 124, 126, 128, 130, and 135 may have different thicknesses than each other. In one embodiment, the second layers 122, 126, and 130 comprise a second material, and the third layers 124, 128, and 135 comprise a third material. Generally, structure 2 may comprise any number of alternating second and third layers. The third material is different from the second material. In some examples, second layers 122, 126, and 130 may comprise the material of second layer 104 in FIG. 2, and third layers 124, 128, and 135 may comprise the material of third layer 106 in FIG. 2. In one example, second layers 122, 126, and 130 comprise silicon oxide, and third layers 124, 128, and 135 comprise silicon nitride. In one embodiment, first layer 102 may comprise the material of third layers 124, 128, and 135. In many embodiments, this additional stack of layers 122, 124, 126, 128, 130, and 135 may be formed by, for example, CVD or ALD, and in some embodiments, the process for forming the stack may also include multiple steps of deposition and etching.

[0046] Figure 10 shows the substrate 100 after an anisotropic dry etching process.

[0047] Figure 10 shows structure 2 after the anisotropic dry etching process. As described in the previous embodiment (Figure 4), by removing the main portions of the stacks 122, 124, 126, 128, 130, and 135 except for the portions on the sidewalls 117, the anisotropic dry etching process results in the formation of second sidewall spacers 132, 136, and 140 from the second layers 122, 126, and 130, and third sidewall spacers 134, 138, and 145 from the third layers 124, 128, and 135. In the embodiment illustrated in Figure 10, the anisotropic dry etching process terminates on the first layer 102; however, in other embodiments, it may continue etching through the first layer 102 and terminate on the substrate 100.

[0048] Figure 11 shows the substrate 100 after isotropic etching.

[0049] Figure 11 shows structure 2 after selective removal of the second sidewall spacers 132, 136, and 140. This exposes multiple portions of the sidewalls 117 of the raised features 110 between the first layer 102 and the third sidewall spacer 134, between the third sidewall spacers 134 and 138, and between the third sidewall spacers 138 and 145. The remaining third sidewall spacers 134, 138, and 145 after isotropic etching are 3D spacers that can be used in subsequent steps such as the formation of ultra-shallow doped regions (Figures 12-14) or lateral etching of the raised features 110 (Figure 15).

[0050] Figure 12 shows the substrate 100 after the deposition of the dopant layer 148.

[0051] Figure 12 shows structure 2 after conformal deposition of a dopant layer 148 on the sidewall 117 of the protruding feature 110. As shown in Figure 12, the dopant layer 148 can be in direct physical contact with the exposed sidewall 117. In some embodiments, the dopant layer 148 can be deposited by CVD or ALD.

[0052] Figure 13 shows the substrate 100 after heat treatment for solid-state diffusion.

[0053] Subsequently, structure 2 in FIG12 can be heat-treated to allow the dopant to diffuse from the dopant layer 148 to the raised feature portion 110 via the sidewall 117 to form the dopant region 144. This is schematically shown in FIG13.

[0054] Figure 14 shows the substrate 100 after the remaining portion of the dopant layer 148 has been removed. Any remaining portion of the dopant layer 148 can be removed using a dry etching process or a wet etching process after heat treatment. The resulting structure is illustrated in Figure 14. Furthermore, a dry or wet cleaning process can be performed after heat treatment to remove any etching residue from structure 2.

[0055] Figure 15 schematically shows, through a cross-sectional view, the subsequent lateral etching of the raised feature 110 according to an alternative embodiment, which uses the third sidewall spacers 134, 138, and 145 as an etching mask after the steps of Figures 9-11.

[0056] As shown in Figure 15, subsequent process steps after the step of forming the 3D spacers are not limited to the formation of doped regions. In some embodiments, an isotropic etching process can be performed to use the 3D spacers (e.g., third sidewall spacers 134, 138, and 145) as an etching mask to etch a portion of the raised feature 110 and form a groove 150. This etching process can achieve the formation step along the sidewall 117 of the raised feature 110.

[0057] In a further embodiment as described below, the shape of the 3D spacer to be formed can be changed by introducing a gradient in the chemical composition into the stack of layers to be manufactured as the 3D spacer (e.g., the third layers 124, 128, and 135 in FIG. 9).

[0058] Figures 16-18 schematically show, through cross-sectional views, the formation of a plurality of 3D spacers according to yet another embodiment.

[0059] Figure 16 shows an input substrate 100 having some stacked layers using gradients in chemical composition.

[0060] In Figure 16, structure 3 is similar to structure 2 shown in Figure 9 and includes a substrate 100, a raised feature 110, an optional cap layer 108 on top of the raised feature 110, and a first layer 102 deposited on the substrate 100 adjacent to the raised feature 110. Structure 3 further includes second layers 122, 126, and 130 and third layers 124, 128, and 135. In many embodiments, the second layers 122, 126, and 130 comprise a second material, and the third layers 124, 128, and 135 comprise a third material. Generally, structure 3 may comprise any number of alternating second and third layers. The third material is different from the second material. In one example, the second layers 122, 126, and 130 comprise silicon oxide, and the third layers 124, 128, and 135 comprise silicon nitride.

[0061] In many embodiments, the third layers 124, 128, and 135 can be formed by CVD or ALD, which advantageously allows for changes in chemical composition during deposition. In several embodiments, the concentration of some components in the third layers 124, 128, and 135 can be gradually varied in a vertical direction perpendicular to the main surface of the substrate 100. For example, in several embodiments, the stack 124, 128, and 135 may comprise both silicon nitrides and silicon oxides, and the nitrogen concentration may have a gradient in the vertical direction. In one embodiment, the nitrogen concentration may be lowest at the bottom and top of each of the third layers 124, 128, and 135, and highest in the middle. In other embodiments, various chemical composition gradients may be used.

[0062] During subsequent etching processes (e.g., isotropic etching in Figures 5 and 11 of the previous embodiments), gradients in the chemical composition can advantageously result in different etching selectivity in each of the third layers 124, 128, and 135. Therefore, the resulting sidewall spacers can advantageously have a non-uniform thickness on the sidewall 117.

[0063] Figure 17 shows the substrate 100 after the formation of 3D spacers with varying thickness.

[0064] The substrate 100 can be etched to form third sidewall spacers 134, 138, and 145 by anisotropic etching processes and isotropic etching processes as described above (e.g., Figures 3-5 and 9-11). Due to the gradient in chemical composition, some portions of the third layers 124, 128, and 135 can be etched together with the second layers 122, 126, and 130 during isotropic etching. For example, when isotropic etching is used to selectively remove oxide material relative to nitride material, the oxygen-rich portions of the third layers 124, 128, and 135 can be etched without removing the nitrogen-rich portions. Therefore, this varying etch selectivity within the third layers 124, 128, and 135 can result in the third sidewall spacers 134, 138, and 145 having a curved shape with non-uniform thickness on the sidewall 117, as shown in Figure 17.

[0065] Figure 18 shows the substrate 100 after the subsequent etching process.

[0066] Subsequently, an isotropic etching process can be performed to use non-uniform 3D spacers (e.g., the third sidewall spacers 134, 138, and 145 in FIG. 17) as an etching mask to etch a portion of the raised feature 110 and form a groove 180. Compared to FIG. 15, the curved shape of the 3D spacers can result in a corrugated shape of the etched raised feature 110. Generally, the shape of the 3D spacers can be controlled by designing a gradient in the chemical composition of the third layers 124, 128, and 135.

[0067] Figures 19A-19F schematically show examples of gradients in the chemical composition of 3D spacers according to various embodiments through cross-sectional views.

[0068] In Figure 19A, the initial deposited layer (e.g., one of the third layers 124, 128, or 135 in Figure 16) may have a concentration gradient of the composition, such that the concentration gradient is lowest at the bottom and top and highest in the middle. If the subsequent etching process is selected to be selective for this composition, the resulting 3D spacer may have a semi-elliptical shape as shown in Figure 19B. Similarly, in another embodiment, the initial layer may be formed with three lowest points in the concentration (e.g., at the bottom, middle, and top) and two highest points between these lowest points (Figure 19C), which may thus result in two semi-elliptical shapes (Figure 19D). In yet another embodiment, the initial layer may be formed with a uniform composition throughout the layer, except near the bottom and top where the concentration may drop sharply (Figure 19E). In this case, the resulting 3D spacer may have a uniform thickness except near the bottom and top edges (Figure 19F).

[0069] Figures 20A-20C show flowcharts of methods for forming 3D spacers according to various embodiments. The process flow may be accompanied by the diagrams discussed above (e.g., Figures 1-5, 9-13, 16-17), and therefore will not be repeated.

[0070] In Figure 20A, process flow 20 begins by loading a substrate having raised features 110 into a processing chamber (block 2010, Figure 1). Next, a first layer is deposited over the substrate adjacent to the raised features to cover a first portion of the sidewalls of the raised features (block 2020, Figure 2). Subsequently, a second layer is deposited over the first layer adjacent to the raised features to cover a second portion of the sidewalls (block 2030, Figure 2). Then, a third layer is deposited over the second layer and the raised features to cover a third portion of the sidewalls and the top surface of the raised features (block 2040, Figure 3). Afterward, anisotropic dry etching is performed to remove portions of the second and third layers, where the remaining portions of the second layer form second sidewall spacers and the remaining portions of the third layer form third sidewall spacers (block 2050, Figure 4). Then, isotropic etching can be performed to selectively remove the second sidewall spacers to expose multiple portions of the two sidewalls of the raised feature (block 2060, FIG. 5).

[0071] In Figure 20B, process flow 22 begins by loading a substrate with raised features and exposed sidewalls into a processing chamber (block 2010, Figure 1). Next, multiple layers can be formed by: depositing a first dielectric material on the substrate adjacent to the raised features to cover a first portion of the sidewalls (block 2022); depositing a second dielectric material on the first dielectric material adjacent to the raised features to cover a second portion of the sidewalls (block 2032); and depositing a third dielectric material on the second dielectric material adjacent to the raised features to cover a third portion of the sidewalls (block 2042). Furthermore, the process then involves repeatedly depositing the second dielectric material and the third dielectric material (blocks 2032 and 2042) to form an alternating stack of layers (Figure 9). Subsequently, anisotropic dry etching is performed to etch multiple portions of the layer stack to form a second sidewall spacer containing a first dielectric material and a third sidewall spacer containing a third dielectric material (block 2050, FIG. 10). The second sidewall spacer is then selectively removed to expose multiple portions of the sidewalls of the raised feature (block 2062, FIG. 11). The process then proceeds to conservatively deposit a dopant layer onto the raised feature (block 2070, FIG. 12), followed by heating the substrate to form a doped region in the raised feature by diffusion of the dopant from the dopant layer into the raised feature (block 2080, FIG. 13).

[0072] In Figure 20C, process flow 24 begins with loading a substrate with raised features into a processing chamber (block 2010, Figure 1). Next, a first layer is deposited on top of the substrate adjacent to the raised features to cover a first portion of the sidewalls of the raised features (block 2020, Figure 2). Subsequently, a second layer is deposited on top of the first layer adjacent to the raised features to cover a second portion of the sidewalls (block 2030, Figure 2). Then, a third layer is deposited on top of the second layer by atomic layer deposition (ALD) to cover a third portion of the sidewalls, wherein the third layer has a varying chemical composition that changes in a direction perpendicular to the main surface of the substrate (block 2044, Figure 16). Afterward, anisotropic dry etching is performed to remove portions of the second and third layers, wherein the remaining portions of the second layer form second sidewall spacers and the remaining portions of the third layer form third sidewall spacers (block 2050). Then, isotropic etching can be performed to remove a portion of the second sidewall spacer and the third sidewall spacer to expose multiple portions of the two sidewalls of the raised feature (block 2064, FIG. 17).

[0073] Exemplary embodiments are summarized herein. Other embodiments may also be understood from the entire specification and the claims set forth herein.

[0074] Example 1. A method of processing a substrate includes: loading the substrate in a processing chamber, the substrate having a raised feature and at least two sidewalls exposed on the surface of the raised feature; depositing a first layer on the substrate adjacent to the raised feature, the first layer covering a first portion of the two sidewalls; depositing a second layer on the first layer adjacent to the raised feature, the second layer covering a second portion of the two sidewalls, wherein the first layer and the second layer comprise different materials; depositing a third layer on the second layer and the raised feature, the third layer covering a third portion of the two sidewalls and the top surface of the raised feature, wherein the second layer and the third layer comprise different materials; performing anisotropic dry etching to remove multiple portions of the second layer and the third layer, the remaining portion of the second layer forming a second sidewall spacer and the remaining portion of the third layer forming a third sidewall spacer; and performing isotropic etching to selectively remove the second sidewall spacer to expose multiple portions of the two sidewalls of the raised feature.

[0075] Example 2. The method of Example 1 further includes: after performing the isotropic etching, conformally depositing a dopant layer over the protruding feature, the dopant layer being in solid contact with a plurality of exposed portions of the sidewalls of the protruding feature; and heating the substrate to form a doped region in the protruding feature by diffusion of the dopant from the dopant layer into the protruding feature.

[0076] Example 3. The method of one of Examples 1 or 2 further includes removing the dopant layer after the heating.

[0077] Example 4. The method of one of Examples 1 to 3 further includes performing another isotropic etching on the protruding feature portion selectively relative to the third sidewall spacer after performing the isotropic etching.

[0078] Example 5. The method of one of Examples 1 to 4, wherein the second and third layers comprise silicon oxide, silicon nitride, silicon carbide, spin-coated carbon, or spin-coated polymer.

[0079] Example 6. The method of one of Examples 1 to 5, wherein the second layer comprises silicon oxide and the third layer comprises silicon nitride.

[0080] Example 7. The method of one of Examples 1 to 6, wherein the first layer comprises silicon nitride.

[0081] Example 8. The method of one of Examples 1 to 7, wherein the selective removal of the second layer comprises an isotropic dry etching process.

[0082] Example 9. The method of one of Examples 1 to 8, wherein the protruding feature includes a fin-like structure and a hard mask covering the top surface of the fin-like structure.

[0083] Example 10. A method for forming a 3D spacer for a semiconductor device includes: loading a substrate having raised features in a processing chamber, the raised features including exposed sidewalls; depositing a first dielectric material on the substrate adjacent to the raised features to cover a first portion of the sidewalls; depositing a second dielectric material on the first dielectric material adjacent to the raised features to cover a second portion of the sidewalls; depositing a third dielectric material on the second dielectric material adjacent to the raised features to cover a third portion of the sidewalls; and repeating the deposition of the second dielectric material and the deposition of the third dielectric material. The steps involve forming a layer stack; performing anisotropic dry etching of multiple portions of the layer stack to form a second sidewall spacer containing the first dielectric material and a third sidewall spacer containing the third dielectric material; selectively removing the second sidewall spacer to expose multiple portions of the sidewalls of the protruding feature; conformally depositing a dopant layer on the protruding feature, the dopant layer being in solid contact with the exposed multiple portions of the sidewalls of the protruding feature; and heating the substrate to form a doped region in the protruding feature by diffusion of the dopant from the dopant layer to the protruding feature.

[0084] Example 11. The method of Example 10, wherein the second dielectric material and the third dielectric material comprise different materials and include silicon oxide, silicon nitride, silicon carbide, spin-coated carbon, or spin-coated polymer.

[0085] Example 12. The method of one of Examples 10 or 11, wherein the second dielectric material comprises silicon oxide and the third dielectric material comprises silicon nitride.

[0086] Example 13. The method of one of Examples 10 to 12, wherein the first dielectric material and the third dielectric material comprise the same material.

[0087] Example 14. The method of one of Examples 10 to 13, wherein one of the second sidewall spacers or one of the third sidewall spacers has a height between about 5 nm and about 15 nm.

[0088] Example 15. The method of one of Examples 10 to 14, wherein the anisotropic dry etching is terminated when the top surface of the first dielectric material is exposed.

[0089] Example 16. The method of one of Examples 10 to 15, wherein forming the layer stack further includes removing the second dielectric material or the third dielectric material.

[0090] Example 17. A method of processing a substrate includes: loading the substrate in a processing chamber, the substrate having a raised feature and at least two sidewalls exposed on the surface of the raised feature; depositing a first layer on the substrate adjacent to the raised feature, the first layer covering a first portion of the two sidewalls; depositing a second layer on the first layer adjacent to the raised feature, the second layer covering a second portion of the two sidewalls, wherein the first layer and the second layer comprise different materials; depositing a third layer on the second layer using atomic layer deposition (ALD), the third layer covering a third portion of the two sidewalls, the third layer having a varying chemical composition that changes in a direction perpendicular to the main surface of the substrate; performing anisotropic dry etching to remove a plurality of portions of the second layer and the third layer, the remaining portions of the second layer forming second sidewall spacers and the remaining portions of the third layer forming third sidewall spacers; and performing isotropic etching to remove a portion of the second sidewall spacers and the third sidewall spacers to expose a plurality of portions of the two sidewalls of the raised feature.

[0091] Example 18. The method of Example 17, wherein the second layer comprises silicon oxide and the third layer comprises silicon oxide and silicon nitride, and wherein the ratio of silicon nitride to silicon oxide in the third layer changes in the vertical direction.

[0092] Example 19. As in one of Examples 17 or 18, wherein the third sidewall spacer has a uniform thickness in the vertical direction.

[0093] Example 20. As in one of Examples 17 to 19, wherein the third sidewall spacer is thinner at the bottom or top portion than at the middle portion.

[0094] Example 21. As in one of Examples 1 to 8, wherein the raised feature comprises Si or SiGe.

[0095] Example 22. The method of one of Examples 1 to 8, wherein the first layer and the third layer contain the same material.

[0096] Example 23. The method of one of Examples 1 to 8, wherein the doped layer contains a p-type dopant or an n-type dopant.

[0097] Example 24. As in one of Examples 10 to 16, wherein the raised feature comprises Si, SiGe, or both Si and SiGe.

[0098] Example 25. The method of one of Examples 10 to 16, wherein the second layer and the third layer contain different materials.

[0099] Example 26. The method of one of Examples 10 to 16, wherein the doped layer contains a p-type dopant or an n-type dopant.

[0100] Example 27. The method of one of Examples 10 to 16, wherein the selective removal of the second layer comprises an isotropic dry etching process.

[0101] Example 28. The method of one of Examples 10 to 16 further includes removing the dopant layer after heating the substrate.

[0102] Example 29. A semiconductor device comprising: a raised feature on a substrate; one or more sidewall spacers on the raised feature, wherein the one or more sidewall spacers are separated by gaps that expose the sidewalls of the raised feature; and a doped region in the raised feature between the one or more sidewall spacers.

[0103] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Many modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art when referring to the description. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

[0104] 1: Structure 2: Structure 3: Structure 20: Manufacturing Process 22: Manufacturing Process 24: Manufacturing Process 100:Substrate 102: First Floor 104: Second layer 106: Third Floor 108: Hat Layer 110: Protruding feature 114: Second sidewall spacer 116: Third sidewall spacer 117: Sidewall 118: Dopant layer 120: Doped region 122: Second layer 124: Third Floor 126: Second layer 128: Third Floor 130: Second layer 132: Second sidewall spacer 134: Third sidewall spacer 135: Third Floor 136: Second sidewall spacer 138: Third sidewall spacer 140: Second sidewall spacer 144: Doped region 145: Third sidewall spacer 148: Dopant layer 150: Groove 180: Groove 2010: Square 2020: Square 2022: Square 2030: Blocks 2032: Blocks 2040: Square 2042: Square 2044: Blocks 2050: Square 2060: Square 2062: Square 2064: Square 2070: Square 2080: Square

Claims

1. A method of processing a substrate, the method comprising: loading the substrate in a processing chamber, the substrate having a raised feature and at least two sidewalls exposed on the surface of the raised feature; depositing a first layer over the substrate and adjacent to the raised feature, the first layer covering a first portion of the two sidewalls; depositing a second layer over the first layer and adjacent to the raised feature, the second layer covering a second portion of the two sidewalls, wherein the first layer and the second layer comprise different materials; depositing a third layer over the second layer and the raised feature, the third layer covering a third portion of the two sidewalls and a top surface of the raised feature, wherein the second layer and the third layer comprise different materials; performing anisotropic dry etching to remove a plurality of portions of the second layer and the third layer, the remaining portion of the second layer forming a second sidewall spacer and the remaining portion of the third layer forming a third sidewall spacer; and performing isotropic etching to selectively remove the second sidewall spacer to expose a plurality of portions of the two sidewalls of the raised feature.

2. The method of processing a substrate as claimed in claim 1 further comprises: after performing the isotropic etching, conformally depositing a dopant layer over the protruding feature, the dopant layer being in solid contact with the exposed portions of the plurality of sidewalls of the protruding feature; and heating the substrate to form a doped region in the protruding feature by diffusion of the dopant from the dopant layer to the protruding feature.

3. The method of processing a substrate as claimed in claim 2 further includes removing the dopant layer after the heating.

4. The method of processing a substrate as claimed in claim 1 further includes, after performing the isotropic etching, performing another isotropic etching that selectively etches the protruding feature relative to the third sidewall spacer.

5. The method of processing a substrate as claimed in claim 1, wherein the second layer and the third layer comprise silicon oxide, silicon nitride, silicon carbide, spin-coated carbon, or spin-coated polymer.

6. The method of processing a substrate as claimed in claim 1, wherein the second layer comprises silicon oxide and the third layer comprises silicon nitride.

7. The method of processing a substrate as claimed in claim 1, wherein the first layer comprises a silicon nitride.

8. The method of processing a substrate as claimed in claim 1, wherein the selective removal of the second layer comprises an isotropic dry etching process.

9. The method of processing a substrate as claimed in claim 1, wherein the raised feature includes a fin-like structure and a hard mask covering the top surface of the fin-like structure.

10. A method of forming 3D spacers for a semiconductor device, the method comprising: loading a substrate having raised features in a processing chamber, the raised features including exposed sidewalls; depositing a first dielectric material over the substrate and adjacent to the raised features to cover a first portion of the sidewalls; depositing a second dielectric material over the first dielectric material and adjacent to the raised features to cover a second portion of the sidewalls; depositing a third dielectric material over the second dielectric material and adjacent to the raised features to cover a third portion of the sidewalls; forming a layer stack by repeatedly depositing the second dielectric material and the third dielectric material; performing anisotropic dry etching of a plurality of portions of the layer stack to form a second sidewall spacer including the first dielectric material and a third sidewall spacer including the third dielectric material; selectively removing the second sidewall spacer to expose a plurality of portions of the sidewalls of the raised features; A dopant layer is conformally deposited on the raised feature, the dopant layer being in solid contact with the exposed portions of the sidewalls of the raised feature; and the substrate is heated to form a doped region in the raised feature by diffusion of the dopant from the dopant layer into the raised feature.

11. The method of forming a 3D spacer for a semiconductor device as claimed in claim 10, wherein the second dielectric material and the third dielectric material comprise different materials and include silicon oxide, silicon nitride, silicon carbide, spin-coated carbon, or spin-coated polymer.

12. The method of forming a 3D spacer for a semiconductor device as claimed in claim 10, wherein the second dielectric material comprises silicon oxide and the third dielectric material comprises silicon nitride.

13. The method of forming a 3D spacer for a semiconductor device as claimed in claim 10, wherein the first dielectric material and the third dielectric material comprise the same material.

14. The method of forming a 3D spacer for a semiconductor device as claimed in claim 10, wherein one of the second sidewall spacers or one of the third sidewall spacers has a height between about 5 nm and about 15 nm.

15. The method of forming a 3D spacer for a semiconductor device as claimed in claim 10, wherein the anisotropic dry etching is terminated when the top surface of the first dielectric material is exposed.

16. The method of forming a 3D spacer of a semiconductor device as claimed in claim 10, wherein forming the layer stack further comprises removing the second dielectric material or the third dielectric material.

17. A method of processing a substrate, the method comprising: loading the substrate into a processing chamber, the substrate having a raised feature and at least two sidewalls exposed on a surface of the raised feature; depositing a first layer over the substrate and adjacent to the raised feature, the first layer covering a first portion of the two sidewalls; depositing a second layer over the first layer and adjacent to the raised feature, the second layer covering a second portion of the two sidewalls, wherein the first layer and the second layer comprise different materials; depositing a third layer over the second layer using atomic layer deposition (ALD), the third layer covering a third portion of the two sidewalls, the third layer having a varying chemical composition in a direction perpendicular to a principal surface of the substrate; performing anisotropic dry etching to remove a plurality of portions of the second layer and the third layer, the remaining portions of the second layer forming second sidewall spacers and the remaining portions of the third layer forming third sidewall spacers; and performing isotropic etching to remove portions of the second sidewall spacers and the third sidewall spacers to expose a plurality of portions of the two sidewalls of the raised feature.

18. The method of processing a substrate as claimed in claim 17, wherein the second layer comprises silicon oxide and the third layer comprises silicon oxide and silicon nitride, and wherein the ratio of silicon nitride to silicon oxide in the third layer changes in the vertical direction.

19. The method of processing a substrate as claimed in claim 17, wherein the third sidewall spacer has a uniform thickness in the vertical direction.

20. The method of processing a substrate as claimed in claim 17, wherein the third sidewall spacer is thinner at the bottom or top portion than at the middle portion.

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