Integrated circuit layout including standard cells and method to form the same

Abstract

A method for forming an integrated circuit layout comprising at least two types of standard cells with different cell heights is disclosed. Each standard cell includes a well boundary that divides the standard cell into a PMOS region and an NMOS region. The standard cells are arranged adjacently in a column with the well boundaries aligned along the component column direction, and the power and ground lines of one standard cell are moved to align with and connect to the power and ground lines of another standard cell.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for forming an integrated circuit layout using standard cells and the integrated circuit layout obtained thereby. Prior Art

[0002] With increasing performance and diverse application requirements, integrated circuit (IC) designs are becoming increasingly complex, often incorporating hundreds of thousands or even millions of logic gates. For design convenience, the industry pre-designs commonly used IC functions using logic gates and fabricates these into standard cells. Examples include NAND gates, NOR gates, D-flip-flops, latches, input / output (I / O) units, amplifiers (OP amps), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). After verifying the manufacturability of the standard cells, the standard cell library is licensed to chip designers. These standard cells are then arranged and combined to create the desired circuit functionality using electronic design automation (EDA) tools such as logic simulators, logic synthesizers, and automatic placement and routing. Generally speaking, the circuit design process usually includes specifying the circuit function using a hardware programming language, synthesizing / mapping the generated circuit description into the basic logic gates of the standard cell library, and then arranging and

[0003] Finally, the overall connectivity and functionality of the layout are verified. This allows the layout of complex large-scale integrated circuit systems to be automatically, accurately, and quickly constructed.

[0004] In advanced technologies, to improve the area efficiency, speed, and power consumption of integrated circuits, standard cell libraries provide standard cells with functional components of varying sizes (and therefore varying cell heights) for designers to choose from based on their design requirements. However, mixing standard cells of varying cell heights within the same circuit block (routing block) often reduces the efficiency of synthesis tools due to irregularities caused by the varying pattern sizes. It can also easily produce patterns that violate design specifications, impacting process yield. To address these issues, the current industry-wide approach is to group standard cells of varying cell heights into separate circuit blocks, then use metal routing to establish electrical connections between the circuit blocks. However, this approach not only limits design flexibility but also increases power loss due to the increased metal routing length.

[0005] Therefore, there is still a need in the art for an improved integrated circuit layout including standard cells of mixed heights and a method for forming the same to improve the deficiencies of the aforementioned conventional technology. Summary of the Invention

[0006] The present invention aims to provide an integrated circuit layout including mixed-height standard cells and a method for forming the same. The mixed-height standard cells can be selected from different standard cell libraries or from the same mixed-height standard cell library. This invention improves design flexibility and layout synthesis efficiency, and the resulting integrated circuit layout exhibits improved manufacturability.

[0007] One embodiment of the present invention provides a method for forming an integrated circuit layout, comprising the following steps. First, a first standard cell and a second standard cell are selected. The first and second standard cells have different cell heights and each include a power line, a ground line, and a well boundary extending in parallel along a first direction. Two active regions of opposite conductivity are disposed between the power line and the ground line and on either side of the well boundary. A gate line extends across the two active regions along a second direction, wherein the first direction is perpendicular to the second direction. Next, the first and second standard cells are adjacently positioned such that their well boundaries align along the first direction, thereby obtaining a temporary cell layout. Then, the power line and the ground line of the second standard cell are moved along the second direction to align with and connect to the power line and the ground line of the first standard cell along the first direction, thereby forming the integrated circuit layout from the temporary cell layout.

[0008] Another embodiment of the present invention provides an integrated circuit layout comprising a power line and a ground line extending parallel to each other along a first direction. A first standard cell and a second standard cell are located between the power line and the ground line and are adjacent to each other. The first standard cell and the second standard cell each include an upper edge, a lower edge, and a well boundary located between the upper and lower edges, extending parallel to each other along the first direction. Two active regions of opposite conductivity are disposed on either side of the well boundary. A gate line extends between the upper and lower edges and across the two active regions along a second direction, wherein the first direction is perpendicular to the second direction. A first cell height between the upper and lower edges of the first standard cell is different from a second cell height between the upper and lower edges of the second standard cell, and the well boundaries of the first standard cell and the second standard cell are aligned along the first direction. Simple diagram description

[0009] The accompanying drawings are schematic diagrams and are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The drawings illustrate some embodiments and, together with the description, serve to explain their principles. For the sake of clarity and convenience, the relative sizes and proportions of parts of the drawings have been exaggerated or reduced and are not necessarily drawn to scale. In modified and different embodiments, the same reference numerals are generally used to indicate corresponding or similar features. FIG1 is a partial plan view of an integrated circuit layout according to an embodiment of the present invention. FIG. 2 is a flow chart of a method for forming an integrated circuit layout according to an embodiment of the present invention. 3 , 4 and 5 are schematic diagrams of the steps of the method shown in FIG. 2 . FIG6 is a schematic plan view of an integrated circuit layout according to an embodiment of the present invention. FIG7 is a schematic plan view of an integrated circuit layout according to an embodiment of the present invention. FIG8 is a schematic plan view of an integrated circuit layout according to an embodiment of the present invention. FIG9 is a circuit diagram of an integrated circuit layout according to an embodiment of the present invention. FIG. 10 is a schematic diagram of an electronic design automation (EDA) environment. Implementation Method

[0010] To help those skilled in the art better understand the present invention, several preferred embodiments of the present invention are listed below, along with accompanying drawings, to provide a detailed description of the present invention's components and intended functions. Structural, logical, and electrical modifications may be made and applied to other embodiments without departing from the scope of the present invention. The figures of the present invention are schematic diagrams only, and their detailed proportions may be adjusted to meet design requirements without departing from the present invention.

[0011] To facilitate illustration of the spatial relationships between features, the figures illustrate mutually perpendicular first and second directions, X and Y. In addition to the orientations shown in the figures, other orientations of the present invention (e.g., rotated 90 degrees or other orientations) can also be explained through the spatially relative descriptions in the specification. Herein, the "cell width" of a standard cell is defined as the width between the two side edges of the abutment box (or abutment area) of the standard cell, taken along the first direction, X. The "cell height" of a standard cell is defined as the height between the upper and lower edges of the abutment box or abutment area of ​​the standard cell, taken along the second direction, Y. The width of a power rail or ground rail is defined as the width taken along the second direction, Y. In some embodiments, the width of the power rail and ground rail can be approximately the same as the track width. Cell height and cell width can also be described by the number of tracks, such as 7T, 8T, or 9T.

[0012] The number of gate lines of the standard cell in the embodiment is merely an example and may be modified and applied to other embodiments without departing from the scope of the present invention. The number of gate lines may be singular or plural.

[0013] Figure 1 is a schematic plan view of a portion of an integrated circuit layout 10 according to an embodiment of the present invention, illustrating how standard cells of varying cell heights are arranged in rows. Figure 1 exemplarily illustrates four rows of components in the integrated circuit layout 10, wherein each row extends along a first direction X, with row edges BN adjacent to each other. The first direction X is also referred to as the row direction. As shown in Figure 1, each row has the same row height RH, meaning that row edges BN are equidistant from each other. Standard cells are arranged within each row and are electrically connected to voltage lines (e.g., power lines and ground lines) that extend continuously along row edges BN through the integrated circuit layout 10. It is noteworthy that the component standard cells of the integrated circuit layout 10 may have varying cell heights, and the row height RH of each row is substantially equal to the maximum cell height of the component standard cells.

[0014] For example, as shown in FIG1 , an integrated circuit layout 10 may include a standard cell 12 and a standard cell 14 arranged in the same component column and having different cell heights. The standard cells may be selected from different standard cell libraries for specific logic functions or from the same mixed-height standard cell library. The adjacent frame of the standard cell 12 includes an upper edge 12a, a lower edge 12b, and two side edges 12c. The cell height H12 of the standard cell 12 is defined as the distance between the upper edge 12a and the lower edge 12b, and the cell width W12 of the standard cell 12 is defined as the distance between the two side edges 12c. Similarly, the adjacent frame of the standard cell 14 includes an upper edge 14a, a lower edge 14b, and two side edges 14c. The cell height H14 of the standard cell 14 is defined as the distance between the upper edge 14a and the lower edge 14b, and the cell width W14 of the standard cell 14 is defined as the distance between the two side edges 14c. Standard cells 12 and 14 are adjacent to each other with their side edges 12c and 14c overlapping, thereby reducing the amount of unused space between them. Standard cells 12 and 14 may have the same logical function (e.g., AND, NAND, OR, NOR, inverter, or flip-flop, but different cell heights to accommodate functional components of different sizes and provide different device performance. According to one embodiment of the present invention, the cell height H12 of standard cell 12 is greater than the cell height H14 of standard cell 14 and is substantially equal to the row height RH of the device row. Therefore, the upper edge 12a and lower edge 12b of standard cell 12 overlap the row edge BN, while the upper edge 14a and lower edge 14b of standard cell 14 are spaced the same or different distances from the row edge BN. The functional components of standard cells 12 and 14 are electrically connected to the same power and / or ground lines that extend along the top row edge BN and / or bottom row edge BN of the device row.

[0015] Integrated circuit layout 10 may include another standard cell 16 disposed in another component column adjacent to bottom edge 12b of standard cell 12. Standard cell 16 may be selected from another standard cell library, the standard cell library of standard cell 12, the standard cell library of standard cell 14, or the same mixed-height standard cell library as standard cells 12 and 14. In some embodiments, the cell height of standard cell 16 may be equal to column height RH, in which case the upper and lower edges of the adjacent frame of standard cell 16 overlap with column edge BN, or may abut one side of standard cell 12 along bottom edge 12b of the adjacent frame of standard cell 12. In other embodiments, the cell height of standard cell 16 may be less than column height RH (similar to standard cell 14), in which case the upper and lower edges of the adjacent frame of standard cell 16 are spaced the same or different distances from column edge BN and are separated from, and do not contact, the adjacent frame of standard cell 12. In some embodiments, the functional components of the standard cell 12 and the standard cell 16 can be electrically connected to the same power line (or the same ground line, depending on the orientation of the standard cells) extending along the column edge BN between the two. This can improve the space efficiency of the integrated circuit layout 10 and obtain a more densely packed array.

[0016] Please refer to Figures 2 to 5 and Figure 9. Figure 2 illustrates a flow chart of a method for forming an integrated circuit layout using standard cells having different cell heights according to one embodiment of the present invention. Figures 3 to 5 illustrate the steps of using the method of Figure 2 to adjacently connect a first standard cell Cell-A and a second standard cell Cell-B having different cell heights to form an integrated circuit layout. Figure 9 is a circuit diagram of the integrated circuit layout shown in Figure 5. The method shown in Figure 2 can be performed in an electronic design automation (EDA) environment.

[0017] First, step 22 is performed to select a first standard cell and a second standard cell based on a designed integrated circuit gate netlist. The first and second standard cells have the same logical function but different cell heights and device performance. For example, as shown in Figure 3, the first standard cell Cell-A and the second standard cell Cell-B may be inverters. The adjacent frame of the first standard cell Cell-A (indicated by the thick dashed frame) includes an upper edge A1 and a lower edge A2 extending parallel along a first direction X, and two side edges A3 extending parallel along a second direction Y. The first standard cell Cell-A has a cell height H1 defined by the upper edge A1 and the lower edge A2, and a cell width W1 defined by the two side edges A3. The centerline 114 of the first standard cell Cell-A extends along the first direction X through the center of the adjacent frame, dividing the adjacent frame into two equal parts (upper and lower halves). In other words, the centerline 114 is equidistant from the upper edge A1 and the lower edge A2. Two active regions 120p and 120n of opposite conductivity types are disposed in the upper and lower halves of the adjacent frame, respectively. A gate line 130 extends along a second direction Y and crosses the active regions 120p and 120n. Two dummy gate lines 132, parallel to the gate line 130, are disposed on either side of the active regions 120p and 120n, respectively, along two side edges A3. According to one embodiment of the present invention, the gate lines 130 and the dummy gate lines 132 have the same length in the second direction Y, and their ends are aligned along the first direction X. The first standard cell Cell-A may further include a well region 116 that overlaps the upper half of the adjacent frame and the active region 120p. As shown in FIG3 , the well boundary 116a of the well region 116 may overlap the centerline 114 of the adjacent frame. According to one embodiment of the present invention, the conductivity type of the active region 120p is p-type, and the conductivity type of the active region 120n is n-type. The overlapping region of the gate line 130 and the active region 120p forms a p-type metal oxide semiconductor transistor (PMOS). The overlapping region of the gate line 130 and the active region 120n forms an n-type metal oxide semiconductor transistor (NMOS). The portions of the active regions 120p and 120n located to the left of the gate line 130 (near the conductive connectors 142 and 152) serve as the source regions S of the PMOS and NMOS transistors, respectively. The portions of the active regions 120p and 120n located to the right of the gate line 130 serve as the drain regions D of the PMOS and NMOS transistors. During integrated circuit manufacturing, the well region 116 is used to define an n-type well region in a p-conductivity substrate for arranging the p-type active region 120p.

[0018] The first standard cell Cell-A further includes a power line 140 and a ground line 150 extending along the first direction X and disposed on the upper edge A1 and lower edge A2, respectively. The widths of the power line 140 and the ground line 150 (measured along the second direction Y) may be the same or different. According to one embodiment of the present invention, the centerline 140a of the power line 140, which divides the power line 140 into two equal parts, can completely overlap with the upper edge A1. The centerline 150a of the ground line 150, which divides the ground line 150 into two equal parts, can completely overlap with the lower edge A2.

[0019] The first standard cell Cell-A also includes conductive connectors and contact plugs for electrically connecting the transistor to the power and ground lines to implement the logic functions of the first standard cell Cell-A. Specifically, as shown on the right side of Figure 3, conductive connectors 142 and 152 are disposed on the same side of gate line 130, connected to the edges of power line 140 and ground line 150, respectively, and partially overlapping the source regions S of active regions 120p and 120n, respectively. Conductive connector 162a is disposed on the other side of gate line 130 and partially overlaps the drain regions D of active regions 120p and 120n. Conductive connector 162b is disposed on the same side as conductive connectors 142 and 152 and includes a bump that overlaps the middle portion of gate line 130. Multiple contact plugs 118 electrically connect the source region S of the active region 120p to the conductive connector 142 and the power line 140, the source region S of the active region 120n to the conductive connector 152 and the ground line 150, the gate line 130 to the conductive connector 162b, and the drain region D of the active regions 120p and 120n to the conductive connector 162a. According to one embodiment of the present invention, the power line 140, the ground line 150, and the conductive connectors 142, 152, 162a, and 162b are laid out on the same layout layer, such as the first metal layer. According to one embodiment of the present invention, compared to the second standard cell Cell-B, the first standard cell Cell-A is a high-performance cell with a larger dynamic current and a faster speed.

[0020] Refer to the left side of Figure 3. The second standard cell, Cell-B, is identical to the first standard cell, Cell-A. Its adjacent frame (indicated by the thick dashed box) includes an upper edge B1, a lower edge B2, two side edges A3, as well as a cell height H2 and a cell width W2. A centerline 214 of the second standard cell, Cell-B, extends along the first direction X through the center of the adjacent frame of the second standard cell, Cell-B. Active regions 220p and 220n of p-type conductivity and n-type conductivity are disposed on either side of the centerline 214. Gate lines 230 extend across active regions 220p and 220n along the second direction Y, forming NMOS and PMOS transistors, respectively. Two dummy gate lines 232 are located on either side of the active regions 120p and 120n. Gate lines 230 and dummy gate lines 232 can have the same length along the second direction Y, and their ends can be aligned with each other along the first direction X. Well 216 overlaps the upper half of the adjacent frame of the second standard cell Cell-B, and well boundary 216a may overlap centerline 214. Power line 240 and ground line 250 are disposed on upper edge B1 and lower edge B2, respectively. Centerline 240a of power line 240, which divides power line 240 into two equal parts, may completely overlap upper edge B1. Centerline 250a of ground line 250, which divides ground line 250 into two equal parts, may completely overlap lower edge B2. Power line 240 of second standard cell Cell-B may have the same width as power line 140 of first standard cell Cell-A. Ground line 250 of second standard cell Cell-B may have the same width as ground line 150 of first standard cell Cell-A. The second standard cell Cell-B further includes a plurality of conductive connectors 242, 252, 262a, and 262b and a contact plug 218 for electrically connecting the transistor to the power line 240 and the ground line 250, thereby implementing the logic function of the second standard cell Cell-B. For further detailed descriptions of the second standard cell Cell-B, reference can be made to the previous description of the first standard cell Cell-A. For simplicity, these details are omitted here. According to one embodiment of the present invention, compared to the first standard cell Cell-A, the second standard cell Cell-B is a low-power cell with better space efficiency and lower power leakage. In some embodiments, as shown in FIG3 , along the second direction Y, the width of the active region 220p, the width of the active region 220n, and the length of the gate line 230 of the second standard cell Cell-B are respectively smaller than the width of the active region 220p, the width of the active region 220n, and the length of the gate line 130 of the first standard cell Cell-A. The cell height H2 of the second standard cell Cell-B is smaller than the cell height H1 of the first standard cell Cell-A.

[0021] Next, step 24 is performed to abut the first standard cell and the second standard cell to obtain a temporary cell layout. As shown in FIG4 , the first standard cell Cell-A and the second standard cell Cell-B are abutted in such a manner that the side edges A3 of the first standard cell Cell-A and B3 of the second standard cell Cell-B overlap, and the well boundary 116a of the first standard cell Cell-A and the well boundary 216a of the second standard cell Cell-B are aligned along the first direction X, thereby obtaining a temporary cell layout 10A. According to one embodiment of the present invention, the dummy gate line 132 and the dummy gate line 232 located on the overlapping side edges A3 and B3 overlap and combine to form a common dummy gate line 332. According to one embodiment of the present invention, the dummy gate line 332 is spaced the same distance from the gate line 130 and the gate line 230. According to one embodiment of the present invention, the dummy gate line 332 and the gate line 130 may have the same length along the second direction Y, and their ends may be aligned along the first direction X.

[0022] Next, step 26 is performed to form the integrated circuit layout from the temporary cell layout. As shown in Figures 4 and 5 , after the first standard cell Cell-A and the second standard cell Cell-B are adjacent, the power line 240 and the ground line 250 of the second standard cell Cell-B are identified. Then, the power line 240 and the ground line 250 of the second standard cell Cell-B are shifted by distances P1 and P2, respectively, along the second direction Y (as shown in Figure 4 ), until the centerline 240a' of the shifted power line 240' of the second standard cell Cell-B is aligned with the centerline 140a of the power line 140 of the first standard cell Cell-A along the first direction X, and the centerline 250a' of the shifted ground line 250' of the second standard cell Cell-B is aligned with the centerline 150a of the ground line 150 of the first standard cell Cell-A along the first direction X. Therefore, the power line 240' and ground line 250' of the second standard cell Cell-B can be smoothly connected to the power line 140 and ground line 150 of the first standard cell Cell-A, respectively, resulting in continuously extended power line 340 and ground line 350. According to one embodiment of the present invention, distance P1 and distance P2 are the same. When the power line 240 and ground line 250 of the second standard cell Cell-B move, the conductive connectors 242 and 252 must extend along the second direction Y to maintain connection with the displaced power line 240' and ground line 250', while the contact plug 118 of the second standard cell Cell-B remains in place and does not move. According to one embodiment of the present invention, the length L1 of the extended conductive connector 242 and the length L2 of the extended conductive connector 252 can be the same. The length L3 of the conductive connector 142 can be equal to or different from the lengths L1 and L2 of the conductive connector 242 and the conductive connector 252. After completing step 26, the integrated circuit layout 10B according to an embodiment of the present invention is obtained.

[0023] Next, step 28 is performed to verify the connectivity and circuit function of the integrated circuit layout 10B. After passing the verification, the integrated circuit layout 10B is output as a set of masks used in the process of manufacturing the integrated circuit chip.

[0024] Please refer to Figure 9, which is a circuit diagram of the integrated circuit layout 10B shown in Figure 5. A first standard cell Cell-A and a second standard cell Cell-B are connected in series, each including a p-type metal oxide semiconductor transistor (PMOS) T1 and an n-type metal oxide semiconductor transistor (NMOS) T2. In each cell, the gates of the PMOS T1 and NMOS T2 are interconnected and serve as the cell's input, electrically connected to an input voltage Vin. The drain regions D of the PMOS T1 and NMOS T2 are coupled to each other and serve as the cell's output, electrically connected to an output voltage Vout. The source region S of the PMOS T1 is electrically connected to a power line Vdd, and the source region S of the NMOS T2 is electrically connected to a ground line Vss. The output of the second standard cell Cell-B serves as the input of the first standard cell Cell-A. The power line Vdd is electrically connected to a high potential or an operating voltage. The ground line Vss is electrically connected to a low potential, a reference voltage, or a ground voltage.

[0025] It is noteworthy that in the embodiments of Figures 3 and 5 , since the centerline 114 of the first standard cell Cell-A and the centerline 214 of the second standard cell Cell-B are aligned, the distance P1 moved by the power line 240 is equal to the distance P2 moved by the ground line 250. At this point, the distance D1 between the power line 240' and the upper edge B1 of the second standard cell Cell-B is equal to the distance D2 between the ground line 250' and the lower edge B2 of the second standard cell Cell-B, and is greater than the distance D3 between the power line 140 and the upper edge A1 of the first standard cell Cell-A. In some embodiments, the edge a1 of the active region 120p and the edge b1 of the active region 220p, which are adjacent to and parallel to the well boundaries 116a and 216a and of the same conductivity type (e.g., p-type), may be aligned along the first direction X, for example, along the tangent line I. In some embodiments, edges a2 of the active region 120n and b2 of the active region 220n adjacent to and parallel to the well boundaries 116a and 216a and of the same conductivity type (eg, n-type) may be aligned along the first direction X, eg, along the tangent line II.

[0026] The following describes various embodiments of the present invention. To simplify the description, the following focuses on the differences between the various embodiments, without reiterating the similarities. Identical components in each embodiment are labeled with the same reference numerals to facilitate cross-reference between the various embodiments.

[0027] In some embodiments, the n-type active region and p-type active region of a standard cell may have different well enclosure / space specifications, resulting in a situation where the well boundary does not overlap with the centerline of the standard cell. For example, referring to the plan view of an integrated circuit layout 10C according to an embodiment of the present invention shown in FIG6 , the primary difference from the integrated circuit layout 10B of FIG5 is that the well boundary 116a of the first standard cell Cell-A and the well boundary 216a of the second standard cell Cell-B do not overlap with the centerlines 114 and 214 , respectively. Other features are substantially the same. More specifically, well boundary 116a is located on the side of centerline 114 near the active region 120p of the first standard cell Cell-A and extends along the first direction X. Well boundary 216a is located on the side of centerline 214 near the active region 220p of the second standard cell Cell-B and extends along the first direction X. As shown in FIG6 , in some embodiments, the spacing between the well boundary 116 a and the center line 114 and the spacing between the well boundary 216 a and the center line 214 can be the same. Therefore, after the first standard cell Cell-A and the second standard cell Cell-B are adjacent to each other by aligning the well boundary 116 a and the well boundary 216 a, the center line 114 and the center line 214 can also be aligned along the first direction X, and the length L1 of the extended conductive connector 242 is equal to the length L2 of the extended conductive connector 252. The length L3 of the conductive connector 142 can be equal to or different from L1 and L2.

[0028] FIG7 is a schematic plan view of an integrated circuit layout 10D according to an embodiment of the present invention. The primary difference between this layout and the integrated circuit layout 10B of FIG5 is that the well boundary 216a of the second standard cell Cell-B does not overlap with the centerline 214. Other features are substantially the same. More specifically, the well boundary 116a overlaps with the centerline 114 of the first standard cell Cell-A. The well boundary 216a is located on the side of the centerline 214 closer to the active region 220p of the second standard cell Cell-B and extends along the first direction X. After the first standard cell Cell-A and the second standard cell Cell-B are adjacently aligned with the well boundary 116a and the well boundary 216a, the center lines 114 and 214 are offset in the first direction X. The distance P1 moved by the power line 240 is greater than the distance P2 moved by the ground line 250 (P1 and P2 are shown in FIG4 ). The length L1 of the extended conductive connector 242 is greater than the length L2 of the extended conductive connector 252. In some embodiments, L1 is also greater than the length L3 of the conductive connector 142.

[0029] FIG8 is a schematic plan view of an integrated circuit layout 10E according to an embodiment of the present invention. The primary difference between this layout and the integrated circuit layout 10B of FIG5 is that the well boundary 116a of the first standard cell Cell-A does not overlap with the centerline 114. Other features are substantially the same. More specifically, the well boundary 116a is located on the side of the centerline 114 closer to the active region 120p of the first standard cell Cell-A and extends along the first direction X. The well boundary 216a overlaps with the centerline 214 of the second standard cell Cell-B. After the first standard cell Cell-A and the second standard cell Cell-B are adjacently aligned with the well boundary 116a and the well boundary 216a, the center lines 114 and 214 are offset in the first direction X. The distance P1 moved by the power line 240 is less than the distance P2 moved by the ground line 250 (P1 and P2 are shown in FIG4 ). The length L1 of the extended conductive connector 242 is less than the length L2 of the extended conductive connector 252. In some embodiments, L1 is also less than the length L3 of the conductive connector 142.

[0030] Referring to FIG. 10 , an electronic design automation (EDA) environment for executing the method shown in FIG. 2 is illustrated. Environment 100 includes a specification tool 102, a synthesis tool 104, a place / route tool 106, a verification tool 108, and a standard cell library set 110. The integrated circuit design process involves using a standard hardware description language (e.g., Verilog) in the specification tool 102 to formulate chip functionality and design specifications. Synthesis tool 104 (e.g., Synopsys' Design Compiler) then synthesizes and maps the circuit description into a gate-level netlist of basic logic gates based on standard cells, where the standard cells can be selected from at least one standard cell library in the standard cell library set 110. Next, a place / route tool 106 (e.g., Magma's Blast Fusion) performs physical structure placement and routing based on the gate-level netlist. Subsequently, verification tool 108 is used to verify the connectivity and functionality of the circuit layout.

[0031] In summary, the present invention provides a method for forming an integrated circuit layout comprising standard cells of mixed heights, wherein standard cells in the same component row are adjacent to each other with overlapping side edges and well boundaries aligned along the row direction. Furthermore, voltage lines (e.g., power and ground lines) of standard cells with smaller cell heights are moved until they align and connect with voltage lines of standard cells with larger cell heights, thereby obtaining continuous voltage lines extending along the row edges to connect the standard cells. The method provided by the present invention can effectively improve layout synthesis efficiency, and the resulting layout can reduce the probability of violating design specifications (e.g., well enclosure / spacing specifications). By mixing standard cells of different cell heights (i.e., different performance), the integrated circuit of the present invention can improve space efficiency, as well as chip speed and power efficiency. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0032] 10: Integrated Circuit Layout 10A: Temporary Unit Layout 10B: Integrated Circuit Layout 10C: Integrated Circuit Layout 10D: Integrated Circuit Layout 10E: Integrated Circuit Layout 12: Standard unit 14: Standard unit 16: Standard unit 22: Steps 24: Steps 26: Steps 28: Steps 100: Environment 102: Specification Description Tool 104:Synthesis Tools 106: Configuration / wiring tools 108: Verification Tools 110: Standard cell library combination 114: Centerline 116: Well Area 118: Contact plug 130: Gate line 132: dummy gate line 140: Power cord 142: Conductive connector 150: Ground wire 152: Conductive connector 214: Centerline 216: Well Area 218: Contact plug 230: Gate line 232: dummy gate line 240: Power cord 240a: Centerline 242: Conductive connector 250: Ground wire 250a: Centerline 252: Conductive connector 116a: Well area boundary 120n: Active area 120p: Active area 12a: Upper edge 12b: bottom edge 12c: side edge 140a: Centerline 14a: Upper edge 14b: Lower edge 14c: side edge 150a: Centerline 162b: Conductive connector 216a: Well area boundary 220n: Active Zone 220p: Active area 240': Power cord 240a: Centerline 250': Ground wire 250a': center line 262b: Conductive connector A1: Top edge A2: bottom edge A3: Side edge B1: Top edge B2: bottom edge B3: Side edge BN: Column Edge Cell-A: The first standard cell Cell-B: Second standard cell D: Drain region D1: Distance D2: Distance D3: Distance H1: unit height H12: Unit height H14: Unit height H2: unit height I: Tangent II: Tangent L1: Length L2: Length L3: Length P1: Distance P2: Distance RH: Column height S: Source region W1: unit width W12: unit width W14: unit width W2: unit width X: first direction Y: Second direction T1:PMOS T2:NMOS Vdd: power line Vin: input voltage Vout: output voltage Vss: ground line a1: edge b1: edge a2: edge b2: edge

Claims

1. A method for forming an integrated circuit layout, comprising: selecting a first standard cell and a second standard cell, the first standard cell and the second standard cell having different cell heights, and each including: a power line, a ground line, and a well boundary extending parallel to each other along a first direction; two active regions having opposite conductivity types, disposed between the power line and the ground line and located on both sides of the well boundary; a gate line extending across the two active regions along a second direction, wherein the first direction is perpendicular to the second direction; abutting the first standard cell and the second standard cell with the well boundaries of the first standard cell aligned along the first direction to obtain a temporary cell layout; and moving the power line and the ground line of the second standard cell along the second direction to align with and connect to the power line and the ground line of the first standard cell along the first direction, thereby forming the integrated circuit layout from the temporary cell layout.

2. The method for forming an integrated circuit layout as described in claim 1, wherein the power line and the ground line of the second standard unit are moved by the same distance to form the integrated circuit layout.

3. The method for forming an integrated circuit layout as described in claim 1, wherein the well boundary of the first standard cell and the second standard cell overlaps with a center line of the first standard cell and the second standard cell, respectively.

4. The method of forming an integrated circuit layout as described in claim 1, wherein in the temporary cell layout, a center line of the first standard cell and a center line of the second standard cell are aligned along the first direction and parallel to the well boundary of the first standard cell and the second standard cell.

5. The method for forming an integrated circuit layout as described in claim 1, wherein in the temporary cell layout, a center line of the first standard cell and a center line of the second standard cell are misaligned in the first direction, and the power line and the ground line of the second standard cell are moved by different distances to form the integrated circuit layout.

6. The method for forming an integrated circuit layout as described in claim 1, wherein the first standard unit and the second standard unit further comprise: A conductive connector is attached to one edge of the power line and overlaps with one of the two active regions adjacent to the power line; And another conductive connector, connected to one edge of the grounding wire and overlapping with the other of the two active regions adjacent to the grounding wire, wherein the conductive connector of the second standard unit and the other conductive connector extend as the power line and the grounding wire move to form the integrated circuit layout.

7. The method of forming an integrated circuit layout as described in claim 1, wherein the power line and the ground line of the first standard cell and the second standard cell, and the power line of the second standard cell, are performed in an electronic design automation (EDA) environment.

8. The method for forming an integrated circuit layout as described in claim 1, wherein the first standard unit and the second standard unit further comprise: Two virtual gate lines are set on both sides of the two active regions and are parallel to the gate lines.

9. The method of forming an integrated circuit layout as described in claim 8, wherein the step of adjoining the first standard cell and the second standard cell includes combining one of the dummy gate lines of the first standard cell and one of the dummy gate lines of the second standard cell.

10. The method of forming an integrated circuit layout as described in claim 1, further comprising outputting the integrated circuit layout to a set of photomasks used in the process of manufacturing an integrated circuit wafer.

11. An integrated circuit layout, comprising: a power line and a ground line extending parallel to each other along a first direction; and a first standard cell and a second standard cell located between the power line and the ground line and adjacent to each other, and each including: an upper edge, a lower edge, and a well boundary located between the upper edge and the lower edge, extending parallel to each other along the first direction; and two active regions having opposite conductivity types disposed on both sides of the well boundary; a gate line extending between the upper edge and the lower edge and crossing the two active regions along a second direction, wherein the first direction is perpendicular to the second direction, wherein a first cell height between the upper edge and the lower edge of the first standard cell is different from a second cell height between the upper edge and the lower edge of the second standard cell, and the well boundary of the first standard cell and the well boundary of the second standard cell are aligned along the first direction.

12. The integrated circuit layout of claim 11, wherein a center line between the upper edge and the lower edge of the first standard cell and a center line between the upper edge and the lower edge of the second standard cell are aligned along the first direction.

13. The integrated circuit layout of claim 12, wherein the center line of the first standard cell and the boundary of the well area of ​​the second standard cell overlap.

14. The integrated circuit layout of claim 12, wherein the center line of the first standard unit and the boundary of the well area of ​​the second standard unit do not overlap.

15. The integrated circuit layout of claim 11, wherein the distance between the power line of the second standard unit and the upper edge is greater than the distance between the power line of the first standard unit and the upper edge.

16. The integrated circuit layout of claim 11, wherein: a center line between the upper edge and the lower edge of the first standard unit and a center line between the upper edge and the lower edge of the second standard unit are misaligned in the first direction; and the distance between the power line of the second standard unit and the upper edge is different from the distance between the ground line and the lower edge.

17. The integrated circuit layout of claim 11, wherein the edges of the active regions of the same conductivity type, adjacent to the first standard cell and the second standard cell and parallel to the boundary of the well region, are aligned along the first direction.

18. The integrated circuit layout of claim 11, wherein the edges of the active regions of the same conductivity type adjacent to the first standard cell and the second standard cell and parallel to the boundary of the well region include a misalignment in the first direction.

19. The integrated circuit layout of claim 18 further includes: a first conductive connector extending from an edge of the power line along the second direction for a first length and partially overlapping one of the active regions of the first standard cell; and a second conductive connector extending from the edge of the power line along the second direction for a second length and partially overlapping one of the active regions of the second standard cell, wherein the first length is different from the second length.

20. The integrated circuit layout of claim 11 further includes: a first dummy gate line disposed on one side of the first standard cell and relative to the second standard cell; a second dummy gate line disposed on one side of the second standard cell and relative to the first standard cell; and a third dummy gate line disposed between the first standard cell and the second standard cell, wherein the ends of the first dummy gate line and the third dummy gate line are respectively aligned with the end of the gate line of the first standard cell, and the end of the second dummy gate line is aligned with the end of the gate line of the second standard cell.

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