Semiconductor structure and method of fabricating the same

Abstract

The semiconductor structure includes a first multi-gate device, a second multi-gate device, and an isolation structure. The first multi-gate device has a first channel layer extending along a first direction between a first epitaxial source / drain. The second multi-gate device has a second channel layer extending along the first direction between a second epitaxial source / drain. The first and second epitaxial sources / drains have a first width and a second width, respectively, along a second direction different from the first direction. The isolation structure includes a dielectric fin above a substrate isolation member. The dielectric fin is located between the first and second epitaxial sources / drains. The dielectric fin has a third width along the second direction. The distance between the first and second epitaxial sources / drains along the second direction is greater than the third width, less than the second width, and less than the first width.

Description

Semiconductor structure and manufacturing method This invention relates to semiconductor manufacturing technology, and particularly to multi-gate devices and their manufacturing methods. Multi-gate devices include gate structures that extend partially or completely around a channel region to provide access to the channel region on at least two sides. Exemplary multi-gate devices include fin-like field-effect transistors (FinFETs) and gate-all-around (GAA) transistors, such as nanowire transistors. Multi-gate devices can significantly reduce integrated circuit technology, maintain gate control, and mitigate short-channel effects (SCE), while seamlessly integrating with conventional integrated circuit manufacturing processes. However, as multi-gate devices continue to shrink, epitaxial source / drain configurations are needed to facilitate smaller integrated circuit component sizes and the packaging required for denser advanced integrated circuit technology nodes. A semiconductor structure is provided according to some embodiments. This semiconductor structure includes a first multi-gate device having a first channel layer extending along a first direction between a plurality of first epitaxial source / drain electrodes, wherein the first epitaxial source / drain electrodes have a first width along a second direction different from the first direction; a second multi-gate device having a second channel layer extending along the first direction between a plurality of second epitaxial source / drain electrodes, wherein the second epitaxial source / drain electrodes have a second width along the second direction; an isolation structure having dielectric fins above a substrate isolation member, wherein the dielectric fins are located between the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes, and the dielectric fins have a third width along the second direction; and wherein the distance between the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes along the second direction is greater than the third width, less than the second width, and less than the first width. A semiconductor structure is provided according to some other embodiments. This semiconductor structure includes a first multi-gate device having a first channel layer extending along a first direction between a plurality of first epitaxial source / drain electrodes; a second multi-gate device having a second channel layer extending along the first direction between a plurality of second epitaxial source / drain electrodes; a third multi-gate device having a third channel layer extending along the first direction between a plurality of third epitaxial source / drain electrodes; a fourth multi-gate device having a fourth channel layer extending along the first direction between a plurality of fourth epitaxial source / drain electrodes; a first isolation fin and a second isolation fin, wherein the first isolation fin is located between the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes, and the second isolation fin is located between... Between the third epitaxial source / drain and the fourth epitaxial source / drain, the first isolation fin has a first width along a second direction different from the first direction, and the second isolation fin has a second width along the second direction; and wherein: the first multi-gate device is adjacent to the second multi-gate device, and the third multi-gate device is adjacent to the fourth multi-gate device, the first distance along the second direction is between the first epitaxial source / drain and the second epitaxial source / drain, the second distance along the second direction is between the third epitaxial source / drain and the fourth epitaxial source / drain, and the first distance is different from the second distance, the first distance is greater than the first width and the second distance is greater than the second width. According to some embodiments, a method for manufacturing a semiconductor structure is provided. This method includes forming a first fin, a second fin, a third fin, and a fourth fin extending from a substrate, wherein each of the first, second, third, and fourth fins extends longitudinally along a first direction, a first space is located between the first and second fins along a second direction different from the first direction, and a second space is located between the third and fourth fins along a second direction; forming a first isolation fin and a second isolation fin above the substrate, wherein the first isolation fin is located in the first space between the first and second fins, and the second isolation fin is located in the second space between the third and fourth fins, the first isolation fin having a first width along the second direction, and the second isolation fin having a second width along the second direction; in the first… A plurality of first epitaxial source / drain electrodes are formed above a fin, a plurality of second epitaxial source / drain electrodes are formed above a second fin, a plurality of third epitaxial source / drain electrodes are formed above a third fin, and a plurality of fourth epitaxial source / drain electrodes are formed above a fourth fin; and wherein the formation of the first epitaxial source / drain electrodes, the second epitaxial source / drain electrodes, the third epitaxial source / drain electrodes, and the fourth epitaxial source / drain electrodes is adjusted to provide: a first distance between the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes along a second direction, a second distance between the third epitaxial source / drain electrodes and the fourth epitaxial source / drain electrodes along a second direction, and wherein the first distance is different from the second distance, the first distance is greater than the first width, and the second distance is greater than the second width. The embodiments of the present invention generally relate to the configuration of epitaxial source / drain electrodes, which can enhance performance and / or facilitate dense packaging of multi-gate devices, such as fin field-effect transistors (FETs) and / or fully wound gate (GAA) field-effect transistors. The following provides many different embodiments or examples for implementing different components of embodiments of the present invention. Specific examples of components and configurations are described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to limit embodiments of the present invention. For example, the description mentioning that a first component is formed on or above a second component may include embodiments in which the first and second components are in direct contact, or embodiments in which an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Additionally, spatial relative terms may be used herein, such as “down,” “up,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), which are used to facilitate the description of the relationship between one component and another. These spatial relative terms are used to cover different orientations of the apparatus containing these components. Furthermore, when numerical values ​​or ranges are described using terms such as "about," "approximately," and similar expressions, these terms are intended to cover values ​​within a reasonable range that takes into account inherent variations during manufacturing that would be understandable to those skilled in the art. For example, a numerical value or range encompasses a reasonable range including, for instance, within + / -10% of the value, based on known manufacturing tolerances associated with the manufactured component, which possesses characteristics related to that value. For example, a material layer having a thickness of "about 5 nm" can cover a size range of 4.5 nm to 5.5 nm, where the manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / -10%. Moreover, reference numerals and / or letters may be repeated in different embodiments of the invention. This repetition is for simplification and clarity and does not represent a specific relationship between the different embodiments and / or configurations discussed. For advanced integrated circuit technology nodes, non-planar transistors, such as fin field-effect transistors and fully wound gate transistors (collectively referred to as multi-gate devices), have become popular and promising candidates for high-performance and low-leakage applications. Figure 1 is a partial perspective view of some or all of an illustrative multi-gate device 10 according to various aspects of an embodiment of the present invention. The multi-gate device 10 is a fin field-effect transistor comprising fins 15 extending from a substrate 20. The fins 15 have a length in the y-direction and a width (W) in the x-direction. finThe fin 15 has a non-recessed portion disposed between the recessed portions, and the fin field-effect transistor further includes a gate stack 25 and an epitaxial source / drain 30. The gate stack 25 covers and engages the non-recessed portions of the fin 15 (e.g., the gate stack 25 is disposed on the side walls and top of the non-recessed portions of the fin 15), and the epitaxial source / drain 30 is disposed above the recessed portions of the fin 15 (e.g., the epitaxial source / drain 30 is disposed on the top of the recessed portions of the fin 15). The fin field-effect transistor has a channel region (C) disposed between the source / drain regions (S / D), wherein the channel region is provided by the non-recessed portions of the fin 15, and the source / drain regions are provided by the epitaxial source / drain 30 and the recessed portions of the fin 15 below. During operation of the finned field-effect transistor, current can flow between the channel region (e.g., the non-recessed portion of fin 15) and the source / drain region (e.g., the epitaxial source / drain structure 30). The gate stack 25 has a gate length (L) along the y-direction. GIn the depicted embodiment, the gate stack 25 includes a gate dielectric 25A and a gate electrode 25B. In some embodiments, gate spacers are disposed along the sidewalls of the gate stack 25 and cover the non-recessed portions of the fin 15. A substrate isolation member 40 (e.g., a shallow trench isolation (STI) structure) electrically isolates the fin field-effect transistor from other devices and / or other regions of the multi-gate device 10. The substrate isolation member 40 is disposed above the substrate 20, along the sidewalls of the recessed portions of the fin 15, and along the sidewalls of the lower portion of the non-recessed portions of the fin 15. The gate stack 25 extends above the top of the substrate isolation member 40. In some embodiments, the substrate isolation member 40 surrounds the lower portion of the fin 15. In some embodiments, the fin 15 is not recessed in the source / drain region of the finned field-effect transistor, and the epitaxial source / drain 30 covers the fin 15 (e.g., the epitaxial source / drain 30 is disposed on the top and sidewalls of the fin 15). In some embodiments, dielectric sidewall spacers are formed before the epitaxial source, such as fin sidewall spacers disposed above the substrate isolation member 40 and along a portion of the sidewall of the fin 15, and gate spacers / drains 30 disposed above the substrate isolation member 40 and along the sidewall of the gate stack 25. In some embodiments, the multi-gate device 10 is part of an integrated circuit chip, a system-on-a-chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. For clarity, Figure 1 has been simplified to better understand the inventive concept of the embodiments of the present invention. Additional components may be added to the multi-gate device 10, and some components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 10. Metal contacts are typically formed to provide electrical connections to and facilitate the operation of the finned field-effect transistor, such as gate contacts to the gate stack 25 and source / drain contacts to the epitaxial source / drain 30. As the size of integrated circuit components continues to shrink with advanced integrated circuit technology nodes, the lateral dimensions of the epitaxial source / drain 30 decrease accordingly. This results in reduced landing windows / areas for the source / drain contacts and increased sensitivity of the finned field-effect transistor to source / drain contact coverage / alignment issues during manufacturing. To increase the landing windows / drain contacts, it is desirable to increase the lateral dimensions of the epitaxial source / drain 30, for example, by configuring epitaxial growth process parameters to increase the lateral growth of the epitaxial source / drain material and extending the epitaxial source / drain 30 laterally in the x-direction beyond the sidewalls of the fin 15. However, increasing the lateral dimensions of the epitaxial source / drain 30 reduces the spacing between the epitaxial source / drain 30 and the epitaxial source / drain 30 of adjacent fin field-effect transistors. This can lead to unintended merging of the epitaxial source / drain 30 with the epitaxial source / drain of adjacent fin field-effect transistors, especially when reducing fin pitch and / or gate pitch to increase device density. As an example, it has been observed that dopants extruded from the epitaxial source / drain during an annealing process to activate dopants in the epitaxial source / drain after deposition have caused merging of the epitaxial source / drain of adjacent fin field-effect transistors. As another example, it has been observed that dopants extruded from epitaxial source / drain electrodes during the annealing process performed to form source / drain contacts, such as dopants used to form silicon components above the epitaxial source / drain electrodes, can cause merging of the epitaxial source / drain electrodes of adjacent fin field-effect transistors. Unintended merging of the epitaxial source / drain electrodes of adjacent fin field-effect transistors can cause electrical short circuits, which reduce the performance and / or reliability of multi-gate devices. Furthermore, due to limitations in lithography resolution (i.e., the smallest component size that can be printed onto the photoresist layer), when fabricating fin field-effect transistors (FETs) with tighter fin pitch and / or fin spacing, the size of the photoresist opening used to expose the n-type FET region may be larger than intended, unintentionally exposing the p-type FET region. This can lead to the formation of n-type epitaxial source / drain residues in the p-type FET region when depositing n-type epitaxial source / drain material in the source / drain region of the n-type FET region. Such n-type epitaxial source / drain residues (sometimes referred to as device residual defects) can prevent and / or reduce the deposition of p-type epitaxial source / drain material in the source / drain region of the p-type FET region, and also negatively affect and / or undesirably alter the performance of the FET in the p-type FET region. Device residual defects may also occur in the n-type fin field-effect transistor region, such as p-type epitaxial source / drain residues. Embodiments of the present invention address these challenges and provide finned field-effect transistors with epitaxial source / drain electrodes having optimized lateral dimensions and / or lateral spacing for advanced technology nodes, such as those having a fin pitch of about 20 nm to about 35 nm and / or a gate pitch of about 35 nm to about 60 nm, to maximize finned field-effect transistor density and / or device density. For example, increasing the lateral dimensions (e.g., width) of the epitaxial source / drain electrodes relaxes source / drain contact alignment / coverage requirements and / or increases source / drain contact landing margin when forming source / drain contacts. The epitaxial source / drain electrodes described herein therefore have lateral dimensions and lateral spacing that maximize source / drain contact landing margin while minimizing and / or preventing unintended merging between the epitaxial source / drain electrodes of adjacent finned field-effect transistors. As another example, the lateral dimensions and spacing of the epitaxial source / drain described herein minimize epitaxial material residues (i.e., device residual defects) in both n-type and p-type finned transistor regions, where such residues may originate from limited lithography resolution. The lateral dimensions and / or spacing disclosed herein also take into account variations in the epitaxial source / drain profiles of different types of multi-gate devices and the additional isolation and / or merging prevention provided by the isolation fins disposed between the epitaxial source / drain. For example, the lateral spacing is configured to be greater than the width of the isolation fins to reduce and / or prevent epitaxial material residues formed and / or retained on the isolation fins during the fabrication of the epitaxial source / drain. Different embodiments may have different advantages, and no particular embodiment necessarily requires a specific advantage. Figures 2-4 are partial cross-sectional views of multi-gate devices having optimized epitaxial source / drain dimensions in some or all of their respective aspects according to embodiments of the present invention. For example, Figure 2 depicts multi-gate device 100, Figure 3 depicts multi-gate device 200, and Figure 4 depicts multi-gate device 300. Multi-gate devices 100, 200, and 300 each include at least one finned field-effect transistor, which generally refers to a transistor in which a channel is formed by at least one semiconductor fin extending from a substrate, wherein the channel is disposed between a source and a drain, and the gate of the transistor covers at least one semiconductor fin (e.g., the gate is disposed on three sides of the channel, opposite to one side of the channel in a planar transistor). The cross-sectional views of Figures 2-4 are obtained by "cutting" the finned field-effect transistors of multi-gate devices 100, 200, and 300 along the x-direction shown in Figure 1; therefore, Figures 2-4 can be referred to as x-section views. Furthermore, the x-section view captures the source / drain region of the fin field-effect transistor (i.e., the portion of the fin field-effect transistor that includes, for example, epitaxial source / drain regions and is located outside the gate / channel region of the fin field-effect transistor and therefore not covered by the gate). Therefore, the gates of the fin field-effect transistors in multi-gate devices 100, 200, and 300 are not directly visible in Figures 2-4. Multi-gate devices 100, 200, and 300, or combinations thereof, can be included in a microprocessor, memory, other integrated circuit devices, or combinations thereof. In some embodiments, multi-gate device 100, multi-gate device 200, multi-gate device 300, or combinations thereof are part of an integrated circuit chip, a SoC, or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. For clarity, Figures 2-4 have been simplified to better understand the inventive concept of the embodiments of the present invention. Additional components may be added to multi-gate device 100, multi-gate device 200, multi-gate device 300, or combinations thereof, and some components described below may be replaced, modified, or eliminated in other embodiments of multi-gate device 100, multi-gate device 200, multi-gate device 300, or combinations thereof. Referring to Figure 2, the multi-gate device 100 includes device region 102A and device region 102B. Device region 102A includes p-type fin field-effect transistors 104A and 104B, and device region 102B includes p-type fin field-effect transistors 104C, 104D, n-type fin field-effect transistors 106A and 106B. Each of the p-type fin field-effect transistors 104A-104D, n-type fin field-effect transistors 106A and 106B is a single-fin fin field-effect transistor (i.e., each fin field-effect transistor contains a single fin, wherein the channel of the fin field-effect transistor is formed in the single fin). For example, p-type fin field-effect transistors 104A to 104D have fins 110A, 110B, 110C, and 110D extending from the substrate 112, respectively, and each n-type fin field-effect transistor 106A and n-type fin field-effect transistor 106B has fins 110E and 110F extending from the substrate 112, respectively. The fins 110A to 110F are oriented substantially parallel to each other, extending longitudinally along the y-direction (i.e., length along the y-direction, width along the x-direction, and height along the z-direction), and are spaced apart from each other along the x-direction. In Figure 2, spacing S1 is between the fins of a p-type fin field-effect transistor (e.g., fins 110A and 110B are separated by spacing S1), spacing S2 is between the fins of an n-type fin field-effect transistor (e.g., fins 110E and 110F are separated by spacing S2), and spacing S3 is between the fins of different types of fin field-effect transistors (e.g., fins 110C and 110E are separated by spacing S3, and fins 110F and 110D are separated by spacing S3). In some embodiments, spacing S1 is about 40 nm to about 60 nm. In some embodiments, spacing S2 is about 40 nm to about 60 nm. In some embodiments, spacing S3 is about 35 nm to about 55 nm. In some embodiments, spacings S1, S2, and S3 are the same. In some embodiments, spacings S1 and S2 are different. In some embodiments, spacings S1 and S3 are different. In some embodiments, spacings S2 and S3 are different. Fins 110A-110F and / or substrate 112 comprise elemental semiconductors, such as silicon and / or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In some embodiments, substrate 112 is a silicon substrate, and fins 110A-110F comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, fins 110A-110F are part of substrate 112, such as part of a material layer of substrate 112. For example, if substrate 112 comprises silicon, fins 110A-110F are silicon fins. In some embodiments, fins 110A-110F are semiconductor layers disposed on substrate 112. In some embodiments, fins 110A to 110F comprise the same material (e.g., fins 110A to 110F are silicon fins). In some embodiments, fins 110A to 110F comprise different materials. In some embodiments, the composition of fins 110A to 110F is configured based on the type of fin field-effect transistor to which fins 110A to 110F belong. For example, fins 110A to 110D forming a portion of p-type fin field-effect transistors 104A to 104D are silicon-germanium fins, while fins 110E and 110F forming a portion of n-type fin field-effect transistors 106A and 106B are silicon fins. In some embodiments, substrate 112 is an insulator-on-semiconductor substrate, such as an insulator-on-silicon substrate, an insulator-on-silicon-germanium substrate, or an insulator-on-germanium substrate. In Figure 2, the source / drain regions of fins 110A to 110F are depicted as recessed portions of fins 110A to 110F. P-type fin field-effect transistors 104A to 104D each have a p-type epitaxial source / drain 120A extending from the recessed portions of fins 110A to 110D, and n-type fin field-effect transistors 106A and 106B each have an n-type epitaxial source / drain 120B extending from the recessed portions of fins 110E and 110F, respectively. The p-type epitaxial source / drain 120A comprises a semiconductor material doped with a p-type dopant (e.g., boron, indium, other p-type dopants, or combinations thereof). The n-type epitaxial source / drain 120B comprises a semiconductor material doped with an n-type dopant (e.g., phosphorus, arsenic, other n-type dopants, or combinations thereof). In some embodiments, the p-type epitaxial source / drain 120A and the n-type epitaxial source / drain 120B comprise the same semiconductor material. In some embodiments, the p-type epitaxial source / drain 120A and the n-type epitaxial source / drain 120B comprise different semiconductor materials. For example, the p-type epitaxial source / drain 120A comprises silicon and germanium doped with boron, other p-type dopants, or combinations thereof, and the n-type epitaxial source / drain 120B comprises silicon and / or carbon doped with phosphorus, other n-type dopants, or combinations thereof. In some embodiments, the p-type epitaxial source / drain 120A and / or the n-type epitaxial source / drain 120B have a multilayer structure, as described herein. Lightly doped source / drain (LDD) regions, heavily doped source / drain (HDD) regions, other doped regions, or combinations thereof can be provided in the p-type epitaxial source / drain 120A and / or the n-type epitaxial source / drain 120B. Such doped regions can extend into the fins 110A to 110F. In embodiments of the present invention considering cases where the source / drain regions of the fins 110A to 110F are not recessed, the p-type epitaxial source / drain 120A is disposed above the top and sidewalls of the fins 110A to 110D, and the n-type epitaxial source / drain 120B is disposed above the top and sidewalls of the fins 110E and 110F. In such an embodiment, the fins 110A to 110F can be covered by the corresponding p-type epitaxial source / drain 120A or n-type epitaxial source / drain 120B. In the depicted embodiment, the p-type epitaxial source / drain 120A and the n-type epitaxial source / drain 120B each have a lower portion and an upper portion. The lower portion of the p-type epitaxial source / drain 120A and the lower portion of the n-type epitaxial source / drain 120B extend laterally (e.g., along the x-direction) between the respective fin spacers 125, and vertically (e.g., along the z-direction) from the respective fins 110A to 110F to the top surface of the respective fin spacers 125, and the width is approximately equal to the width of the respective fins 110A to 110F. The upper portions of the p-type epitaxial source / drain 120A and the n-type epitaxial source / drain 120B extend vertically (e.g., along the z-direction) from the top surface of each fin spacer 125 to a height above each fin spacer 125, and laterally (e.g., along the x-direction) to a distance beyond the outer wall of the corresponding fin spacer 125 (i.e., the sidewall of the fin spacer 125 opposite to the inner sidewall of the fin spacer 125). The width W1 of the upper portion of the p-type epitaxial source / drain 120A is greater than the width of fins 110A to 110D, and the width W2 of the upper portion of the n-type epitaxial source / drain 120B is greater than the widths of fins 110E and 110F. Width W1 is the maximum width of the p-type epitaxial source / drain 120A along the x-direction, and width W2 is the maximum width of the n-type epitaxial source / drain 120B along the x-direction. In other words, widths W1 and W2 are located between the outermost walls (also referred to as the outermost surfaces, outermost points, and / or outermost facets) of the p-type epitaxial source / drain 120A and the n-type epitaxial source / drain 120B, respectively. In Figure 2, width W1 is greater than width W2. In some embodiments, this width difference arises from the p-type epitaxial source / drain 120A and the n-type epitaxial source / drain 120B having different cross-sectional profiles and / or shapes. For example, in Figure 2, the upper portion of the p-type epitaxial source / drain 120A is rhomboid, and the upper portion of the n-type epitaxial source / drain 120B is elliptical. In such embodiments, the lateral extension of the p-type epitaxial source / drain 120A beyond the fin spacer 125 is greater than the lateral extension of the n-type epitaxial source / drain 120B beyond the fin spacer 125. In some embodiments, width W1 is approximately 20 nm to approximately 40 nm. In some embodiments, the width W2 is from about 15 nm to about 35 nm. p-type epitaxial source / drain 120A and / or n-type epitaxial source / drain 120B with widths greater than about 40 nm and about 35 nm, respectively, may unintentionally merge with the epitaxial source / drain of directly adjacent different fin field-effect transistors, resulting in epitaxial-epithelial short circuits, electrical short circuits and / or device degradation.P-type epitaxial source / drain 120A and / or n-type epitaxial source / drain 120B with widths less than about 20 nm and about 15 nm, respectively, may not provide sufficient landing margin for the source / drain contacts, thereby increasing the difficulty of subsequent landing of the source / drain contacts on the p-type epitaxial source / drain 120A and / or n-type epitaxial source / drain 120B, and increasing the sensitivity of the fin field-effect transistor to source / drain contact misalignment and / or overlay shifts. Furthermore, p-type epitaxial source / drain 120A and / or n-type epitaxial source / drain 120B with widths less than about 20 nm and about 15 nm, respectively, may be too small to adequately offset and / or reduce short-channel effects (especially short-channel effects that may occur when the gate length of the transistor is less than about 10 nm), minimize parasitic capacitance, minimize parasitic resistance, or a combination thereof. Spacing S4 is between the epitaxial source / drain of a p-type single-fin fin field-effect transistor, for example, between the p-type epitaxial source / drain 120A of p-type fin field-effect transistors 104A and 104B. Spacing S5 is between the epitaxial source / drain of an n-type single-fin fin field-effect transistor, for example, between the n-type epitaxial source / drain 120B of n-type fin field-effect transistors 106A and 106B. Spacing S6 is located between the epitaxial source / drain electrodes of n-type single-fin fin field-effect transistors and p-type single-fin fin field-effect transistors, for example, between the p-type epitaxial source / drain electrode 120A of p-type fin field-effect transistor 104C and the n-type epitaxial source / drain electrode 120B of n-type fin field-effect transistor 106A, and between the n-type epitaxial source / drain electrode 120B of n-type fin field-effect transistor 106B and the p-type epitaxial source / drain electrode 120A of p-type fin field-effect transistor 104D. Spacing S4, spacing S5, and spacing S6 are each along the x-direction, for example, along the width direction of fins 110A to 110F and the width direction of p-type epitaxial source / drain electrode 120A and n-type epitaxial source / drain electrode 120B. Spacing S4, S5, and S6 are the minimum distances between the epitaxial sources / drains of directly adjacent fin field-effect transistors. For example, spacing S4 is the minimum distance between the p-type epitaxial sources / drains 120A of directly adjacent different p-type fin field-effect transistors, spacing S5 is the minimum distance between the n-type epitaxial sources / drains 120B of directly adjacent different n-type fin field-effect transistors, and spacing S6 is the minimum distance between the p-type epitaxial sources / drains 120A and n-type epitaxial sources / drains 120B of directly adjacent p-type fin field-effect transistors. Spacing S4 is smaller than spacing S1, spacing S5 is smaller than spacing S2, and spacing S6 is smaller than spacing S3 to allow lateral extension / expansion of the p-type epitaxial source / drain 120A and n-type epitaxial source / drain 120B (thus expanding the epitaxial volume and / or increasing the lateral dimensions of the epitaxial layer, which increases the landing area of ​​the source / drain contacts). Spacing S4 and spacing S5 are also smaller than widths W1 and W2, respectively. In some embodiments, spacings S4, S5, and / or S6 are also smaller than the width W3 of the isolation fin 140, which is inserted between adjacent epitaxial sources / drains of different finned field-effect transistors and is further described below. In some embodiments, the width W3 is about 5 nm to about 10 nm. In some embodiments, the spacing S4 is from about 15 nm to about 30 nm. In some embodiments, the spacing S5 is from about 10 nm to about 25 nm. In some embodiments, the spacing S6 is from about 10 nm to about 20 nm. Reducing the spacing S4, spacing S5, and / or spacing S6 to less than about 10 nm can lead to unintended merging of adjacent epitaxial sources / drains of different finned field-effect transistors during epitaxial source / drain formation, after epitaxial source / drain formation (e.g., during annealing processes for activating dopants in the epitaxial source / drain and / or during annealing processes performed during source / drain contact formation, such as annealing processes for forming silicon components above the epitaxial source / drain), other subsequent processes, or combinations thereof. In some embodiments, reducing the spacing S4, spacing S5, and / or spacing S6 to less than about 10 nm can lead to unintended merging of subsequently formed source / drain contacts with adjacent epitaxial sources / drains of different finned field-effect transistors. Furthermore, spacings that are too small (e.g., less than about 10 nm) for S4, S5, and / or S6 may not provide sufficient isolation between devices (i.e., the width W3 is correspondingly reduced). Increasing spacings for S4, S5, and / or S6 to greater than about 30 nm, 25 nm, and 20 nm, respectively, while maintaining a fixed fin pitch and / or fin spacing (e.g., spacings S1, S2, and S3, respectively) to maintain the desired fin field-effect transistor density and / or device density of the multi-gate device 100, can reduce the corresponding width and / or area of ​​the epitaxial source / drain, excessively reducing the landing margin of the source / drain contacts and making it difficult to land subsequently formed source / drain contacts on the epitaxial source / drain. Furthermore, increasing the spacings S4, S5, and / or S6 to greater than approximately 30 nm, 25 nm, and 20 nm, respectively, can reduce the corresponding volume of the epitaxial source / drain, making the epitaxial source / drain too small to adequately offset and / or reduce short-channel effects (especially those that may occur when the gate length of the transistor is less than approximately 10 nm), minimize parasitic capacitance, minimize parasitic resistance, or a combination thereof. Moreover, excessively large spacings S4, S5, and / or S6 (e.g., greater than approximately 30 nm, 25 nm, and 20 nm, respectively) undesirably reduce device density (i.e., fewer devices can be manufactured and / or located within a given area) and / or increase manufacturing costs. The multi-gate device 100 is configured with an optimal spacing between the epitaxial source / drain electrodes of single-fin FETs. For example, the epitaxial source / drain spacing (1F NN spacing and / or 1F PP spacing) between single-fin FETs of the same type is greater than the epitaxial source / drain spacing (1F NP spacing and / or 1F PN spacing) between single-fin FETs of different types, and the epitaxial source / drain spacing (1F PP spacing) between p-type single-fin FETs is greater than the epitaxial source / drain spacing (1F NN spacing) between n-type single-fin FETs. This spacing difference explains the profile variations of the different types of epitaxial source / drain electrodes and the additional isolation and / or additional reduction / prevention of unintended coalescence provided by the isolation fins 140. For example, because the width and lateral extension beyond the fin sidewall of an n-type epitaxial source / drain are smaller than those of a p-type epitaxial source / drain, adjacent NN and NP epitaxial sources / drains are less susceptible to unintended merging than adjacent PP epitaxial sources / drains. As another example, because n-type and p-type epitaxial sources / drains are typically formed separately to protect the n-type source / drain during p-type source / drain formation (e.g., by being covered by a masking layer, such as a photoresist layer) and / or vice versa, adjacent NP epitaxial sources / drains are less susceptible to unintended merging than adjacent PP and / or adjacent NN epitaxial sources / drains. Therefore, the 1F NN spacing (spacing S5, which accommodates two n-type epitaxial source / drain electrodes, with a width and lateral extension smaller than that of a p-type epitaxial source / drain electrode) and the 1F NP spacing (spacing S6, which accommodates the lateral dimension of one p-type epitaxial source / drain electrode and one n-type epitaxial source / drain electrode) can be configured to be smaller than the 1F PP spacing (spacing S4, which accommodates two p-type epitaxial source / drain electrodes, with a width and lateral extension larger than that of an n-type epitaxial source / drain electrode). In Figure 2, spacing S5 is smaller than spacing S4 (i.e., the 1F NN spacing is smaller than the 1F PP spacing), and spacing S6 is smaller than spacing S4 (i.e., the 1F NP / PN spacing is smaller than the 1F PP spacing). The spacing S5 is approximately 5% to approximately 30% smaller than the spacing S4, and the spacing S6 is approximately 20% to approximately 40% smaller than the spacing S4, to minimize unintended merging of adjacent epitaxial source / drain electrodes while maximizing the lateral dimensions of the epitaxial source / drain electrodes and the landing margin of the source / drain contacts. The spacing S6 is also smaller than the spacing S5 (i.e., the 1F NP / NP spacing is smaller than the 1F NN spacing), for example, approximately 20% to approximately 40% smaller than the spacing S5, to minimize unintended merging of adjacent epitaxial source / drain electrodes while maximizing the lateral dimensions of the epitaxial source / drain electrodes and the landing margin of the source / drain contacts. The channel regions of fins 110A to 110F are the non-recessed portions of fins 110A to 110F, depicted by dashed lines in Figure 2. In some embodiments, the p-type epitaxial source / drain 120A and / or the n-type epitaxial source / drain 120B contain materials and / or dopants in the channel regions of fins 110A to 110F that achieve the desired tensile and / or compressive stresses. The channel regions of fins 110A to 110F are located between and extend along the y-direction between the respective p-type epitaxial source / drain 120A or the respective n-type epitaxial source / drain 120B, and are depicted after the respective p-type epitaxial source / drain 120A or the respective n-type epitaxial source / drain 120B in Figure 2. The gate stack covers the channel regions of fins 110A-110F in the XZ plane (for example, each of fins 110A-110F has a corresponding gate stack disposed above its top and sidewalls), and in the YZ plane, above the top of the channel regions of fins 110A-110F. The gate stack is configured to achieve the desired function according to the design requirements of the multi-gate device 100, such that the gate stacks of p-type fin field-effect transistors 104A-104D, n-type fin field-effect transistors 106A and 106B can contain the same or different layers and / or materials. The multi-gate device 100 further includes various dielectric structures, such as fin spacers 125, substrate isolation members 130, isolation fins 140, and dielectric layers 150. For example, each depicted multi-gate device 100 has fin spacers 125 disposed along the sidewalls of its respective epitaxial source / drain (e.g., p-type epitaxial source / drain 120A or n-type epitaxial source / drain 120B). In the depicted embodiment, the fin spacers 125 have inner sidewalls and outer sidewalls relative to the inner sidewalls, wherein the inner sidewalls physically contact the p-type epitaxial source / drain 120A or n-type epitaxial source / drain 120B, and the outer sidewalls physically contact the dielectric layer 150. The fin spacer 125 further has a bottom surface that physically contacts the substrate isolation member 130 and a top surface that physically contacts the p-type epitaxial source / drain 120A or n-type epitaxial source / drain 120B, wherein the bottom and top surfaces extend between the inner and outer sidewalls. The fin spacer 125 comprises silicon, oxygen, carbon, nitrogen, other suitable dielectric material components, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitrocarbide, silicon nitrocarbon oxide, or combinations thereof. The fin spacer 125 may have a multilayer structure. For example, the fin spacer 125 may comprise a first dielectric layer and a second dielectric layer, the first dielectric layer comprising silicon nitride and / or silicon oxide, and the second dielectric layer comprising silicon nitrocarbon oxide. In some embodiments, the fin spacer 125 includes more than one set of spacers, such as fin spacer liners (e.g., L-shaped spacer liners) and main fin spacers disposed above the fin spacer liners. In some embodiments, the fin spacer 125 is omitted from the multi-gate device 100. The substrate isolation component 130, isolation fins 140, and dielectric layer 150 are combined to electrically isolate the active regions of the p-type fin field-effect transistor, n-type fin field-effect transistor, or combinations thereof in the multi-gate device 100, such as p-type fin field-effect transistors 104A-104D, n-type fin field-effect transistors 106A and 106B. The substrate isolation component 130 is disposed in the substrate 112 and electrically isolates the fins 110A-110F from each other. The substrate isolation component 130 is disposed along the source / drain regions of the fins 110A-110F, covers the sidewalls of the source / drain regions of the fins 110A-110F, and fills the gaps between the fins 110A-110F (e.g., gaps S1, S2, and S3). In Figure 2, the top surfaces of the source / drain regions of fins 110A-110F are lower than the top surface of the substrate isolation member 130, and the p-type epitaxial source / drain 120A and n-type epitaxial source / drain 120B extend below the top surface of the substrate isolation member 130. Therefore, the substrate isolation member 130 is also disposed along a portion of the sidewall of the p-type epitaxial source / drain 120A and / or the n-type epitaxial source / drain 120B and covers this portion. In some embodiments, the top surfaces of the source / drain regions of fins 110A-110F are above the top surface of the substrate isolation member 130, and the p-type epitaxial source / drain 120A and / or the n-type epitaxial source / drain 120B do not extend below the top surface of the substrate isolation member 130. The substrate isolation component 130 comprises silicon, oxygen, nitrogen, carbon, other suitable isolation and / or dielectric components, or combinations thereof. For example, the substrate isolation component 130 comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials, or combinations thereof. The substrate isolation component 130 is configured as a shallow trench isolation structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof. In the depicted embodiment, the substrate isolation component 130 is a shallow trench isolation structure. The substrate isolation component 130 may have a multilayer structure. In some embodiments, the substrate isolation component 130 includes an oxide layer disposed above a silicon nitride pad. In some embodiments, the substrate isolation component 130 includes a dielectric layer disposed above a doped pad, such as a borosilicate glass (BSG) pad and / or a phosphosilicate glass (PSG) pad. In some embodiments, the substrate isolation member 130 includes a bulk dielectric layer disposed above the dielectric pad. Isolation fins 140 are located between the epitaxial source / drain electrodes of different fin field-effect transistors and electrically isolate them, such as the p-type epitaxial source / drain 120A of p-type fin field-effect transistors 104A and 104B, the n-type epitaxial source / drain 120B of n-type fin field-effect transistors 106A and 106B, the p-type epitaxial source / drain 120A of p-type fin field-effect transistor 104C and the n-type epitaxial source / drain 120B of n-type fin field-effect transistor 106A, and the p-type epitaxial source / drain 120A of p-type fin field-effect transistor 104D and the n-type epitaxial source / drain 120B of n-type fin field-effect transistor 106B. Isolation fins 140 can further electrically isolate fins 110A to 110F from each other. Isolation fins 140 are disposed in dielectric layer 150 and extend into substrate isolation member 130, such that isolation fins 140 extend below the top surface of substrate isolation member 130. In Figure 2, isolation fins 140 further extend below the top surfaces of fins 110A to 110F. The spacing between adjacent epitaxial source / drain electrodes is configured to be greater than the width of isolation fins 140 to reduce and / or prevent the formation and / or retention of epitaxial source / drain residues on isolation fins 140 after the formation of epitaxial source / drain electrodes, thereby reducing and / or eliminating device residual defects. For example, when isolation fins 140 have a width W3 along the x-direction, spacings S4, S5, and S6 are greater than the width W3. In such an embodiment, dielectric layer 150 is located between isolation fins 140 and p-type epitaxial source / drain electrodes 120A and between isolation fins 140 and n-type epitaxial source / drain electrodes 120B. In some embodiments, the width W3 is from about 5 nm to about 10 nm, where 5 nm is the minimum permissible spacing between the active regions of directly adjacent devices (e.g., the minimum permissible spacing between epitaxial source / drain). In such embodiments, the spacing S6 can be greater than about 5 nm, and the spacings S4 and S6 can be greater than about 10 nm. The isolation fin 140 comprises silicon, oxygen, nitrogen, carbon, other suitable isolation and / or dielectric components, or combinations thereof. For example, the isolation fin 140 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, other suitable isolation materials, or combinations thereof. Embodiments of the invention consider various configurations of the isolation fin. For example, the isolation fin 140 may have a multilayer structure, such as a bulk dielectric layer (e.g., an oxide layer) disposed above a dielectric pad (e.g., a silicon nitride pad). In some embodiments, the isolation fin 140 comprises a lower dielectric portion and an upper dielectric portion, wherein the lower dielectric portion and the upper dielectric portion are configured differently. In some embodiments, the lower portion comprises a dielectric layer (e.g., an oxide layer) disposed above the dielectric pad. In some embodiments, the upper portion comprises a high dielectric constant dielectric layer. A dielectric layer 150 is disposed above the p-type epitaxial source / drain 120A, the n-type epitaxial source / drain 120B, the fin spacer 125, the substrate isolation member 130, and the isolation fin 140. Because the spacings S4, S5, and S6 are smaller than the width W3, the dielectric layer 150 is located between the isolation fin 140 and the p-type epitaxial source / drain 120A, the isolation fin 140 and the n-type epitaxial source / drain 120B, and the isolation fin 140 and the fin spacer 125. The dielectric layer 150 contains a dielectric material that differs from the dielectric material on the outer surface of the insulating fin 140, allowing the dielectric layer 150 to be selectively etched relative to the isolation fin 140 during source / drain contact formation. The dielectric layer 150 can have a multilayer structure, such as an interlayer dielectric (ILD) layer formed above the contact etch stop layer (CESL). The interlayer dielectric layer comprises a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), fluorosilicone glass (FSG), Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, phenylcyclobutene-based dielectric materials (BCB), SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the interlayer dielectric layer comprises a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, the interlayer dielectric layer comprises a dielectric material with a dielectric constant less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as SiO2. 2 (e.g., porous silicon dioxide), silicon carbide (SiC) and / or carbon-doped oxides (e.g., materials based on SiCOH (having, for example, Si-CH) (3-bond), each of these dielectric materials is tuned / configured to have a dielectric constant of less than about 2.5. The interlayer dielectric layer can comprise a multilayer structure with multiple dielectric materials. The contact etch stop layer comprises a material different from that of the interlayer dielectric layer, such as a dielectric material different from that of the interlayer dielectric layer. For example, where the interlayer dielectric layer comprises a dielectric material containing silicon and oxygen and has a dielectric constant less than that of silicon dioxide, the contact etch stop layer may comprise silicon and nitrogen, such as silicon nitride or silicon oxynitride. Referring to Figure 3, for clarity and simplification, similar components of the multi-gate device 100 in Figure 2 and the multi-gate device 200 in Figure 3 are represented by the same reference numerals. The multi-gate device 200 is similar to the multi-gate device 100 in many aspects. For example, the multi-gate device 200 includes fins 210A-210F similar to fins 110A-110F, a substrate 212 similar to a substrate 112, a p-type epitaxial source / drain 220A similar to a p-type epitaxial source / drain 120A, an n-type epitaxial source / drain 220B similar to an n-type epitaxial source / drain 120B, fin spacers 125, a substrate isolation member 130, isolation fins 140, and a dielectric layer 150. In Figure 3, the multi-gate device 200 includes device regions 202A and 202B. Device region 202A includes p-type fin field-effect transistors 204A and 204B, and device region 202B includes n-type fin field-effect transistors 206A and 206B. The p-type fin field-effect transistors 204A and 206A are single-fin fin field-effect transistors (i.e., each fin field-effect transistor includes one fin, wherein the channel of the fin field-effect transistor is formed in one fin), and the p-type fin field-effect transistors 204B and 206B are double-fin fin field-effect transistors (i.e., each fin field-effect transistor includes two fins, wherein the channel of the fin field-effect transistor is formed in both fins). For example, p-type fin field-effect transistor 204A includes fins 210A extending from substrate 212, p-type fin field-effect transistor 204B includes fins 210B and fins 210C extending from substrate 212, n-type fin field-effect transistor 206A includes fins 210D extending from substrate 212, and n-type fin field-effect transistor 206B includes fins 210E and fins 210F extending from substrate 212. Spacing S7 is between the fins of a p-type dual-fin fin field-effect transistor (e.g., fins 210B and 210C are separated by spacing S7), spacing S8 is between the fins of a p-type single-fin fin field-effect transistor and the fins of a p-type dual-fin fin field-effect transistor (e.g., fins 210A and 210B are separated by spacing S8), spacing S9 is between the fins of an n-type dual-fin fin field-effect transistor (e.g., fins 210E and 210F are separated by spacing S9), and spacing S10 is between the fins of an n-type single-fin fin field-effect transistor and the fins of an n-type dual-fin fin field-effect transistor (e.g., fins 210D and 210E are separated by spacing S10). In Figure 3, spacing S7 is greater than spacing S8 and spacing S9 is greater than spacing S10 to optimize epitaxial source / drain merging. For example, such spacing enhances the merging of epitaxial source / drain electrodes of directly adjacent dual-fin FETs while preventing the merging of epitaxial source / drain electrodes of single-fin FETs with the epitaxial source / drain electrodes of other directly adjacent FETs. In some embodiments, spacing S7 is about 10 nm to about 20 nm. In some embodiments, spacing S8 is about 40 nm to about 60 nm. In some embodiments, spacing S9 is about 10 nm to about 20 nm. In some embodiments, spacing S10 is about 40 nm to about 60 nm. Epitaxial source / drain electrodes grown from fins with a spacing of S7 and / or S9 greater than about 20 nm may not merge to provide merged epitaxial source / drain electrodes for a dual-fin fin field-effect transistor. However, when the spacings S8 and / or S10 are each less than about 40 nm, epitaxial source / drain electrodes grown from the fins of a single-fin fin field-effect transistor may undesirably merge with the epitaxial source / drain electrodes of a directly adjacent dual-fin fin field-effect transistor. In some embodiments, spacings S7 and S9 are the same. In some embodiments, spacings S7 and S9 are different. In some embodiments, spacings S8 and S10 are the same. In some embodiments, spacings S8 and S10 are different. The P-type fin field-effect transistor 204A has a p-type epitaxial source / drain 220A extending from the recessed portion of fin 210A, and the n-type fin field-effect transistor 206A has an n-type epitaxial source / drain 220B extending from the recessed portion of fin 210D. The p-type epitaxial source / drain 220A of the P-type fin field-effect transistor 204B extends from the recessed portions of fins 210B and fin 210C and merges together to form a merged p-type epitaxial source / drain 220A-M, and the n-type epitaxial source / drain 220B of the n-type fin field-effect transistor 206B extends from the recessed portions of fins 210E and fin 210F and merges together to form a merged n-type epitaxial source / drain 220B-M. The upper portion of the p-type epitaxial source / drain 220A of the p-type fin field-effect transistor 204A has a width W1, and the upper portion of the n-type epitaxial source / drain 220B of the n-type fin field-effect transistor 206A has a width W2. The upper portion of the combined p-type epitaxial source / drain 220A-M of the p-type fin field-effect transistor 204B has a width W4, and the upper portion of the combined n-type epitaxial source / drain 220B-M of the n-type fin field-effect transistor 206B has a width W5. Width W4 is the maximum width of the combined p-type epitaxial source / drain 220A-M along the x-direction, and width W5 is the maximum width of the combined n-type epitaxial source / drain 220B-M along the x-direction. In other words, widths W4 and W5 are located between the outermost walls of the combined p-type epitaxial source / drain 220A-M and the combined n-type epitaxial source / drain 220B-M, respectively. In Figure 3, width W4 is greater than width W5. In some embodiments, this width difference arises from the p-type epitaxial source / drain 220A and n-type epitaxial source / drain 220B having different cross-sectional profiles and / or shapes. For example, in Figure 3, the upper portion of the p-type epitaxial source / drain 220A is rhomboid, and the upper portion of the n-type epitaxial source / drain 220B is elliptical. In some embodiments, width W4 is from about 40 nm to about 80 nm. In some embodiments, width W5 is from about 35 nm to about 65 nm. Widths W4 and W5 less than approximately 40 nm and 35 nm, respectively, may not provide sufficient landing areas for the source / drain contacts, while widths W4 and W5 greater than approximately 80 nm and 65 nm, respectively, may be too large for the fin pitch and / or fin spacing of advanced technology nodes, leading to unintended merging and / or device defects (e.g., epitaxial residues). In some embodiments, the ratio of width W4 to width W5 is approximately 1.1 to approximately 1.5. In some embodiments, the length (d1) of the merged region along the z-direction of the merged p-type epitaxial source / drain 220A-M is greater than the length (d2) of the merged region along the z-direction of the n-type epitaxial source / drain 220A-M. Spacing S11 is located between the p-type epitaxial source / drain 220A of the p-type fin field-effect transistor 204A and the combined p-type epitaxial source / drain 220A-M of the p-type fin field-effect transistor 204B, and spacing S12 is located between the n-type epitaxial source / drain 220B of the n-type fin field-effect transistor 206A and the combined n-type epitaxial source / drain 220B-M of the n-type fin field-effect transistor 206B. Spacing S11 and spacing S12 are along the x-direction, for example, the width direction of fins 210A to 210F. Spacing S11 is the minimum distance between the epitaxial source / drain electrodes of directly adjacent p-type single-fin and p-type double-fin field-effect transistors, and spacing S12 is the minimum distance between the epitaxial source / drain electrodes of directly adjacent n-type single-fin and n-type double-fin field-effect transistors. For example, spacing S11 is the minimum distance between the p-type epitaxial source / drain 220A of p-type fin field-effect transistor 204A and the combined p-type epitaxial source / drain 220A-M of p-type fin field-effect transistor 204B, and spacing S12 is the minimum distance between the n-type epitaxial source / drain 220B of n-type fin field-effect transistor 206A and the combined n-type epitaxial source / drain 220B-M of n-type fin field-effect transistor 206B. In some embodiments, spacing S11 is from about 15 nm to about 30 nm. In some embodiments, the spacing S12 is from about 20 nm to about 35 nm. Reducing the spacing S11 and / or the spacing S12 to less than about 15 nm can lead to unintended merging of epitaxial source / drain electrodes with directly adjacent different fin field-effect transistors during epitaxial source / drain formation, during heat treatment after epitaxial source / drain formation (e.g., during annealing processes to activate dopants in the epitaxial source / drain after deposition and / or during annealing processes implemented during source / drain contact formation, such as annealing processes to form silicon components above the epitaxial source / drain), other subsequent processes, or combinations thereof. In some embodiments, reducing the spacing S11 and / or the spacing S12 to less than about 15 nm may result in unintended merging of subsequently formed source / drain contacts with directly adjacent epitaxial source / drain electrodes of different fin field-effect transistors. While maintaining a fixed fin pitch and / or fin spacing (e.g., spacing S8 and spacing S10 respectively) to maintain the desired fin field-effect transistor density and / or device density of the multi-gate device 200, increasing the spacing S11 and / or spacing S12 to greater than about 35 nm can reduce the corresponding width and / or area of ​​the epitaxial source / drain, which reduces the landing margin of the source / drain contacts, making it difficult to land the subsequently formed source / drain contacts on the epitaxial source / drain.Furthermore, increasing the spacing S11 and / or the spacing S12 to greater than about 35 nm can reduce the corresponding volume of the epitaxial source / drain, making the epitaxial source / drain too small to adequately offset and / or reduce short-channel effects (especially short-channel effects that may occur when the gate length of the transistor is less than about 10 nm), minimize parasitic capacitance, minimize parasitic resistance, or a combination thereof. The multi-gate device 200 is configured with the optimal spacing between the epitaxial source / drain electrodes of the same type of single-fin fin field-effect transistor and double-fin fin field-effect transistor. For example, the epitaxial source / drain spacing (1F to 2F PP spacing) between p-type single-fin and p-type double-fin FETs is smaller than that between n-type single-fin and n-type double-fin FETs (1F to 2F NN spacing), the epitaxial source / drain spacing between p-type single-fin and p-type double-fin FETs is larger than that between p-type single-fin FETs (1F PP spacing), and the epitaxial source / drain spacing between n-type single-fin and n-type double-fin FETs is larger than that between n-type single-fin FETs (1F NN spacing). This spacing difference explains the profile variations of the different types of epitaxial source / drains and the additional isolation and / or additional merging prevention provided by the isolation fins 140. For example, in Figure 3, the spacings S11 and S12 are greater than the width W3 (i.e., the width of the isolation fin 140), the spacing S11 is less than the spacing S12 (i.e., the 1F to 2F PP spacing is less than the 1F to 2F NN spacing), the spacing S11 is greater than the spacing S4 (i.e., the 1F to 2F PP spacing is greater than the 1F PP spacing), and the spacing S12 is greater than the spacing S5 (i.e., the 1F to 2F NN spacing is greater than the 1F NN spacing). The spacing S12 is greater than the spacing S11 because the widths of the n-type epitaxial source / drain (e.g., widths W2 and W5) are less than the widths of the p-type epitaxial source / drain (e.g., widths W1 and W4), therefore the spacing between adjacent NN epitaxial sources / drains is greater than the spacing between adjacent PP epitaxial sources / drains. In some embodiments, the difference between the spacings S12 and S11 (i.e., spacing S12 - spacing S11) is approximately 3 nm to approximately 10 nm. Spacing S11 and spacing S12 are also greater than widths W1 and W2, respectively. Furthermore, to ensure the merging of the epitaxial sources / drains of the dual-fin FET, the epitaxial growth / deposition parameters used to form the epitaxial sources / drains of the dual-fin FET can be configured differently from those used to form the epitaxial sources / drains of the single-fin FET. For example, a longer deposition time can be used when forming the epitaxial sources / drains of the dual-fin FET compared to when forming the epitaxial sources / drains of the single-fin FET, to ensure that the epitaxial sources / drains growing from the two fins merge with each other. The different epitaxial growth / deposition parameters ensuring merging result in the merged epitaxial sources / drains having a greater lateral growth outside the fin sidewalls of the dual-fin FET than the epitaxial sources / drains outside the fin sidewalls of the single-fin FET.This invention addresses this lateral growth difference by configuring the 1F to 2F PP spacing to be greater than the 1F PP spacing and the 1F to 2F NN spacing to be greater than the 1F NN spacing, thereby preventing unintended merging of epitaxial source / drain electrodes of the same type of dual-fin FET and adjacent single-fin FET. In some embodiments, the difference between spacing S4 and spacing S11 (i.e., spacing S11 - spacing S4) is about 2 nm to about 10 nm. In some embodiments, the difference between spacing S5 and spacing S12 (i.e., spacing S12 - spacing S5) is about 5 nm to about 10 nm. Referring to Figure 4, for clarity and simplification, similar components of the multi-gate device 100 in Figure 2, the multi-gate device 200 in Figure 3, and the multi-gate device 300 in Figure 4 are represented by the same reference numerals. The multi-gate device 300 is similar to the multi-gate device 100 and / or the multi-gate device 200 in many aspects. For example, the multi-gate device 300 includes fins 310A-310D similar to fins 110A-110F and / or fins 210A-210F, a substrate 312 similar to substrate 112 and / or substrate 212, a p-type epitaxial source / drain 320A similar to p-type epitaxial source / drain 120A and / or p-type epitaxial source / drain 220A, and an n-type epitaxial source / drain 120B and... / or n-type epitaxial source / drain 320B of n-type epitaxial source / drain 220B, similar to the combined p-type epitaxial source / drain 220A-M, similar to the combined n-type epitaxial source / drain 220B-M, fin spacer 125, substrate isolation member 130, isolation fin 140, and dielectric layer 150. In Figure 4, the multi-gate device 300 includes a device region 302 having a p-type fin field-effect transistor 304 and an n-type fin field-effect transistor 306. Both the p-type fin field-effect transistor 304 and the n-type fin field-effect transistor 306B are dual-fin fin field-effect transistors (i.e., each fin field-effect transistor includes two fins, wherein the channel of the fin field-effect transistor is formed in the two fins). For example, the p-type fin field-effect transistor 304 includes fins 310A and fins 310B extending from the substrate 312 and having a spacing S7, and the n-type fin field-effect transistor 306 includes fins 310C and fins 310D extending from the substrate 312 and having a spacing S9. The p-type epitaxial source / drain 320A of the p-type fin field-effect transistor 304 extends from and merges with the recessed portions of fins 310A and fins 310B to form a merged p-type epitaxial source / drain 320A-M with a width W4, and the n-type epitaxial source / drain 320B of the n-type fin field-effect transistor 306 extends from and merges with the recessed portions of fins 310C and fins 310D to form a merged n-type epitaxial source / drain 320B-M with a width W5. In Figure 4, the spacing S14 is between the combined p-type epitaxial source / drain 320A-M of the p-type fin field-effect transistor 304 and the combined n-type epitaxial source / drain 320B-M of the n-type fin field-effect transistor 306. The spacing S14 is along the x-direction, for example, the width direction of the fins 310A-310D and the width direction of the combined p-type epitaxial source / drain 320A-M and the combined n-type epitaxial source / drain 320B-M. The spacing S14 is the minimum distance between the combined epitaxial source / drain of directly adjacent dual-fin fin field-effect transistors of different types. For example, the spacing S14 is the minimum distance between directly adjacent combined p-type epitaxial source / drain 320A-M and combined n-type epitaxial source / drain 320B-M. In some embodiments, the spacing S14 is from about 15 nm to about 25 nm. Reducing the spacing S14 to less than about 15 nm would result in the unintended merging of the p-type epitaxial source / drain 320A-M and the n-type epitaxial source / drain 320B-M during epitaxial source / drain formation, during heat treatment after epitaxial source / drain formation (e.g., during annealing processes performed after deposition to activate dopants in the epitaxial source / drain and / or during annealing processes performed during source / drain contact formation, such as annealing processes for forming silicon components above the epitaxial source / drain), other subsequent processes, or combinations thereof. While maintaining a fixed fin pitch and / or fin spacing (e.g., spacing S13) to maintain the desired fin field-effect transistor density and / or device density of the multi-gate device 300, increasing the spacing S14 to greater than about 25 nm can reduce the corresponding width and / or area of ​​the combined p-type epitaxial source / drain 320A-M and / or the combined n-type epitaxial source / drain 320B-M, which reduces the landing margin of the source / drain contacts, making it difficult to land the subsequently formed source / drain contacts on the combined p-type epitaxial source / drain 320A-M and / or the combined n-type epitaxial source / drain 320B-M. The multi-gate device 300 is configured with an optimal spacing between the epitaxial source / drain electrodes of different types of dual-fin FETs. For example, the epitaxial source / drain spacing (2F NP spacing) between different types of dual-fin FETs is smaller than the epitaxial source / drain spacing between p-type single-fin FETs, larger than the epitaxial source / drain spacing between n-type single-fin FETs, and larger than the epitaxial source / drain spacing between different types of single-fin FETs. In Figure 4, the spacing S14 is larger than the width W3 (i.e., the width of the isolation fin 140), smaller than the spacing S4 (1F PP spacing), larger than the spacing S5 (1F NN spacing), and larger than the spacing S6 (1F NP spacing). This spacing difference explains the profile variations of the different types of epitaxial source / drain electrodes and the additional isolation and / or additional merging prevention provided by the isolation fin 140. For example, because the width and lateral extension beyond the fin sidewalls of an n-type epitaxial source / drain are smaller than those of a p-type epitaxial source / drain, adjacent NP epitaxial sources / drains are less likely to accidentally merge than adjacent PP epitaxial sources / drains, but more likely to accidentally merge than adjacent NN epitaxial sources / drains. Therefore, a 2F NP pitch (pitch S14, which accommodates the lateral dimensions of one p-type epitaxial source / drain and one n-type epitaxial source / drain) can be configured to be smaller than a 1F PP pitch (pitch S4, which accommodates two p-type epitaxial sources / drains, whose width and lateral extension are greater than those of an n-type epitaxial source / drain) but larger than a 1F NN pitch (pitch S5, which accommodates two n-type epitaxial sources / drains, whose width and lateral extension are smaller than those of a p-type epitaxial source / drain). In some embodiments, the difference between pitch S4 and pitch S14 (i.e., pitch S4 - pitch S14) is approximately 2 nm to approximately 6 nm. In some embodiments, the difference between spacing S14 and spacing S5 (i.e., spacing S14 - spacing S5) is approximately 1 nm to approximately 5 nm. Furthermore, to ensure the merging of the epitaxial sources / drains of the dual-fin FET, the epitaxial growth / deposition parameters for forming the epitaxial sources / drains of the dual-fin FET can be configured differently from the epitaxial growth / deposition parameters for forming the epitaxial sources / drains of the single-fin FET. For example, a longer deposition time can be used when forming the epitaxial sources / drains of the dual-fin FET compared to when forming the epitaxial sources / drains of the single-fin FET, to ensure that the epitaxial sources / drains growing from the two fins merge with each other. Ensuring that the different epitaxial growth / deposition parameters of the merged epitaxial source / drain will result in the lateral growth of the merged epitaxial source / drain outside the fin sidewall of the dual-fin fin field-effect transistor being greater than the lateral growth of the epitaxial source / drain outside the fin sidewall of the single-fin fin field-effect transistor.This invention addresses this lateral growth difference by configuring the 2F NP spacing to be greater than the 1F NP spacing, thereby preventing unintended merging between adjacent epitaxial source / drain electrodes of different types of dual-fin fin field-effect transistors. This invention provides embodiments in which the device regions and / or fin field-effect transistors of multi-gate devices 100, 200, and / or 300 are fabricated on the same or different wafers to provide different devices and / or structures. For example, this invention provides embodiments of various multi-gate devices including device regions 102A, 102B, 202A, 202B, 302, or combinations thereof. In another example, embodiments of the invention consider various embodiments of multi-gate devices comprising p-type fin field-effect transistors 104A, 104B, 104C, 104D, 106A, 106B, 204A, 204B, 206A, 206B, 304, 306, or combinations thereof. In some embodiments, the various device regions are directly adjacent to each other. In some embodiments, the various device regions are located at different positions on the wafer, such that one or more other device regions and / or device structures are disposed between them. Figures 5A to 5F are partial cross-sectional views of the p-type device region 402A of the multi-gate device at various manufacturing stages according to embodiments of the present invention. Figures 6A to 6F are partial cross-sectional views of the n-type device region 402B of the multi-gate device at various manufacturing stages according to embodiments of the present invention. The p-type device region 402A is similar to the device region 202A of the multi-gate device 200, while the n-type device region 402B is similar to the device region 202B of the multi-gate device 200. For ease of description and understanding, Figures 5A to 5F and Figures 6A to 6F are discussed herein. For clarity, Figures 5A to 5F and Figures 6A to 6F have been simplified to better understand the inventive concept of the embodiments of the present invention. Additional components may be added to the p-type device region 402A and / or n-type device region 402B of the depicted multi-gate device, and some of the components described below may be replaced, modified or eliminated in other embodiments of the p-type device region 402A and / or n-type device region 402B of the depicted multi-gate device. Turning to Figures 5A and 6A, the process begins after forming fins, forming isolation structures, and forming dummy gates, receiving a multi-gate device. The multi-gate device includes a p-type device region 402A, which includes a p-type fin field-effect transistor 404A with two fins (e.g., fins 410A and 410B) and a p-type fin field-effect transistor 404B with one fin (e.g., fin 410C), and an n-type device region 402B, which includes an n-type fin field-effect transistor 406A with two fins (e.g., fins 410D and 410E) and an n-type fin field-effect transistor 406B with one fin (e.g., fin 410F). Fins 410A–410F are similar to fins 110A–110F, fins 210A–210F, and / or fins 310A–310D as described herein. P-type device region 402A and n-type device region 402B each further include a fin spacer 425 similar to fin spacer 125, a base isolation member 430 similar to base isolation member 130, and an isolation fin 440 similar to isolation fin 140. In some embodiments, the base 412 is a silicon substrate, the fins 410A to 410C are silicon-germanium fins, and the fins 410D to 410F are silicon fins. In Figure 5A, there is a spacing S8 between fins 410A and fins 410B, a spacing S7 between fins 410B and fins 410C, fins 410A to 410C have a height H1 along the z-direction, and the fin spacer 425 has a height H2 along the z-direction. In Figure 6A, there is a spacing S9 between fins 410D and fins 410E, a spacing S10 between fins 410E and fins 410F, fins 410D-410F having a height H3 along the z-direction, and fin spacer 425 having a height H4 along the z-direction. In some embodiments, height H1 is about 30 nm to about 80 nm. In some embodiments, height H2 is about 5 nm to about 20 nm. In some embodiments, height H3 is about 30 nm to about 80 nm. In some embodiments, height H4 is about 5 nm to about 20 nm. In some embodiments, heights H1 and H3 are the same. In some embodiments, heights H1 and H3 are different. In some embodiments, heights H2 and H4 are the same. In some embodiments, heights H2 and H4 are different. In some embodiments, the height and / or width of fin spacer 425 can be configured to control the shape and / or profile of the subsequently formed epitaxial source / drain electrode. Turning to Figures 5B and 6B, an etching process is performed to form source / drain grooves (trenches) 442A in the source / drain regions of fins 410A–410C, and source / drain grooves 442B in the source / drain regions of fins 410D–410F. Source / drain grooves 442A extend to a depth D1 below the top surface of the substrate isolation member 430 (e.g., those in contact with the bottom of the fin spacer 425), and source / drain grooves 442B extend to a depth D2 below the top surface of the substrate isolation member 430 (e.g., those in contact with the bottom of the fin spacer 425). In such an embodiment, portions of fins 410A–410F between the fin spacers 425 are removed by the etching process. In some embodiments, depth D1 is about 2 nm to about 10 nm. In some embodiments, depth D2 is about 2 nm to about 10 nm. In some embodiments, depths D1 and D2 are the same. In some embodiments, depth D1 and depth D2 are different. The etching process selectively removes fins 410A to 410F relative to the isolation fins 440, the substrate isolation member 430, and / or the fin spacers 425. In other words, the etching process substantially removes fins 410A to 410F, but does not remove or substantially does not remove the isolation fins 440, the substrate isolation member 430, and / or the fin spacers 425. For example, the etchant used in the etching process is selected to etch the semiconductor material (e.g., fins 410A to 410F) at a higher rate than the semiconductor material (e.g., isolation fins 440, substrate isolation member 430, and / or fin spacers 425). In the depicted embodiment, the etching process removes a portion of the fin spacers 425 such that the fin spacers 425 have varying heights and / or widths after the formation of the source / drain recesses 442A and / or source / drain recesses 442B. In some embodiments, the etching process may etch the top surface of the substrate isolation member 430. The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In the depicted embodiment, the fins of a single-fin fin field-effect transistor and the fins of a double-fin fin field-effect transistor are etched simultaneously (i.e., fins 410A-410C and / or fins 410D-410F are etched simultaneously). In some embodiments, different etching processes are used to etch the fins of the single-fin fin field-effect transistor and the fins of the double-fin fin field-effect transistor, respectively. In some embodiments, the fins of a p-type fin field-effect transistor and the fins of an n-type fin field-effect transistor are etched simultaneously (i.e., fins 410A-410F are etched simultaneously). In some embodiments, different etching processes are used to etch the fins of the p-type fin field-effect transistor and the fins of the n-type fin field-effect transistor, respectively. For example, a first etching process can be performed on fins 410A to 410C to form source / drain grooves 442A, and a second etching process can be performed on fins 410D to 410F to form source / drain grooves 442B.In such an embodiment, the patterning layer (e.g., a hard mask layer and / or a photoresist layer) may cover the n-type device region 402B during the first etching process, and the patterning layer may cover the p-type device region 402A during the second etching process. Turning to Figures 5C-5E and 6C-6E, the process continues to form various epitaxial source / drain electrodes, such as the combined p-type epitaxial source / drain electrode 420A-M of p-type fin field-effect transistor 404A, the p-type epitaxial source / drain electrode 420A of p-type fin field-effect transistor 404B, the combined n-type epitaxial source / drain electrode 420B-M of n-type fin field-effect transistor 406A, and the n-type epitaxial source / drain electrode 420B of n-type fin field-effect transistor 406B. For example, the process includes epitaxially growing a first semiconductor layer in a source / drain trench, such as epitaxial layer 444A in source / drain trench 442A and epitaxial layer 444B in source / drain trench 442B (Figures 5C and 6C); epitaxially growing a second semiconductor layer over the first semiconductor layer in the source / drain trench, such as epitaxial layer 446A in source / drain trench 442A and epitaxial layer 446B in source / drain trench 442B (Figures 5D and 6D); and epitaxially growing a third semiconductor layer over the second semiconductor layer in the source / drain trench, such as epitaxial layer 448A in source / drain trench 442A and epitaxial layer 448B in source / drain trench 442B (Figures 5E and 6E). The first semiconductor layer, such as epitaxial layer 444A and epitaxial layer 444B, has a first dopant concentration. The second semiconductor layer, such as epitaxial layers 446A and 446B, has a second dopant concentration. The third semiconductor layer, such as epitaxial layers 448A and 448B, has a third dopant concentration. The first, second, and third dopant concentrations are different. For example, the second dopant concentration is greater than both the first and third dopant concentrations, and the third dopant concentration is greater than the first dopant concentration. The formation of epitaxial layers 444A, 444B, 446A, 446B, 448A, 448B, or combinations thereof can be achieved by performing chemical vapor deposition (CVD) techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), and / or plasma-enhanced CVD (PECVD)), molecular beam epitaxy, other suitable selective epitaxy growth (SEG) processes, or combinations thereof. In some embodiments, epitaxial layers 444A, 444B, 446A, 446B, 448A, 448B, or combinations thereof are formed by selective chemical vapor deposition, such as remote plasma chemical vapor deposition (RPCVD), which introduces silicon-containing and / or germanium-containing precursors and a carrier gas into a process chamber. The silicon-containing and / or germanium-containing precursors interact with the composition of fins 410A–410F, epitaxial layers 446A, 446B, 448A, 448B, or combinations thereof to form an epitaxial source / drain. The silicon-containing precursors contain SiH. 4. Si 2H 6. Dichlorosilane (DCS), SiHCl 3. SiCl 4. Other suitable silicon-containing precursors or combinations thereof. Germanium-containing precursors include GeH. 4. Ge 2H 6. GeCl 4. GeCl 2. Other suitable germanium-containing precursors or combinations thereof. The carrier gas can be an inert gas, such as H₂. 2 and / or N 2. In some embodiments, a doped precursor is introduced into the process chamber to promote in-situ doping of epitaxial layers 444A, 444B, 446A, 446B, 448A, 448B, or combinations thereof. The doped precursor contains boron (e.g., B). 2H 6) Phosphorus (e.g., pH) 3) Arsenic (e.g., AsH) 3) Other suitable doped precursors or combinations thereof. In some embodiments, epitaxial layers 444A, 444B, 446A, 446B, 448A, 448B, or combinations thereof are doped by an ion implantation process after deposition. In some embodiments, an etchant-containing precursor is introduced into the process chamber to prevent or limit the growth of silicon and / or germanium materials on dielectric and / or non-semiconductor surfaces. In such embodiments, chemical vapor deposition process parameters are adjusted to ensure net deposition of semiconductor materials on semiconductor surfaces. The etchant-containing precursor contains Cl 2. HCl, other etchant-containing precursors that can promote the selective growth of desired semiconductor materials (e.g., silicon and / or germanium), or combinations thereof. In some embodiments, an annealing process is performed to activate dopants in epitaxial layers 444A, 444B, 446A, 446B, 448A, 448B, other source / drain regions (e.g., heavily doped source / drain regions and / or lightly doped source / drain regions), or combinations thereof. P-type epitaxial source / drain electrodes (i.e., epitaxial layers 444A, 446A, and 448A) and n-type epitaxial source / drain electrodes (i.e., epitaxial layers 444B, 446B, and 448B) are formed in separate process chambers. In some embodiments, when depositing epitaxial layers 444A, 446A, 448A, or combinations thereof, a silicon-containing precursor (e.g., DCS and / or SiH) is used. 4) Germanium-containing precursors (e.g., GeH) 4) Carrier precursor (e.g., H) 2) Etching precursors (e.g., HCl) and dopant precursors (e.g., B) 2H 6) Introduced into the process chamber. In some embodiments, during the deposition of epitaxial layer 444B, epitaxial layer 446B, epitaxial layer 448B, or a combination thereof, a silicon-containing precursor (e.g., DCS and / or SiH) is introduced. 4) Carrier precursor (e.g., H) 2 and / or N 2) Etching precursors (e.g., HCl) and dopant precursors (e.g., pH) 3 and / or AsH 3) Introducing a process chamber. Epitaxial deposition parameters are controlled to achieve optimal lateral spacing and / or lateral dimensions of the epitaxial source / drain, such as those described herein. For example, the lateral growth of the epitaxial material is controlled (particularly during the deposition of epitaxial layers 446A and 446B) to provide a p-type epitaxial source / drain 420A with width W1, a merged p-type epitaxial source / drain 420A-M with width W4, an n-type epitaxial source / drain 420B with width W2, a merged n-type epitaxial source / drain 420B-M with width W5, a spacing S11 between the p-type epitaxial source / drain 420A and the merged p-type epitaxial source / drain 420A-M, and a spacing S12 between the n-type epitaxial source / drain 420B and the merged n-type epitaxial source / drain 420B-M. Epitaxial deposition parameters may include deposition / growth time, deposition / growth temperature, precursor flow rate, precursor concentration, precursor type, other parameters, or combinations thereof. In Figures 5C and 6C, epitaxial layers 444A and 444B are grown from fins 410A-410C and fins 410D-410F, respectively. Epitaxial layers 444A and 444B can be referred to as shielding layers. In some embodiments, epitaxial layers 444A and 444B are configured to prevent and / or reduce the extrusion of dopants and / or other components of epitaxial layers 446A or 446B into the channel region of the multi-gate device. In some embodiments, epitaxial layers 444A and 444B are configured to reduce short-channel effects. Epitaxial layer 444A is disposed above fins 410A-410C and fills a portion of the source / drain groove 442A between fin spacers 425, and epitaxial layer 444B is disposed above fins 410D-410F and fills a portion of the source / drain groove 442B between fin spacers 425. Epitaxial layers 444A and 444B do not extend over the fin spacer 425. In the depicted embodiment, the tops of epitaxial layers 444A and 444B are approximately at the height of the top of the fin spacer 425 and / or slightly recessed therefrom. Epitaxial layer 444A has a thickness T1, and epitaxial layer 444B has a thickness T2. In some embodiments, thickness T1 is about 5 nm to about 15 nm. In some embodiments, thickness T2 is about 5 nm to about 15 nm. In some embodiments, thickness T1 and thickness T2 are the same. In some embodiments, thickness T1 and thickness T2 are different. Epitaxial layers 444A and 444B comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the depicted embodiment, epitaxial layer 444A comprises p-doped silicon-germanium and epitaxial layer 444B comprises n-doped silicon. The p-type dopant is boron, indium, other suitable p-type dopant, or combinations thereof, while the n-type dopant is phosphorus, arsenic, other suitable n-type dopant, or combinations thereof. In some embodiments, epitaxial layer 444A has a germanium concentration of about 25 at% to about 40 at%. In some embodiments, epitaxial layer 444A has about 1 × 10⁻⁶ ppm. 20 cm -3 Approximately 8×10 20 cm -3 The boron doping concentration. In some embodiments, the epitaxial layer 444B has a boron doping concentration of approximately 1 × 10⁻⁶. 20 cm -3 To approximately 1×10 21 cm -3 The arsenic or phosphorus dopant concentration. Epitaxial layer 444A has any suitable germanium concentration distribution and any suitable dopant distribution, such as any suitable boron dopant distribution, and epitaxial layer 444B has any suitable dopant distribution, such as any suitable arsenic or phosphorus dopant distribution. In some embodiments, epitaxial layer 444A has a substantially uniform (constant) germanium distribution and / or a substantially uniform boron dopant distribution along thickness T1, for example, substantially the same germanium and / or boron concentration from the bottom to the top of epitaxial layer 444A. In some embodiments, epitaxial layer 444A has a gradient germanium distribution and / or a gradient boron distribution along thickness T1, for example, increasing or decreasing germanium and / or boron concentration from the bottom to the top of epitaxial layer 444A (e.g., from about 25 at% to about 40 at% or vice versa and / or about 1 × 10⁻⁶). 20 cm -3 Approximately 8×10 20 cm -3 (Or vice versa). In some embodiments, the epitaxial layer 444B has a substantially uniform n-type dopant distribution. In some embodiments, the epitaxial layer 444B has a gradient arsenic dopant distribution and / or a gradient phosphorus dopant distribution. In Figures 5D and 6D, epitaxial layers 446A and 446B can be grown from epitaxial layers 444A and 444B, respectively. The lateral extension of epitaxial layers 446A and 446B is controlled to optimize the lateral dimensions and / or lateral spacing 402A of the n-type epitaxial source / drain in the n-type device region 402B and the p-type epitaxial source / drain in the p-type device region, as described herein. For example, the growth of epitaxial layers 446A and 446B is controlled to minimize unintended merging of epitaxial layers 446A and 446B with epitaxial layers 446A and / or 446B of different fin field-effect transistors, while maximizing the width and / or volume of epitaxial layers 446A and 446B to maximize the source / drain contact landing margin. In the p-type fin field-effect transistor 404A, epitaxial layers 446A are merged to form merged p-type epitaxial layers 446A-M. In the n-type fin field-effect transistor 406A, epitaxial layers 446B are merged to form merged n-type epitaxial layers 446B-M. Epitaxial layers 446A and 446B have different shapes and / or cross-sectional profiles, resulting in different shapes and / or cross-sectional profiles for the merged p-type epitaxial layers 446A-M and the merged n-type epitaxial layers 446B-M. For example, epitaxial layer 446A is rhomboid and epitaxial layer 446B is elliptical, resulting in different merging amounts of the p-type epitaxial source / drain and the n-type epitaxial source / drain. In Figure 5D, the merged p-type epitaxial layer 446A-M has a generally flat top, while in Figure 6D, the merged n-type epitaxial layer 446B-M has a generally wavy top. In the depicted embodiment, a groove is formed in the merged n-type epitaxial layers 446B-M by adjacent merged epitaxial layers 446B. In some embodiments, an etching process is performed after the deposition of epitaxial layers 446A and / or 446B to modify the shape and / or cross-sectional profile of epitaxial layers 446A and / or 446B. Epitaxial layers 446A and 446B have thicknesses T3 and T4, respectively, along the z-direction. In some embodiments, thickness T3 is about 20 nm to about 60 nm. In some embodiments, thickness T4 is about 20 nm to about 60 nm. In some embodiments, thicknesses T3 and T4 are the same. In some embodiments, thicknesses T3 and T4 are different. Epitaxial layers 446A and 446B comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the depicted embodiment, epitaxial layer 446A comprises p-doped silicon-germanium and epitaxial layer 446B comprises n-doped silicon. The p-type dopant is boron, indium, other suitable p-type dopant, or combinations thereof, while the n-type dopant is phosphorus, arsenic, other suitable n-type dopant, or combinations thereof. The germanium concentration of epitaxial layer 446A is greater than that of epitaxial layer 444A, the p-type dopant concentration of epitaxial layer 446A is greater than that of epitaxial layer 444A, and the n-type dopant concentration of epitaxial layer 446B is greater than that of epitaxial layer 444B. In some embodiments, epitaxial layer 446A has a germanium concentration of about 40 at% to about 60 at%. In some embodiments, epitaxial layer 446A has a germanium concentration of about 8 × 10⁻⁶. 20 cm -3 Approximately 3×10 21 cm -3 The boron doping concentration. In some embodiments, the epitaxial layer 446B has a boron doping concentration of approximately 8 × 10⁻⁶. 20 cm -3 Approximately 5×10 21 cm -3 The arsenic or phosphorus dopant concentration. In some embodiments, the epitaxial layer 446A has a substantially uniform (constant) germanium distribution and / or a substantially uniform boron dopant distribution along thickness T3, for example, a substantially uniform germanium and / or boron concentration from the bottom to the top of the epitaxial layer 446A. In some embodiments, the epitaxial layer 446A has a gradient germanium and / or gradient boron distribution along thickness T3, for example, an increasing or decreasing germanium and / or boron concentration from the bottom to the top of the epitaxial layer 446A (e.g., from about 40 at% to about 60 at% or vice versa and / or 8 × 10⁻⁶). 20 cm -3 Approximately 3×10 21 cm -3(Or vice versa). In some embodiments, epitaxial layer 446B has a substantially uniform n-type dopant distribution. In some embodiments, epitaxial layer 446B has a gradient arsenic dopant distribution and / or a gradient phosphorus dopant distribution. Epitaxial layer 446A and / or epitaxial layer 446B may have a multilayer structure, such as a first semiconductor layer covering a second semiconductor layer. In some embodiments, epitaxial layer 446A may comprise a first silicon-germanium layer above a second silicon-germanium layer, wherein the boron concentration in the first silicon-germanium layer is greater than the boron concentration in the second silicon-germanium layer. In some embodiments, epitaxial layer 446B may comprise a first silicon layer above a second silicon layer, wherein the phosphorus concentration in the first silicon layer is greater than the phosphorus concentration in the second silicon layer. In Figures 5E and 6E, epitaxial layers 448A and 448B can be grown from epitaxial layers 446A and 446B, respectively. Epitaxial layers 448A and 448B can be referred to as capping layers. In some embodiments, epitaxial layers 448A and 448B serve as capping layers to protect epitaxial layers 446A and 446B (i.e., heavily doped portions of the epitaxial source / drain) during subsequent processes, such as those associated with the fabrication of source / drain contacts. Epitaxial layers 448A and 448B have thicknesses T5 and T6, respectively, along the z-direction. In some embodiments, thickness T5 is about 2 nm to about 10 nm. In some embodiments, thickness T6 is about 2 nm to about 10 nm. In some embodiments, thicknesses T5 and T6 are the same. In some embodiments, thicknesses T5 and T6 are different. Epitaxial layers 448A and 448B comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the depicted embodiment, epitaxial layer 448A comprises p-doped silicon-germanium and epitaxial layer 448B comprises n-doped silicon. The p-type dopant is boron, indium, other suitable p-type dopant, or combinations thereof, while the n-type dopant is phosphorus, arsenic, other suitable n-type dopant, or combinations thereof. The p-type dopant concentration of epitaxial layer 448A is less than that of epitaxial layer 446A, and the n-type dopant concentration of epitaxial layer 448B is less than that of epitaxial layer 446B. In some embodiments, epitaxial layer 448A has a germanium concentration of about 45 at% to about 50 at%. In some embodiments, epitaxial layer 448A has about 1 × 10⁻⁶ g / cm³. 21 cm -3 Approximately 2×10 21 cm -3 The boron doping concentration. In some embodiments, the epitaxial layer 448B has a boron doping concentration of approximately 1 × 10⁻⁶. 21 cm -3 Approximately 3×10 21 cm -3 The arsenic or phosphorus dopant concentration. Epitaxial layer 448A has any suitable germanium concentration distribution and any suitable dopant distribution, and epitaxial layer 448B has any suitable dopant distribution. Turning to Figures 5F and 6F, the source / drain contacts are formed as epitaxial source / drain contacts. For example, a dielectric layer 450, similar to dielectric layer 150, is formed over p-type device region 402A and n-type device region 402B. The dielectric layer 450 fills the space between the isolation fins 440 and the epitaxial source / drain contacts (e.g., merged p-type epitaxial source / drain contacts 420A-M, p-type epitaxial source / drain contacts 420A, merged n-type epitaxial source / drain contacts 420B-M and n-type epitaxial source / drain contacts 420B), the space between the isolation fins 440 and the fin spacers 425, and the space between the fin spacers 425. Device-level contacts, such as metal-to-poly (MP) contacts (typically referring to contacts with gate structures) and metal-to-device (MD) contacts (typically referring to contacts with the electrical active regions (e.g., epitaxial source / drain) of multi-gate devices), can then be formed in dielectric layer 450. Device-level contacts electrically and physically connect integrated circuit device components to local contacts (interconnects). In Figure 5F, source / drain contacts 460A extend through dielectric layer 450 to physically contact the p-type epitaxial source / drain of different fin field-effect transistors (i.e., the combined p-type epitaxial source / drain 420A-M of p-type fin field-effect transistor 404A and the p-type epitaxial source / drain 420A of p-type fin field-effect transistor 404B). In Figure 6F, source / drain contacts 460B extend through dielectric layer 450 to physically contact the n-type epitaxial sources / drains of different fin field-effect transistors (i.e., the combined source / drain 420B-M of the n-type epitaxial n-type fin field-effect transistor 406A and the n-type epitaxial source / drain 420B of the n-type fin field-effect transistor 406B). In some embodiments, epitaxial layers 448A and 448B are consumed (e.g., during silicate formation) and / or removed (e.g., during etching dielectric layer 450 to form source / drain contact openings) during the formation of source / drain contacts, such that source / drain contacts 460A and 460B can physically contact epitaxial layers 446A and 446B, respectively. The source / drain contacts 460A and 460B can be formed by performing photolithography and etching processes (such as those described herein) to form a first contact opening extending through the dielectric layer 450 to expose a p-type epitaxial source / drain in the p-type device region 402A and a second contact opening extending through the dielectric layer 450 to expose an n-type epitaxial source / drain in the n-type device region 402B; performing a first deposition process to form a contact barrier material over the dielectric layer 450 that partially fills the first and second contact openings; and performing a second deposition process to form a contact bulk material over the contact barrier material, wherein the contact bulk material fills the remaining portions of the first and second contact openings. In such an embodiment, the contact barrier material and the contact bulk material are disposed in the first and second contact openings and above the top surface of the dielectric layer 450. The first and second deposition processes may include chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-assisted atomic layer deposition (PEALD), electroplating, electroless plating, other suitable deposition methods, or combinations thereof. In some embodiments, prior to forming the contact barrier material, a silica layer is formed above the epitaxial source / drain, such as silica layer 460A-1 and silica layer 460B-1 (e.g., by depositing a metal layer above the epitaxial source / drain and heating the multi-gate device to react the composition of the epitaxial source / drain with the metal composition of the metal layer). In some embodiments, the silicate layer comprises a metallic component (e.g., nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof) and an epitaxial source / drain component (e.g., silicon and / or germanium). In the depicted embodiment, silicate layers 460A-1 and 460B-1 comprise titanium and silicon. Chemical mechanical polishing (CMP) and / or other planarization processes are performed to remove, for example, excess contact bulk material and contact barrier material above the top surface of dielectric layer 450, producing source / drain contacts 460A and 460B (in other words, the contact barrier layer and contact bulk layer fill the contact openings). The chemical mechanical polishing process planarizes the top surfaces of source / drain contacts 460A, source / drain contacts 460B, and dielectric layer 450. The contact barrier layer includes a material that promotes adhesion between the surrounding dielectric material (e.g., dielectric layer 450) and the contact bulk layer. The material of the contact barrier layer can further prevent metallic components from diffusing from the source / drain contacts 460A, 460B into the surrounding dielectric material. In some embodiments, the contact barrier layer includes titanium, titanium alloys, tantalum, tantalum alloys, cobalt, cobalt alloys, ruthenium, ruthenium alloys, molybdenum, molybdenum alloys, palladium, palladium alloys, other suitable components configured to promote and / or enhance adhesion between the metallic material and the dielectric material and / or prevent metallic components from diffusing from the metallic material into the dielectric material, or combinations thereof. For example, the contact barrier layer includes tantalum, tantalum nitride, aluminum tantalum nitride, silicon tantalum nitride, tantalum carbide, titanium, titanium nitride, silicon titanium nitride, aluminum titanium nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or combinations thereof. In some embodiments, the contact barrier layer comprises multiple layers. For example, the contact barrier layer may comprise a first sublayer and a second sublayer, the first sublayer comprising titanium or tantalum, and the second sublayer comprising titanium nitride or tantalum nitride. The contact bulk layer comprises tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low resistivity metal composition, an alloy of the foregoing, or a combination thereof. In the depicted embodiment, source / drain contacts 460A and / or source / drain contacts 460B comprise tungsten and / or silicon. In some embodiments, source / drain contacts 460A and / or source / drain contacts 460B do not contain a contact barrier layer (i.e., no barrier) or source / drain contacts 460A and / or source / drain contacts 460B are partially barrier-free, wherein the contact barrier layer is disposed between a portion of the contact bulk layer and the dielectric layer. In some embodiments, the contact bulk layer comprises multiple layers. Before forming source / drain contacts 460A and 460B, the gate replacement process can replace a dummy gate stack with a gate stack. In embodiments where the multi-gate device is a fully wound gate transistor and fins 410A–410F are semiconductor layer stacks configured to form a fully wound gate transistor, a channel release process is performed after removing the dummy gate stack and before forming the gate stack to form a floating channel layer in the channel region of the multi-gate device. The gate stack includes a gate dielectric (e.g., a gate dielectric layer) and gate electrodes (e.g., a work function layer and a bulk (or fill) conductive layer). The gate stack may include many other layers, such as a capping layer, an interface layer, a diffusion layer, a barrier layer, a hard masking layer, or a combination thereof. In some embodiments, the gate dielectric layer is disposed above the interface layer (containing a dielectric material, such as silicon oxide), and the gate electrodes are disposed above the gate dielectric layer. The gate dielectric layer comprises a dielectric material, such as silicon oxide, a high-dielectric-constant dielectric material, other suitable dielectric materials, or a combination thereof. Examples of high-dielectric-constant dielectric materials include hafnium dioxide (HfO). 2) HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO) 2-Al 2O 3) Alloys, other suitable high-dielectric-constant dielectric materials, or combinations thereof. High-dielectric-constant dielectric materials generally refer to dielectric materials with a high dielectric constant (k value) relative to the dielectric constant of silicon dioxide (k≈3.9). For example, a high-dielectric-constant dielectric material has a dielectric constant greater than about 3.9. In some embodiments, the gate dielectric layer is a high-dielectric-constant dielectric layer. In such embodiments, the gate stack may be referred to as a high-dielectric-constant / metal gate. The gate electrode comprises a conductive material, such as polycrystalline silicon, Al, Cu, Ti, Ta, W, Mo, Ru, Co, Ag, Mn, Zr, TaN, NiSi, CoSi, TiN, TaN, WN, TiAl, TaAl, TaAlC, TiAlN, TaCN, TaC, TaSiN, MoSi 2. TaSi 2. NiSi 2. Other conductive materials or combinations thereof. This document discloses epitaxial source / drain structures and methods for manufacturing epitaxial source / drain structures to enhance the performance of multi-gate devices, such as fin field-effect transistors (FETs) or fully wound gate (GAA) FETs. In some embodiments, the epitaxial source / drain disclosed herein has lateral dimensions and lateral spacing that maximize the landing margin of the source / drain contacts while minimizing and / or preventing unintended merging between the epitaxial source / drain of adjacent multi-gate devices. In some embodiments, the epitaxial source / drain disclosed herein has lateral dimensions and lateral spacing that minimize epitaxial material residue (i.e., device residual defects). The lateral dimensions and / or lateral spacing disclosed herein take into account variations in the epitaxial source / drain profiles of different types of multi-gate devices and the additional isolation and / or additional merging prevention provided by isolation fins disposed between the epitaxial source / drain. Many different embodiments are provided in this invention. An exemplary semiconductor structure includes a first multi-gate device and a second multi-gate device. The first multi-gate device has a first channel layer extending along a first direction between a first epitaxial source / drain. The first epitaxial source / drain has a first width along a second direction different from the first direction. The second multi-gate device has a second channel layer extending along the first direction between the second epitaxial source / drain. The second epitaxial source / drain has a second width along the second direction. The semiconductor structure further includes an isolation structure having dielectric fins above a substrate isolation member. The dielectric fins are located between the first and second epitaxial source / drains. The dielectric fins have a third width along the second direction. The distance between the first and second epitaxial source / drains along the second direction is greater than the third width, less than the second width, and less than the first width. In some embodiments, the second width is different from the first width. In some embodiments, the first epitaxial source / drain has a first cross-sectional profile, and the second epitaxial source / drain has a second cross-sectional profile. In some embodiments, the first multi-gate device is a first single-fin p-type fin field-effect transistor, the second multi-gate device is a second single-fin p-type fin field-effect transistor, and the distance between them is about 15 nm to about 30 nm. In some embodiments, the first multi-gate device is a first single-fin n-type fin field-effect transistor, the second multi-gate device is a second single-fin n-type fin field-effect transistor, and the distance between them is about 10 nm to about 25 nm. In some embodiments, the first multi-gate device is a single-fin p-type fin field-effect transistor, the second multi-gate device is a double-fin p-type fin field-effect transistor, and the distance between them is about 15 nm to about 30 nm. In some embodiments, the first multi-gate device is a single-fin n-type fin field-effect transistor, the second multi-gate device is a double-fin n-type fin field-effect transistor, and the distance between them is about 20 nm to about 35 nm. In some embodiments, the first multi-gate device is a dual-fin p-type fin field-effect transistor, and the second multi-gate device is a dual-fin n-type fin field-effect transistor, with a distance of about 15 nm to about 25 nm. In some embodiments, the first multi-gate device is a single-fin p-type fin field-effect transistor, and the second multi-gate device is a single-fin n-type fin field-effect transistor, with a distance of about 5 nm to about 20 nm. Another exemplary semiconductor structure includes a first multi-gate device, a second multi-gate device, a third multi-gate device, and a fourth multi-gate device. The first multi-gate device has a first channel layer extending along a first direction between a first epitaxial source / drain. The second multi-gate device has a second channel layer extending along the first direction between a second epitaxial source / drain. The third multi-gate device has a third channel layer extending along the first direction between a third epitaxial source / drain. The fourth multi-gate device has a fourth channel layer extending along the first direction between a fourth epitaxial source / drain. The semiconductor structure further includes a first isolation fin and a second isolation fin. The first isolation fin is located between the first epitaxial source / drain and the second epitaxial source / drain. The second isolation fin is located between the third epitaxial source / drain and the fourth epitaxial source / drain. The first isolation fin has a first width along a second direction different from the first direction, and the second isolation fin has a second width along the second direction. The first multi-gate device is adjacent to the second multi-gate device, and the third multi-gate device is adjacent to the fourth multi-gate device. The first distance, along the second direction, lies between the first epitaxial source / drain and the second epitaxial source / drain. The second distance, along the second direction, lies between the third epitaxial source / drain and the fourth epitaxial source / drain. The first distance differs from the second distance; the first distance is greater than the first width, and the second distance is greater than the second width. In some embodiments, the first and second multi-gate devices are single-fin n-type fin field-effect transistors, and the third and fourth multi-gate devices are single-fin p-type fin field-effect transistors, and the first distance is smaller than the second distance. In some embodiments, the first distance is about 5% to about 30% smaller than the second distance. In some embodiments, the first epitaxial source / drain and the second epitaxial source / drain have a first cross-sectional profile, and the third and fourth epitaxial source / drain have a second cross-sectional profile. In some embodiments, the first multi-gate device is a single-fin n-type fin field-effect transistor, the second multi-gate device is a double-fin n-type fin field-effect transistor, the third multi-gate device is a single-fin p-type fin field-effect transistor, the fourth multi-gate device is a double-fin p-type fin field-effect transistor, and the first distance is greater than the second distance. In some embodiments, the difference between the first distance and the second distance is about 3 nm to about 10 nm. In some embodiments, the first, third, and fourth multi-gate devices are single-fin FETs and the second multi-gate device is a double-fin FET, wherein the single-fin FET and the double-fin FET are of the same type, and the first distance is greater than the second distance. In some embodiments, the same type is p-type, and the difference between the first distance and the second distance is about 2 nm to about 10 nm. In some embodiments, the same type is n-type, and the difference between the first distance and the second distance is about 5 nm to about 10 nm. An exemplary method includes forming a first fin, a second fin, a third fin, and a fourth fin extending from a substrate. Each of the first, second, third, and fourth fins extends longitudinally along a first direction. A first space lies between the first and second fins along a second direction different from the first direction. A second space lies between the third and fourth fins along a second direction. The method further includes forming a first isolation fin and a second isolation fin above the substrate. The first isolation fin is located in the first space between the first and second fins, and the second isolation fin is located in the second space between the third and fourth fins. The first isolation fin has a first width along the second direction, and the second isolation fin has a second width along the second direction. The method further includes forming a first epitaxial source / drain above the first fin, a second epitaxial source / drain above the second fin, a third epitaxial source / drain above the third fin, and a fourth epitaxial source / drain above the fourth fin. The formation of the first epitaxial source / drain electrode, the second epitaxial source / drain electrode, the third epitaxial source / drain electrode, and the fourth epitaxial source / drain electrode is adjusted to provide a first distance along a second direction between the first epitaxial source / drain electrode and the second epitaxial source / drain electrode, and a second distance along the second direction between the third epitaxial source / drain electrode and the fourth epitaxial source / drain electrode. The first distance is different from the second distance. The first distance is greater than a first width. The second distance is greater than a second width. The first epitaxial source / drain electrode and the second epitaxial source / drain electrode may have a first cross-sectional profile, and the third epitaxial source / drain electrode and the fourth epitaxial source / drain electrode may have a second cross-sectional profile. The foregoing overview of components in several embodiments enables those skilled in the art to better understand various aspects of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and that they can make various changes, substitutions, and adjustments without departing from the spirit and scope of the embodiments of the present invention. 10, 100, 200, 300: Multi-gate device; 15, 110A, 110B, 110C, 110D, 110E, 110F; 210A, 210B: Fins; 210C, 210D, 210E, 210F; 310A, 310B, 310C, 310D; 410A: Fins; 410B, 410C, 410D, 410E, 410F: Fins; 20, 112, 212, 312, 412: Substrate 25 Gate stack 25A; Gate dielectric 25B; Gate electrode 30; Epitaxial source / drain 40, 130, 430; Substrate isolation components 102A, 102B, 202A, 202B, 302; Device region 104A, 104B, 104C, 104D, 204A, 204B, 304, 404A, 404B; p-type fin field-effect transistor 106A, 106B, 206A, 206B, 306, 406A, 406B. n-type finned field-effect transistors 120A, 220A, 320A, 420A: p-type epitaxial source / drain; 120B, 220B, 320B, 420B: n-type epitaxial source / drain; 125, 425: fin spacers; 140, 440: isolation fins; 150, 450: dielectric layer; 220A-M, 320A-M, 420A-M, 446A-M: merged p-type epitaxial source / drain; 220B-M, 320B-M, 420B- M,446B-M: Merged n-type epitaxial source / drain; 402A: p-type device region; 402B: n-type device region; 442A,442B: Source / drain grooves; 444A,444B,446A,446B,448A,448B: Epitaxial layers; 460A,460B: Source / drain contacts; 460A-1,460B-1: Silicon layer; C: Channel region; d1,d2: Length; D1,D2: Depth; H1,H2,H3,H4: Height; L G Gate length S / D; Source / Drain regions S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14; Spacing T1, T2, T3, T4, T5, T6; Thickness W1, W2, W3, W4, W5, W fin :width The aspects of embodiments of the present invention can be better understood through the following detailed description and accompanying drawings. It should be emphasized that, according to industry standard practice, many components are not drawn to scale. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a partial perspective view of a portion or the entirety of a multi-gate device according to various aspects of an embodiment of the present invention. Figure 2 is a partial cross-sectional view of a portion or the entirety of a multi-gate device according to various aspects of an embodiment of the present invention. Figure 3 is a partial cross-sectional view of a portion or the entirety of a multi-gate device according to various aspects of an embodiment of the present invention. Figure 4 is a partial cross-sectional view of a portion or the entirety of a multi-gate device according to various aspects of an embodiment of the present invention. Figures 5A to 5F are partial cross-sectional views of a portion or the entirety of a multi-gate device according to various aspects of an embodiment of the present invention at various manufacturing stages. Figures 6A to 6F are partial cross-sectional views of a portion or the entirety of a multi-gate device according to various aspects of an embodiment of the present invention at various manufacturing stages. 100: Multi-gate device 102A, 102B: Device Area 104A, 104B, 104C, 104D: p-type fin field-effect transistors 106A, 106B: n-type fin field-effect transistors 110A, 110B, 110C, 110D, 110E, 110F: Fins 112: Base 120A: p-type epitaxial source / drain 120B: n-type epitaxial source / drain 125: Fin spacers 130: Base isolation component 140: Isolation fins 150: Dielectric layer S1, S2, S3, S4, S5, S6: Spacing W1, W2, W3: Width

Claims

1. A semiconductor structure, comprising: A first multi-gate device having a first channel layer extending along a first direction between a plurality of first epitaxial source / drain electrodes, wherein the first epitaxial source / drain electrodes have a first width along a second direction different from the first direction; a second multi-gate device having a second channel layer extending along the first direction between a plurality of second epitaxial source / drain electrodes, wherein the second epitaxial source / drain electrodes have a second width along the second direction; an isolation structure having a dielectric fin above a substrate isolation member, wherein the dielectric fin is located between the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes, and the dielectric fin has a third width along the second direction; and wherein a distance between the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes along the second direction is greater than the third width, less than the second width, and less than the first width. The first multi-gate device is a first single-fin p-type fin field-effect transistor, and the second multi-gate device is a second single-fin p-type fin field-effect transistor, with a distance of approximately 15 nm to approximately 30 nm; or the first multi-gate device is a first single-fin n-type fin field-effect transistor, and the second multi-gate device is a second single-fin n-type fin field-effect transistor, with a distance of approximately 10 nm to approximately 25 nm; or the first multi-gate device is a single-fin p-type fin field-effect transistor, and the second multi-gate device is a dual-fin p-type fin field-effect transistor, with a distance of approximately 15 nm to approximately 30 nm; or the first multi-gate device is a single-fin n-type fin field-effect transistor, and the second multi-gate device is a dual-fin n-type fin field-effect transistor, with a distance of approximately 20 nm to approximately 35 nm. nm; or the first multi-gate device is a dual-fin p-type fin field-effect transistor, the second multi-gate device is a dual-fin n-type fin field-effect transistor, and the distance is about 15 nm to about 25 nm; or the first multi-gate device is a single-fin p-type fin field-effect transistor, the second multi-gate device is a single-fin n-type fin field-effect transistor, and the distance is about 5 nm to about 20 nm.

2. The semiconductor structure of claim 1, wherein the second width is different from the first width.

3. A semiconductor structure, comprising: A first multi-gate device having a first channel layer extending along a first direction between a plurality of first epitaxial source / drain electrodes; A second multi-gate device having a second channel layer extending along the first direction between a plurality of second epitaxial source / drain electrodes; a third multi-gate device having a third channel layer extending along the first direction between a plurality of third epitaxial source / drain electrodes; a fourth multi-gate device having a fourth channel layer extending along the first direction between a plurality of fourth epitaxial source / drain electrodes; a first isolation fin and a second isolation fin, wherein the first isolation fin is located between the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes, and the second isolation fin is located between the third epitaxial source / drain electrodes and the fourth epitaxial source / drain electrodes; the first isolation fin has a first width along the second direction different from the first direction, and the second isolation fin has a second width along the second direction; and wherein: the first multi-gate device is adjacent to the second multi-gate device, and the third multi-gate device is adjacent to the fourth multi-gate device. A first distance along the second direction lies between the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes; a second distance along the second direction lies between the third epitaxial source / drain electrodes and the fourth epitaxial source / drain electrodes; and the first distance is different from the second distance, the first distance being greater than the first width and less than the width of the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes along the second direction, wherein the second distance is greater than the second width and less than the width of the third epitaxial source / drain electrodes and the fourth epitaxial source / drain electrodes along the second direction.

4. The semiconductor structure of claim 3, wherein the first multi-gate device and the second multi-gate device are single-fin n-type fin field-effect transistors, the third multi-gate device and the fourth multi-gate device are single-fin p-type fin field-effect transistors, and the first distance is smaller than the second distance, wherein the first distance is about 5% to about 30% smaller than the second distance.

5. The semiconductor structure of claim 3, wherein the first multi-gate device is a single-fin n-type fin field-effect transistor, the second multi-gate device is a double-fin n-type fin field-effect transistor, the third multi-gate device is a single-fin p-type fin field-effect transistor, the fourth multi-gate device is a double-fin p-type fin field-effect transistor, and the first distance is greater than the second distance, wherein the difference between the first distance and the second distance is about 3 nm to about 10 nm.

6. The semiconductor structure as described in claim 3, wherein: The first multi-gate device, the third multi-gate device, and the fourth multi-gate device are single-fin MOSFETs, and the second multi-gate device is a double-fin MOSFET; the single-fin MOSFETs and the double-fin MOSFETs are of the same type; and the first distance is greater than the second distance.

7. The semiconductor structure of claim 6, wherein the same type is p-type and the difference between the first distance and the second distance is about 2 nm to about 10 nm; or the same type is n-type and the difference between the first distance and the second distance is about 5 nm to about 10 nm.

8. A method for manufacturing a semiconductor structure, comprising: A first fin, a second fin, a third fin, and a fourth fin are formed extending from a base, wherein each of the first, second, third, and fourth fins extends longitudinally along a first direction, a first space lies between the first fin and the second fin along a second direction different from the first direction, and a second space lies between the third fin and the fourth fin along the second direction; a first isolation fin and a second isolation fin are formed above the base, wherein the first isolation fin is located in the first space between the first fin and the second fin, and the second isolation fin is located in the second space between the third fin and the fourth fin, the first isolation fin having a first width along the second direction, and the second isolation fin having a second width along the second direction; A plurality of first epitaxial source / drain electrodes are formed above the first fin, a plurality of second epitaxial source / drain electrodes are formed above the second fin, a plurality of third epitaxial source / drain electrodes are formed above the third fin, and a plurality of fourth epitaxial source / drain electrodes are formed above the fourth fin; wherein the formation of the first, second, third, and fourth epitaxial source / drain electrodes is adjusted to provide: a first distance along the second direction between the first and second epitaxial source / drain electrodes. A second distance along the second direction between the third epitaxial source / drain electrodes and the fourth epitaxial source / drain electrodes, wherein the first distance is different from the second distance, the first distance is greater than the first width and less than the width of the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes along the second direction, wherein the second distance is greater than the second width and less than the width of the third epitaxial source / drain electrodes and the fourth epitaxial source / drain electrodes along the second direction.

9. A method for manufacturing a semiconductor structure as claimed in claim 8, wherein the first epitaxial source / drain electrodes and the second epitaxial source / drain electrodes have a first cross-sectional profile, and the third epitaxial source / drain electrodes and the fourth epitaxial source / drain electrodes have a second cross-sectional profile.

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