Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a semiconductor substrate, a first gate structure, and a first gap structure. The semiconductor substrate includes a first active structure, and the first gate structure is disposed on the first active structure. The first gate structure includes a first gate oxide layer and a first high-dielectric-constant dielectric layer. The first gate oxide layer has a U-shaped structure in a cross-sectional view of the first gate structure, and the first high-dielectric-constant dielectric layer is disposed on the first gate oxide layer. The first gap structure is disposed on a sidewall of the first gate structure, and a first portion of the first gate oxide layer is located horizontally between the first gap structure and the first high-dielectric-constant dielectric layer.

Description

Semiconductor structure and method for manufacturing the same The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure including a gate oxide layer and a manufacturing method thereof. In integrated circuits, transistor components often have different structures to meet different operating voltages and / or other related requirements. For example, transistors corresponding to lower operating voltages can be used in core components, input / output (I / O) components, etc., while transistors with high-voltage handling capabilities can be used in high-voltage operating environments, such as CPU power supplies, power management systems, DC / AC converters, and power amplifiers. However, in order to form transistors corresponding to different operating voltages on the same wafer or chip, the overall process is often complicated and the processes of different transistors affect each other. Therefore, how to improve related issues through structural and / or process design is a direction of continuous research for people in related fields. The present invention provides a semiconductor structure and a manufacturing method thereof, which utilizes a gate oxide layer with a U-shaped structure to adjust the thickness of the oxide layer in the gate structure, thereby reducing the negative impact of related processes. One embodiment of the present invention provides a semiconductor structure comprising a semiconductor substrate, a first gate structure, and a first gap substructure. The semiconductor substrate comprises a first active structure, and the first gate structure is disposed on the first active structure. The first gate structure comprises a first gate oxide layer and a first high-k dielectric layer. The first gate oxide layer has a U-shaped structure in a cross-sectional view of the first gate structure, and the first high-k dielectric layer is disposed on the first gate oxide layer. The first gap substructure is disposed on a sidewall of the first gate structure, and a first portion of the first gate oxide layer is horizontally located between the first gap substructure and the first high-k dielectric layer. One embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps. A semiconductor substrate is provided, and the semiconductor substrate includes a first active structure. A first gate structure is formed on the first active structure, and the first gate structure includes a first gate oxide layer and a first high-k dielectric layer. The first gate oxide layer has a U-shaped structure in a cross-sectional view of the first gate structure, and the first high-k dielectric layer is disposed on the first gate oxide layer. A first gap substructure is formed, and the first gap substructure is disposed on a sidewall of the first gate structure, and a first portion of the first gate oxide layer is located between the first gap substructure and the first high-k dielectric layer in a horizontal direction. The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the present invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present invention. Before further describing each embodiment, specific terms used throughout the document are explained below. The terms “on,” “over,” and “over” should be interpreted in the broadest sense, so that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something). The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name. The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching. The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc. Please refer to Figure 1. Figure 1 is a schematic diagram of a semiconductor structure 100 according to an embodiment of the present invention. As shown in Figure 1, the semiconductor structure 100 includes a semiconductor substrate 10, a first gate structure GS1, and a first spacer structure 18A. The semiconductor substrate 10 includes a first active structure 10A, and the first gate structure GS1 is disposed on the first active structure 10A. The first gate structure GS1 includes a first gate oxide layer (for example, the gate oxide layer 30A shown in Figure 1) and a first high dielectric constant (high-k) dielectric layer 42A. The gate oxide layer 30A has a U-shaped structure in a cross-sectional view of the first gate structure GS1 (for example, Figure 1). The first high dielectric constant dielectric layer 42A is disposed on the gate oxide layer 30A. The first spacer substructure 18A is disposed on the sidewall of the first gate structure GS1 , and a first portion P1 of the gate oxide layer 30A is located between the first spacer substructure 18A and the first high-k dielectric layer 42A in a horizontal direction (eg, direction D2 shown in FIG. 1 ). In some embodiments, the semiconductor substrate 10 may have a top surface TS1 and a bottom surface BS1 opposite each other in a vertical direction (e.g., direction D1 shown in FIG. 1 ), and the first gate structure GS1 and the first spacer substructure 18A may be disposed on one side of the top surface TS1. In some embodiments, direction D1 may be considered the thickness direction of the semiconductor substrate 10, and horizontal directions substantially orthogonal to direction D1 (e.g., direction D2, direction D3, and other directions orthogonal to direction D1 shown in FIG. 1 ) may be substantially parallel to the top surface TS1 and / or the bottom surface BS1 of the semiconductor substrate 10, but are not limited thereto. As described herein, the distance between a relatively higher position or / and component in the vertical direction (e.g., direction D1) and the bottom surface BS1 of the semiconductor substrate 10 in the direction D1 may be greater than the distance between a relatively lower position or / and component in the direction D1 and the bottom surface BS1 of the semiconductor substrate 10 in the direction D1. The lower portion or bottom of each component may be closer to the bottom surface BS1 of the semiconductor substrate 10 in the direction D1 than the upper portion or top of the component. Another component above a certain component may be considered to be relatively far away from the bottom surface BS1 of the semiconductor substrate 10 in the direction D1, and another component below a certain component may be considered to be relatively close to the bottom surface BS1 of the semiconductor substrate 10 in the direction D1. To further illustrate, in some embodiments, a first portion P1 of the gate oxide layer 30A can be considered as a portion extending in a vertical direction (e.g., direction D1) within the U-shaped structure, while a second portion P2 of the gate oxide layer 30A can be considered as a portion extending in a horizontal direction (e.g., direction D2) within the U-shaped structure, and the second portion P2 can be directly connected to the first portion P1. Furthermore, in some embodiments, the first gate structure GS1 can further include a second gate oxide layer (e.g., the gate oxide layer 14A shown in FIG. 1 ). The gate oxide layer 30A can be disposed on the gate oxide layer 14A, and the gate oxide layer 14A can be disposed in the direction D1 between the gate oxide layer 30A and the first active structure 10A. In some embodiments, the gate oxide layer 14A has only a portion extending horizontally and no portion extending vertically in a cross-sectional view of the first gate structure GS1. The gate oxide layer 14A may be sandwiched between the gate oxide layer 30A and the first active structure 10A in the direction D1 and directly connected to the gate oxide layer 30A and the first active structure 10A, respectively, but the present invention is not limited thereto. Furthermore, the second portion P2 of the gate oxide layer 30A may be sandwiched between the first high-k dielectric layer 42A and the gate oxide layer 14A in the direction D1 and directly connected to both the first high-k dielectric layer 42A and the second gate oxide layer 14A. In some embodiments, the first gate structure GS1 can be regarded as being disposed in a first trench TR1 surrounded by the first gap substructure 18A in the horizontal direction, and the projection pattern and / or projection area of ​​the gate oxide layer 30A in the direction D1 can be substantially the same as the projection pattern and / or projection area of ​​the gate oxide layer 14A in the direction D1, and the contact area between the gate oxide layer 30A and the gate oxide layer 14A can be substantially equal to the upper surface area of ​​the gate oxide layer 14A and / or the bottom surface area of ​​the gate oxide layer 30A, but is not limited to this. In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. The first active structure 10A may be a portion of the semiconductor substrate 10 and have the same or similar material composition as the semiconductor substrate 10. For example, the first active structure 10A may be a fin-shaped semiconductor structure formed by partially patterning the semiconductor substrate 10, but is not limited to this. The gate oxide layer 14A may include an oxide layer formed by oxidizing the semiconductor substrate 10, so the gate oxide layer 14A may include an oxide of the material of the semiconductor substrate 10, such as silicon oxide, but is not limited to this. In addition, the gate oxide layer 30A may include an oxide layer formed by a deposition process, and the material of the gate oxide layer 30A may include silicon oxide or other suitable oxide dielectric materials, but is not limited to this. The first high dielectric constant dielectric layer 42A may include hafnium oxide (HfO X ), hafnium silicon oxide (HfSiO 4) Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2O 3) Tantalum oxide 2O 5) Zirconium oxide (ZrO 2) or other suitable high-k dielectric materials, such as, but not limited to, high-k materials having a higher dielectric constant than silicon oxide. Therefore, the dielectric constant of the material of the first high-k dielectric layer 42A can be higher than 3.9, higher than 4.5 (the dielectric constant of silicon oxide is generally between 3.9 and 4.5), or can have a higher dielectric constant depending on design requirements. In other words, the material composition of the first high-k dielectric layer 42A is different from the material composition of the gate oxide layer 30A and the material composition of the gate oxide layer 14A, and the dielectric constant of the material of the first high-k dielectric layer 42A can be higher than the dielectric constant of the material of the gate oxide layer 30A and the dielectric constant of the material of the gate oxide layer 14A, respectively. In addition, in some embodiments, the gate oxide layer 30A can be used to increase the overall thickness of the gate oxide layer in the first gate structure GS1 to meet the required requirements (for example, but not limited to the requirements for adjusting the operating voltage). Therefore, the thickness of the gate oxide layer 30A (for example, the thickness TK1 of the second portion P2 in the direction D1) can be greater than the thickness of the first high dielectric constant dielectric layer 42A (for example, the thickness TK2 of the portion of the first high dielectric constant dielectric layer 42A extending along the horizontal direction in the direction D1), but is not limited to this. In some embodiments, the first gate structure GS1 may further include a first conductive layer 44A, a first gate electrode 46A, and a first capping layer 48A. The first gate electrode 46A may be disposed on the first high-k dielectric layer 42A, the first conductive layer 44A may be disposed between the first high-k dielectric layer 42A and the first gate electrode 46A, and the first capping layer 48A may be disposed in the direction D1 on the gate oxide layer 30A, the first high-k dielectric layer 42A, the first conductive layer 44A, and the first gate electrode 46A. The first conductive layer 44A may include a structure formed by stacking multiple layers of conductive materials, such as, but not limited to, a bottom barrier layer, a work function layer, and a top barrier layer. The materials of the barrier layer and the work function layer may include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium tri-aluminide (TiAl 3) aluminum titanium nitride (TiAlN) or other suitable conductive materials. The first gate electrode 46A may comprise a low-resistance material such as tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable low-resistance materials. The first cap layer 48A may comprise an insulating material such as silicon oxide, silicon nitride, or other suitable insulating materials. In some embodiments, the gate oxide layer 30A, the first high-k dielectric layer 42A, and the first conductive layer 44A may each have a U-shaped structure in the cross-sectional view of the first gate structure GS1, and these U-shaped structures may be stacked in the direction D1 and surround at least a portion of the first gate electrode 46A (for example, the lower portion of the first gate electrode 46A), but are not limited to this. In addition, in some embodiments, an upper surface TS3 of the first portion P1 of the gate oxide layer 30A, an upper surface of the first high-k dielectric layer 42A, and an upper surface of the first conductive layer 44A may be substantially coplanar with each other, and the upper surface TS3 of the first portion P1, the upper surface of the first high-k dielectric layer 42A, and the upper surface of the first conductive layer 44A may be lower than an upper surface TS2 of the first gate electrode 46A and higher than a bottom surface BS2 of the first gate electrode 46A in the direction D1, respectively. The upper surface TS3 of the first portion P1, the upper surface of the first high-k dielectric layer 42A, and the upper surface of the first conductive layer 44A may be lower than an upper surface TS4 of the first gap substructure 18A in the direction D1, respectively, but the present invention is not limited thereto. Furthermore, the top surface TS2 of the first gate electrode 46A may be lower than the top surface TS4 of the first spacer substructure 18A in the direction D1, and the top surface of the first cap layer 48A may be substantially coplanar with the top surface TS4 of the first spacer substructure 18A, but this is not a limitation. It is worth noting that the top surface of a specific object described herein may include the topmost surface of the object in the direction D1, and the bottom surface of a specific object may include the bottommost surface of the object in the direction D1, but this is not a limitation. In some embodiments, the first spacer substructure 18A may include a single layer or multiple layers of insulating material, such as silicon nitride, silicon oxide, or other suitable insulating materials. The first portion P1 of the gate oxide layer 30A may be sandwiched between the first spacer substructure 18A and the first high-k dielectric layer 42A in a horizontal direction (e.g., direction D2), and the first portion P1 of the gate oxide layer 30A may be directly connected to the first spacer substructure 18A and the first high-k dielectric layer 42A in direction D2. In some embodiments, the first spacer substructure 18A may horizontally surround the first gate structure GS1 and may be directly connected to the first cap layer 48A, the gate oxide layer 30A, and the gate oxide layer 14A, respectively, but this is not limited to the foregoing. In some embodiments, the semiconductor substrate 10 may include a first region R1 and a second region R2. The first active structure 10A may be located in the first region R1, and the first gate structure GS1 and the first spacer substructure 18A may be disposed on the first region R1. Furthermore, in some embodiments, the semiconductor structure 100 may further include a second gate structure GS2 and a second spacer substructure 18B, and the second gate structure GS2 and the second spacer substructure 18B are disposed on the second region R2 of the semiconductor substrate 10. In some embodiments, the semiconductor substrate 10 may further include a second active structure 10B located in the second region R2, and the second gate structure GS2 and the second spacer substructure 18B may be disposed on the second active structure 10B. In some embodiments, similar to the first active structure 10A described above, the second active structure 10B may also be a fin-shaped semiconductor structure formed by partially patterning the semiconductor substrate 10, such as, but not limited to, a fin-shaped semiconductor structure extending along a direction D2. Furthermore, the second gate structure GS2 may include a third gate oxide layer (e.g., the gate oxide layer 14B shown in FIG. 1 ) and a second high-k dielectric layer 42B, and the second high-k dielectric layer 42B may be disposed on the gate oxide layer 14B. In some embodiments, the gate oxide layer 14B may be sandwiched between the second high-k dielectric layer 42B and the second active structure 10B in the direction D1, and the gate oxide layer 14B may be directly connected to the second high-k dielectric layer 42B and the second active structure 10B, respectively. In some embodiments, the gate oxide layer 14B may include an oxide layer formed by oxidizing the semiconductor substrate 10. Therefore, the gate oxide layer 14B may include an oxide of the material of the semiconductor substrate 10, such as silicon oxide, but is not limited thereto. The second high-k dielectric layer 42B may include a high-k dielectric material similar to that of the first high-k dielectric layer 42A. The material composition of the second high-k dielectric layer 42B may be the same as or different from that of the first high-k dielectric layer 42A. In some embodiments, the second gate structure GS2 may further include a second conductive layer 44B, a second gate electrode 46B, and a second cap layer 48B. The second gate electrode 46B may be disposed on the second high-k dielectric layer 42B, the second conductive layer 44B may be disposed between the second high-k dielectric layer 42B and the second gate electrode 46B, and the second cap layer 48B may be disposed on the second high-k dielectric layer 42B, the second conductive layer 44B, and the second gate electrode 46B in direction D1. The second conductive layer 44B may include a structure formed by stacking multiple layers of conductive materials, such as, but not limited to, a structure formed by stacking a bottom barrier layer, a work function layer, and a top barrier layer. The second conductive layer 44B may include a conductive material similar to that of the first conductive layer 44A described above, and the material composition of the second conductive layer 44B may be the same as or different from that of the first conductive layer 44A depending on design requirements. The second gate electrode 46B may include a low-resistance conductive material similar to the first gate electrode 46A described above, and the material composition of the second gate electrode 46B may be the same as or different from the material composition of the first gate electrode 46A, depending on design requirements. The second capping layer 48B may include an insulating material such as silicon oxide, silicon nitride, or other suitable insulating materials, and the material composition of the second capping layer 48B may be the same as or different from the material composition of the first capping layer 48A, depending on design requirements. In some embodiments, the second high-k dielectric layer 42B and the second conductive layer 44B may each have a U-shaped structure in a cross-sectional view of the second gate structure GS2, and these U-shaped structures may be stacked in the direction D1 and surround at least a portion of the second gate electrode 46B (e.g., the lower portion of the second gate electrode 46B), but are not limited thereto. In addition, in some embodiments, an upper surface of the second high-k dielectric layer 42B and an upper surface of the second conductive layer 44B may be substantially coplanar with each other, and the upper surface of the second high-k dielectric layer 42B and the upper surface of the second conductive layer 44B may be lower than an upper surface of the second gate electrode 46B and higher than a bottom surface of the second gate electrode 46B in the direction D1, respectively. The upper surface of the second high-k dielectric layer 42B and the upper surface of the second conductive layer 44B may be lower than an upper surface of the second gap substructure 18B in the direction D1, respectively, but the present invention is not limited thereto. In some embodiments, the second spacer substructure 18B may be disposed on the sidewalls of the second gate structure GS2, and the second spacer substructure 18B may be directly connected to the gate oxide layer 14B, the second high-k dielectric layer 42B, and the second capping layer 48B, respectively. The second gate structure GS2 may be considered to be disposed in a second trench TR2 horizontally surrounded by the second spacer substructure 18B. The projection pattern and / or projection area of ​​the second high-k dielectric layer 42B in the direction D1 may be substantially the same as the projection pattern and / or projection area of ​​the gate oxide layer 14B in the direction D1. The contact area between the second high-k dielectric layer 42B and the gate oxide layer 14B may be substantially equal to the top surface area of ​​the gate oxide layer 14B and / or the bottom surface area of ​​the second high-k dielectric layer 42B, but the present invention is not limited thereto. Furthermore, in some embodiments, the first gate structure GS1 and the second gate structure GS2 may serve as gates of different semiconductor devices (e.g., but not limited to transistor devices), and the difference in thickness and / or structural composition of the gate oxide layers in the first gate structure GS1 and the second gate structure GS2 may be used to correspond to semiconductor devices of different specifications (e.g., but not limited to transistor devices with different operating voltages). Therefore, the thickness of the gate oxide layer 14B in the second gate structure GS2 in the direction D1 may be less than the total thickness of the gate oxide layer 30A and the gate oxide layer 14B in the first gate structure GS1 in the direction D1 (e.g., the sum of the aforementioned thickness TK1 and the thickness of the gate oxide layer 14B in the direction D1). In other words, the gate oxide layer 30A in the first gate structure GS1 may be used to increase the total thickness of the gate oxide layer in the first gate structure GS1, thereby meeting the design requirements of the corresponding semiconductor device. In some embodiments, semiconductor structure 100 may further include an etch stop layer 22 and a dielectric layer 24. Etch stop layer 22 may be disposed on first region R1 and second region R2 of semiconductor substrate 10, and may conformally be disposed on the sidewalls of first and second spacer substructures 18A and 18B. Dielectric layer 24 may be disposed on etch stop layer 22, and dielectric layer 24, etch stop layer 22, first and second spacer substructures 18A, 18B, first capping layer 48A, and second capping layer 48B may have substantially coplanar upper surfaces, but are not limited thereto. Etch stop layer 22 may include silicon nitride or other suitable insulating materials, and dielectric layer 24 may include silicon oxide or other dielectric materials different from etch stop layer 22. Please refer to Figures 1 to 8. Figures 2 to 8 illustrate a method for fabricating a semiconductor structure according to an embodiment of the present invention. Figure 3 illustrates a state after Figure 2, Figure 4 illustrates a state after Figure 3, Figure 5 illustrates a state after Figure 4, Figure 6 illustrates a state after Figure 5, Figure 7 illustrates a state after Figure 6, and Figure 8 illustrates a state after Figure 7. Figure 1 may be considered to illustrate a state after Figure 8, but is not limited thereto. As shown in Figure 1, the method for fabricating a semiconductor structure 100 according to this embodiment may include the following steps: A semiconductor substrate 10 is provided, and the semiconductor substrate 10 includes a first active structure 10A. A first gate structure GS1 is formed on the first active structure 10A, and the first gate structure GS1 includes a first gate oxide layer (e.g., gate oxide layer 30A) and a first high-k dielectric layer 42A. The gate oxide layer 30A has a U-shaped structure in a cross-sectional view of the first gate structure GS, and the first high-k dielectric layer 42A is disposed on the gate oxide layer 30A. A first spacer substructure 18A is formed and disposed on the sidewalls of the first gate structure GS1. The first portion P1 of the gate oxide layer 30A is located between the first spacer substructure 18A and the first high-k dielectric layer 42A in a horizontal direction (e.g., direction D2). To further illustrate, the manufacturing method of the semiconductor structure 100 of this embodiment may include but is not limited to the following steps. As shown in Figure 2, a plurality of first active structures 10A and a plurality of second active structures 10B can be formed by patterning the semiconductor substrate 10, the first active structure 10A being located in the first region R1 of the semiconductor substrate 10, and the second active structure 10B being located in the second region R2 of the semiconductor substrate 10. Then, an isolation structure 12 can be formed to form an isolation effect between the plurality of first active structures 10A and between the plurality of second active structures 10B. The isolation structure 12 may include a single layer or multiple layers of insulating material, such as an oxide insulating material, a nitride insulating material, or other suitable insulating material. Then, a gate oxide layer 14A and a gate oxide layer 14B can be formed on the first active structure 10A and the second active structure 10B, respectively. In some embodiments, the gate oxide layer 14A and the gate oxide layer 14B can be formed simultaneously through the same process (e.g., oxidation process 91). Therefore, the gate oxide layer 14A and the gate oxide layer 14B can have the same or similar material composition, but are not limited thereto. In some embodiments, the gate oxide layer 14A and the gate oxide layer 14B can be formed separately using different processes and / or materials depending on design requirements. In some embodiments, an oxidation process 91 can be used to oxidize a portion of the first active structure 10A and a portion of the second active structure 10B that are exposed and not covered by the isolation structure 12, thereby forming a gate oxide layer 14A and a gate oxide layer 14B. Therefore, the formation of the gate oxide layer 14A and the gate oxide layer 14B consumes a portion of the first active structure 10A and a portion of the second active structure 10B, respectively. Therefore, when the first active structure 10A and the second active structure 10B are fin-shaped semiconductor structures, the thickness of the gate oxide layer 14A and the gate oxide layer 14B must be limited to avoid excessively affecting the dimensional changes of the fin semiconductor structures and cannot meet certain specific thickness requirements. Furthermore, in some embodiments, the oxidation process 91 can include a thermal oxidation process (e.g., rapid thermal oxidation (RTO)) or other suitable oxidation methods. The thermal oxidation process can include an in-situ steam generation (ISSG) process or other suitable thermal oxidation methods. Then, as shown in FIG2 and FIG3 , a dummy gate 16A and a dummy gate 16B can be formed on the gate oxide layer 14A and the gate oxide layer 14B, respectively. In some embodiments, the dummy gate 16A and the dummy gate 16B can be formed simultaneously by patterning the same material layer (e.g., a dummy gate material layer). The gate oxide layer 14A and the gate oxide layer 14B not covered by the dummy gate 16A and the dummy gate 16B in the direction D1 can be removed simultaneously during this patterning process, but the present invention is not limited thereto. The dummy gate material layer can include polysilicon or other suitable dummy gate materials. After the dummy gate 16A and the dummy gate 16B are formed, a first spacer substructure 18A, a second spacer substructure 18B, an etch stop layer 22, a dielectric layer 24, and a dielectric layer 26 can be formed. The first spacer substructure 18A may be formed on the sidewalls of the dummy gate 16A and the sidewalls of the gate oxide layer 14A, while the second spacer substructure 18B may be formed on the sidewalls of the dummy gate 16B and the sidewalls of the gate oxide layer 14B. The first spacer substructure 18A may surround the dummy gate 16A and the gate oxide layer 14A in a horizontal direction (e.g., direction D2 and / or direction D3), while the second spacer substructure 18B may surround the dummy gate 16B and the gate oxide layer 14B in a horizontal direction (e.g., direction D2 and / or direction D3). In other words, the dummy gate 16A and the gate oxide layer 14A may be considered to be located in the first trench TR1 surrounded by the first spacer substructure 18A and may completely fill the first trench TR1, while the dummy gate 16B and the gate oxide layer 14B may be considered to be located in the second trench TR2 surrounded by the second spacer substructure 18B and may completely fill the second trench TR2, but the present invention is not limited thereto. Furthermore, dielectric layer 26 may be formed on dielectric layer 24. Dielectric layer 26 and dielectric layer 24 may be formed using different processes and have different material properties. For example, in some embodiments, dielectric layer 24 may be formed using a flowable chemical vapor deposition (FCVD) process to achieve better gap-filling performance, while dielectric layer 26 may be formed using a high-density plasma chemical vapor deposition (HDP-CVD) process, but the present invention is not limited thereto. In some embodiments, a planarization process may be performed on the materials used to form the first and second spacer substructures 18A and 18B, the etch stop layer 22, and the dielectric layer 26 to expose the tops of the dummy gates 16A and 16B. Then, as shown in FIG3 and FIG4, the dummy gate 16A may be removed to expose the gate oxide layer 14A. In other words, the dummy gate 16A is removed after the dummy gate 16B and the second spacer substructure 18B are formed. In some embodiments, a patterned mask layer 28 may be formed to cover the material layers on the second region R2 to prevent the dummy gate 16B and the dummy gate 16A on the second region R2 from being removed together. The patterned mask layer 28 may include patterned photoresist or other suitable masking material, and the patterned mask layer 28 may be removed after the dummy gate 16A is removed. As shown in FIG. 4 to FIG. 7 , after the dummy gate 16A is removed, a gate oxide layer 30A may be formed on the gate oxide layer 14A. The method for forming the gate oxide layer 30A may include, but is not limited to, the following steps. As shown in Figures 4 and 5 , after removing the dummy gate 16A, an oxide layer 30 may be formed on the semiconductor substrate 10. A portion of the oxide layer 30 may be conformally formed in the first trench TR1, and another portion of the oxide layer 30 may be formed outside the first trench TR1, for example, on the dielectric layer 26 formed in the first region R1 and on the dummy gate 16B, the second spacer substructure 18B, and the dielectric layer 26 formed in the second region R2, but the present invention is not limited thereto. The oxide layer 30 formed in the first trench TR1 may be considered the gate oxide layer 30A described above. The oxide layer 30 may be formed by a deposition process 92, so the gate oxide layer 30A may also be considered to be formed by the deposition process 92. In some embodiments, the deposition process 92 may include an atomic layer deposition (ALD) process or other suitable deposition methods. Then, as shown in Figures 5 and 6 , after the deposition process 92, a dummy gate material 32 may be formed on the oxide layer 30. The dummy gate material 32 may include polysilicon or other suitable materials. A portion of the dummy gate material 32 may be formed within the first trench TR1, while another portion of the dummy gate material 32 may be formed outside the first trench TR1. Then, as shown in Figures 6 and 7 , a planarization process 93 may be performed to remove the oxide layer 30 and the dummy gate material 32 outside the first trench TR1. In some embodiments, the first trench TR1 may be filled with the gate oxide layer 14A, the oxide layer 30, and the dummy gate material 32. The dummy gate material 32 remaining in the first trench TR1 after the planarization process 93 may become the dummy gate 32A, and the oxide layer 30 remaining in the first trench TR1 after the planarization process 93 may become the gate oxide layer 30A. Therefore, the dummy gate 32A can be considered to be formed on the gate oxide layer 30A, and the first spacer substructure 18A can surround the dummy gate 32A, the gate oxide layer 30A, and the gate oxide layer 14A in a horizontal direction (e.g., direction D2 and / or direction D3). In some embodiments, a portion of the dielectric layer 26, a portion of the etch stop layer 22, a portion of the first spacer substructure 18A, a portion of the second spacer substructure 18B, and a portion of the dummy gate 16B can be removed simultaneously by the planarization process 93, but this is not limited to this. It is worth noting that when removing the oxide layer 30 outside the first trench TR1, the gate oxide layer 14B on the second region R2 can be covered by the dummy gate 16B and the second spacer substructure 18B to achieve a protective effect. This can reduce the negative impact of the oxide layer 30 removal process (e.g., the planarization process 93) on the gate oxide layer 14B, thereby improving the material condition and / or thickness control of the gate oxide layer 14B. As shown in Figures 7 and 8 , after the planarization process 93, the dummy gate 16B and the dummy gate 32A may be removed to expose the gate oxide layer 30A (e.g., the second portion of the gate oxide layer 30A) in the first trench TR1 and the gate oxide layer 14B in the second trench TR2, respectively. Then, as shown in Figures 7 , 8 , and 1 , after removing the dummy gate 16B and the dummy gate 32A, a first high-k dielectric layer 42A, a first conductive layer 44A, a first gate electrode 46A, and a first capping layer 48A may be formed in the first trench TR1, and a second high-k dielectric layer 42B, a second conductive layer 44B, a second gate electrode 46B, and a second capping layer 48B may be formed in the second trench TR2, thereby forming the semiconductor structure 100 shown in Figure 1 . In some embodiments, an etch-back process may be performed during the process of forming the first high-k dielectric layer 42A, the second high-k dielectric layer 42B, the first conductive layer 44A, the second conductive layer 44B, the first gate electrode 46A, and the second gate electrode 46B. This etch-back process may have a relatively low etching rate on the materials of the first gate electrode 46A and the second gate electrode 46B. Therefore, after the etch-back process, the upper surfaces of the gate oxide layer 30A, the first high-k dielectric layer 42A, and the first conductive layer 44A may be lower than the upper surface of the first gate electrode 46A in the direction D1, and the upper surfaces of the second high-k dielectric layer 42B and the second conductive layer 44B may be lower than the upper surface of the second gate electrode 46B in the direction D1, but the present invention is not limited thereto. In addition, in some embodiments, the first capping layer 48A and the second capping layer 48B can be formed by filling the first trench TR1 and the second trench TR2 with an insulating material and performing a planarization process on the insulating material, and a portion of the etch stop layer 22, a portion of the first gap substructure 18A, a portion of the second gap substructure 18B, and the dielectric layer 26 can be removed together by the planarization process, but the present invention is not limited thereto. By the above-mentioned manufacturing method, a semiconductor structure 100 as shown in FIG. 1 can be formed, wherein the first gate structure GS1 is formed on the first active structure 10A, and the second gate structure GS2 is formed on the second active structure 10B, and the structural composition of the first gate structure GS1 may be different from the structural composition of the second gate structure GS2. It is worth noting that, in the present invention, the method for forming the first gate structure GS1 and the second gate structure GS2 may include but is not limited to the manufacturing steps shown in FIG. 2 to FIG. 8 above. In other words, other methods may also be used to form the semiconductor structure 100 as shown in FIG. 1 depending on design requirements. In the first gate structure GS1, the gate oxide layer 30A may be used to increase the total thickness of the gate oxide layer in the first gate structure GS1, thereby meeting the design requirements of the corresponding semiconductor device. Furthermore, the above-described manufacturing method can avoid excessive damage to the active structure in order to form a thicker gate oxide layer and / or avoid damage to the gate oxide layer remaining in a specific area in order to remove part of the gate oxide layer in this area (for example, the step of removing the oxide layer 30 on the second area R2 in Figures 6 to 7 above), thereby achieving the effect of improving the process yield. In summary, in the semiconductor structure and fabrication method of the present invention, different methods can be used to form a gate oxide layer, allowing different regions of the gate structure to have different gate oxide layer thicknesses, thereby meeting the corresponding semiconductor device design requirements. Furthermore, the fabrication method of the present invention can also reduce the negative impact of related processes, thereby improving process yield and / or enhancing product performance. The above description is merely a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the present invention are intended to be covered by the present invention. 10: Semiconductor substrate 10A: First active structure 10B: Second active structure 12: Isolation structure 14A: Gate oxide layer 14B: Gate oxide layer 16A: Dummy gate 16B: Dummy gate 18A: First spacer structure 18B: Second spacer structure 22: Etch stop layer 24: Dielectric layer 26: Dielectric layer 28: Patterned mask layer 30: Oxide layer 30A: Gate oxide layer 32: Dummy gate material 32A: Dummy gate 42A: First high-k dielectric layer 42B: Second high-k dielectric layer 44A: First conductive layer 44B: Second conductive layer Electrical layer 46A: First gate electrode 46B: Second gate electrode 48A: First cap layer 48B: Second cap layer 91: Oxidation process 92: Deposition process 93: Planarization process 100: Semiconductor structure BS1: Bottom surface BS2: Bottom surface D1: Direction D2: Direction D3: Direction GS1: First gate structure GS2: Second gate structure P1: First portion P2: Second portion R1: First region R2: Second region TK1: Thickness TK2: Thickness TR1: First trench TR2: Second trench TS1: Top surface TS2: Top surface TS3: Top surface TS4: Top surface FIG1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. FIG2 through FIG8 are schematic diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present invention, wherein FIG3 is a schematic diagram illustrating a state subsequent to FIG2; FIG4 is a schematic diagram illustrating a state subsequent to FIG3; FIG5 is a schematic diagram illustrating a state subsequent to FIG4; FIG6 is a schematic diagram illustrating a state subsequent to FIG5; FIG7 is a schematic diagram illustrating a state subsequent to FIG6; and FIG8 is a schematic diagram illustrating a state subsequent to FIG7. 10:Semiconductor substrate 10A: First active structure 10B: Second active structure 14A: Gate oxide layer 14B: Gate oxide layer 18A: First gap substructure 18B: Second gap substructure 22: Etch stop layer 24: Dielectric layer 30A: Gate oxide layer 42A: first high-k dielectric layer 42B: Second high-k dielectric layer 44A: first conductive layer 44B: second conductive layer 46A: first gate electrode 46B: second gate electrode 48A: First cover layer 48B: Second cover layer 100:Semiconductor structure BS1: bottom surface BS2: bottom surface D1: Direction D2: Direction D3: Direction GS1: First Gate Structure GS2: Second gate structure P1: Part 1 P2: Part 2 R1: First Zone R2: Second Zone TK1:Thickness TK2:Thickness TR1: First groove TR2: Second groove TS1: Top surface TS2: Top surface TS3: Top surface TS4: Top surface

Claims

1. A semiconductor structure, comprising: A semiconductor substrate, including a first active structure; A first gate structure is disposed on the first active structure, wherein the first gate structure includes: a first gate oxide layer, the first gate oxide layer having a U-shaped structure in a cross-sectional view of the first gate structure; The first high dielectric constant dielectric layer is disposed on the first gate oxide layer; and a first gap substructure is disposed on the sidewall of the first gate structure, wherein a first portion of the first gate oxide layer is located in a horizontal direction between the first gap substructure and the first high dielectric constant dielectric layer, and the thickness of the first gate oxide layer is greater than the thickness of the first high dielectric constant dielectric layer.

2. The semiconductor structure as claimed in claim 1, wherein the first portion of the first gate oxide layer is sandwiched between the first spacer substructure and the first high dielectric constant dielectric layer in the horizontal direction.

3. The semiconductor structure as claimed in claim 2, wherein the first portion of the first gate oxide layer is directly connected in the horizontal direction to the first spacer substructure and the first high dielectric constant dielectric layer.

4. The semiconductor structure as described in claim 1, wherein the first gate structure further comprises: A second gate oxide layer, wherein the first gate oxide layer is disposed on the second gate oxide layer, and a second portion of the first gate oxide layer is sandwiched between the first high dielectric constant dielectric layer and the second gate oxide layer in a vertical direction.

5. The semiconductor structure as claimed in claim 4, wherein the second portion of the first gate oxide layer is directly connected to the first high-dielectric-constant dielectric layer and the second gate oxide layer.

6. The semiconductor structure as described in claim 4, further comprising: A second gate structure, wherein the semiconductor substrate further includes a second active structure, the second gate structure being disposed on the second active structure, and the second gate structure including: a third gate oxide layer; and a second high dielectric constant dielectric layer disposed on the third gate oxide layer, wherein the third gate oxide layer is directly connected to the second active structure and the second high dielectric constant dielectric layer.

7. The semiconductor structure as claimed in claim 6, wherein the thickness of the third gate oxide layer in a vertical direction is less than the total thickness of the first gate oxide layer and the second gate oxide layer in that vertical direction.

8. The semiconductor structure as described in claim 6, further comprising: A second gap substructure is disposed on the sidewall of the second gate structure, wherein the second high dielectric constant dielectric layer is directly connected to the second gap substructure.

9. The semiconductor structure as described in claim 1, wherein the first gate structure further comprises: A gate electrode is disposed on the first high dielectric constant dielectric layer, wherein the first high dielectric constant dielectric layer surrounds at least a portion of the gate electrode.

10. The semiconductor structure as claimed in claim 9, wherein an upper surface of the first portion of the first gate oxide layer is lower than an upper surface of the gate electrode and higher than a bottom surface of the gate electrode in a vertical direction.

11. The semiconductor structure as claimed in claim 1, wherein an upper surface of the first portion of the first gate oxide layer is lower in a vertical direction than an upper surface of the first spacer substructure.

12. The semiconductor structure as claimed in claim 1, wherein the first active structure includes a fin semiconductor structure.

13. A method for fabricating a semiconductor structure, comprising: A semiconductor substrate is provided, the semiconductor substrate including a first active structure; A first gate structure is formed on the first active structure, wherein the first gate structure includes: a first gate oxide layer having a U-shaped structure in a cross-sectional view of the first gate structure; The first high dielectric constant dielectric layer is disposed on the first gate oxide layer; and a first gap substructure is formed, wherein the first gap substructure is disposed on the sidewall of the first gate structure, a first portion of the first gate oxide layer is located in a horizontal direction between the first gap substructure and the first high dielectric constant dielectric layer, and the thickness of the first gate oxide layer is greater than the thickness of the first high dielectric constant dielectric layer.

14. A method for fabricating a semiconductor structure as described in claim 13, wherein the method for forming the first gate structure comprises: A second gate oxide layer is formed on the first active structure; A first dummy gate is formed on the second gate oxide layer, wherein the first gap substructure is formed after the step of forming the first dummy gate, and the first gap substructure surrounds the first dummy gate and the second gate oxide layer in the horizontal direction; after the step of forming the first gap substructure, the first dummy gate is removed; After the first dummy gate is removed, the first gate oxide layer is formed on the second gate oxide layer; and a second dummy gate is formed on the first gate oxide layer, wherein the first gap substructure surrounds the second dummy gate, the first gate oxide layer and the second gate oxide layer in the horizontal direction.

15. A method for fabricating a semiconductor structure as described in claim 14, wherein the first gate oxide layer is formed by an atomic layer deposition process, and the second gate oxide layer is formed by an oxidation process on the first active structure.

16. A method for fabricating a semiconductor structure as described in claim 14, wherein the method for forming the first gate oxide layer comprises: An oxide layer is formed on the semiconductor substrate, wherein a portion of the oxide layer is conformally formed in a first trench, the first trench is surrounded by the first spacer substructure, and another portion of the oxide layer is formed outside the first trench; And a planarization process is performed to remove the oxide layer located outside the first trench.

17. A method for fabricating a semiconductor structure as described in claim 16, wherein the method for forming the first gate structure further comprises: Prior to the planarization process, a dummy gate material is formed on the oxide layer, wherein a portion of the dummy gate material is formed in the first trench and another portion of the dummy gate material is formed outside the first trench. The dummy gate material located outside the first trench is removed by the planarization process, and the dummy gate material located in the first trench after the planarization process becomes the second dummy gate.

18. The method for fabricating the semiconductor structure as described in claim 16 further includes: A second gate structure is formed, wherein the semiconductor substrate further includes a second active structure, the second gate structure is formed on the second active structure, and the second gate structure includes: a third gate oxide layer; and a second high dielectric constant dielectric layer disposed on the third gate oxide layer, wherein the third gate oxide layer is directly connected to the second active structure and the second high dielectric constant dielectric layer.

19. A method for fabricating a semiconductor structure as described in claim 18, wherein the method for forming the second gate structure comprises: A third dummy gate is formed on the third gate oxide layer; A second gap substructure is formed on the sidewall of the third dummy gate and the sidewall of the third gate oxide layer, wherein the first dummy gate is removed after the third dummy gate and the second gap substructure are formed; and after the planarization process, the third dummy gate is removed, wherein the second high dielectric constant dielectric layer is formed after the third dummy gate is removed, and the second high dielectric constant dielectric layer is formed in a second trench surrounded by the second gap substructure.

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