Low temperature selective etching of silicon nitride using microwave plasma

Abstract

The embodiments disclosed herein include a method for etching a 3D structure. In one embodiment, the method includes the step of providing a 3D structure in a microwave plasma chamber. In one embodiment, the 3D structure includes a substrate and alternating layers of silicon oxide and silicon nitride over the substrate. In one embodiment, the method further includes the step of influencing a first gas into the microwave plasma chamber, wherein the first gas includes sulfur and fluorine. In one embodiment, the method includes the step of influencing a second gas into the microwave plasma chamber, wherein the second gas includes an inert gas. In one embodiment, the method further includes the steps of impacting a plasma in the microwave plasma chamber and etching the silicon nitride, wherein the etch selectivity of silicon nitride to silicon oxide is 50:1 or greater.

Description

Silicon nitride was selectively etched at low temperature using microwave plasma. Cross-reference of related applications This patent application claims priority to U.S. Provisional Application No. 63 / 253,487, filed October 7, 2021, the contents of which are incorporated herein by reference in their entirety. The embodiments relate to the field of semiconductor manufacturing, and more specifically, to the use of a microwave plasma source to selectively etch silicon nitride relative to silicon oxide. The fabrication of three-dimensional (3D) NAND devices involves forming alternating layers of silicon oxide (such as SiO₂). 2) Layers and silicon nitride (such as Si) 3N 4) Layers. After forming a stack of alternating layers, the silicon nitride layer is selectively removed to form trenches that are ultimately filled with conductors such as tungsten. Currently, wet etching processes are used to selectively remove the silicon nitride layer. However, during the drying process after etching, the suspended silicon oxide layer may collapse due to the surface tension of the liquid. This results in yield loss. Another problem with wet etching processes is that as the scale of future 3D NAND devices increases, the number of silicon oxide and silicon nitride layers will increase. This is problematic because the liquid etchant will have difficulty filling deeper trenches. This results in the etching at the top of the 3D structure differing from the etching at the bottom of the 3D structure. The embodiments disclosed herein include a method for etching a 3D structure. In one embodiment, the method includes the step of providing a 3D structure in a microwave plasma chamber. In one embodiment, the 3D structure includes a substrate and alternating layers of silicon oxide and silicon nitride over the substrate. In one embodiment, the method further includes the step of influencing a first gas into the microwave plasma chamber, wherein the first gas includes sulfur and fluorine. In one embodiment, the method includes the step of influencing a second gas into the microwave plasma chamber, wherein the second gas includes an inert gas. In one embodiment, the method further includes the steps of impacting a plasma in the microwave plasma chamber and etching the silicon nitride, wherein the etch selectivity of silicon nitride to silicon oxide is 50:1 or greater. In another embodiment, a method for selectively etching silicon nitride relative to silicon oxide includes the steps of: providing a substrate comprising silicon nitride and silicon oxide in a microwave plasma chamber. In one embodiment, the microwave plasma chamber includes a chamber, a chamber cover, a plurality of microwave applicators, a plurality of power sources, and a gas injection path, wherein the chamber cover is a dielectric material, the plurality of microwave applicators span the surface of the cover, each power source is coupled to one of the plurality of microwave applicators, and the gas injection path passes through the cover. In one embodiment, the method further includes the steps of: infusing a first gas into the chamber, wherein the first gas comprises sulfur and fluorine, and infusing a second gas into the chamber, wherein the second gas is an inert gas. In one embodiment, the method further includes the steps of: impacting a plasma in the chamber and etching the silicon nitride, wherein the etching selectivity of silicon nitride to silicon oxide (silicon nitride:silicon oxide) is 50:1 or greater. The embodiments described herein may also include a method for etching a 3D structure, the method comprising the steps of: providing a 3D structure in a microwave plasma chamber. In one embodiment, the 3D structure includes a substrate and alternating layers of silicon oxide and silicon nitride over the substrate. In one embodiment, the microwave plasma chamber includes a chamber, a chamber cover, a plurality of microwave applicators, a plurality of power sources, and a gas injection path, wherein the chamber cover is a dielectric material, the plurality of microwave applicators span the surface of the cover, each power source is coupled to one of the plurality of microwave applicators, and the gas injection path passes through the cover. In one embodiment, the method further comprises the steps of: infusing a first gas into the chamber, wherein the first gas contains sulfur and fluorine; infusing a second gas into the chamber, wherein the second gas is an inert gas; impacting a plasma in the chamber; and etching the silicon nitride layers, wherein the silicon nitride to silicon oxide (silicon nitride: silicon oxide) etching selectivity is 50:1 or greater. The system described herein includes a modular microwave plasma processing tool for selectively etching silicon nitride relative to silicon oxide. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. It will be apparent to those skilled in the art to which this invention pertains that the embodiments may be practiced without these specific details. In other instances, conventional forms have not been described in detail to avoid unnecessarily obscuring the embodiments. Furthermore, it should be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale. As mentioned above, wet etching of 3D NAND structures is limited in effectiveness, especially as devices continue to scale up to include larger stacks of alternating silicon oxide and silicon nitride layers. Given these limitations, dry etching processes have been explored to accommodate the increased scaling of 3D NAND structures. One proposed etching chemical is NF-4-4 with an inert gas. 3. Gases. NF 3. This provides selective etching of the 3D NAND structure, but leaves fluorine residue. Fluorine residue is unacceptable because fluorine can cause corrosion of subsequently deposited metals such as tungsten. Therefore, the embodiments disclosed herein include those containing sulfur and fluorine (such as SF6). 6) Etching chemicals. SF 6. It can flow into the chamber along with an inert gas (such as argon or helium). SF 6. Inert gas etching is a dry etching process. This eliminates the need for a post-etch drying step that could potentially damage the final features. Furthermore, it should be understood that the type of plasma chamber used to perform the etching contributes to the effectiveness of the etching chemistry. In a particular embodiment, the plasma chamber is a modular microwave plasma source. Such plasma sources have high plasma density and very low plasma potential (e.g., less than 10 eV). This results in significantly less sputtering damage to the etched structure compared to typical inductively coupled plasma (ICP) sources with higher plasma potentials (e.g., about 20 eV or higher). Furthermore, it should be understood that SF used in dry etching processes 6. Furthermore, argon source gases may not even be suitable for use in all types of chambers. For example, as already indicated, in remote plasma processes, the use of SF6... 6 and inert gases do not cause any etching at all. In other types of plasma chamber sources (such as ICP), SiN versus SiO X The etching selectivity is significantly lower than that achievable in modular microwave plasma sources. Therefore, using SF... The use of 6 and inert gases to provide high etch selectivity in dry etching processes is an unexpected result. Referring now to Figures 1A and 1B, a pair of cross-sectional views illustrating a dry etching process according to an embodiment are shown. In one embodiment, the etching process is performed on a 3D structure 100. For example, the 3D structure 100 may be a structure for a 3D NAND device. The 3D structure 100 may include a substrate 101, such as a polysilicon substrate or the like. Polysilicon pillars 102 may extend upward from the substrate 101. In one embodiment, each pillar 102 is composed of alternating layers of silicon oxide (such as SiO2). X )103 and silicon nitride layers (such as Si) X N Y The silicon nitride layer 104 and the silicon oxide layer 103 are arranged in a line. The sidewalls of the silicon nitride layer 104 and the silicon oxide layer 103 can be exposed by trenches 106 through the layers between the pillars 102. In a particular embodiment, the silicon nitride layer 104 is a sacrificial layer. That is, the silicon nitride layer 104 is etched away, as shown in FIG1B. The removal of the silicon nitride layer 104 results in the formation of trenches 105 between the silicon oxide layers 103. In some cases, the trenches 105 are subsequently filled with a conductive layer (such as tungsten, not shown). Because a conductive (and oxidizable) material is provided in the trenches 105, the surface of the silicon oxide layer 103 should be free of materials that would cause corrosion (such as fluorine). In one embodiment, the etching process requires a highly selective silicon nitride layer 104 above the silicon oxide layer 103. An additional beneficial characteristic is the high absolute etch rate of silicon nitride, reducing the etching time required. Furthermore, the etching chemistry should not leave residual fluorine. As will be described in more detail below, it has been indicated that the use of SF6... Modular microwave sources for etching chemicals with inert gases meet these parameters. In Figures 1A and 1B, structure 100 is shown as suitable for 3D NAND devices. The etching process described herein is particularly advantageous for use in 3D NAND devices. This is because the etching uniformity in highly scaled 3D NAND devices is excellent. That is, for structures with a high aspect ratio and numerous silicon nitride layers 104 and silicon oxide layers 103, the etching at the top and bottom of the structure is substantially uniform. Furthermore, it is possible to completely remove the silicon nitride layer 104 without significantly damaging the silicon oxide layer 103. However, it should be understood that the embodiments are not limited to the etching of 3D NAND structures. For example, a similar etching process can be used whenever it is necessary to selectively etch the silicon nitride structure relative to the silicon oxide layer. For instance, a silicon nitride layer can be provided above the silicon oxide layer, and the etching process etches through the silicon nitride layer and stops on the oxide layer. In such embodiments, the silicon oxide layer can be considered an etching stop layer. While providing benefits from SF Two examples of the architecture for the 6-etching process are provided, but it should be understood that the examples provided are non-limiting, and there may be embodiments of SF that benefit from the present invention. 6. Many different applications and architectures of the etching process. Referring now to FIG2, a cross-sectional view is shown of a processing tool 280 including component 270 according to one embodiment. In one embodiment, the processing tool includes a chamber 278 sealed by component 270. For example, component 270 may be positioned against one or more O-rings 281 to provide a vacuum seal to the internal space 283 of chamber 278. In other embodiments, component 270 may interface with chamber 278. That is, component 270 may be part of a cover sealing chamber 278. In one embodiment, a suction cup 279 or the like may support a workpiece 274 (such as a wafer, substrate, etc.). In one embodiment, component 270 may include a monolithic source array 250, a housing 272, and a cover plate 276. The monolithic source array 250 may include a dielectric plate 260 and a plurality of protrusions 266 extending upward from the dielectric plate 260. Although shown as a monolithic source array 250, it should be understood that the protrusions 266 may be distinct from the dielectric plate 260. That is, the protrusions 266 may be isolators located on top of the dielectric plate 260. In one embodiment, there may be five or more protrusions 266, or ten or more protrusions 266. In a particular embodiment, there may be 19 protrusions 266. The protrusions 266 comprise a dielectric material. The protrusions 266 function as dielectric resonators to couple microwaves into the chamber space 283. In some embodiments, the protrusions 266 may be referred to as microwave applicators, or simply applicators. In one embodiment, housing 272 may have openings, the size of which is adjusted to receive protrusion 266. Housing 272 may be made of a conductive material. In some embodiments, housing 272 is grounded. In the illustrated embodiment, housing 272 is directly supported by dielectric plate 260; however, it should be understood that a thermal interface material or the like may separate housing 272 from dielectric plate 260. In one embodiment, monopole antenna 268 may extend into a hole in protrusion 266. In one embodiment, the hole in protrusion 266 is larger than monopole antenna 268 to allow thermal expansion and thus prevent damage to monopole source array 250. Monopole antenna 268 may pass through housing 272 and cover plate 276 above protrusion 266. In one embodiment, monopole antennas 268 may each be coupled to a different power supply. The construction of the power supply will be described in more detail below. In one embodiment, chamber space 283 may be adapted for striking plasma 282. That is, chamber space 283 may be a vacuum chamber. Specifically, a vacuum source may be fluidly coupled to chamber space 283. For striking plasma 282, process gas may be flowed into chamber space 283. The process gas may enter assembly 270 via gas line 218. The process gas then passes through holes 214 in cover plate 276 and enters holes 235 in housing 272. Holes 235 intersect with gas distribution channels 230 that laterally distribute the process gas. Although a plurality of discrete gas distribution channels 230 are shown, it should be understood that the gas distribution channels 230 are fluidly coupled to each other outside the plane of FIG. 2. In one embodiment, the process gas exits the channel 230 through a group of 232 holes 237 in a cover above the channel 230. The process gas then passes through a gas distribution hole 263 through a dielectric plate 260 of a monolithic source array 250 and enters a chamber space 283. Referring now to FIG. 3, a schematic diagram of a solid-state high-frequency transmitting module 305 according to one embodiment is shown. The high-frequency transmitting module 305 can be considered as a power supply coupled to the monopole antenna in FIG. 2. In one embodiment, the high-frequency transmitting module 305 includes an oscillator module 306. The oscillator module 306 may include a voltage control circuit 310 for providing an input voltage to a voltage-controlled oscillator 320 to generate high-frequency electromagnetic radiation at a desired frequency. Embodiments may include an input voltage between approximately 1V and 10V DC. The voltage-controlled oscillator 320 is an electronic oscillator whose oscillation frequency is controlled by the input voltage. According to one embodiment, the input voltage from the voltage control circuit 310 causes the voltage-controlled oscillator 320 to oscillate at a desired frequency. In one embodiment, the high-frequency electromagnetic radiation may have a frequency between approximately 0.1MHz and 30MHz. In another embodiment, the high-frequency electromagnetic radiation may have a frequency between approximately 30MHz and 300MHz. In yet another embodiment, the high-frequency electromagnetic radiation may have a frequency between approximately 300MHz and 1GHz. In one embodiment, the high-frequency electromagnetic radiation may have a frequency between about 1 GHz and 300 GHz. According to one embodiment, electromagnetic radiation is transmitted from a voltage-controlled oscillator 320 to an amplifier module 330. The amplifier module 330 may include a driver / preamplifier 334 and a main power amplifier 336, each coupled to a power supply 339. According to one embodiment, the amplifier module 330 may operate in a pulsed mode. For example, the amplifier module 330 may have a duty cycle between 1% and 99%. In a more specific embodiment, the amplifier module 330 may have a duty cycle between approximately 15% and 50%. In one embodiment, after being processed by the amplification module 330, electromagnetic radiation can be transmitted to the thermal break 384 and the applicator 342. However, due to output impedance mismatch, a portion of the power transmitted to the thermal break 384 may be reflected back. Therefore, some embodiments include a detector module 381 that allows sensing the levels of the forward power 383 and the reflected power 382 and feeding them back to the control circuit module 321. It should be understood that the detector module 381 may be located in one or more different locations in the system (e.g., between the circulator 338 and the thermal break 349). In one embodiment, the control circuit module 321 interprets the forward power 383 and the reflected power 382, ​​and determines the level of the control signal 385, which is communicatively coupled to the oscillator module 306, and the level of the control signal 386, which is communicatively coupled to the amplification module 330. In one embodiment, control signal 385 adjusts oscillator module 306 to optimize high-frequency radiation coupled to amplifier module 330. In one embodiment, control signal 386 adjusts amplifier module 330 to optimize output power coupled to applicator 342 via thermal interrupter 384. In one embodiment, feedback control of oscillator module 306 and amplifier module 330, in addition to impedance matching tailoring in thermal interrupter 384, may allow the reflected power level to be less than about 5% of the forward power. In some embodiments, feedback control of oscillator module 306 and amplifier module 330 may allow the reflected power level to be less than about 2% of the forward power. Therefore, the embodiment allows for an increase in the percentage of forward power to be coupled into the processing chamber 378, as well as an increase in the available power coupled to the plasma. Furthermore, using feedback control for impedance adjustment is superior to impedance adjustment in typical slot-plate antennas. In slot-plate antennas, impedance adjustment involves moving two dielectric slugs formed in the applicator. This involves mechanical movement of two separate components in the applicator, which increases the complexity of the applicator. Moreover, the accuracy of mechanical movement may not be as precise as the frequency variation provided by the voltage-controlled oscillator 320. Referring now to FIG4, a flowchart illustrating a process 490 for selectively etching silicon nitride relative to silicon oxide is shown according to one embodiment. In one embodiment, process 490 begins at operation 491, which includes providing a 3D structure having alternating layers of silicon nitride and silicon oxide in a chamber. In one embodiment, the 3D structure may be a 3D NAND structure, or more specifically, an intermediate structure used in the fabrication of a 3D NAND structure. In one embodiment, the 3D structure may be substantially similar to the structure described above with respect to FIG1A. For example, the underlying semiconductor substrate may be covered by a plurality of alternating layers of silicon nitride and silicon oxide. Deep trenches may be provided through the thickness of the layers. In this way, the sidewall surfaces of the silicon nitride and silicon oxide layers are exposed. Although a particular 3D structure is described as an example, it should be understood that any architecture having silicon nitride and oxide layers may be provided in the chamber according to various embodiments. In one embodiment, the 3D structure may be disposed on a substrate, such as a semiconductor substrate. In a particular embodiment, a wafer comprising a plurality of 3D structures is provided in a cavity. In one embodiment, the cavity may include a modular microwave plasma source. For example, according to one embodiment, a processing tool similar to the modular microwave plasma source described in more detail above may be used. In one embodiment, process 490 can continue to operation 492, which includes allowing a process gas to flow into the chamber. In one embodiment, the process gas includes sulfur and fluorine. In a particular embodiment, the process gas includes SF6. 6. In one embodiment, process 490 may proceed to operation 493, which includes influencing an inert gas into the chamber. In one embodiment, the inert gas includes argon or helium. In some embodiments, argon is used because argon is readily ionized and increases plasma density. However, embodiments using helium may exhibit reduced oxide damage and improved etch selectivity compared to using argon. Although described as discrete processing operations, it should be understood that fluorinated gas and inert gas may flow into the chamber substantially simultaneously. In one embodiment, the ratio of process gas to inert gas (e.g., SF6) is... The concentration of 6 / Ar can be about 0.4 or less, about 0.1 or less, or about 0.05 or less. In some embodiments, a third gas may also flow into the chamber. For example, H 2S or dichlorosilane (DCS) can be combined with SF 6 flows into the chamber along with the inert gas. In one embodiment, H The amount of 2S or DCS can be less than SF. The amount is 6. In one embodiment, process 490 may continue to operation 494, which includes impinging plasma in chamber 494. In one embodiment, the pressure in the chamber during plasma impingement may be about 0.5 Torr or less, or about 0.2 Torr or less. In one embodiment, the distance between the plasma source and the substrate having the 3D structure may be about one inch or less, or a quarter inch or less. In one embodiment, the plasma may be generated by a plurality of microwave applicators (similar to the structure shown in Figure 2). In one embodiment, process 490 can proceed to operation 495, which includes etching silicon nitride. In one embodiment, silicon nitride can be etched with a selectivity relative to silicon oxide of about 50:1 or greater, about 400:1 or greater, or about 1,600:1 or greater. Furthermore, it should be understood that the etching process substantially leaves no fluorine residue. This avoids subsequent corrosion problems. Furthermore, it should be understood that etching uniformity is very high on high aspect ratio structures. For example, the etching rate of silicon nitride at the top of a 3D NAND structure can be substantially similar to the etching rate of silicon nitride at the bottom of a 3D NAND structure. In some embodiments, the ratio of silicon nitride etching rates between the top and bottom of the structure can be between about 1.3:1 and about 1:1. In some embodiments, the silicon nitride etching rate can be about 15 nm / min or greater, or about 25 nm / min or greater. Referring now to Figure 5, a series of graphs illustrating the effects of various pressures, temperatures, and process gas ratios are shown. According to one embodiment, the top three graphs plot the selectivity between silicon nitride and silicon oxide, and the bottom three graphs plot the etch rate of silicon nitride. As shown, pressure has the least effect on the etch rate of silicon nitride. Lower pressures indicate some beneficial effect on selectivity. Lower temperatures result in slightly lower etch rates, but still show improved selectivity. The greatest effect is seen in variations in the process gas ratio. Typically, the process gas (such as SF6)... 6) A lower ratio with an inert gas (such as Ar) results in improved etching rate and etching selectivity. It should be understood that the etching temperatures (i.e., substrate temperatures) disclosed herein for use in embodiments can be considered as low-temperature processes. For example, the substrate temperature may be about 500°C or lower. In a particular embodiment, the substrate temperature may be about 100°C. Figure 6 presents a series of graphs illustrating the effects of a fixed temperature of 100°C, pressure, time, and process gas ratio on etch selectivity and etch rate. Similar to Figure 5, the top three graphs describe the effect on etch selectivity, and the bottom three graphs describe the effect on silicon nitride etch rate. As shown in the figure, the etching selectivity at 100°C is significantly better than that at the higher temperatures shown in Figure 5. Selectivity is also least affected by pressure. However, the etching rate decreases with decreasing pressure. At lower pressures, selectivity is improved with minimal impact on the etching rate. The process gas ratio has the least effect on selectivity, while a higher ratio improves the etching rate. Referring now to FIG7, a block diagram of an exemplary computer system 700 of a processing tool according to one embodiment is shown. In one embodiment, the computer system 700 is coupled to and controls processing within the processing tool. The computer system 700 may be connected (e.g., via a network connection) to other machines in a local area network (LAN), intranet, extranet, or internet. The computer system 700 may operate as a server or client machine in a master-slave architecture network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 700 may be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing one set of instructions (sequentially or otherwise) specifying the actions that the machine wishes to take. Furthermore, although only a single machine is depicted for computer system 700, the term "machine" should also be considered to include any collection of machines (such as computers) that individually or collectively execute a set (or more) of instructions to perform any one or more methods described in this case. Computer system 700 may include computer program products or software 722 having a non-transitory machine-readable medium on which instructions are stored, which can be used to program computer system 700 (or other electronic device) to perform the processes according to the embodiments. Machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable form. For example, machine-readable (e.g., computer-readable) media includes machine-readable storage media (e.g., read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), machine-readable transmission media (e.g., electrical, optical, acoustic, or other forms of propagation signals (e.g., infrared signals, digital signals, etc.)). In one embodiment, the computer system 700 includes a system processor 702 that communicates with each other via a bus 730, main memory 704 (such as read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 706 (such as flash memory, static random access memory (SRAM), etc.), and auxiliary memory 718 (such as data storage device). System processor 702 represents one or more general-purpose processing devices, such as microsystem processors, central processing units, or the like. More specifically, the system processor may be a Complex Instruction Set Computing (CISC) microsystem processor, a Reduced Instruction Set Computing (RISC) microsystem processor, a Very Long Instruction Word (VLIW) microsystem processor, a system processor that implements other instruction sets, or a system processor that implements a combination of instruction sets. System processor 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal system processors (DSPs), network system processors, or the like. System processor 702 is configured to execute processing logic 726 for performing the operations described herein. The computer system 700 may further include a system network interface device 708 for communicating with other devices or machines. The computer system 700 may also include an image display unit 710 (such as a liquid crystal display (LCD), a light-emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 712 (such as a keyboard), a cursor control device 714 (such as a mouse), and a signal generation device 716 (such as a speaker). Auxiliary memory 718 may include machine-accessible storage medium 732 (or more specifically, computer-readable storage medium) storing one or more sets of instructions (such as software 722) embodying any one or more methods or functions described herein. During execution of software 722 by computer system 700, software 722 may also reside wholly or at least partially within main memory 704 and / or system processor 702, which also constitute machine-readable storage media. Software 722 may be further transmitted or received on network 720 via system network interface device 708. In one embodiment, network interface device 708 may operate using RF coupling, optical coupling, acoustic coupling, or inductive coupling. Although the machine-accessible storage medium 732 is shown as a single medium in the exemplary embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (such as a centralized or distributed database, and / or associated caches and servers) that store a set or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and to enable the machine to perform any one or more methods. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, as well as optical and magnetic media. Specific exemplary embodiments have been described in the foregoing specification. It is obvious that various modifications may be made to the embodiments without departing from the scope of the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive. 100: 3D Structure 101: Substrate 102: Polycrystalline Silicon Pillar 103: Silicon Oxide Layer 104: Silicon Nitride Layer 105: Trench 106: Groove 214: Hole 218: Gas Pipeline 230: Gas Distribution Channel 232: Cluster 235: Hole 237: Hole 250: Monopole Source Array 260: Dielectric Plate 263: Gas Distribution Hole 266: Protrusion 268: Monopole Antenna 270: Component 272: Housing 274: Workpiece 276: Cover Plate 278: Chamber 279: Suction Cup 280: Processing Tool 281: O-ring 282: Plasma 283: Chamber Space 305: Solid-State High-Frequency Transmitter Module 306: Oscillator Module 310: Voltage Control Circuit 320: Voltage-Controlled Oscillator 321: Control Circuit Module 330: Amplification Module 334: Preamplifier 336: Main power amplifier 338: Circulator 339: Power supply 342: Applicator 349: Thermal interruptor 378: Processing chamber 381: Detector module 382: Reflected power 383: Forward power 384: Thermal interruptor 385: Control signal 386: Control signal 490: Process 491: Operation 492: Operation 493: Operation 494: Operation 495: Operation 700: Computer system 702: System processor 704: Main memory 706: Static memory 708: System network interface device 710: Image display unit 712: Alphanumeric input device 714: Cursor control device 716: Signal generation device 718: Auxiliary memory 722: Software 726: Processing logic 730: Bus Figure 1A is a cross-sectional view of a portion of a 3D NAND structure having alternating silicon oxide and silicon nitride layers according to one embodiment. Figure 1B is a cross-sectional view of a portion of a 3D NAND structure having a silicon nitride layer removed by an etching process, according to one embodiment. Figure 2 is a cross-sectional view of a microwave plasma chamber for dry etching of a 3D NAND structure according to an embodiment. Figure 3 is a schematic diagram of a power supply for the microwave applicator in Figure 2 according to one embodiment. Figure 4 is a flowchart of a process for etching a silicon nitride layer in a 3D NAND structure using a microwave plasma chamber according to one embodiment. Figure 5 is a series of graphs illustrating the selectivity and etch rate for various processing conditions according to one embodiment. Figure 6 is a series of graphs depicting the selectivity and etching rate for various processing conditions while maintaining a constant temperature, according to one embodiment. Figure 7 illustrates a block diagram of an exemplary computer system that can be used in conjunction with a plasma tool according to an embodiment. Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None. 490: Manufacturing Process 491: Operation 492: Operation 493: Operation 494: Operation 495: Operation

Claims

1. A method for etching a 3D structure, comprising the following steps: The 3D structure is provided in a microwave plasma chamber, wherein the 3D structure comprises: One substrate; The substrate has alternating layers of silicon oxide and silicon nitride; a first gas is introduced into the microwave plasma chamber, wherein the first gas includes sulfur and fluorine; a second gas is introduced into the microwave plasma chamber, wherein the second gas includes an inert gas, and wherein the ratio of the first gas to the second gas is 0.4 or less; a plasma is bombarded in the microwave plasma chamber; and the silicon nitride is etched, wherein the etch selectivity of silicon nitride to silicon oxide is 50:1 or greater.

2. The method as described in claim 1, wherein the first gas comprises SF6.

3. The method as described in claim 1, wherein the second gas comprises Ar or He.

4. The method as described in claim 1, wherein a ratio (first gas / second gas) of the first gas to the second gas is 0.3 or less.

5. The method as described in claim 1, wherein a temperature of the substrate is 500°C or lower.

6. The method as described in claim 5, wherein the temperature of the substrate is 100°C or lower.

7. The method as described in claim 1, wherein a pressure in the microwave plasma chamber is 0.6 Torr or lower.

8. The method as described in claim 7, wherein the pressure in the microwave plasma chamber is 0.3 Torr or lower.

9. The method as described in claim 1, further comprising the step of: allowing a third gas to flow into the microwave plasma chamber, wherein the third gas comprises H2S or dichlorosilane (DCS).

10. The method as described in claim 1, wherein the microwave plasma chamber comprises: Multiple microwave applicators, each of which is coupled to a different power source.

11. The method as described in claim 10, wherein the plurality of applicators are integrally integrated with a chamber cover.

12. The method as described in claim 1, wherein the first gas and the second gas flow into the microwave plasma chamber through a top gas injection structure.

13. A method for selectively etching silicon nitride relative to silicon oxide, comprising the following steps: A substrate comprising silicon nitride and silicon oxide is provided in a microwave plasma chamber, wherein the microwave plasma chamber includes: a chamber; a chamber cover, wherein the chamber cover is a dielectric material; a plurality of microwave applicators spanning a surface of the cover; a plurality of power supplies, wherein each power supply is coupled to one of the plurality of microwave applicators; and a gas injection path passing through the cover; allowing a first gas to flow into the chamber, wherein the first gas includes sulfur and fluorine; allowing a second gas to flow into the chamber, wherein the second gas is an inert gas, and wherein the ratio of the first gas to the second gas is 0.4 or less; impacting a plasma in the chamber; and etching the silicon nitride, wherein the etching selectivity of silicon nitride to silicon oxide (silicon nitride:silicon oxide) is 50:1 or greater.

14. The method as described in claim 13, wherein the first gas comprises SF6.

15. The method as described in claim 13, wherein the second gas comprises Ar or He.

16. The method as described in claim 13, wherein a ratio (first gas / second gas) of the first gas to the second gas is 0.3 or less.

17. The method as described in claim 13, wherein a temperature of the substrate is 100°C or lower.

18. A method for etching a 3D structure, comprising the following steps: The 3D structure is provided in a microwave plasma chamber, wherein the 3D structure includes: a substrate; and alternating layers of silicon oxide and silicon nitride over the substrate, wherein the microwave plasma chamber includes: a chamber; a chamber cover, wherein the chamber cover is a dielectric material; a plurality of microwave applicators spanning a surface of the cover; a plurality of power sources, wherein each power source is coupled to one of the plurality of microwave applicators; and a gas injection path passing through the cover; allowing a first gas to flow into the chamber, wherein the first gas includes sulfur and fluorine; allowing a second gas to flow into the chamber, wherein the second gas is an inert gas, and wherein a ratio of the first gas to the second gas is 0.4 or less; impacting a plasma in the chamber; and etching the silicon nitride layers, wherein the silicon nitride to silicon oxide (silicon nitride: silicon oxide) etching selectivity is 50:1 or greater.

19. The method as described in claim 18, wherein the first gas comprises SF6, and wherein the second gas comprises Ar or He.

20. The method as described in claim 18, wherein a temperature of the substrate is 100°C or lower.

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