Semiconductor device

Abstract

This disclosure provides a semiconductor device capable of improving device performance and reliability. The semiconductor device includes: a lower wiring structure; an upper interlayer insulating layer disposed on the lower wiring structure and including an upper wiring trench, the upper wiring trench exposing a portion of the lower wiring structure; and an upper wiring structure including an upper liner in the upper wiring trench and an upper filler layer on the upper liner, wherein the upper liner includes a sidewall portion extending along the sidewall of the upper wiring trench and a bottom portion extending along the bottom surface of the upper wiring trench, the sidewall portion of the upper liner comprising cobalt (Co) and ruthenium (Ru), and the bottom portion of the upper liner being formed of cobalt (Co).

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] This application claims priority to and all rights arising therefrom of Korean Patent Application No. 10 - 2021 - 0169761, filed on December 1, 2021 with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

[0003] This disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor element including wiring lines formed in a back - end - of - line (BEOL) process and a method of manufacturing the same. Prior Art

[0004] Due to the development of electronic technology, as the scaling down of semiconductor devices is rapidly progressing, high integration and low power consumption of semiconductor wafers are required. In response to the demand for high integration and low power consumption of semiconductor wafers, the feature size of semiconductor devices is reduced.

[0005] On the other hand, as the feature size is reduced, various studies are being conducted on a stable connection method between wirings. Summary of the Invention

[0006] Aspects of the present disclosure provide a semiconductor device capable of improving component performance and reliability.

[0007] Aspects of the present disclosure provide a method for manufacturing a semiconductor device capable of improving component performance and reliability.

[0008] However, aspects of the present disclosure are not limited to the aspects described herein. By referring to the detailed description of the present disclosure given below, the above - mentioned and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0009] According to an aspect of the present disclosure, a semiconductor device is provided, including: a lower wiring structure; an upper interlayer insulating layer located on the lower wiring structure and including upper wiring grooves vertically overlapping a part of the lower wiring structure; and an upper wiring structure including an upper liner layer in the upper wiring grooves and an upper filling layer on the upper liner layer, wherein the upper liner layer includes a sidewall portion extending along the sidewalls of the upper wiring grooves and a bottom portion extending along the bottom surface of the upper wiring grooves, the sidewall portion of the upper liner layer includes cobalt (Co) and ruthenium (Ru), and the bottom portion of the upper liner layer is formed of cobalt (Co).

[0010] According to another aspect of the present disclosure, a semiconductor device is provided, including: a lower wiring structure; an upper interlayer insulating layer located on the lower wiring structure and including upper wiring grooves, the upper wiring grooves including upper wiring line grooves and upper vias grooves on the bottom surface of the upper wiring line grooves, and the bottom surface of the upper vias grooves includes the lower wiring structure; and an upper wiring structure including an upper barrier layer, an upper filling layer, and an upper liner layer between the upper barrier layer and the upper filling layer in the upper wiring grooves, wherein the upper barrier layer extends along the sidewalls and the bottom surface of the upper wiring line grooves and the sidewalls of the upper vias grooves, the upper barrier layer includes a metal nitride, the upper liner layer includes a sidewall portion extending along the sidewalls and the bottom surface of the upper wiring line grooves and the sidewalls of the upper vias grooves and a bottom portion extending along the bottom surface of the upper vias grooves, the upper liner layer contacts the lower wiring structure, the upper liner layer includes cobalt (Co) and ruthenium (Ru), and the sidewall portion of the upper liner layer has a different component or composition from the bottom portion of the upper liner layer.

[0011] According to still another aspect of the present disclosure, a semiconductor device is provided, including: a lower wiring structure; an upper interlayer insulating layer located on the lower wiring structure and including upper wiring grooves, the upper wiring grooves exposing a part of the lower wiring structure; and an upper wiring structure including an upper liner layer in the upper wiring grooves and an upper filling layer on the upper liner layer, wherein the upper liner layer contacts the lower wiring structure, the upper liner layer includes a sidewall portion extending along the sidewalls of the upper wiring grooves and a bottom portion extending along the bottom surface of the upper wiring grooves, the sidewall portion of the upper liner layer includes a first portion containing a ruthenium-cobalt (RuCo) alloy layer and a second portion formed of cobalt (Co), the second portion of the sidewall portion of the upper liner layer contacts the lower wiring structure, and the bottom portion of the upper liner layer is formed of cobalt (Co).

[0012] According to yet another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: forming a lower wiring structure; forming an upper interlayer insulating layer including upper wiring grooves on the lower wiring structure, the upper wiring grooves exposing a first region of the lower wiring structure; forming a first selective inhibition layer on the first region of the lower wiring structure exposed by the upper wiring grooves; forming an upper barrier layer along sidewalls of the upper wiring grooves in a state where the first selective inhibition layer is formed, wherein a bottom surface of the upper wiring grooves does not include the upper barrier; exposing a second region of the lower wiring structure by removing the first selective inhibition layer; forming a second selective inhibition layer on the exposed second region of the lower wiring structure; forming a ruthenium (Ru) layer on the upper barrier layer along sidewalls of the upper wiring grooves in a state where the second selective inhibition layer is formed, wherein the bottom surface of the upper wiring grooves does not include the Ru layer; forming a cobalt (Co) layer on the Ru layer along sidewalls and a bottom surface of the upper wiring grooves in a state where the second selective inhibition layer is formed; and forming a pre-upper filling layer in the upper grooves after removing the second selective inhibition layer. Brief Description of the Drawings

[0013] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments thereof in detail with reference to the accompanying drawings, in which: FIG. 1 is an example layout diagram showing a semiconductor device according to some example embodiments. FIG. 2 is an example cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is an example cross-sectional view taken along line B-B of FIG. 1. FIG. 4 is an enlarged view of part P of FIG. 2. FIG. 5 is an enlarged view of part Q of FIG. 3. FIG. 6 is a view showing a semiconductor device according to some example embodiments. FIG. 7 is a view showing a semiconductor device according to some example embodiments. FIG. 8 is a view showing a semiconductor device according to some example embodiments. FIG. 9 is a view showing a semiconductor device according to some exemplary embodiments. FIG. 10 is a view showing a semiconductor device according to some example embodiments. FIGS. 11 and 12 are views showing a semiconductor device according to some example embodiments. FIGS. 13 and 14 are views showing a semiconductor device according to some example embodiments. FIG. 15 is a view showing a semiconductor device according to some example embodiments. FIG. 16 is a view showing a semiconductor device according to some example embodiments. FIG. 17 is a view showing a semiconductor device according to some example embodiments. FIGS. 18, 19, and 20 are views showing a semiconductor device according to some example embodiments. FIGS. 21, 22, 23, 24, 25, 26, 27, 28, and 29 are intermediate step views showing a method of manufacturing a semiconductor device according to some example embodiments. Embodiments

[0014] In the diagrams of a semiconductor device according to some example embodiments, for example, a fin-type transistor (FinFET) including a fin-shaped channel region, a transistor including a nanowire or a nanosheet, a multi-bridge channel field effect transistor (MBCFET™), or a vertical FET are shown, but the present disclosure is not limited thereto. A semiconductor device according to some example embodiments may include a tunneling FET or a three-dimensional (3D) transistor. A semiconductor device according to some example embodiments may include a planar transistor. Additionally, the technical idea of the present disclosure may be applied to FET-based 2D materials and their heterostructures.

[0015] Furthermore, a semiconductor device according to some example embodiments may also include a bipolar junction transistor, a laterally double-diffused metal oxide semiconductor (LDMOS) transistor, or the like.

[0016] FIG. 1 is an example layout diagram showing a semiconductor device according to some example embodiments. FIG. 2 is an example cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is an example cross-sectional view taken along line B-B of FIG. 1. FIG. 4 is an enlarged view of a portion P of FIG. 2. FIG. 5 is an enlarged view of a portion Q of FIG. 3.

[0017] Referring to FIGS. 1 to 5, a semiconductor device according to some example embodiments may include a lower wiring structure 110 and an upper wiring structure 210.

[0018] The lower wiring structure 110 may be disposed in the first interlayer insulating layer 150. The lower wiring structure 110 may extend to elongate in a first direction D1. Terms such as first, second, etc. may be used herein only to distinguish one element or layer from another element or layer.

[0019] The lower wiring structure 110 may have a linear shape extending in a first direction D1. For example, the first direction D1 may be the longitudinal direction of the lower wiring structure 110, and the second direction D2 may be the width direction of the lower wiring structure 110. Here, the first direction D1 intersects the second direction D2 and the third direction D3. The second direction D2 intersects the third direction D3.

[0020] The first interlayer insulating layer 150 may cover the gate electrode and the source / drain of the transistor formed in the front-end-of-line (FEOL) process. Alternatively, the first interlayer insulating layer 150 may be an interlayer insulating layer formed in the back-end-of-line (BEOL) process.

[0021] In other words, as an example, the lower wiring structure 110 may be a contact or a contact wiring formed in the middle-of-line (MOL) process. As another example, the lower wiring structure 110 may be a connection wiring formed in the back-end-of-line (BEOL) process. In the following description, the lower wiring structure 110 will be described as a connection wiring formed in the BEOL process.

[0022] The first interlayer insulating layer 150 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The low-k material may be, for example, silicon oxide having moderately high carbon and hydrogen, and may be a material such as SiCOH. At the same time, since carbon is included in the insulating material, the dielectric constant of the insulating material may be reduced. However, in order to further reduce the dielectric constant of the insulating material, the insulating material may include pores such as air-filled or air-filled cavities in the insulating material.

[0023] Low-k materials may include, for example: Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Borate (TMSP), PolyTetraFluoroEthylene (PTFE), Tonen Silazene (TOSZ), fluoride silicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon doped silicon oxide (CDO), organo silicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or combinations thereof, but are not limited thereto.

[0024] The lower wiring structure 110 may be disposed at the first metal layer level. The first interlayer insulating layer 150 may include lower wiring grooves 110t that are extended to elongate in the first direction D1.

[0025] The lower wiring structure 110 may be disposed in the lower wiring grooves 110t. The lower wiring grooves 110t are filled with the lower wiring structure 110.

[0026] The lower wiring structure 110 may include a lower barrier layer 111, a lower liner layer 112, a lower filling layer 113, and a lower capping layer 114. The lower liner layer 112 may be disposed between the lower barrier layer 111 and the lower filling layer 113. The lower capping layer 114 may be disposed on the lower filling layer 113.

[0027] The lower barrier layer 111 may extend along the sidewalls and bottom surface of the lower wiring groove 110t. The lower liner 112 may be disposed on the lower barrier layer 111. The lower liner 112 may extend along the sidewalls and bottom surface of the lower wiring groove 110t on the lower barrier layer 111.

[0028] The lower fill layer 113 is disposed on the lower liner 112. The remaining portion of the lower wiring groove 110t may be filled with the lower fill layer 113.

[0029] The lower capping layer 114 may extend along the upper surface 113US of the lower fill layer. In some embodiments, the lower capping layer 114 may be disposed on the upper surface of the lower liner 112. In some embodiments, different from those embodiments shown in the figures, the lower capping layer 114 may not cover the upper surface of the lower liner 112.

[0030] When the lower liner 112 and the lower capping layer 114 are formed of the same material, the upper surface of the lower liner 112 may not be distinguished at the boundary between the lower liner 112 and the lower capping layer 114.

[0031] In some embodiments, the lower capping layer 114 may not cover the upper surface of the lower barrier layer 111. In some embodiments, different from those embodiments shown in the figures, the lower capping layer 114 may cover at least a portion of the upper surface of the lower barrier layer 111.

[0032] The upper surface of the lower liner 112 is shown to be coplanar with the upper surface 113US of the lower fill layer and the upper surface of the lower barrier layer 111, but is not limited thereto. Here, the upper surface of the lower liner 112 may refer to the uppermost surface of the portion of the lower liner 112 that extends along the sidewalls of the lower wiring groove 110t.

[0033] The lower barrier layer 111 may comprise a conductive material, such as a metal nitride. The lower barrier layer 111 may comprise at least one of, for example, tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), zirconium nitride (ZrN), vanadium nitride (VN), or niobium nitride (NbN). In the following description, the lower barrier layer 111 will be described as comprising tantalum nitride (TaN).

[0034] The lower liner 112 may comprise a conductive material, such as a metal or a metal alloy. The lower liner 112 may comprise at least one of, for example, ruthenium (Ru), cobalt (Co), or a ruthenium-cobalt (RuCo) alloy.

[0035] In a semiconductor device according to some example embodiments, the lower liner 112 may be formed of cobalt (Co). The lower liner 112 may be formed of cobalt and may be a lower cobalt layer 112_BF. Here, the "cobalt layer" may be a layer formed purely of cobalt and may include impurities introduced during the process of forming the cobalt layer. That is, when an element or layer of a device is "formed" of a material, the element or layer may substantially or entirely comprise the material. For example, the lower liner 112 may be formed of Co and may not contain Ru.

[0036] The lower fill layer 113 may include a conductive material such as at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), rhodium (Rh), iridium (Ir), RuAl, NiAl, NbB2, MoB2, TaB2, V2AlC, or CrAlC. In a semiconductor device according to some example embodiments, the lower fill layer 113 may include copper (Cu).

[0037] The lower capping layer 114 may include a conductive material such as a metal. The lower capping layer 114 may include at least one of, for example, cobalt (Co), ruthenium (Ru), or manganese (Mn). In a semiconductor device according to some example embodiments, the lower capping layer 114 may include cobalt. The lower capping layer 114 may be formed of cobalt (Co).

[0038] In some embodiments, different from the embodiments shown in the drawings, the lower wiring structure 110 may have a single-layer structure. Although not shown, via patterns connecting conductive patterns disposed under the lower wiring structure 110 may be further included.

[0039] The lower wiring structure 110 may be formed using, for example, an embedding method. In FIG. 2, the width of the lower wiring structure 110 in the second direction D2 is shown as constant, but is not limited thereto. In some embodiments, different from the embodiments shown in FIG. 2, as the distance from the upper surface of the first interlayer insulating layer 150 increases, the width of the lower wiring structure 110 in the second direction D2 may decrease.

[0040] The first etch stop layer 155 may be disposed on the lower wiring structure 110 and the first interlayer insulating layer 150. The second interlayer insulating layer 160 may be disposed on the first etch stop layer 155. The first etch stop layer 155 may be disposed between the first interlayer insulating layer 150 and the second interlayer insulating layer 160.

[0041] The second interlayer insulating layer 160 may include upper wiring grooves 210t. The upper wiring grooves 210t may penetrate through the first etch stop layer 155. The upper wiring grooves 210t expose portions of the lower wiring structure 110. The upper wiring grooves 210t overlap perpendicularly with portions of the lower wiring structure 110 (e.g., in the direction D3).

[0042] The upper wiring grooves 210t may include upper via grooves 210V_t and upper wiring line grooves 210L_t. The upper wiring line grooves 210L_t may extend to elongate in the second direction D2. The upper wiring line grooves 210L_t may extend into the upper surface of the second interlayer insulating layer 160. The upper via grooves 210V_t may be formed on the bottom surface of the upper wiring line grooves 210L_t.

[0043] For example, the bottom surface of the upper wiring grooves 210t may be the bottom surface of the upper via grooves 210V_t. The bottom surface of the upper wiring grooves 210t may be defined by the lower wiring structure 110.

[0044] The sidewalls of the upper wiring grooves 210t may include the sidewalls and the bottom surface of the upper wiring line grooves 210L_t and the sidewalls of the upper via grooves 210V_t. The sidewalls and the bottom surface of the upper wiring line grooves 210L_t may be defined by the second interlayer insulating layer 160. The sidewalls of the upper via grooves 210V_t may be defined by the second interlayer insulating layer 160 and the first etch stop layer 155.

[0045] In a semiconductor device according to some example embodiments, the upper wiring grooves 210t may penetrate through the lower capping layer 114. The upper wiring grooves 210t expose portions of the upper surface 113US of the lower filling layer. In this case, portions of the sidewalls of the upper via grooves 210V_t may be defined by the lower capping layer 114. The bottom surface of the upper wiring grooves 210t may be defined by the upper surface 113US of the lower filling layer.

[0046] The second interlayer insulating layer 160 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

[0047] The first etch stop layer 155 may include a material having etch selectivity relative to the second interlayer insulating layer 160. The first etch stop layer 155 may include, for example, at least one of the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxynitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), or a combination thereof.

[0048] The first etch stop layer 155 has been shown as a single layer, but this is only for ease of explanation and the present disclosure is not limited thereto. In some embodiments, different from that shown in the drawings, the first etch stop layer 155 may include a plurality of insulating layers sequentially stacked on the first interlayer insulating layer 150.

[0049] The upper wiring structure 210 may be disposed in the upper wiring trench 210t. The upper wiring trench 210t may be filled with the upper wiring structure 210. The upper wiring structure 210 may be disposed in the second interlayer insulating layer 160.

[0050] The upper wiring structure 210 is disposed on the lower wiring structure 110. The upper wiring structure 210 is electrically connected to the lower wiring structure 110. The upper wiring structure 210 is in contact with the lower wiring structure 110. Being described as "contacting other elements or layers" or "in contact with other elements or layers" may refer to direct physical contact without intervening elements or layers therebetween.

[0051] The upper wiring structure 210 includes an upper wiring line 210L and an upper via 210V. The upper via 210V electrically connects the upper wiring line 210L and the lower wiring structure 110. The upper via 210V is in contact with the lower wiring structure 110.

[0052] In a semiconductor device according to some exemplary embodiments, the upper surface 113US of the lower fill layer may include a first region 113US_R1 in contact with the upper wiring structure 210 and a second region 113US_R2 not in contact with the upper wiring structure 210. The upper via 210V is in contact with the first region 113US_R1 of the upper surface of the lower fill layer.

[0053] For example, the lower capping layer 114 is disposed on the second region 113US_R2 of the upper surface of the lower filling layer. The lower capping layer 114 covers the second region 113US_R2 of the upper surface of the lower filling layer. The lower capping layer 114 is not disposed on the first region 113US_R1 of the upper surface of the lower filling layer. The lower capping layer 114 does not cover the first region 113US_R1 of the upper surface of the lower filling layer.

[0054] When a portion of the lower capping layer 114 is etched to expose the first region 113US_R1 of the upper surface of the lower filling layer, the lower filling layer 113 is not removed by the etching process. The first region 113US_R1 of the upper surface of the lower filling layer is coplanar with the second region 113US_R2 of the upper surface of the lower filling layer.

[0055] The upper via trench 210V_t and the upper wiring line trench 210L_t are filled with the upper wiring structure 210. The upper wiring line 210L is disposed in the upper wiring line trench 210L_t. The upper via 210V is disposed in the upper via trench 210V_t.

[0056] The upper wiring line 210L is disposed at a second metal level different from the first metal level. The upper wiring line 210L is disposed at a second metal level higher than the first metal level.

[0057] The upper wiring structure 210 includes an upper barrier layer 211, an upper liner layer 212, and an upper filling layer 213. Although not shown, the upper wiring structure 210 may include an upper capping layer such as or similar to the lower capping layer 114.

[0058] The upper barrier layer 211 extends along the sidewalls of the upper wiring trench 210t. The upper barrier layer 211 does not extend along the bottom surface of the upper wiring trench 210t. The upper barrier layer 211 does not cover all of the lower wiring structure 110 exposed by the upper via trench 210V_t.

[0059] The upper barrier layer 211 extends along the sidewalls and the bottom surface of the upper wiring line trench 210L_t and the sidewalls of the upper via trench 210V_t. The upper barrier layer 211 extends to the lower wiring structure 110 that defines the bottom surface of the upper wiring trench 210t.

[0060] In a semiconductor device according to some example embodiments, an upper barrier layer 211 extends to an upper surface 113US of a lower fill layer. The upper barrier layer 211 contacts the upper surface 113US of the lower fill layer. Additionally, the upper barrier layer 211 contacts a lower capping layer 114 defining sidewalls of an upper via trench 210V_t.

[0061] The upper barrier layer 211 may include a conductive material, for example, a metal nitride. The upper barrier layer 211 may include at least one of, for example, tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), zirconium nitride (ZrN), vanadium nitride (VN), or niobium nitride (NbN). In the following description, it will be described that the upper barrier layer 211 is formed of tantalum nitride (TaN).

[0062] An upper liner layer 212 is disposed on the upper barrier layer 211. The upper liner layer 212 is disposed between the upper barrier layer 211 and an upper fill layer 213. For example, the upper liner layer 212 may contact the upper barrier layer 211.

[0063] The upper liner layer 212 extends along sidewalls and a bottom surface of an upper wiring trench 210t. The upper liner layer 212 extends along sidewalls and a bottom surface of an upper wiring line trench 210L_t and sidewalls and a bottom surface of an upper via trench 210V_t.

[0064] The upper liner layer 212 contacts a lower wiring structure 110. The upper liner layer 212 contacts the upper surface 113US of the lower fill layer. The upper liner layer 212 extends along the upper surface 113US of the lower fill layer.

[0065] The upper liner layer 212 does not contact the lower capping layer 114. More specifically, the upper liner layer 212 does not contact the lower capping layer 114 defining sidewalls of the upper via trench 210V_t.

[0066] The upper liner layer 212 includes a sidewall portion 212S and a bottom portion 212B.

[0067] The sidewall portion 212S of the upper liner layer extends along sidewalls of the upper wiring trench 210t. The sidewall portion 212S of the upper liner layer extends along sidewalls and a bottom surface of the upper wiring line trench 210L_t and sidewalls of the upper via trench 210V_t.

[0068] The sidewall portion 212S of the upper liner extends to the lower wiring structure 110. The sidewall portion 212S of the upper liner contacts the upper surface 113US of the lower fill layer that defines the bottom surface of the upper via trench 210V_t.

[0069] The bottom portion 212B of the upper liner extends along the bottom surface of the upper wiring trench 210t. The bottom portion 212B of the upper liner extends along the bottom surface of the upper via trench 210V_t.

[0070] The bottom portion 212B of the upper liner contacts the lower wiring structure 110. In a semiconductor device according to some example embodiments, the bottom portion 212B of the upper liner contacts the upper surface 113US of the lower fill layer that defines the bottom surface of the upper wiring trench 210t.

[0071] The upper liner 212 includes ruthenium (Ru) and cobalt (Co). For example, the upper liner 212 may include an upper ruthenium-cobalt (RuCo) alloy layer 212_AF and an upper cobalt layer 212_BF. Here, the "ruthenium-cobalt alloy layer" may be a layer formed purely of ruthenium and pure cobalt (and may include impurities introduced in the process of forming the alloy layer).

[0072] In a semiconductor device according to some example embodiments, the upper ruthenium-cobalt alloy layer 212_AF extends along a portion of the sidewall of the upper wiring trench 210t.

[0073] The upper ruthenium-cobalt alloy layer 212_AF extends along the sidewall and bottom surface of the upper wiring line trench 210L_t. The upper ruthenium-cobalt alloy layer 212_AF extends along a portion of the sidewall of the upper via trench 210V_t. The upper ruthenium-cobalt alloy layer 212_AF does not extend to the upper surface 113US of the lower fill layer. The upper ruthenium-cobalt alloy layer 212_AF does not contact the lower fill layer 113.

[0074] For example, the upper ruthenium-cobalt alloy layer 212_AF contacts the upper barrier layer 211. The upper ruthenium-cobalt alloy layer 212_AF contacts the upper fill layer 213.

[0075] The upper cobalt layer 212_BF extends along the bottom surface of the upper wiring trench 210t. In a semiconductor device according to some example embodiments, the upper cobalt layer 212_BF contacts the upper barrier layer 211. The upper cobalt layer 212_BF contacts the lower fill layer 113.

[0076] The sidewall portion 212S of the upper liner contains ruthenium (Ru) and cobalt (Co). The bottom portion 212B of the upper liner is formed of cobalt (Co). For example, the composition of the sidewall portion 212S of the upper liner is different from the composition of the bottom portion 212B of the upper liner.

[0077] The bottom portion 212B of the upper liner is formed as part of the upper cobalt layer 212_BF. The sidewall portion 212S of the upper liner contains the remaining portion of the upper cobalt layer 212_BF and the upper cobalt alloy layer 212_AF.

[0078] A portion of the sidewall portion 212S of the upper liner is formed of ruthenium (Ru) and cobalt (Co). The sidewall portion 212S of the upper liner contains a first portion 212S_P1 formed of ruthenium (Ru) and cobalt (Co) and a second portion 212S_P2 formed of cobalt (Co). The first portion 212S_P1 of the sidewall portion of the upper liner is disposed on the second portion 212S_P2 of the sidewall portion of the upper liner. The second portion 212S_P2 of the sidewall portion of the upper liner is in contact with the lower wiring structure 110.

[0079] The first portion 212S_P1 of the sidewall portion of the upper liner contains the upper ruthenium cobalt alloy layer 212_AF. For example, the first portion 212S_P1 of the sidewall portion of the upper liner is formed of the upper ruthenium cobalt alloy layer 212_AF. The second portion 212S_P2 of the sidewall portion of the upper liner is formed of the upper cobalt layer 212_BF.

[0080] The upper filling layer 213 is disposed on the upper liner 212. The upper filling layer 213 may be in contact with the upper liner 212. The remaining portion of the upper wiring groove 210t may be filled with the upper filling layer 213.

[0081] FIG. 6 is a view showing a semiconductor device according to some example embodiments. FIG. 7 is a view showing a semiconductor device according to some example embodiments. FIG. 8 is a view showing a semiconductor device according to some example embodiments. FIG. 9 is a view showing a semiconductor device according to some example embodiments. For ease of explanation, the points different from those described with reference to FIGS. 1 to 5 will be mainly described. For reference, FIGS. 6 to 9 are enlarged views of a portion P of FIG. 2.

[0082] Referring to FIG. 6, in a semiconductor device according to some example embodiments, the upper cobalt layer 212_BF may be disposed along the boundary between the upper ruthenium cobalt alloy layer 212_AF and the upper filling layer 213.

[0083] The portion of the upper cobalt layer 212_BF may extend along the sidewalls of the upper via trench 210V_t and the sidewalls and bottom surface of the upper wiring line trench 210L_t.

[0084] The upper ruthenium-cobalt alloy layer 212_AF may not contact the upper filling layer 213. That is, the upper ruthenium-cobalt alloy layer 212_AF may be separated from the upper filling layer 213 by the portion of the upper cobalt layer 212_BF extending between the upper ruthenium-cobalt alloy layer 212_AF and the upper filling layer 213.

[0085] Referring to FIGS. 7 and 8, in a semiconductor device according to some example embodiments, the sidewall portion 212S of the upper liner may further include an upper ruthenium layer 212_CF extending along the sidewalls of the upper wiring trench 210t.

[0086] The upper ruthenium layer 212_CF extends along the sidewalls and bottom surface of the upper wiring line trench 210L_t. The upper ruthenium layer 212_CF may extend along a portion of the sidewalls of the upper via trench 210V_t. The upper ruthenium layer 212_CF may contact the upper barrier layer 211.

[0087] The upper ruthenium layer 212_CF may not extend to the upper surface 113US of the lower filling layer. The upper ruthenium layer 212_CF may not contact the lower filling layer 113.

[0088] The upper ruthenium-cobalt alloy layer 212_AF is disposed between the upper ruthenium layer 212_CF and the upper filling layer 213. The upper ruthenium layer 212_CF is disposed between the upper ruthenium-cobalt alloy layer 212_AF and the upper barrier layer 211.

[0089] Here, the "ruthenium layer" may be a layer formed purely of ruthenium (and may include impurities introduced during the process of forming the ruthenium layer).

[0090] In FIG. 7, the upper ruthenium-cobalt alloy layer 212_AF may contact the upper filling layer 213.

[0091] In FIG. 8, the upper ruthenium-cobalt alloy layer 212_AF may not contact the upper filling layer 213. The portion of the upper cobalt layer 212_BF may be disposed along the boundary between the upper ruthenium-cobalt alloy layer 212_AF and the upper filling layer 213.

[0092] Referring to FIG. 9, in a semiconductor device according to some exemplary embodiments, the entire sidewall portion 212S of the upper liner is formed of ruthenium (Ru) and cobalt (Co).

[0093] The upper ruthenium-cobalt alloy layer 212_AF extends to the upper surface 113US of the lower fill layer. The upper ruthenium-cobalt alloy layer 212_AF contacts the lower fill layer 113. The upper cobalt layer 212_BF is not inserted between the upper ruthenium-cobalt alloy layer 212_AF and the lower fill layer 113.

[0094] The sidewall portion 212S of the upper liner formed of ruthenium (Ru) and cobalt (Co) contacts the lower wiring structure 110.

[0095] In FIGS. 7 and 8, when the upper ruthenium-cobalt alloy layer 212_AF extends to the upper surface 113US of the lower fill layer, the upper ruthenium layer 212_CF may extend to the upper surface 113US of the lower fill layer. That is, the upper ruthenium layer 212_CF may contact the lower fill layer 113.

[0096] FIG. 10 is a view showing a semiconductor device according to some exemplary embodiments. For ease of explanation, points different from those described with reference to FIGS. 1 to 5 will be mainly described. For reference, FIG. 10 is an enlarged view of a portion Q of FIG. 3.

[0097] Referring to FIG. 10, in a semiconductor device according to some exemplary embodiments, the upper barrier layer 211 may include a pit region 211_DP.

[0098] The pit region 211_DP may be a portion protruding between the lower surface of the first etch stop layer 155 facing each other and the upper surface of the lower fill layer 113.

[0099] In the manufacturing process, a portion of the lower capping layer 114 may be removed by wet etching to expose the lower fill layer 113. During the wet etching, the lower capping layer 114 may be undercut. The undercut region of the lower capping layer 114 may be filled with the upper barrier layer 211.

[0100] FIGS. 11 and 12 are views showing a semiconductor device according to some exemplary embodiments. For ease of explanation, points different from those described with reference to FIGS. 1 to 5 will be mainly described.

[0101] Referring to FIGS. 4, 11, and 12, in a semiconductor device according to some example embodiments, an upper liner 212 contacts a lower capping layer 114. A bottom portion 212B of the upper liner contacts the lower capping layer 114.

[0102] An upper wiring trench 210t does not penetrate the lower capping layer 114. The upper wiring trench 210t does not expose an upper surface 113US of the lower filling layer.

[0103] Sidewalls of an upper via trench 210V_t are not defined by the lower capping layer 114. A bottom surface of the upper wiring trench 210t may be defined by the lower capping layer 114.

[0104] The lower capping layer 114 may include a lower surface facing the lower filling layer 113 and an upper surface facing the first etch stop layer 155. An upper barrier layer 211 contacts the upper surface of the lower capping layer 114.

[0105] FIGS. 13 and 14 are views showing a semiconductor device according to some example embodiments. For ease of explanation, points different from those described with reference to FIGS. 1 to 5 will be mainly described.

[0106] Referring to FIGS. 13 and 14, in a semiconductor device according to some example embodiments, a lower liner 112 may include cobalt (Co) and ruthenium (Ru).

[0107] The lower liner 112 may include a lower ruthenium-cobalt alloy layer 112_AF. As an example, all of the lower liner 112 may be formed of the lower ruthenium-cobalt alloy layer 112_AF. As another example, the lower liner 112 may include a ruthenium layer as shown in FIGS. 7 and 8. As yet another example, the lower liner 112 may include a cobalt layer disposed along a boundary between the lower ruthenium-cobalt alloy layer 112_AF and the lower filling layer 113.

[0108] FIG. 15 is a view showing a semiconductor device according to some example embodiments. For ease of explanation, points different from those described with reference to FIGS. 1 to 5 will be mainly described.

[0109] Referring to FIG. 15, in a semiconductor device according to some example embodiments, as the lower wiring structure 110 moves away from an upper surface of the first interlayer insulating layer 150, a width of the lower wiring structure 110 in a second direction D2 may increase.

[0110] The lower wiring structure 110 can be formed using, for example, a subtractive process. In other words, after forming the conductive layer that serves as the base material of the lower wiring structure 110, a mask pattern is formed on the conductive layer. By using the mask pattern as a mask, the conductive layer is etched. Thus, the lower wiring structure 110 can be formed.

[0111] The lower wiring structure 110 is shown as including a lower barrier layer 111 and a lower filling layer 113, but is not limited thereto. As an example, different from what is shown, a hard mask pattern can be disposed along the upper surface of the lower filling layer 113. As another example, different from what is shown, a passivation layer can be disposed along the sidewalls of the lower filling layer 113. As yet another example, the lower barrier layer 111 can be omitted. As yet another example, the lower barrier layer 111 can include at least one of, for example, a metal nitride, a metal, a metal carbide, or a two-dimensional (2D) material. The 2D material can be a metal material and / or a semiconductor material. The 2D material can include two-dimensional allotropes or two-dimensional compounds, and can include at least one of, for example, graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), or tungsten disulfide (WS2), but is not limited thereto. That is, since the above 2D materials are only listed as an example, the 2D materials that can be included in the semiconductor device of the present disclosure are not limited by the above materials.

[0112] FIG. 16 is a view showing a semiconductor device according to some example embodiments. For ease of explanation, points different from those described with reference to FIGS. 1 to 5 will be mainly described.

[0113] For reference, FIG. 16 illustratively shows a semiconductor device cut along the first gate electrode GE.

[0114] In FIG. 16, the fin pattern AF is shown extending in a first direction D1 and the first gate electrode GE is shown extending in a second direction D2, but the present disclosure is not limited thereto.

[0115] Referring to FIG. 16, a semiconductor device according to some example embodiments can include a transistor TR disposed between a substrate 10 and a lower wiring structure 110.

[0116] The substrate 10 can be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 10 can include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0117] The transistor TR may include a fin pattern AF, a first gate electrode GE on the fin pattern AF, and a first gate insulating layer GI between the fin pattern AF and the first gate electrode GE.

[0118] Although not shown, the transistor TR may include source / drain patterns disposed on both sides of the first gate electrode GE.

[0119] The fin pattern AF may protrude from the substrate 10. The fin pattern AF may extend to elongate in the first direction D1. The fin pattern AF may be part of the substrate 10 and may include an epitaxial layer grown from the substrate 10. The fin pattern AF may include silicon or germanium which is an elemental semiconductor material. Additionally, the fin pattern AF may include a compound semiconductor, such as a group-IV-IV compound semiconductor or a group-III-V compound semiconductor.

[0120] The group-IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including two or more than two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping carbon (C), silicon (Si), germanium (Ge), and tin (Sn) with a group-IV element. The group-III-V compound semiconductor may be, for example, one of binary compounds, ternary compounds, or quaternary compounds formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group-III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as group-V elements.

[0121] The field insulating layer 15 may be formed on the substrate 10. The field insulating layer 15 may be formed on a part of the sidewall of the fin pattern AF. The fin pattern AF protrudes above the upper surface of the field insulating layer 15. The field insulating layer 15 may include, for example, an oxide film, a nitride film, a nitroxide film, or a combination thereof.

[0122] The first gate electrode GE may be disposed on the fin pattern AF. The first gate electrode GE may extend in the second direction D2. The first gate electrode GE may cross or intersect the fin pattern AF.

[0123] The first gate electrode GE may include, for example, at least one of the following: a metal, a conductive metal nitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal nitroxide, or a conductive metal oxide.

[0124] The first gate insulating layer GI can be disposed between the first gate electrode GE and the fin pattern AF and between the first gate electrode GE and the field insulating layer 15. The first gate insulating layer GI can include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material can include, for example, at least one of boron nitride, metal oxide, or metal oxysilicon.

[0125] A semiconductor device according to some example embodiments can include a negative capacitance (NC) FET using a negative capacitor. For example, the first gate insulating layer GI can include a ferroelectric material layer having ferroelectric characteristics and a paraelectric material layer having paraelectric characteristics.

[0126] The ferroelectric material layer can have a negative capacitance, and the paraelectric material layer can have a positive capacitance. For example, when two or more capacitors are connected in series with each other and the capacitance of each capacitor has a positive value, the total capacitance decreases compared to the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series with each other has a negative value, the total capacitance can have a positive value and can be greater than the absolute value of each individual capacitance.

[0127] When the ferroelectric material layer having a negative capacitance and the paraelectric material layer having a positive capacitance are connected in series with each other, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series with each other can increase. Using the fact that the total capacitance value increases, a transistor including the ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0128] The ferroelectric material layer can have ferroelectric characteristics. The ferroelectric material layer can include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanate, barium titanate, or lead zirconate titanate. Here, as an example, hafnium zirconium oxide can be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide can be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0129] The ferroelectric material layer can further include a doped dopant. For example, the dopant can include at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The type of dopant included in the ferroelectric material layer can vary depending on the type of ferroelectric material included in the ferroelectric material layer.

[0130] When the ferroelectric material layer contains hafnium oxide, the dopant contained in the ferroelectric material layer may include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), or yttrium (Y).

[0131] When the dopant is aluminum (Al), the ferroelectric material layer may contain 3 atomic % to 8 atomic % (atomic %; at%) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0132] When the dopant is silicon (Si), the ferroelectric material layer may contain 2 atomic % to 10 atomic % of silicon. When the dopant is yttrium (Y), the ferroelectric material layer may contain 2 atomic % to 10 atomic % of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may contain 1 atomic % to 7 atomic % of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may contain 50 atomic % to 80 atomic % of zirconium.

[0133] The paraelectric material layer may have paraelectric characteristics. The paraelectric material layer may include at least one of, for example, silicon oxide or metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material layer may include at least one of, for example, hafnium oxide, zirconium oxide, or aluminum oxide, but is not limited thereto.

[0134] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric characteristics, but the paraelectric material layer may not have ferroelectric characteristics. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of hafnium oxide contained in the ferroelectric material layer is different from the crystal structure of hafnium oxide contained in the paraelectric material layer.

[0135] The ferroelectric material layer may have a thickness having ferroelectric characteristics. The thickness of the ferroelectric material layer may be, for example, 0.5 nm to 10 nm, but is not limited thereto. Since the critical thickness indicating ferroelectric characteristics may vary for each ferroelectric material, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0136] As an example, the first gate insulating layer GI may include a ferroelectric material layer. As another example, the first gate insulating layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The first gate insulating layer GI may have a stacked layer structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0137] The gate capping pattern GE_CAP may be disposed on the first gate electrode GE. The conductive lower wiring 110 and the conductive lower wiring 120 may be disposed on the first gate electrode GE. Although the conductive lower wiring 110 and the conductive lower wiring 120 are shown not connected to the first gate electrode GE, the present disclosure is not limited thereto. One of the conductive lower wiring 110 and the conductive lower wiring 120 may be connected to the first gate electrode GE.

[0138] FIG. 17 is a view showing a semiconductor device according to some example embodiments. For ease of explanation, parts different from those described with reference to FIG. 16 will be mainly described.

[0139] Referring to FIG. 17, in a semiconductor device according to some example embodiments, the transistor TR may include a nanosheet NS, a first gate electrode GE surrounding the nanosheet NS, and a first gate insulating layer GI between the nanosheet NS and the first gate electrode GE.

[0140] The nanosheet NS may be disposed on the lower fin pattern BAF. The nanosheet NS may be spaced apart from the lower fin pattern BAF in the third direction D3. The transistor TR is shown to include three nanosheets NS spaced apart from each other in the third direction D3, but is not limited thereto. The number of nanosheets NS disposed on the lower fin pattern BAF in the third direction D3 may be greater than three or less than three.

[0141] Each of the lower fin pattern BAF and the nanosheet NS may include, for example, silicon or germanium as an elemental semiconductor material. Each of the lower fin pattern BAF and the nanosheet NS may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The lower fin pattern BAF and the nanosheet NS may include the same material or different materials.

[0142] FIGS. 18 to 20 are views showing a semiconductor device according to some example embodiments. For reference, FIG. 18 is a view showing a semiconductor device according to some example embodiments. FIG. 19 is a cross-sectional view taken along line C-C and line D-D of FIG. 18. FIG. 20 is a cross-sectional view taken along line E-E of FIG. 18.

[0143] Referring to FIGS. 18 to 20, the logic unit LC may be disposed on the substrate 10. The logic unit LC may refer to a logic device that performs a specific function (e.g., an inverter, a flip-flop, etc.). The logic unit LC may include vertical FETs constituting the logic device and wirings connecting the vertical FETs to each other.

[0144] The logic unit LC on the substrate 10 may include a first active region RX1 and a second active region RX2. For example, the first active region RX1 may be a PMOSFET region, and the second active region RX2 may be an NMOSFET region. The first active region RX1 and the second active region RX2 may be defined by a trench T_CH formed in the upper portion of the substrate 10. The first active region RX1 and the second active region RX2 may be spaced apart from each other in a first direction D1.

[0145] A first lower epitaxial pattern SPO1 may be disposed on the first active region RX1, and a second lower epitaxial pattern SPO2 may be disposed on the second active region RX2. In a plan view, the first lower epitaxial pattern SPO1 may overlap with the first active region RX1, and the second lower epitaxial pattern SPO2 may overlap with the second active region RX2. The first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 may be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SPO1 may be disposed in a first recessed region RS1 of the substrate 10, and the second lower epitaxial pattern SPO2 may be disposed in a second recessed region RS2 of the substrate 10.

[0146] A first active pattern AP1 may be disposed on the first active region RX1, and a second active pattern AP2 may be disposed on the second active region RX2. Each of the first active pattern AP1 and the second active AP2 may have a fin shape protruding vertically (e.g., in the direction D3). In a plan view, each of the first active pattern AP1 and the second active pattern AP2 may have a rod shape extending in the first direction D1. The first active pattern AP1 may be arranged along a second direction D2, and the second active pattern AP2 may be arranged along the second direction D2.

[0147] Each of the first active patterns AP1 may include a first channel pattern CHP1 protruding vertically from the first lower epitaxial pattern SPO1 and a first upper epitaxial pattern DOP1 on the first channel pattern CHP1. Each of the second active patterns AP2 may include a second channel pattern CHP2 protruding vertically from the second lower epitaxial pattern SPO2 and a second upper epitaxial pattern DOP2 on the second channel pattern CHP2.

[0148] An element isolation layer ST may be disposed on the substrate 10 to fill the trench T_CH. The element isolation layer ST may cover the upper surfaces of the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2. The first active pattern AP1 and the second active pattern AP2 protrude vertically above the element isolation layer ST.

[0149] A plurality of second gate electrodes 420 extending parallel to each other in a first direction D1 may be disposed on the element isolation layer ST. The second gate electrodes 420 may be arranged along a second direction D2. The second gate electrodes 420 may surround a first channel pattern CHP1 of the first active pattern AP1 and may surround a second channel pattern CHP2 of the second active pattern AP2. For example, the first channel pattern CHP1 of the first active pattern AP1 may have first sidewalls SW1 to fourth sidewalls SW4. The first sidewall SW1 and the second sidewall SW2 may face each other or be opposite to each other in the second direction D2, and the third sidewall SW3 and the fourth sidewall SW4 may face each other or be opposite to each other in the first direction D1. The second gate electrodes 420 may be disposed on the first sidewalls SW1 to fourth sidewalls SW4. In other words, the second gate electrodes 420 may surround the first sidewalls SW1 to fourth sidewalls SW4.

[0150] A second gate insulating layer 430 may be inserted between the second gate electrodes 420 and each of the first channel pattern CHP1 and the second channel pattern CHP2. The second gate insulating layer 430 may cover a bottom surface and an inner sidewall of the second gate electrodes 420. For example, the second gate insulating layer 430 may directly cover the first sidewalls SW1 to fourth sidewalls SW4 of the first active pattern AP1.

[0151] A first upper epitaxial pattern DOP1 and a second upper epitaxial pattern DOP2 may protrude vertically above the second gate electrodes 420. An upper surface of the second gate electrodes 420 may be lower than a bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the first active pattern AP1 and the second active pattern AP2 may have a structure protruding vertically from the substrate 10 and penetrating the second gate electrodes 420.

[0152] A semiconductor device according to some example embodiments may include a vertical transistor in which carriers move in a third direction D3. For example, when a voltage is applied to the second gate electrode 420 to "turn on" the transistor, carriers may move from the lower epitaxial pattern SOP1 and the lower epitaxial pattern SOP2 to the upper epitaxial pattern DOP1 and the upper epitaxial pattern DOP2 via the channel pattern CHP1 and the channel pattern CHP2. In a semiconductor device according to some example embodiments, the second gate electrode 420 may completely surround the sidewalls SW1 to SW4 of the channel pattern CHP1 and the channel pattern CHP2. The transistor according to the present disclosure may be a three-dimensional field effect transistor (e.g., VFET) having a surrounded gate structure. Since the gate surrounds the channel, the semiconductor device according to some example embodiments may have excellent electrical characteristics.

[0153] The spacer 440 covering the second gate electrode 420 and the first active pattern AP1 and the second active pattern AP2 may be disposed on the element isolation layer ST. The spacer 440 may include a silicon nitride layer or a silicon oxynitride layer. The spacer 440 may include a lower spacer 440LS, an upper spacer 440US, and a gate spacer 440GS between the lower spacer 440LS and the upper spacer 440US.

[0154] The lower spacer 440LS may directly cover the upper surface of the element isolation layer ST. The second gate electrode 420 may be spaced apart from the element isolation layer ST in the third direction D3 by the lower spacer 440LS. The gate spacer 440GS may cover the upper surface and the outer sidewalls of each of the second gate electrodes 420. The upper spacer 440US may cover the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer 440US may not cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2, but may expose the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0155] The first portion 190BP of the lower interlayer insulating layer may be disposed on the spacer 440. The upper surface of the first portion 190BP of the lower interlayer insulating layer may be substantially coplanar with the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. The second portion 190UP of the lower interlayer insulating layer, the first interlayer insulating layer 150, and the second interlayer insulating layer 160 may be sequentially stacked on the first portion 190BP of the lower interlayer insulating layer. The first portion 190BP and the second portion 190UP of the lower interlayer insulating layer may be included in the lower interlayer insulating layer 190. The second portion 190UP of the lower interlayer insulating layer may cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0156] At least one first source / drain contact 470 passing through the second portion 190UP of the lower interlayer insulating layer and connected to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 may be provided. At least one second source / drain contact 570 passing sequentially through the lower interlayer insulating layer 190, the lower spacer 440LS, and the device isolation layer ST and connected to the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 may be provided. A gate contact 480 passing sequentially through the second portion 190UP of the lower interlayer insulating layer, the first portion 190BP of the lower interlayer insulating layer, and the gate spacer 440GS and connected to the second gate electrode 420 may be provided.

[0157] The second etch stop layer 156 may be additionally disposed between the second portion 190UP of the lower interlayer insulating layer and the first interlayer insulating layer 150. The first etch stop layer 155 may be disposed between the first interlayer insulating layer 150 and the second interlayer insulating layer 160.

[0158] The lower wiring structure 110 may be disposed in the first interlayer insulating layer 150. The lower wiring structure 110 may include a lower via 110V and a lower wiring line 110L. The descriptions of the lower via 110V and the lower wiring line 110L may be similar to those of the upper via 210V and the upper wiring line 210L. However, the layer structure of the lower wiring structure 110 may be different from or the same as the layer structure of the upper wiring structure 210.

[0159] The lower wiring structure 110 may be connected to the first source / drain contact 470, the second source / drain contact 570, and the gate contact 480. The upper wiring structure 210 may be disposed in the second interlayer insulating layer 160.

[0160] In some embodiments, different from that shown, for example, an additional wiring structure similar to the upper wiring structure 210 may be further disposed between the first source / drain contact 470 and the lower wiring structure 110.

[0161] The detailed description of the upper wiring structure 210 may be substantially the same as the detailed description described above with reference to FIGS. 1 to 15.

[0162] FIGS. 21 to 29 are intermediate step views showing a method of manufacturing a semiconductor device according to some example embodiments.

[0163] For reference, FIGS. 21, 23 to 25, and 27 to 29 are cross-sectional views taken along line A-A of FIG. 1, respectively. FIGS. 22 and 26 are cross-sectional views taken along line B-B of FIG. 1.

[0164] Referring to FIGS. 21 and 22, the lower wiring structure 110 is formed in the first interlayer insulating layer 150.

[0165] Lower wiring grooves 110t are formed in the first interlayer insulating layer 150. The lower wiring structure 110 is formed in the lower wiring grooves 110t. The lower wiring structure 110 may include a lower barrier layer 111, a lower liner layer 112, a lower filling layer 113, and a lower capping layer 114.

[0166] Subsequently, a first etch stop layer 155 may be formed on the first interlayer insulating layer 150 and the lower wiring structure 110.

[0167] A second interlayer insulating layer 160 may be disposed on the first etch stop layer 155. The second interlayer insulating layer 160 may include upper wiring grooves 210t. The upper wiring grooves 210t include upper via grooves 210V_t and upper wiring line grooves 210L_t.

[0168] The upper wiring grooves 210t may penetrate the first etch stop layer 155. The upper wiring grooves 210t may pass through the lower capping layer 114. In some embodiments, different from that shown, the upper wiring grooves 210t may not pass through the lower capping layer 114.

[0169] The upper wiring grooves 210t may expose a first region 110_R1 of the lower wiring structure. The upper wiring grooves 210t may expose a portion of the upper surface of the lower filling layer 113.

[0170] Referring to FIG. 23, a first selective inhibition layer 170 is formed on a first region 110_R1 of the lower wiring structure exposed by the upper wiring groove 210t.

[0171] The first selective inhibition layer 170 includes an organic material. The first selective inhibition layer 170 can selectively prevent a conductive material from depositing on the surface on which the first selective inhibition layer 170 is formed. For example, the conductive material A does not deposit on the surface on which the first selective inhibition layer 170 is formed. On the other hand, the conductive material B can deposit on the surface on which the first selective inhibition layer 170 is formed.

[0172] The first selective inhibition layer 170 can be formed on a conductive material. For example, the first selective inhibition layer 170 can be formed on a metal or a metal alloy. The first selective inhibition layer 170 is not formed on an insulating material.

[0173] Referring to FIG. 24, in response to or in a state of forming the first selective inhibition layer 170, a pre-lower barrier layer 211P is formed along the sidewalls of the upper wiring groove 210t. The pre-lower barrier layer 211P is formed along the upper surface of the second interlayer insulating layer 160.

[0174] The pre-lower barrier layer 211P is not formed along the bottom surface of the upper wiring groove 210t in which the first selective inhibition layer 170 is formed.

[0175] However, the pre-lower barrier layer 211P can be formed on all of the sidewalls of the upper wiring groove 210t. The first selective inhibition layer 170 covers a part of the sidewalls of the upper wiring groove 210t, but the pre-lower barrier layer 211P can also be formed on the sidewalls of the upper wiring groove 210t covered by the first selective inhibition layer 170. The lower barrier layer 211P contacts the lower wiring structure 110.

[0176] The pre-lower barrier layer 211P is formed using, for example, atomic layer deposition (ALD). The pre-lower barrier layer 211P can include a metal nitride, such as tantalum nitride (TaN).

[0177] Referring to FIGS. 25 and 26, the second region 110_R2 of the lower wiring structure can be exposed by removing the first selective inhibition layer 170.

[0178] Since the lower pre-barrier layer 211P covers a part of the first region 110_R1 of the lower wiring structure, the second region 110_R2 of the lower wiring structure can be smaller than the first region 110_R1 of the lower wiring structure.

[0179] The first selective inhibition layer 170 can be removed by, for example, plasma treatment, but is not limited thereto.

[0180] Referring to FIG. 27, the second selective inhibition layer 175 is formed on the exposed second region 110_R2 of the lower wiring structure.

[0181] The second selective inhibition layer 175 includes an organic material. The second selective inhibition layer 175 can selectively prevent conductive material from depositing on the surface where the second selective inhibition layer 175 is formed.

[0182] The second selective inhibition layer 175 can be formed on a metal or metal alloy. The second selective inhibition layer 175 is not formed on an insulating material. Additionally, the second selective inhibition layer 175 is not formed on a metal nitride having a dense structure.

[0183] Referring to FIG. 28, in response to forming the second selective inhibition layer 175 or in a state where the second selective inhibition layer 175 is formed, a first pre-upper liner 212P_A is formed. The first pre-upper liner 212P_A is formed on the lower pre-barrier layer 211P.

[0184] The first pre-upper liner 212P_A is formed along the sidewalls of the upper wiring trench 210t. The first pre-upper liner 212P_A is formed along the upper surface of the second interlayer insulating layer 160.

[0185] The first pre-upper liner 212P_A is not formed along the bottom surface of the upper wiring trench 210t where the second selective inhibition layer 175 is formed. Additionally, the first pre-upper liner 212P_A may not be formed on the sidewalls of the upper wiring trench 210t covered by the second selective inhibition layer 175. In some embodiments, different from what is shown, the first pre-upper liner 212P_A may also be formed on the sidewalls of the upper wiring trench 210t covered by the second selective inhibition layer 175.

[0186] The first pre-upper liner 212P_A can be, for example, a ruthenium (Ru) layer.

[0187] Here, in a state where the second selective inhibition layer 175 is formed, a second pre-upper liner 212P_B is formed. The second pre-upper liner 212P_B is formed on the first pre-upper liner 212P_A.

[0188] The second pre-upper liner 212P_B is formed along the sidewalls and bottom surface of the upper wiring groove 210t. The second pre-upper liner 212P_B is formed along the upper surface of the second interlayer insulating layer 160.

[0189] The second pre-upper liner 212P_B is formed along the bottom surface of the upper wiring groove 210t in which the second selective inhibition layer 175 is formed.

[0190] The second pre-upper liner 212P_B can be a cobalt (Co) layer.

[0191] In a state where the second selective inhibition layer 175 is formed, the pre-upper liner 212P is formed along the sidewalls and bottom surface of the upper wiring groove 210t. The pre-upper liner 212P includes the first pre-upper liner 212P_A and the second pre-upper liner 212P_B.

[0192] Referring to FIG. 29, the second selective inhibition layer 175 is removed.

[0193] The second selective inhibition layer 175 can be removed via, for example, plasma treatment, but is not limited thereto.

[0194] Subsequently, referring to FIG. 2, a pre-upper filling layer for filling the upper wiring groove 210t can be formed on the pre-upper liner 212P.

[0195] Subsequently, the pre-lower barrier layer 211P, the pre-upper liner 212P, and the pre-upper filling layer disposed on the upper surface of the second interlayer insulating layer 160 can be removed.

[0196] For example, when the second pre-upper liner 212P_B is formed on the first pre-upper liner 212P_A, an alloy reaction between cobalt (Co) and ruthenium (Ru) can be performed.

[0197] As another example, when the second selective inhibition layer 175 is removed, an alloy reaction between cobalt (Co) and ruthenium (Ru) can be performed.

[0198] As yet another example, when the pre-upper fill layer fills the upper wiring groove 210t, an alloy reaction between cobalt (Co) and ruthenium (Ru) can occur. When maintaining the temperature at which the alloy reaction between cobalt (Co) and ruthenium (Ru) occurs, the alloy reaction between cobalt (Co) and ruthenium (Ru) can occur.

[0199] In summary, those of ordinary skill in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the principles of the present invention concept. Therefore, the disclosed embodiments of the present invention are for general and descriptive purposes only and not for restrictive purposes.

[0200] 10: Substrate 15: Field insulation layer 110, 120: Lower wiring structure 110_R1, 113US_R1: First region 110_R2, 113US_R2: Second region 110L: Lower wiring line 110t: Lower wiring groove 110V: Lower via hole 111: Lower barrier layer 112: Lower liner 112_BF: Lower cobalt layer 113: Lower fill layer 113US: Upper surface 114: Lower capping layer 150: First interlayer insulation layer 155: First etch stop layer 156: Second etch stop layer 160: Second interlayer insulation layer 170: First selective inhibition layer 175: Second selective inhibition layer 190: Lower interlayer insulation layer 190BP: First part 190UP: Second part 210: Upper wiring structure 210L: Upper wiring line 210L_t: Upper wiring line groove 210t: Upper wiring groove 210V: Upper via hole 210V_t: Upper via hole groove 211: Upper barrier layer 211_DP: Pit region 211P: Pre-lower barrier layer 212: Upper liner 212_AF: Upper ruthenium-cobalt alloy layer 212B: Bottom part 212_BF: Upper cobalt layer 212_CF: Upper ruthenium layer 212P: Pre-upper liner 212P_A: First pre-upper liner 212P_B: Second pre-upper liner 212S: Sidewall part 212S_P1: First part 212S_P2: Second part 213: Upper fill layer 420: Second gate electrode 430: Second gate insulating layer 440: Spacer 440GS: Gate spacer 440LS: Lower spacer 440US: Upper spacer 470: First source / drain contact 480: Gate contact 570: Second source / drain contact A-A, B-B, C-C, D-D, E-E: Lines AF: Fin pattern AP1: First active pattern AP2: Second active pattern BAF: Lower fin pattern CHP1: First channel pattern CHP2: Second channel pattern D1: First direction D2: Second direction D3: Third direction DOP1: First upper epitaxial pattern DOP2: Second upper epitaxial pattern GE: First gate electrode GE_CAP: Gate capping pattern GI: First gate insulating layer LC: Logic unit NS: Nanoscale sheet P, Q: Portions RS1: First recessed area RS2: Second recessed area RX1: First active area RX2: Second active area SPO1: First lower epitaxial pattern SPO2: Second lower epitaxial pattern ST: Element isolation layer SW1: First sidewall SW2: Second sidewall SW3: Third sidewall SW4: Fourth sidewall T_CH: Trench TR: Transistor

Claims

1. A semiconductor device, comprising: Lower wiring structure; An upper interlayer insulation layer is located on the lower wiring structure and includes an upper wiring trench that partially overlaps with the lower wiring structure. The upper wiring structure includes an upper liner in the upper wiring trench and an upper filler layer on the upper liner, wherein the upper liner includes a sidewall portion extending along the sidewall of the upper wiring trench and a bottom portion extending along the bottom surface of the upper wiring trench, the sidewall portion of the upper liner including cobalt (Co) and ruthenium (Ru), the bottom portion of the upper liner being formed of cobalt (Co), and wherein the upper wiring structure further includes an upper barrier layer extending along the sidewall of the upper wiring trench, the upper liner being located between the upper barrier layer and the upper filler layer, the upper barrier layer including a metal nitride, and the upper barrier layer not extending along the bottom surface of the upper wiring trench.

2. The semiconductor device of claim 1, wherein the sidewall portion of the upper liner includes a first portion formed of cobalt (Co) and ruthenium (Ru) and a second portion formed of cobalt (Co), and the first portion of the sidewall portion of the upper liner is located on the second portion of the sidewall portion of the upper liner.

3. The semiconductor device of claim 1, wherein the entire sidewall portion of the upper liner is formed of cobalt (Co) and ruthenium (Ru), and the sidewall portion of the upper liner is in contact with the lower wiring structure.

4. The semiconductor device of claim 1, wherein the sidewall portion of the upper liner comprises a ruthenium cobalt (RuCo) alloy layer.

5. The semiconductor device of claim 4, wherein the sidewall portion of the upper liner further comprises a cobalt (Co) layer extending along the boundary between the ruthenium-cobalt alloy layer and the upper filler layer.

6. The semiconductor device of claim 4, wherein the sidewall portion of the upper liner further includes a ruthenium (Ru) layer extending along the sidewall of the upper wiring trench, and the ruthenium-cobalt alloy layer is located between the ruthenium layer and the upper filler layer.

7. The semiconductor device of claim 1, wherein the bottom portion of the upper liner is in contact with the lower wiring structure and is free of ruthenium (Ru).

8. The semiconductor device of claim 1, wherein the upper barrier layer is in contact with the lower wiring structure.

9. The semiconductor device of claim 1, wherein the lower wiring structure includes a lower fill layer and a lower cover layer on the lower fill layer, and the bottom portion of the upper liner is in contact with the lower cover layer.

10. The semiconductor device of claim 1, wherein the lower wiring structure includes a lower fill layer and a lower cap layer on the lower fill layer, an upper surface of the lower fill layer includes a first region containing the lower cap layer and a second region not containing the lower cap layer, and the upper wiring structure contacts the second region of the upper surface of the lower fill layer.

11. A semiconductor device, comprising: Lower wiring structure; An upper interlayer insulation layer is located on the lower wiring structure and includes an upper wiring trench. The upper wiring trench includes an upper wiring line trench and an upper through-hole trench on the bottom surface of the upper wiring line trench, wherein the bottom surface of the upper through-hole trench is defined by the lower wiring structure. The upper wiring structure includes an upper barrier layer, an upper filling layer, and an upper liner between the upper barrier layer and the upper filling layer in the upper wiring trench. The upper barrier layer extends along the sidewalls and bottom surface of the upper wiring trench and the sidewalls of the upper via trench. The upper barrier layer comprises a metal nitride. The upper liner includes a sidewall portion and a bottom portion. The sidewall portion extends along the sidewalls and bottom surface of the upper wiring trench and along the sidewalls of the upper via trench. The bottom portion extends along the bottom surface of the upper via trench. The upper liner is in contact with the lower wiring structure. The upper liner comprises cobalt (Co) and ruthenium (Ru). The sidewall portion of the upper liner has a different composition from the bottom portion of the upper liner, and the upper barrier layer does not extend along the bottom surface of the upper via trench.

12. The semiconductor device of claim 11, wherein the sidewall portion of the upper liner comprises cobalt (Co) and ruthenium (Ru), and the bottom portion of the upper liner is formed of cobalt (Co).

13. The semiconductor device of claim 11, wherein the sidewall portion of the upper liner includes a first portion containing cobalt (Co) and ruthenium (Ru) and a second portion formed of cobalt (Co), and the second portion of the sidewall portion of the upper liner is in contact with the lower wiring structure.

14. The semiconductor device of claim 11, wherein all of the sidewall portions of the upper liner comprise cobalt (Co) and ruthenium (Ru), and the sidewall portions of the upper liner are in contact with the lower wiring structure.

15. The semiconductor device of claim 11, wherein the upper barrier layer contacts the lower wiring structure, and the bottom portion of the upper liner is free of ruthenium (Ru).

16. A semiconductor device, comprising: Lower wiring structure; An upper interlayer insulation layer is located on the lower wiring structure and includes an upper wiring trench that partially overlaps with the lower wiring structure. The upper wiring structure includes an upper liner in the upper wiring trench and an upper filler layer on the upper liner, wherein the upper liner is in contact with the lower wiring structure, the upper liner includes a sidewall portion extending along the sidewall of the upper wiring trench and a bottom portion extending along the bottom surface of the upper wiring trench, the sidewall portion of the upper liner includes a first portion containing a ruthenium-cobalt (RuCo) alloy layer and a second portion formed of cobalt (Co), the second portion of the sidewall portion of the upper liner is in contact with the lower wiring structure, the bottom portion of the upper liner is formed of cobalt (Co), wherein the upper wiring structure further includes an upper barrier layer extending along the sidewall of the upper wiring trench, the upper liner being located between the upper barrier layer and the upper filler layer, the upper barrier layer comprising a metal nitride, and the upper barrier layer not extending along the bottom surface of the upper wiring trench.

17. The semiconductor device of claim 16, wherein the upper barrier layer comprises tantalum nitride and the upper barrier layer is in contact with the lower wiring structure.

18. The semiconductor device of claim 16, further comprising a lower interlayer insulating layer having a lower wiring trench, wherein the lower wiring structure includes: The lower liner extends along the sidewall of the lower wiring trench and is formed of cobalt (Co); the lower filler layer is located in the lower wiring trench on the lower liner; and the lower cover layer is located on the upper surface of the lower filler layer, in contact with the lower liner and is formed of cobalt (Co).

19. The semiconductor device of claim 16, further comprising a lower interlayer insulating layer having a lower wiring trench, wherein the lower wiring structure includes: The lower liner extends along the sidewall of the lower wiring trench and includes cobalt (Co) and ruthenium (Ru); the lower filler layer is located in the lower wiring trench on the lower liner; and the lower cover layer is located on the upper surface of the lower filler layer, in contact with the lower liner and formed of cobalt (Co).

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