Analog-to-digital converting circuit and operation method thereof

Abstract

The present invention provides an analog-to-digital converter circuit, comprising: a first amplifier, which in a first operating cycle compares a first comparison ramp signal with a reset signal of a pixel signal output from a pixel array, and in a second operating cycle compares a second comparison ramp signal with an image signal of the pixel signal, and generates a first output signal based on the first comparison result and the second comparison result in the first and second operating cycles; and a second amplifier, which in a second zero-cycle responds to a second zero-cycle signal to charge a capacitor, stops operating the second amplifier from the end of the second zero-cycle to the beginning of the first operating cycle, and generates a second output signal based on the first output signal in the first and second operating cycles.

Description

Technical Field

[0001] Embodiments of the disclosure described herein relate to analog-to-digital converters, and more particularly to analog-to-digital conversion circuits employing self-zero cycle optimization and methods of operating the same. [Cross-Reference to Related Applications]

[0002] This application claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2021-0156902, filed on November 15, 2021, 10-2022-0049493, filed on April 21, 2022, and 10-2022-0068855, filed on June 7, 2022, with the Korean Intellectual Property Office, the disclosures of each of which are incorporated herein by reference in their entireties. Background Art

[0003] Image sensors may include charge coupled device (CCD) image sensors, complementary metal-oxide semiconductor (CMOS) image sensors (complementary metal-oxide semiconductor image sensor; CIS), and the like. A CMOS image sensor may include pixels formed of CMOS transistors, and converts light energy into an electrical signal by using a photoelectric conversion element (or device) included in each pixel. The CMOS image sensor obtains information about the captured / captured image by using the electrical signal generated by each pixel.

[0004] An analog-to-digital converter (ADC) receives an analog input voltage and converts the received analog input voltage into a digital signal. The converted digital signal may be provided to other devices. The ADC may be used in various signal processing devices. As the performance of signal processing devices has been improved, there is a need for improved resolution for analog signals these days. Accordingly, an ADC that can process many signals simultaneously or provide improved resolution for each signal is employed. However, the ADC causes an increase in power consumption. Therefore, the power consumption of the ADC may need to be reduced. Summary of the Invention

[0005] Embodiments of the present disclosure provide an analog-to-digital conversion circuit capable of reducing power consumption by adopting zero-cycle optimization, a method of operating the same, and an image sensor including the analog-to-digital conversion circuit.

[0006] According to an embodiment, a circuit includes a first amplifier and a second amplifier. The first amplifier that equalizes voltage levels of an input node and an output node in response to a first auto-zero signal during a first auto-zero cycle resets a comparison ramp signal and a pixel signal output from a pixel array during a first operation cycle, compares the comparison ramp signal with an image signal of the pixel signal during a second operation cycle after the first operation cycle, and generates a first output signal at the output node based on first and second comparison results during the first and second operation cycles. The second amplifier that charges a capacitor in response to a second auto-zero signal during a second auto-zero cycle stops operating from a time point at which the second auto-zero cycle ends to a time point at which the first operation cycle starts, and generates a second output signal based on the first output signal during the first and second operation cycles.

[0007] According to an embodiment, a method of operating an analog-to-digital conversion circuit including a first amplifier and a second amplifier includes: equalizing voltage levels of an input node and an output node of the first amplifier in response to a first auto-zero signal during a first auto-zero cycle; charging a capacitor of the second amplifier in response to a second auto-zero signal during a second auto-zero cycle; stopping operation of the second amplifier from a time point at which the second auto-zero cycle ends to a time point at which the first operation cycle starts; generating a first output signal by comparing a ramp signal with a reset signal of a pixel signal output from a pixel array during a first operation cycle and comparing the ramp signal with an image signal of the pixel signal during a second operation cycle after the first operation cycle; and generating a second output signal based on the first output signal during the first and second operation cycles.

[0008] According to an embodiment, an image sensor includes: a pixel array that converts light into an electrical signal to generate a pixel signal; a ramp signal generator that generates a ramp signal; and an analog-to-digital conversion circuit that converts the pixel signal into a digital signal. The analog-to-digital conversion circuit includes a first amplifier, a second amplifier, and a counter. The first amplifier that generates a first output signal by equalizing the voltage levels of an input node and an output node in response to a first auto-zero signal in a first auto-zero period compares a ramp signal with a reset signal of the pixel signal output from the pixel array in a first operation period, and compares the ramp signal with an image signal of the pixel signal in a second operation period. The second amplifier charges a capacitor in response to a second auto-zero signal in a second auto-zero period, generates a second output signal based on the first output signal in the first operation period and the second operation period, and stops operating the second amplifier from the time point when the second auto-zero period ends to the time point when the first operation period starts. The counter counts pulses of the second output signal and outputs a count result as a digital signal.

[0009] According to an embodiment, a circuit that charges a capacitor in response to an auto-zero signal in an auto-zero period and generates an output signal in an operation period includes: a first transistor that provides a power supply voltage to a first output node, and the output signal is output from the first output node; a second transistor that is connected to the capacitor via a bias node and turns on in response to a second auto-zero signal; a current source that is connected to the first transistor via the first output node, is connected to the capacitor and the second transistor via the bias node, and generates a power current based on a voltage level maintained by the capacitor at the bias node; and a third transistor that is connected to the first transistor, provides the power supply voltage to the first transistor, and turns off in response to a power-off signal to stop the operation of the circuit. Brief Description of the Drawings

[0010] The above and other objects and features of the present disclosure will become apparent by referring to the embodiments described in detail with reference to the accompanying drawings. FIG. 1 shows an example of the configuration of an image processing block according to an embodiment of the present disclosure. FIG. 2 shows an example of the configuration of the image sensor of FIG. 1 according to an example embodiment. FIG. 3 is a circuit diagram showing an example of one of the pixel groups of the pixel array of FIG. 2 according to an example embodiment. FIG. 4 shows an example of the configuration of the analog-to-digital conversion circuit of FIG. 2 according to an example embodiment. FIG. 5 is a circuit diagram showing an example of the first amplifier of FIG. 4 according to an example embodiment. FIG. 6 is a circuit diagram showing an example of the second amplifier of FIG. 4 according to an example embodiment. FIG. 7 is a timing diagram showing the operation of the analog-to-digital conversion circuit of FIG. 4 according to an exemplary embodiment. FIG. 8 shows another example of the configuration of the analog-to-digital conversion circuit of FIG. 2 according to an exemplary embodiment. FIG. 9 is a circuit diagram showing another example of the second amplifier of FIG. 8 according to an exemplary embodiment. FIG. 10A is a timing diagram showing an example of the operation of the analog-to-digital conversion circuit of FIG. 4 showing the operation of the feedback circuit of FIG. 9 according to an exemplary embodiment. FIG. 10B is a timing diagram showing an example of the operation of the analog-to-digital conversion circuit of FIG. 4 showing the operation of the feedback circuit of FIG. 9 according to self-zero cycle optimization and an exemplary embodiment. FIG. 11 is a circuit diagram showing another example of the second amplifier of FIG. 8 according to an exemplary embodiment. FIG. 12 is a flowchart showing a method of operating an analog-to-digital conversion circuit employing self-zero cycle optimization according to an exemplary embodiment of the present disclosure. Embodiments

[0011] Hereinafter, exemplary embodiments of the present disclosure will be described in detail and clearly to the extent that those of ordinary skill in the art can easily implement the present disclosure.

[0012] In the detailed description, components described by reference terms such as "unit", "module", "block", "~er / ~or", etc. and functional blocks shown in the drawings will be implemented by software, hardware, or a combination thereof. For example, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0013] FIG. 1 shows an example of the configuration of an image processing block 10 according to an embodiment of the present disclosure. The image processing block 10 may be implemented as part of various electronic devices, such as a smart phone, a digital camera, a laptop computer, and a desktop computer. The image processing block 10 may include a lens 12, an image sensor 14, an image signal processor (ISP) front-end block 16, and an image signal processor 18.

[0014] Light can be reflected by objects, scenes, etc. targeted for photography, and the lens 12 can receive the reflected light. The image sensor 14 can generate an electrical signal based on the light received via the lens 12. For example, the image sensor 14 can be implemented by a complementary metal oxide semiconductor (CMOS) image sensor or the like. For example, the image sensor 14 can be a multi-pixel image sensor having a dual-pixel structure or a four-cell structure.

[0015] The image sensor 14 can include a pixel array. The pixels of the pixel array can convert light into an electrical signal to generate a pixel value or a pixel signal. In addition, the image sensor 14 can include an analog-to-digital conversion (ADC) circuit for performing correlated double sampling (CDS) on the pixel value. The configuration of the image sensor 14 will be described in detail with reference to FIG. 2.

[0016] The ISP front-end block 16 can perform preprocessing on the electrical signal output from the image sensor 14 to make it suitable for processing by the image signal processor 18.

[0017] The image signal processor 18 can generate image data associated with the photographed objects and scenes by appropriately processing the electrical signal processed by the ISP front-end block 16. For this purpose, the image signal processor 18 can perform various processing operations, such as color correction, automatic white balance, gamma correction, color saturation correction, formatting, defective pixel correction, and tone correction.

[0018] One lens 12 and one image sensor 14 are shown in FIG. 1. However, in other embodiments, the image processing block 10 can include multiple lenses, multiple image sensors, and multiple ISP front-end blocks. In this case, the multiple lenses can have different fields of view. In addition, the multiple image sensors can have different functions, different performances, and / or different characteristics, and can respectively include pixel arrays with different configurations.

[0019] FIG. 2 shows an example of the configuration of the image sensor 14 of FIG. 1 according to an exemplary embodiment. The image sensor 100 can include a pixel array 110, a column driver 120, a ramp signal generator 130, a voltage buffer 140, an ADC circuit 150, a timing controller 160, and a buffer 170.

[0020] The pixel array 110 may include a plurality of pixels arranged in a matrix form, that is, arranged along columns and rows. Each of the plurality of pixels may include a photoelectric conversion element (or device). For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, a pin photodiode, or the like.

[0021] The pixel array 110 may include a plurality of pixel groups PG. Each pixel group PG may include two or more than two pixels, that is, a plurality of pixels. In this text, for convenience of description, the terms of a plurality of pixel groups PG and one pixel group PG may be used interchangeably. The plurality of pixels constituting the pixel group PG may share one floating diffusion region or a plurality of floating diffusion regions. An example in which the pixel array 110 includes pixel groups PG arranged in the form of a matrix having four columns and four rows (that is, including 4×4 pixel groups PG) is shown in FIG. 2. However, the present disclosure is not limited thereto.

[0022] The pixel group PG may include pixels of the same color. For example, the pixel group PG may include red pixels for converting light in the red spectrum into an electrical signal, green pixels for converting light in the green spectrum into an electrical signal, or blue pixels for converting light in the blue spectrum into an electrical signal. For example, the pixels constituting the pixel array 110 may be arranged in the form of a tetra-Bayer pattern.

[0023] The pixels of the pixel array 110 may output pixel signals via the row lines CL1 to CL4 depending on the intensity or amount of light received from the outside. For example, the pixel signal may be an analog signal corresponding to the intensity or amount of light received from the outside. The pixel signal may pass through a voltage buffer (for example, a source follower), and may then be provided to the ADC circuit 150 via the row lines CL1 to CL4.

[0024] The column driver 120 may select and drive a column of the pixel array 110. The column driver 120 may decode the address and / or control signals generated by the timing controller 160, and may generate control signals for selecting and driving a column of the pixel array 110. For example, the control signals may include signals for selecting pixels, signals for resetting the floating diffusion region, and the like.

[0025] The ramp signal generator 130 can generate a ramp signal RAMP under the control of the timing controller 160. For example, the ramp signal generator 130 can operate in response to a control signal such as a ramp enable signal. When the ramp enable signal is activated, the ramp signal generator 130 can generate the ramp signal RAMP depending on preset values (e.g., start level, end level, and slope). In other words, the ramp signal RAMP can be a signal that increases or decreases along a preset slope during a specific time period. The ramp signal RAMP can be provided to the ADC circuit 150 via the voltage buffer 140.

[0026] The ADC circuit 150 can receive pixel signals from multiple pixels via the row lines CL1 to CL4, and can receive the ramp signal RAMP from the ramp signal generator 130 via the voltage buffer 140. The ADC circuit 150 can operate based on the correlated double sampling (CDS) technique to obtain a reset signal and an image signal from the received pixel signals and extract the difference between the reset signal and the image signal as an effective signal component. The ADC circuit 150 can include multiple comparators COMP and multiple counters CNT.

[0027] Specifically, each of the comparators COMP can compare the reset signal of the pixel signal with the ramp signal RAMP, compare the image signal of the pixel signal with the ramp signal RAMP, and perform correlated double sampling (CDS) on the comparison results. Each of the counters CNT can count the pulses of the signal that has undergone correlated double sampling and can output the count result as a digital signal. In addition, the ADC circuit 150 of the present disclosure can be implemented to reduce power consumption by adopting auto-zero cycle optimization and / or output feedback. An example in which the ADC circuit 150 includes four comparators COMP and four counters CNT is shown in FIG. 2, but the present disclosure is not limited thereto.

[0028] The timing controller 160 can generate control signals and / or clocks for controlling the operations and / or timings of each of the column driver 120, the ramp signal generator 130, and the ADC circuit 150.

[0029] The buffer 170 can include a memory MEM and a sense amplifier SA. The memory MEM can store the digital signals output from the corresponding counters CNT of the ADC circuit 150. The sense amplifier SA can sense and amplify the digital signals stored in the memory MEM. The sense amplifier SA can output the amplified digital signals as image data IDAT and can provide the image data IDAT to the ISP front-end block 16 of FIG. 1.

[0030] FIG. 3 is a circuit diagram showing an example of one of the pixel groups PG of the pixel array 110 of FIG. 2 according to an exemplary embodiment. For example, the pixel group PG may include pixels PX1 to PX4, photoelectric conversion elements PD1 to PD4, transfer transistors Tx1 to Tx4, a reset transistor RST, a dual conversion transistor DC, a driving transistor Dx, and a selection transistor SEL. In FIG. 3, an example of a four-unit structure in which the pixel group PG has four pixels PX1 to PX4 respectively including photoelectric conversion elements PD1 to PD4 is shown, but the present disclosure is not limited thereto. For example, the pixel group PG may be implemented to have various different structures.

[0031] The first pixel PX1 may include a first photoelectric conversion element PD1 and a first transfer transistor Tx1, and each of the remaining pixels PX2, PX3, and PX4 may also include similar components / elements. The pixels PX1 to PX4 may share the reset transistor RST, the dual conversion transistor DC, the driving transistor Dx, and the selection transistor SEL. In addition, the pixels PX1 to PX4 may share a first floating diffusion region FD1. The reset transistor RST and the dual conversion transistor DC may share a second floating diffusion region FD2.

[0032] The first floating diffusion region FD1 or the second floating diffusion region FD2 may accumulate (or integrate) charges corresponding to the amount of incident light. Although the transfer transistors Tx1 to Tx4 are turned on by transfer signals VT1 to VT4 respectively, the first floating diffusion region FD1 or the second floating diffusion region FD2 may accumulate (or integrate) charges supplied from the photoelectric conversion elements PD1 to PD4. Since the first floating diffusion region FD1 is connected to the gate terminal of the driving transistor Dx operating as a source follower amplifier, a voltage corresponding to the charges accumulated at the first floating diffusion region FD1 may be formed. For example, the capacitance of the first floating diffusion region FD1 is depicted as a first capacitance CFD1.

[0033] The dual conversion transistor DC may be driven by a dual conversion signal VDC. When the dual conversion transistor DC is turned off, the capacitance of the first floating diffusion region FD1 may correspond to the first capacitance CFD1. In a general environment, since the first floating diffusion region FD1 is not easily saturated, it is not necessary to increase the capacitance of the first floating diffusion region FD1 (i.e., CFD1). In this case, the dual conversion transistor DC may be turned off.

[0034] However, in a high-brightness environment, the first floating diffusion region FD1 may be prone to saturation. To prevent saturation, the dual-conversion transistor DC may be turned on so that the first floating diffusion region FD1 is electrically connected to the second floating diffusion region FD2. In this case, the capacitance of the floating diffusion region FD1 and the floating diffusion region FD2 may increase to the sum of the first capacitance CFD1 and the second capacitance CFD2.

[0035] The transfer transistors Tx1 to Tx4 may be driven by transfer signals VT1 to VT4, respectively, and may transfer (or integrate) the charges generated by the photoelectric conversion elements PD1 to PD4 to the first floating diffusion region FD1 or the second floating diffusion region FD2. For example, the first ends of the transfer transistors Tx1 to Tx4 may be connected to the photoelectric conversion elements PD1 to PD4, respectively, and their second ends may be commonly connected to the first floating diffusion region FD1.

[0036] The reset transistor RST may be driven by a reset signal VRST and may supply the power supply voltage VDD to the first floating diffusion region FD1 or the second floating diffusion region FD2. Accordingly, the charges accumulated in the first floating diffusion region FD1 or the second floating diffusion region FD2 may move to the terminal of the power supply voltage VDD, and the voltage of the first floating diffusion region FD1 or the second floating diffusion region FD2 may be reset.

[0037] The driving transistor Dx may amplify the voltage of the first floating diffusion region FD1 or the second floating diffusion region FD2 and may generate a pixel signal PIX corresponding to the amplified result. The selection transistor SEL may be driven by a selection signal VSEL and may select the pixels to be read column by column. When the selection transistor SEL is turned on, the pixel signal PIX may be output to the ADC circuit 150 of FIG. 2 via the row line CL.

[0038] FIG. 4 shows an example of the configuration of the analog-to-digital conversion (ADC) circuit 150 of FIG. 2 according to an exemplary embodiment. The ADC circuit 150 may include a comparator 151 and a counter 152. The ADC circuit 150 may convert and output the pixel signal PIX, which is an analog signal output from the pixel array 110, into a digital signal DS. For clarity of description and simplicity of the drawing, an example in which the pixel array 110 includes only one pixel is shown in FIG. 4, and the configuration and functions of the pixel array 110 are the same as those described with reference to FIG. 3.

[0039] Specifically, as described with reference to FIG. 2, the comparator 151 can compare the reset signal and the ramp signal RAMP of the pixel signal, can compare the image signal and the ramp signal RAMP of the pixel signal, and can perform correlated double sampling (CDS) on the comparison result. The counter 152 can count the pulses of the signal that has undergone correlated double sampling (CDS) and can output the counting result as a digital signal. FIGS. 4 will be described with reference to FIGS. 2 and 3. Herein, the reset signal of the pixel signal can represent the signal of the pixel before receiving the reflected light, and the image signal of the pixel signal can represent the signal of the pixel after receiving the reflected light.

[0040] For example, the comparator 151 can have a two-stage structure, the two-stage structure includes two amplifiers (i.e., the first amplifier 151_1 and the second amplifier 151_2), and each of the first amplifier 151_1 and the second amplifier 151_2 can be implemented as an operational transconductance amplifier (OTA). However, the present disclosure is not limited thereto. For example, the comparator 151 can have a structure including three or more amplifiers. In addition, the ADC circuit 150 can include multiple comparators and multiple counters, but for the sake of clear description, one comparator 151 and one counter 152 are shown in FIG. 4.

[0041] The first amplifier 151_1 can receive the pixel signal PIX from the pixel array 110 via the row line CL, and can receive the ramp signal RAMP from the ramp signal generator 130 via the voltage buffer 140. The first amplifier 151_1 can output a first output signal OTA1_OUT based on the received signals. For example, in the period when the level of the ramp signal RAMP is higher than the level of the pixel signal PIX, the first amplifier 151_1 can output the first output signal OTA1_OUT with a high level, and in the period when the level of the ramp signal RAMP is lower than the level of the pixel signal PIX, the first amplifier 151_1 can output the first output signal OTA1_OUT with a low level. In addition, the comparison operation of the first amplifier 151_1 described above can be performed when comparing the reset signal of the pixel signal PIX and the ramp signal RAMP and when comparing the image signal of the pixel signal PIX and the ramp signal RAMP.

[0042] The second amplifier 151_2 can amplify the first output signal OTA1_OUT and output a second output signal OTA2_OUT as a comparison signal. For example, the second output signal OTA2_OUT can be an inverted version of the first output signal OTA1_OUT. In other words, the second amplifier 151_2 can output the second output signal OTA2_OUT with a low level during the high level period of the first output signal OTA1_OUT, and can output the second output signal OTA2_OUT with a high level during the low level period of the first output signal OTA1_OUT.

[0043] In the following description, when the comparator 151 performs a comparison operation, the voltage level of the first output signal OTA1_OUT or the second output signal OTA2_OUT changing from a high level to a low level or from a low level to a high level can be referred to as "the decision of the ADC circuit 150". In other words, "after the decision of the ADC circuit 150 ends" can mean "after the voltage level of the first output signal OTA1_OUT or the second output signal OTA2_OUT changes from a high level to a low level or from a low level to a high level".

[0044] During the auto-zero cycle before performing the comparison operation, the comparator 151 can be initialized in response to the auto-zero signal and then perform the comparison operation again. Specifically, the first amplifier 151_1 can be initialized in response to the first auto-zero signal AZ_OTA1, and the second amplifier 151_2 can be initialized in response to the second auto-zero signal AZ_OTA2.

[0045] In the following description, the auto-zero cycle of the first amplifier 151_1 is called the "first auto-zero cycle", and the auto-zero cycle of the second amplifier 151_2 is called the "second auto-zero cycle". For example, during the first auto-zero cycle and the second auto-zero cycle, the voltage levels of the input nodes and / or output nodes of the first amplifier 151_1 and the second amplifier 151_2 can be equalized.

[0046] In addition, the time taken to initialize the first amplifier 151_1 and the time taken to initialize the second amplifier 151_2 can be different from each other. For example, the time taken to initialize the first amplifier 151_1 can be longer than the time taken to initialize the second amplifier 151_2. In this case, when the second amplifier 151_2 is fully initialized, the second auto-zero signal AZ_OTA2 does not have to be applied to the second amplifier 151_2.

[0047] In other words, when the initialization of the second amplifier 151_2 is completed before the initialization of the first amplifier 151_1, regardless of the remaining length of the first auto-zero period, the second auto-zero period can be adjusted to terminate. For example, the second auto-zero period of the present disclosure can be optimized to terminate when the initialization of the second amplifier 151_2 is completed. For example, the second amplifier 151_2 can be implemented such that when the second auto-zero period ends, power is not consumed until the comparison operation of the first amplifier 151_1 is performed. For this purpose, the second amplifier 151_2 can include a switch for temporarily preventing power consumption in response to the end of the second auto-zero period. Therefore, the power consumption of the ADC circuit 150 can be reduced by auto-zero period optimization.

[0048] The counter 152 can operate under the control of the timing controller 160, can count the pulses of the second output signal OTA2_OUT, and can output the counting result as a digital signal DS. For example, the counter 152 can operate in response to control signals such as a counter clock signal CNT_CLK and an inversion signal CONV for inverting the internal bits of the counter 152.

[0049] For example, the counter 152 can include an up / down counter, a bit-by-bit inversion counter, etc. The operation of the bit-by-bit inversion counter can be similar to the operation of the up / down counter. For example, the bit-by-bit inversion counter can perform the function of only performing an up count and the function of converting all the internal bits of the counter to obtain the one's complement when a specific signal is input thereto. The bit-by-bit inversion counter can perform a reset count operation and can then invert the reset count result to convert it to the one's complement, i.e., a negative value.

[0050] FIG. 5 is a circuit diagram showing an example of the first amplifier 151_1 of FIG. 4 according to an exemplary embodiment. The first amplifier 200 can include a plurality of transistors TR11 to TR16, a plurality of switches SW1 and SW2, and a first current source 210. For example, the first transistor TR11, the second transistor TR12, the fifth transistor TR15, and the sixth transistor TR16 can be NMOS transistors, and the third transistor TR13 and the fourth transistor TR14 can be PMOS transistors. However, the present disclosure is not limited thereto. The first transistor TR11 to the sixth transistor TR16 can be implemented by transistors whose types are different from those shown in FIG. 5.

[0051] Referring to FIG. 5, a ramp signal RAMP can be input to the gate terminal of the first transistor TR11, and a pixel signal PIX can be input to the gate terminal of the second transistor TR12. The source terminals of the first transistor TR11 and the second transistor TR12 can be connected to a first current source 210 at a common node COMM. For example, the third transistor TR13 and the fourth transistor TR14 can be connected in the form of a current mirror. The sum of the currents flowing to (or through) the first transistor TR11 and the second transistor TR12 can be equal to a first power current ISS1.

[0052] The gate terminal and the drain terminal of the third transistor TR13 and the drain terminal of the first transistor TR11 can be commonly connected to a second output node OUT12, and the drain terminal of the fourth transistor TR14 and the drain terminal of the second transistor TR12 can be commonly connected to a first output node OUT11. A fifth transistor TR15 can be connected between the first output node OUT11 and the second output node OUT12. For example, the fifth transistor TR15 can limit the voltage level of the signal output from the first output node OUT11.

[0053] A first output signal OTA1_OUT can be output from the first output node OUT11, and an inverted first output signal OTA1_OUT' can be output from the second output node OUT12. For example, in a period when the level of the ramp signal RAMP is higher than the level of the pixel signal PIX, the first output signal OTA1_OUT can have a high level, and in a period when the level of the ramp signal RAMP is lower than the level of the pixel signal PIX, the first output signal OTA1_OUT can have a low level. The first output signal OTA1_OUT can be provided to the second amplifier 151_2 in FIG. 4.

[0054] The first current source 210 can include a sixth transistor TR16. The sixth transistor TR16 can be connected to a ground voltage VSS and can generate a first power current ISS1 based on a first bias signal BIAS1.

[0055] Meanwhile, during the first auto-zero period, switches SW1 and SW2 can be turned on in response to the first auto-zero signal AZ_OTA1. When switches SW1 and SW2 are turned on, the second input node IN12 and the first output node OUT11 can be connected to each other, and the first input node IN11 and the second output node OUT12 can be connected to each other. Thus, during the first auto-zero period, the levels of the first input node IN11, the second input node IN12, the first output node OUT11, and the second output node OUT12 can be equalized. Although not shown, a first capacitor connected to the first input node IN11 can receive the ramp signal RAMP, and a second capacitor connected to the second input node IN12 can receive the pixel signal PIX. For example, the first capacitor and the second capacitor can act as auto-zero level sampling capacitors.

[0056] FIG. 6 is a circuit diagram showing an example of the second amplifier 151_2 of FIG. 4 according to an example embodiment. The second amplifier 300 may include a plurality of transistors TR21 to TR24, a capacitor C1, a switching circuit 310, and a current source 320. For example, the seventh transistor TR21 and the tenth transistor TR24 may be PMOS transistors, and the eighth transistor TR22 and the ninth transistor TR23 may be NMOS transistors. However, the present disclosure is not limited thereto. The seventh transistor TR21 to the tenth transistor TR24 may be implemented by transistors of a type different from those shown in FIG. 6.

[0057] The seventh transistor TR21 can receive the first output signal OTA1_OUT from the first amplifier 151_1 of FIG. 4 as an input and can operate in response to the first output signal OTA1_OUT. For example, when the voltage level of the first output signal OTA1_OUT is high, the seventh transistor TR21 can be turned off. In this case, since current does not flow to the third output node OUT21, the voltage level of the second output signal OTA2_OUT can be low. In contrast, when the voltage level of the first output signal OTA1_OUT is low, the seventh transistor TR21 can be turned on. In this case, since current flows to the third output node OUT21, the voltage level of the second output signal OTA2_OUT can be high. In other words, the second amplifier 300 can operate as an inverting amplifier. For example, when the voltage level of the first output signal OTA1_OUT increases, the voltage level of the second output signal OTA2_OUT can decrease.

[0058] The switching circuit 310 may include an eighth transistor TR22 connected between the third output node OUT21 and the bias node BN. During the second auto-zero period, the eighth transistor TR22 may operate in response to the second auto-zero signal AZ_OTA2 and may turn on when the second auto-zero signal AZ_OTA2 is activated. When the eighth transistor TR22 turns on, the voltage level of the bias node BN may be equalized with the voltage level of the third output node OUT21, and the capacitor C1 connected to the bias node BN may be charged with the charge.

[0059] When the capacitor C1 is fully charged with the charge, the initialization of the second amplifier 300 may be completed, and the second auto-zero period may end. For example, the length of the second auto-zero period may be optimized based on the time taken to charge the capacitor C1 connected to the bias node BN with the charge. As described with reference to FIG. 4, the optimized length of the second auto-zero period may be shorter than the length of the first auto-zero period.

[0060] In contrast, during the comparison operation of the ADC circuit 150 in FIG. 4, when the eighth transistor TR22 is off when the second auto-zero signal AZ_OTA2 is activated, the voltage level of the bias node BN (equal to the voltage level of the third output node OUT21) may be maintained by the capacitor C1, and thus the current source 320 may operate.

[0061] The current source 320 may include a ninth transistor TR23 connected to the third output node OUT21. The ninth transistor TR23 may generate a power current ISS2 based on the voltage of the bias node BN (i.e., the voltage of one end of the capacitor C1).

[0062] As described above, when the capacitor C1 connected to the bias node BN is fully charged with the charge, the second auto-zero signal AZ_OTA2 may be deactivated, and the second auto-zero period may end. In this case, the tenth transistor TR24 may turn off in response to the activated power-off signal PD, and thus, the operation of the second amplifier 300 may be temporarily stopped (i.e., may be temporarily powered off). That is, the tenth transistor TR24 may operate as a power-off switch of the second amplifier 300.

[0063] The operation of the second amplifier 300 may be stopped until the first amplifier 200 in FIG. 10 performs a comparison operation. In other words, when the first auto-zero period of the first amplifier 200 ends (i.e., when the first auto-zero signal AZ_OTA1 is deactivated), the power-off signal PD may be deactivated, and the tenth transistor TR24 may be turned on. Therefore, the second amplifier 300 may start operating again.

[0064] In other words, the tenth transistor TR24 can be turned on in response to a low-level power-off signal PD during the second self-zero period and during the comparison operation period, and can be turned off in response to a high-level power-off signal PD between the second self-zero period and the comparison operation period. Through the above operation of the tenth transistor TR24, the power consumption of the second amplifier 300 can be reduced between the second self-zero period and the comparison operation period.

[0065] FIG. 7 is a timing diagram showing the operation of the analog-to-digital conversion (ADC) circuit 150 of FIG. 4 according to an exemplary embodiment. Referring to FIG. 7, the period from the first time point t0 to the third time point t2 can be defined as the self-zero period (including the first self-zero period and the second self-zero period), the period from the third time point t2 to the twelfth time point t11 can be defined as the comparison operation period, the period from the fourth time point t3 or the fifth time point t4 to the seventh time point t6 can be defined as the first operation period, and the period from the seventh time point t6 or the tenth time point t9 to the eleventh time point t10 can be defined as the second operation period. Specifically, the period from the first time point t0 to the third time point t2 can be defined as the first self-zero period, and the period from the first time point t0 to the second time point t1 can be defined as the second self-zero period. In addition, the period from the second time point t1 to the third time point t2 can be defined as the power-off period.

[0066] The selection signal VSEL can be activated before the first time point t0, and the pixel signal PIX can be output from a plurality of pixel groups of the pixel array in FIG. 2 (e.g., the pixel group shown in FIG. 3). In addition, the power supply voltage can be provided by a reset signal VRST activated before the first time point t0. In an embodiment, the levels of the pixel signal PIX and the ramp signal RAMP can be determined by a circuit (not shown in the figure) before the first time point t0 and after the twelfth time point t11. Hereinafter, FIG. 7 will be described with reference to FIGS. 4 to 6 together.

[0067] The first self-zero signal AZ_OTA1 can be activated from the first time point t0 to the third time point t2. The second self-zero signal AZ_OTA2 can be activated from the first time point t0 to the second time point t1, and deactivated from the second time point t1 to the third time point t2. The first amplifier 151_1 can be initialized in response to the first self-zero signal AZ_OTA1 during the first self-zero period (i.e., from the first time point t0 to the third time point t2), and the second amplifier 151_2 can be initialized in response to the second self-zero signal AZ_OTA2 during the second self-zero period (i.e., from the first time point t0 to the second time point t1).

[0068] As described with reference to FIG. 6, the length of the second self-zero period can be determined based on the time taken to charge a capacitor (e.g., C1 in FIG. 6) included in the second amplifier 151_2 having a charge. When the second amplifier 151_2 is fully initialized, the second self-zero signal AZ_OTA2 can be deactivated, and the second self-zero period can end.

[0069] In this case, the power-down signal PD can be activated. Accordingly, the power-down switch of the second amplifier 151_2 (e.g., TR24 in FIG. 6) can be turned off, and the operation of the second amplifier 151_2 can be temporarily stopped from the second time point t1 to the third time point t2. According to the above description, the power consumption of the second amplifier 151_2 can be reduced from the second time point t1 to the third time point t2, and the overall power consumption of the ADC circuit 150 can also be reduced. When the first self-zero period ends and the comparison operation period starts, the power-down signal PD can be deactivated again.

[0070] To perform digital conversion on the reset signal of the pixel signal PIX, an offset can be applied to the ramp signal RAMP at the fourth time point t3, and the ramp signal RAMP can be decreased from the fifth time point t4. The counter 152 can count the count clock signal CNT_CLK from the fifth time point t4 to the sixth time point t5, at which the polarity of the second output signal OTA2_OUT, which is the output of the second amplifier 151_2, changes.

[0071] In the case where the digital conversion of the reset signal ends, to convert the image signal of the pixel signal PIX into a digital signal at the seventh time point t6, an offset can be applied to the ramp signal RAMP again at the seventh time point t6, and the bits of the counter 152 can be inverted in response to the inversion signal CONV at the eighth time point t7. The transfer signal VT can be activated at the ninth time point t8, and during the activation period of the transfer signal VT, the voltage level of the input node of the first amplifier 151_1 can be changed, and the pixel signal PIX corresponding to the charge integrated by the photoelectric conversion element PD is received via the voltage level.

[0072] To perform digital conversion on an image signal, the level of the ramp signal RAMP may be decreased at the tenth time point t9. The counter 152 may count the counting clock signal CNT_CLK from the tenth time point t9 to the eleventh time point t10, and the polarity of the second output signal OTA2_OUT, which is the output of the second amplifier 151_2 at the eleventh time point, changes. For example, the counter 152 in FIG. 4 may output a digital signal DS at the eleventh time point t10. In the case where the digital conversion of the image signal ends, the ADC circuit 150 may be initialized for the next comparison operation (i.e., for correlated double sampling).

[0073] The operation timing of the ADC circuit 150 is described with reference to FIG. 7, but the present disclosure is not limited thereto. For example, the timing of the signal may vary or be modified depending on the manner in which the ADC circuit 150 is implemented (e.g., the structures of the first amplifier 151_1 and the second amplifier 151_2).

[0074] FIG. 8 shows another example of the configuration of the analog-to-digital conversion (ADC) circuit 150 of FIG. 2 according to an example embodiment. Referring to FIG. 8, the second output signal OTA2_OUT may be fed back to the second amplifier 151_2. The second output signal OTA2_OUT fed back to the second amplifier 151_2 may control the power supply (e.g., current source) of the second amplifier 151_2 and may reduce the power consumption of the ADC circuit 150. The output feedback operation of the second amplifier 151_2 described above may be performed when comparing the reset signal of the pixel signal PIX and the ramp signal RAMP and when comparing the image signal of the pixel signal PIX and the ramp signal RAMP.

[0075] For example, since the ADC circuit 150 in FIG. 8 further performs the output feedback operation and the optimization from the zero cycle, the power consumption of the ADC circuit 150 in FIG. 8 may be further reduced compared to the ADC circuit 150 in FIG. 4. The functions of the ADC circuit 150 in FIG. 8 are the same as those described with reference to FIG. 4 except for the above-described output feedback operation, and thus, additional description will be omitted to avoid redundancy.

[0076] FIG. 9 is a circuit diagram showing another example of the second amplifier 151_2 of FIG. 8 according to an exemplary embodiment. The second amplifier 300a may further include an eleventh transistor TR25 and a feedback circuit 330. For example, the eleventh transistor TR25 may be an NMOS transistor. However, the present disclosure is not limited thereto. For example, the eleventh transistor TR25 may be a transistor of a type different from the type shown in FIG. 9. Referring to FIG. 9, when the seventh transistor TR21 is turned on, current may also flow to the eleventh transistor TR25. The second output signal OTA2_OUT may be provided to the feedback circuit 330.

[0077] The feedback circuit 330 may control the current source 320 based on the second output signal OTA2_OUT and the feedback enable signal FB_EN. To perform the output feedback operation, the feedback circuit 330 may include a logic gate 331. For example, the logic gate 331 may be a NAND gate.

[0078] The logic gate 331 may output a feedback signal FB in response to the second output signal OTA2_OUT and the feedback enable signal FB_EN. For example, the logic gate 331 may be implemented such that when both the voltage level of the feedback enable signal FB_EN and the voltage level of the second output signal OTA2_OUT are high, the voltage level of the feedback signal FB is set to low.

[0079] When the voltage level of the feedback signal FB is high, the eleventh transistor TR25 may be turned on, and the power current ISS2 may flow through the eleventh transistor TR25. However, when the voltage level of the feedback signal FB is low, the eleventh transistor TR25 may be turned off, and the power current ISS2 may not flow through the eleventh transistor TR25.

[0080] Specifically, after the comparison operation between the ramp signal RAMP and the pixel signal PIX is completed, the voltage level of the first output signal OTA1_OUT may be low, and the voltage level of the second output signal OTA2_OUT may be high. In this case, before the feedback enable signal FB_EN is activated, the feedback signal FB may be high, the eleventh transistor TR25 may be in the on state, and the power current ISS2 may flow through the eleventh transistor TR25.

[0081] In contrast, when the feedback enabling signal FB_EN is activated (i.e., when the voltage level of the feedback enabling signal FB_EN is high), the voltage level of the feedback signal FB can be changed to a low level. In this case, since the eleventh transistor TR25 is turned off, the power current ISS2 may not flow through the eleventh transistor TR25. Therefore, by using the output feedback after the comparison operation is completed, the power consumption of the second amplifier 300 can be reduced. This may mean that the power consumption of the ADC circuit 150 is also reduced.

[0082] When maintaining the power consumption difference before and after the comparison operation is performed, the performance of the image sensor (e.g., the performance of the ADC circuit that converts the pixel signal into a digital signal) may be degraded. According to the above operation of the feedback circuit 330, the power current ISS2 may not flow through the output node OUT21 and the output node OUT22 after the comparison operation is performed, and thus, the power consumption difference before and after the comparison operation is performed can be reduced. Therefore, the degradation of the performance of the image sensor can be improved by the operation of the feedback circuit 330.

[0083] Meanwhile, the logic gate 331 in FIG. 9 is shown as a NAND gate, but the present disclosure is not limited thereto. For example, the feedback circuit 330 may be implemented as any other component (e.g., a NOR gate and an inverter) such that when the voltage level of the second output signal OTA2_OUT is high, the feedback signal FB is set to a low level.

[0084] In addition, the feedback circuit 330 in FIG. 9 is shown as directly receiving the second output signal OTA2_OUT, but the present disclosure is not limited thereto. For example, the feedback circuit 330 in FIG. 9 may receive any other signal based on the second output signal OTA2_OUT. For example, the second amplifier 300a may further include a transistor, a switch, an inverter, or a logic gate connected between the seventh transistor TR21 and the third output node OUT21. In this case, the logic gate 331 of the feedback circuit 330 may receive the signal obtained after the second output signal OTA2_OUT passes through the transistor, the switch, the inverter, or the logic gate connected between the seventh transistor TR21 and the third output node OUT21, and may perform the comparison operation described above.

[0085] In other words, the feedback circuit 330 may directly receive the second output signal OTA2_OUT, or may receive the signal obtained after the second output signal OTA2_OUT passes through the transistor, the switch, the inverter, or the logic gate connected between the seventh transistor TR21 and the third output terminal OUT21.

[0086] As a result, compared with the second amplifier 300 in FIG. 6, the second amplifier 300a in FIG. 9 can further reduce power consumption by adopting the operation of the tenth transistor TR24 optimized according to the second auto-zero period and the operation of the feedback circuit 330. The configuration and operation of the second amplifier 300a shown in FIG. 9 are the same as those of the second amplifier 300 in FIG. 6 except for the operation of the feedback circuit 330 described above. Therefore, additional description will be omitted to avoid redundancy.

[0087] FIG. 10A is a timing diagram showing an example of the operation of the ADC circuit 150 in FIG. 4 according to the operation of the feedback circuit 330 in FIG. 9 according to an exemplary embodiment, and FIG. 10B is a timing diagram showing an example of the operation of the ADC circuit 150 in FIG. 4 according to the operation optimized according to the auto-zero period and the operation of the feedback circuit 330 in FIG. 9 according to an exemplary embodiment. That is, FIG. 10A corresponds to the case where the second amplifier 300a in FIG. 9 only adopts the output feedback operation, and FIG. 10B corresponds to the case where the second amplifier 300a in FIG. 9 adopts both the auto-zero period optimization and the output feedback operation. In addition, in FIG. 10A, it is assumed that the length of the second auto-zero period is not optimized and is similar to the length of the first auto-zero period, and it is assumed that the power-down signal PD is not activated.

[0088] Referring to FIGS. 10A and 10B, the first time period T0 may correspond to the auto-zero period, the second time period T1 to the fourth time period T3 may correspond to the period in which the comparator 151 in FIG. 4 compares the reset signal and the ramp signal RAMP of the pixel signal PIX, and the fifth time period T4 to the seventh time period T6 may correspond to the period in which the comparator 151 compares the image signal and the ramp signal RAMP of the pixel signal PIX. When the decision of the ADC circuit 150 is completed (that is, when the third time period T2 ends and when the sixth time period T5 ends), the feedback enable signal FB_EN may be activated. For example, the voltage level of the feedback enable signal FB_EN may be maintained at a high level during the fourth time period T3 (where the ramp signal RAMP slopes down and the second output signal OTA2_OUT changes) and / or during the seventh time period T6 (where the ramp signal RAMP slopes down and the second output signal OTA2_OUT changes).

[0089] The feedback circuit 330 may output a feedback signal FB based on the feedback enable signal FB_EN and the second output signal OTA2_OUT. The transistor (for example, the eleventh transistor TR25) between the current source 320 and the output node OUT21 may be disconnected in response to the low-level feedback signal FB, and the power current ISS2 may not flow.

[0090] Therefore, the operation of the feedback circuit 330 can allow the power current ISS2 to have almost the same level during the second time period T1 to the fourth time period T3 and the fifth time period T4 to the seventh time period T6. For example, the level of the power current ISS2 can be close to "0" during the second time period T1 to the fourth time period T3 and the fifth time period T4 to the seventh time period T6. Therefore, the power consumption of the ADC circuit 150 can be reduced.

[0091] Meanwhile, referring to FIG. 10B, the first time period T0 as the auto-zero period can be subdivided into a first auto-zero time period for starting the first auto-zero signal AZ_OTA1 and a second auto-zero period for starting the second auto-zero signal AZ_OTA2. As described with reference to FIGS. 4 and 6, after the capacitor (e.g., capacitor C1 in FIG. 6) included in the second amplifier 151_2 is charged, the second auto-zero period can end.

[0092] When the second auto-zero period ends, the power-down signal PD can be activated, and thus, the operation of the second amplifier 151_2 can be temporarily stopped until the comparison operation period starts. Therefore, when the power-down signal PD is activated, the power current ISS2 may not flow, and thus, the power consumption of the ADC circuit 150 can be reduced. Therefore, referring to FIG. 10B, through auto-zero period optimization, the level of the power current ISS2 can be close to "0" until the comparison operation period starts after the second amplifier 151_2 is initialized, and thus, the power consumption of the ADC circuit 150 can be further reduced compared to FIG. 10A.

[0093] FIG. 11 is a circuit diagram showing another example of the second amplifier 151_2 of FIG. 8 according to an example embodiment. The second amplifier 300b can further include a control circuit 340. The control circuit 340 can adjust the output of the control current ICN to reduce the power consumption difference of the second amplifier 300b before and after performing the comparison operation. The control circuit 340 can include a twelfth transistor TR26 and a thirteenth transistor TR27 connected between the power supply voltage VDD and the third output node OUT21 and connected in parallel with the seventh transistor TR21 and the tenth transistor TR24.

[0094] The twelfth transistor TR26 can operate in response to a control signal CN, and the thirteenth transistor TR27 can operate in response to a second bias signal BIAS2. Herein, the control signal CN can be generated by the timing controller 160 of FIG. 2. In an embodiment, the gate of the thirteenth transistor TR27 can be connected to a bias node BN. For example, the twelfth transistor TR26 and the thirteenth transistor TR27 can be NMOS transistors. However, the present disclosure is not limited thereto. The twelfth transistor TR26 and the thirteenth transistor TR27 can be implemented by transistors whose types are different from those shown in FIG. 11.

[0095] When the control signal CN is activated, the twelfth transistor TR26 can be turned off, and the control current ICN may not flow through the thirteenth transistor TR27. At the same time, when the twelfth transistor TR26 is turned on by the activated control signal CN and the thirteenth transistor TR27 is turned on by the second bias signal BIAS2, the control current ICN can flow to the output node OUT21 and the output node OUT22 via the twelfth transistor TR26 and the thirteenth transistor TR27.

[0096] After making a decision on the magnitude relationship between the level of the ramp signal RAMP and the level of the pixel signal PIX, the level of the power current ISS2 can increase, and power can be continuously consumed even after the comparison operation is performed. As described above, since the power consumption difference before and after the comparison operation is continuous, the performance of the image sensor can be degraded.

[0097] The control circuit 340 can be operated to prevent the performance degradation of the image sensor. After the ramp signal RAMP starts to decline, when the activation control signal CN and the second bias signal BIAS2 are activated, as described above, the control current ICN can flow to the output node OUT21 and the output node OUT22 via the twelfth transistor TR26 and the thirteenth transistor TR27, and the level of the power current ISS2 can increase to the same level as the level of the control current ICN.

[0098] For example, the level of the power current ISS2 (hereinafter referred to as the "second level") that increases to the same level as the level of the control current ICN after the ramp signal RAMP starts to decline can be higher than the level of the power current ISS2 (hereinafter referred to as the "first level") before the comparison operation is performed, and can be lower than the level of the power current ISS2 (hereinafter referred to as the "third level") after the comparison operation (i.e., after making a decision on the magnitude relationship between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX) is completed.

[0099] According to the above operations of the control circuit 340, both the difference between the first level and the second level and the difference between the second level and the third level can be smaller than the difference between the first level and the third level. Therefore, the power consumption difference before and after the comparison operation of the second amplifier 300b can be reduced, and the performance degradation of the image sensor can be improved. Therefore, the performance degradation of the image sensor due to the power consumption difference before and after the comparison operation can be improved by the operations of the feedback circuit 330 and the control circuit 340, which is described above.

[0100] As a result, compared with the second amplifier 300 in FIG. 6, the second amplifier 300b in FIG. 11 can further reduce the power consumption by adopting both the operations of the feedback circuit 330 and the control circuit 340 and the operation of the tenth transistor TR24 optimized according to the second auto-zero period. The configuration and operation of the second amplifier 300b shown in FIG. 11 are the same as those of the second amplifier 300 in FIG. 6 and the second amplifier 300a in FIG. 9 except for the operation of the control circuit 340 described above. Therefore, additional descriptions will be omitted to avoid redundancy.

[0101] FIG. 12 is a flowchart showing an operation method of an analog-to-digital conversion (ADC) circuit adopting auto-zero period optimization according to an example embodiment of the present disclosure. FIG. 12 will be described with reference to FIGS. 2 and 4 to 6 together.

[0102] In operation S110, the first amplifier 151_1 may set the voltage levels of the input node and the output node to the same voltage level in response to the first auto-zero signal AZ_OTA1. In operation S120, the second amplifier 151_2 may charge the capacitor in response to the second auto-zero signal AZ_OTA2. In operation S130, the operation of the second amplifier 151_2 may be temporarily stopped until the comparison operation period starts after the end of the second zero period.

[0103] In operation S140, the first amplifier 151_1 may compare the pixel signal PIX output from the pixel array 110 with the ramp signal RAMP during the comparison operation period and may generate a first output signal OTA1_OUT. Specifically, the first amplifier 151_1 may compare the reset signal of the pixel signal PIX with the ramp signal RAMP during the first operation period, may compare the image signal of the pixel signal PIX with the ramp signal RAMP during the second operation period, and may perform correlated double sampling (CDS) on the comparison result.

[0104] In operation S150, the second amplifier 151_2 may generate a second output signal OTA2_OUT based on the first output signal OTA1_OUT. For example, the second output signal OTA2_OUT may be an inverted version of the first output signal OTA1_OUT.

[0105] According to an embodiment of the present disclosure, the power consumption of the analog-to-digital conversion circuit can be reduced by optimizing the auto-zero period.

[0106] When the present disclosure has been described with reference to the embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the following claims.

[0107] 10: Image processing block 12: Lens 14: Image sensor 16: Front-end block of image signal processor 18: Image signal processor 100: Image sensor 110: Pixel array 120: Column driver 130: Ramp signal generator 140: Voltage buffer 150: Analog-to-digital converter circuit 151, COMP: Comparator 152, CNT: Counter 151_1: First amplifier 151_2: Second amplifier 160: Timing controller 170: Buffer 200: First amplifier 210: First current source 300, 300a, 300b: Second amplifier 310: Switching circuit 320: Current source 330: Feedback circuit 331: Logic gate 340: Control circuit AZ_OTA1: First auto-zero signal AZ_OTA2: Second auto-zero signal BIAS1: First bias signal BIAS2: Second bias signal BN: Bias node C1: Capacitor CFD1: First capacitance CFD2: Second capacitance CL, CL1 to CL4: Row line CN: Control signal CNT_CLK: Counter clock signal COMM: Common node CONV: Inverted signal DC: Dual conversion transistor DS: Digital signal Dx: Drive transistor FB: Feedback signal FB_EN: Feedback enable signal FD1: First floating diffusion region FD2: Second floating diffusion region ICN: Control current IDAT: Image data IN11: First input node IN12: Second input node ISS1: First power current ISS2: Power current MEM: Memory OTA1_OUT: First output signal OTA1_OUT': Inverted first output signal OTA2_OUT: Second output signal OUT11: First output node OUT12: Second output node OUT21: Third output node / Third output terminal OUT22: Output node PD: Power-off signal PD1 to PD4: Photoelectric conversion element PG: Pixel group PIX: Pixel signal PX1 to PX4: Pixel RAMP: Ramp signal RST: Reset transistor S110, S120, S130, S140, S150: Operation SA: Sense amplifier SEL: Selection Transistor SW1, SW2: Switches t0: First Time Point t1: Second Time Point t2: Third Time Point t3: Fourth Time Point t4: Fifth Time Point t5: Sixth Time Point t6: Seventh Time Point t7: Eighth Time Point t8: Ninth Time Point t9: Tenth Time Point t10: Eleventh Time Point t11: Twelfth Time Point T0: First Time Period T1: Second Time Period T2: Third Time Period T3: Fourth Time Period T4: Fifth Time Period T5: Sixth Time Period T6: Seventh Time Period TR11: First Transistor TR12: Second Transistor TR13: Third Transistor TR14: Fourth Transistor TR15: Fifth Transistor TR16: Sixth Transistor TR21: Seventh Transistor TR22: Eighth Transistor TR23: Ninth Transistor TR24: Tenth Transistor TR25: Eleventh Transistor TR26: Twelfth Transistor TR27: Thirteenth Transistor Tx1 to Tx4: Transfer Transistors VDC: Dual Conversion Signal VDD: Power Supply Voltage VRST: Reset Signal VSEL: Selection Signal VSS: Ground Voltage VT: Transfer Signal VT1 to VT4: Transfer Signals

Claims

1. An analog-to-digital converter circuit, comprising: A first amplifier is configured to: respond to a first zero-state signal in a first zero-state cycle to equalize the voltage levels of its input and output nodes; receive a ramp signal at a first input node of the input node and receive a pixel signal output from the pixel array via a row line of the pixel array at a second input node of the input node, the row line being connected to the second input node of the first amplifier; perform a first comparison of the ramp signal and a reset signal of the pixel signal in a first operating cycle; perform a second comparison of the ramp signal and an image signal of the pixel signal in a second operating cycle following the first operating cycle; and generate a first output signal at the output node in both the first and second operating cycles based on the first and second comparison results. And a second amplifier having an input node connected to the output node of the first amplifier, the second amplifier being configured to: charge a capacitor in response to a second self-zero signal different from the first self-zero signal during a second self-zero cycle; stop operation of the second amplifier from the end of the second self-zero cycle to the start of the first operating cycle; receive the first output signal from the first amplifier at the input node of the second amplifier; and generate a second output signal based on the first output signal from the first amplifier during both the first and second operating cycles, wherein the second self-zero cycle overlaps with the first self-zero cycle, and wherein when the operation of the second amplifier is stopped, the circuit is configured such that supplying power voltage to the second amplifier is prevented from the end of the second self-zero cycle to the start of the first operating cycle.

2. The analog-to-digital converter circuit as claimed in claim 1, wherein the length of the second self-zero cycle is determined based on the time taken to fully charge the capacitor and is shorter than the length of the first self-zero cycle.

3. The analog-to-digital converter circuit as claimed in claim 1, wherein the second amplifier comprises: a first transistor configured to provide the power supply voltage to a first output node in response to a first output signal, the second output signal being output from the first output node; a second transistor connected to the capacitor via a bias node and configured to turn on in response to a second zero-signal; a current source connected to the first transistor via the first output node, connected to the capacitor and the second transistor via the bias node, and configured to generate a power current based on a voltage level maintained by the capacitor at the bias node; and a third transistor connected to the first transistor and configured to provide the power supply voltage to the first transistor and turn off in response to a power-off signal to stop the operation of the second amplifier.

4. The analog-to-digital converter circuit as claimed in claim 3, wherein the third transistor is configured to: disconnect in response to the power-off signal initiating at the end of the second zero-cycle, and turn on in response to the power-off signal initiating at the beginning of the first operating cycle.

5. The analog-to-digital converter circuit as claimed in claim 3, wherein the first transistor and the third transistor are PMOS transistors, and the second transistor is an NMOS transistor.

6. The analog-to-digital converter circuit as claimed in claim 3, wherein the second amplifier further comprises: a feedback circuit connected to the first output node and configured to receive the second output signal and output a feedback signal; and a fourth transistor connected to the current source via the second output node and configured to electrically connect the first output node to the second output node in response to the feedback signal.

7. The analog-to-digital converter circuit as claimed in claim 6, wherein the feedback circuit includes a logic gate configured to output the feedback signal based on the second output signal and the feedback enable signal, and wherein the fourth transistor disconnects in response to the feedback signal.

8. The analog-to-digital converter circuit as claimed in claim 7, wherein the fourth transistor is an NMOS transistor and the logic gate is a NAND gate.

9. The analog-to-digital converter circuit as claimed in claim 6, wherein the second amplifier further comprises: a control circuit configured to output a control current in response to a control signal, wherein the control circuit comprises: a fifth transistor configured to generate the control current based on the power supply voltage in response to the control signal; and a sixth transistor configured to provide the control current to the first output node in response to a bias signal.

10. The analog-to-digital converter circuit as described in claim 9, wherein, During the first or second operating cycle, when the ramp signal begins to slope down, the control circuit outputs the control current to the current source via the first and second output nodes.

11. A method of operating an analog-to-digital converter circuit including a first amplifier and a second amplifier, the method comprising: The voltage levels of the input and output nodes of the first amplifier are equalized in response to the first zero-state signal during the first zero-state cycle. In response to the second zero signal, the capacitor of the second amplifier is charged during the second zero cycle that overlaps with the first zero cycle; The operation of the second amplifier is stopped from the end of the second zero cycle to the start of the first operating cycle; a pixel signal output from the pixel array is received at an input node of the first amplifier via a row line connected to the input node of the first amplifier; a first output signal is generated from the output node of the first amplifier by comparing a ramp signal with a reset signal of the pixel signal during the first operating cycle, and comparing the ramp signal with an image signal of the pixel signal during a second operating cycle after the first operating cycle; the first output signal from the first amplifier is received at an input node of the second amplifier, the input node of the second amplifier being connected to the output node of the first amplifier; and a second output signal is generated from the output node of the second amplifier based on the first output signal from the first amplifier during both the first and second operating cycles; The operation of stopping the second amplifier includes: preventing the supply of power voltage to the second amplifier from the time point at the end of the second zero cycle to the time point at the start of the first operating cycle.

12. The method of operation as claimed in claim 11, wherein charging the capacitor of the second amplifier includes determining the length of the second self-zero cycle based on the time taken to fully charge the capacitor, wherein the length of the second self-zero cycle is shorter than the length of the first self-zero cycle, and wherein the stop of the operation of the second amplifier is performed in response to a power-off signal initiated at the end of the second self-zero cycle and de-initiated at the beginning of the first operating cycle.

13. The operating method as described in claim 11 further includes: The power current of the analog-to-digital converter circuit is controlled by using the second output signal, wherein the control of the power current is performed during at least one of the first operating cycle and the second operating cycle.

14. The method of operation as described in claim 13, wherein the control of the power current comprises: outputting a feedback signal based on the second output signal and the feedback enable signal; and allowing the power current to stop flowing in response to the feedback signal.

15. An analog-to-digital converter circuit that charges a capacitor in response to a zero-state signal during a zero-state cycle and generates an output signal during an operating cycle, the analog-to-digital converter circuit comprising: A first transistor is configured to provide a power supply voltage to a first output node, and the output signal is output from the first output node; A second transistor is connected to the capacitor via a bias node and configured to turn on in response to the self-zero signal; a current source is connected to the first transistor via the first output node, connected to the capacitor and the second transistor via the bias node, and configured to generate power current based on the voltage level maintained by the capacitor at the bias node. and a third transistor, connected to the first transistor and configured to supply the power supply voltage to the first transistor and disconnect in response to a power-off signal to stop the operation of the analog-to-digital conversion circuit, wherein when the operation of the circuit stops, the circuit is configured such that the third transistor responds to the power-off signal to prevent the supply of power supply voltage to the first transistor.

16. The analog-to-digital converter circuit of claim 15, wherein the third transistor is configured to: disconnect in response to a power-off signal initiated at the end of the zero-cycle, and to connect in response to the power-off signal initiated at the beginning of the operating cycle, wherein the length of the zero-cycle is determined based on the time taken to fully charge the capacitor, and wherein the operation of the analog-to-digital converter circuit stops from the end of the zero-cycle to the beginning of the operating cycle.

17. The analog-to-digital converter circuit as claimed in claim 15, wherein the first transistor and the third transistor are PMOS transistors, and the second transistor is an NMOS transistor.

18. The analog-to-digital converter circuit as described in claim 15, further comprising: A feedback circuit is connected to the first output node and configured to receive the output signal and output a feedback signal. And a fourth transistor, connected to the current source via a second output node, and configured to connect the first output node to the second output node in response to the feedback signal.

19. The analog-to-digital converter circuit of claim 18, wherein the feedback circuit includes a logic gate configured to output the feedback signal based on the output signal and the feedback enable signal, and wherein the fourth transistor disconnects in response to the feedback signal.

20. The analog-to-digital converter circuit as claimed in claim 19, wherein the fourth transistor is an NMOS transistor and the logic gate is a NAND gate.

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