Systems and methods for producing epitaxial wafers

Abstract

A method for producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer configuration produced by an epitaxial device. The method further includes polishing a semiconductor wafer using a polishing assembly, and measuring the polished semiconductor wafer to determine a surface configuration of the polished wafer. The method further includes generating a predicted post-epitaxymographic surface configuration of the polished wafer by comparing the surface configuration of the polished wafer with a determined epitaxial deposition layer configuration produced by the epitaxial device. The method also includes determining a predicted post-epitaxymographic parameter based on the predicted post-epitaxymographic surface configuration, and adjusting process conditions of the polishing assembly based on the predicted post-epitaxy parameter.

Description

Technical Field

[0001] This invention relates generally to the production of epitaxial wafers, and more specifically to systems and methods for producing epitaxial wafers with controlled flatness. Prior Technology

[0002] Epitaxial semiconductor wafers are commonly used in the production of integrated circuit (IC) chips on which printed circuit systems are fabricated. The circuit system is first printed in a miniaturized form onto the surface of the epitaxial wafer. The wafer is then cleaved into circuit chips. To ensure that this miniaturized circuit system can be properly printed across the entire surface of the wafer, the front and back surfaces of the epitaxial wafer must be substantially defect-free, extremely flat, and parallel to each other. Furthermore, ICs are rapidly becoming increasingly miniaturized, and this trend is constantly imposing stringent requirements related to acceptable epitaxial wafer flatness parameters, such as Site Back Side Ideal Plane / Range (SBIR), Global Back Side Ideal Plane / Range (GBIR), Site Front Side Minimum Squared Focal Plane Range (SFQR), and Edge Site Front Side Minimum Squared Focal Plane Range (ESFQR).

[0003] Semiconductor substrate wafers are used as starting materials in the production process of epitaxial wafers and are initially obtained from single-crystal ingots of suitable semiconductor materials (e.g., silicon). The substrate wafer can be diced from the ingot using, for example, a wire saw. Grinding and polishing processes are commonly used to improve the flatness and parallelism of the front and back surfaces of the substrate wafer after ingot dicing. For example, a double-sided polishing process can be used first to polish the substrate wafer, where both the front and back surfaces of the wafer are polished simultaneously to improve the flatness and parallelism of the two surfaces. A single-sided polishing process can then be used to polish the double-sided polished wafer, where only one surface of the wafer (e.g., the front surface) is polished.

[0004] Polished wafers then undergo epitaxial processes (or "epitaxy") to produce epitaxial wafers. For example, epitaxial chemical vapor deposition (CVD) is a process used to form epitaxial wafers and involves growing a thin material layer on a polished semiconductor wafer with the same lattice structure as the wafer itself. Epitaxial CVD is commonly used in semiconductor wafer manufacturing to create epitaxial layers, allowing devices (e.g., printable circuit systems) to be fabricated directly on these layers. During epitaxial CVD, the polished semiconductor wafer is heated to a suitable temperature in the deposition chamber of the epitaxial reactor, and a deposition gas (e.g., a vaporized silicon source gas, such as silane or silane chloride) passes through the chamber to deposit and grow an epitaxial material layer on the surface of the previously polished wafer. During epitaxial deposition, a support in the deposition chamber rotates during the process to allow the epitaxial layer to grow uniformly.

[0005] The parameters of an epitaxial wafer (e.g., flatness) depend on the process conditions during polishing and epitaxy. In some cases, process conditions during polishing or epitaxy can lead to unacceptable flatness of the epitaxial wafer. For example, the polishing process may cause changes in the substrate wafer configuration near the wafer edges due to non-uniform distribution of mechanical and / or chemical forces near the edges. The thickness configuration at the outer edges of the wafer can be reduced, i.e., "edge roll-off" can be observed. Edge roll-off reduces the portion of the wafer usable for device fabrication. Furthermore, various process conditions in epitaxy, such as temperature gradients across the wafer surface, airflow, and support design, can affect the uniformity of the epitaxial growth rate across the wafer surface. Deviations between local growth rates on the wafer surface can lead to non-uniform thickness distribution of the epitaxial layer, resulting in degraded flatness of the epitaxial wafer and failure to meet target specifications.

[0006] Process conditions during polishing and epitaxy can be adjusted to prevent the production of unacceptable wafer parameters. For example, polishing process conditions can be adjusted to minimize edge roll-off while maintaining acceptable flatness of the polished wafer. Epitaxy process conditions can also be adjusted to provide a more uniform epitaxial growth rate across the wafer surface. However, these adjustments are typically made to optimize the wafer surface configuration obtained from each step, regardless of whether it is obtained from previous or subsequent steps. Furthermore, it has been observed that if the surface configuration of the polished wafer does not match the configuration of the deposited epitaxial layer, even an epitaxial wafer formed from a polished wafer with acceptable post-polishing flatness and edge roll-off parameters may not have acceptable post-epitaxy flatness. The loss will not be realized until after irreversible epitaxial processing, and the epitaxial wafer must be discarded, resulting in unacceptable yield losses.

[0007] Accordingly, there is a need for a process for producing epitaxial wafers that facilitates control over the flatness of the epitaxial wafers.

[0008] This background section is intended to introduce the reader to various aspects of the technology that may be associated with the various aspects of the invention described below and / or claimed. This discussion is intended to help provide the reader with background information to better understand the various aspects of the invention. Therefore, it should be understood that these statements should be read in this context and not as an endorsement of prior art. Summary of the Invention

[0009] In one embodiment, a method for producing epitaxial semiconductor wafers includes measuring one or more epitaxial semiconductor wafers to determine the epitaxial deposition layer configuration produced by an epitaxial device. The method further includes polishing the semiconductor wafers using a polishing assembly, and measuring the polished semiconductor wafers to determine the surface configuration of the polished wafers. The method further includes generating a predicted epitaxial surface configuration of the polished wafers by comparing the surface configuration of the polished wafers with the determined epitaxial deposition layer configuration produced by the epitaxial device. The method also includes determining predicted epitaxial parameters based on the predicted epitaxial surface configuration, and adjusting the process conditions of the polishing assembly based on the predicted epitaxial parameters.

[0010] In another embodiment, a method for producing epitaxial semiconductor wafers includes measuring one or more epitaxial semiconductor wafers to determine the thickness configuration of an epitaxially deposited layer produced by an epitaxial device. The method further includes polishing the semiconductor wafers using a polishing assembly, and measuring the polished semiconductor wafers to determine the surface configuration near the edges of the polished wafers. The method further includes determining predicted epitaxial near-edge parameters of the polished wafers by comparing the surface configuration near the edges of the polished wafers with the thickness configuration produced by the epitaxial device. The method also includes determining whether the predicted epitaxial near-edge parameters meet predetermined parameter specifications; and if the predicted epitaxial near-edge parameters do not meet the predetermined parameter specifications, adjusting the process conditions of the polishing assembly to control the parameters of the surface configuration near the edges of the polished wafers.

[0011] In another embodiment, a method for producing epitaxial semiconductor wafers includes measuring one or more epitaxial semiconductor wafers to determine the thickness configuration of an epitaxial deposit produced by an epitaxial device. The method further includes polishing the semiconductor wafers using a polishing assembly, and measuring the polished semiconductor wafers to determine the surface configuration of the polished wafers. The method also includes superimposing the thickness configuration of the epitaxial deposit onto the surface configuration of the polished wafers to determine predicted post-epitaxy parameters of the polished wafers. The predicted post-epitaxy parameters include a flatness parameter of at least one of SBIR, GBIR, SFQR, and ESFQR. The method further includes determining whether the predicted post-epitaxy parameters meet predetermined parameter specifications; and if the predicted post-epitaxy parameters do not meet the predetermined parameter specifications, adjusting the process conditions of the polishing assembly.

[0012] Various modifications exist to the features mentioned in the above-described forms. Additional features may also be incorporated into the above-described forms. These modifications and additional features may exist individually or in any combination. For example, the features discussed below with respect to any of the illustrated embodiments may be incorporated individually or in any combination into any of the forms described above. Simple Explanation of the Diagram

[0013] Figure 1 shows an example process for producing epitaxial wafers; Figure 2 is a partial schematic front view of the double-sided polishing assembly; Figure 3 is a partial schematic front view of the single-sided polishing assembly; Figure 4 shows a partial schematic cross-section of the epitaxial wafer; Figure 5 shows an example process for producing epitaxial wafers with controlled flatness; Figure 6 shows a schematic cross-section of a polished wafer with an epitaxial deposition layer superimposed on the surface before polishing; Figure 7 is a block diagram of an example system for controlling the flatness of epitaxial wafers according to the process shown in Figure 5; Figure 8 is a scatter plot showing the correlation between the predicted epitaxial parameters and the yield of the epitaxial wafer; and Figure 9 is a scatter plot of the yield of epitaxial wafers compared to the edge roll-off of polished wafers used to produce epitaxial wafers, showing the curves of epitaxial wafers produced with and without predicted post-epidural parameters. The same reference symbols in each diagram indicate the same element. Implementation

[0014] This application claims priority to U.S. Provisional Patent Application No. 63 / 268,287, filed February 21, 2022, the disclosure of which is incorporated herein by reference in its entirety.

[0015] Referring to Figure 1, an example process 100 for producing epitaxial wafers is shown. At step 102, the substrate wafer is polished to obtain a polished wafer. Suitable substrate "wafers" (which may also be referred to as "semiconductor wafers" or "silicon wafers") include monocrystalline silicon substrate wafers, such as substrate wafers obtained by ingot dicing formed by the Czochralski method or floating zone method. Each substrate wafer includes a central axis, a front surface, and a rear surface parallel to the front surface. The front and rear surfaces are substantially perpendicular to the central axis. The circumferential edges join the front and rear surfaces. The substrate wafer can be of any diameter suitable for use by those skilled in the art, including, for example, 200 mm, 300 mm, or 450 mm diameter wafers.

[0016] The polishing process of the 102 substrate wafer may include simultaneously polishing (e.g., rough polishing) both the front and back surfaces of the substrate wafer using a dual-side polishing (DSP) assembly. Referring to Figure 2, a portion of an example DSP assembly for rough polishing the front and back surfaces of the substrate wafer is schematically shown and generally indicated at 200. Other types of polishing equipment may be used upon careful consideration.

[0017] As shown in Figure 2, the DSP assembly 200 includes a first polishing head 202 attached to a first shaft 204 and a second polishing head 206 attached to a second shaft 207. The first shaft 204 rotates the first polishing head 202, and the second shaft 207 rotates the second polishing head 206. The rotational speed of the first polishing head 202 may be the same as or different from the rotational speed of the second polishing head 206. The first polishing head 202 includes a first plate 208 and a first polishing pad 210 attached to the first plate 208. The second polishing head 206 includes a second plate 212 and a second polishing pad 214 attached to the second plate 212. During polishing, one or more wafers W are inserted into an annular opening in a generally annular carrier 216, and the wafers W and the carrier 216 are positioned between the first and second polishing pads 210 and 214. The carrier 216 and the wafers W can be moved between the polishing pads 210 and 214, for example, using a rolling device (not shown).

[0018] The DSP assembly 200 applies force to polishing heads 202 and 206 to move them vertically relative to the wafer W and carrier 216. The vertical movement of polishing heads 202 and 206 toward the wafer W and carrier 216 causes polishing pads 210 and 214 to press against the carrier 216 and form polishing engagement with the corresponding surfaces of the wafer W. As the force applied by the DSP assembly 200 to cause the polishing heads 202 and 206 to move vertically toward the wafer W and carrier 216 increases, the polishing pressure between the polishing pads 210 and 214 and the corresponding surfaces of the wafer W increases. The carrier 216 restricts the vertical movement of polishing heads 202 and 206 and defines the gap G between the polishing heads 202 and 206. The amount of polishing pressure that can be applied between the polishing pads 210 and 214 and the corresponding surfaces of the wafer W is limited by the gap G. Increasing the thickness of the carrier 216 will also increase the thickness of the gap G, and thus further limit the polishing pressure between the polishing pads 210 and 214 and the corresponding surfaces of the wafer W.

[0019] Rough polishing of wafer W using DSP assembly 200 can be achieved by, for example, chemical mechanical planarization (CMP). CMP typically involves immersing wafer W in an abrasive slurry. DSP assembly 200 includes a slurry supply system (not shown) that supplies slurry to wafer W between first and second polishing pads 210 and 214 during polishing. Suitable slurries that can be used alone or in combination during the polishing process include a first polishing slurry containing a certain amount of silica particles, a second polishing slurry that is alkaline (i.e., caustic alkali) and generally does not contain silica particles, and a third polishing slurry that is deionized water.

[0020] The DSP assembly 200 may also include a preheating system (not shown) that supplies preheating fluid to the first and second polishing heads 202 and 206 prior to polishing. The preheating fluid typically comprises a non-abrasive fluid that is substantially free of silica, such as deionized water. The preheating system supplies the preheating fluid to the polishing heads 202 and 206 at a predetermined temperature and flow rate. The preheating fluid is conveyed to polishing pads 210 and 214 via channels for a predetermined time, while shafts 204 and 207 simultaneously rotate the polishing heads 202 and 206 to coat the polishing pads 210 and 214 with the preheating fluid, respectively. The preheating fluid can increase the temperature of the polishing pads 210 and 214 to less than or equal to the target polishing temperature before polishing using the DSP assembly 200.

[0021] The DSP assembly 200 also includes a controller 218, which allows an operator to select and control the process conditions of the DSP assembly 200 during polishing. For example, the operator can select the rotational speed of one or both of the polishing heads 202 and 206, and can adjust the polishing pressure between the polishing pads 210 and 214 and the corresponding surfaces of the wafer W by controlling the vertical movement of the polishing heads 202 and 206. The operator can also control the process conditions via the controller 218, including, for example, the flow rate of the slurry supplied during polishing, the composition of the polishing slurry, the polishing process time, the polishing process temperature, and the rotational speed of the carrier 216 during polishing.

[0022] During operation, wafer W is positioned in carrier 216, and wafer W and carrier 216 are positioned between polishing pads 210 and 214 within the DSP assembly 200. Polishing pads 210 and 214 can be preheated using preheating fluid supplied by a preheating system as described herein before positioning wafer W and carrier 216. Polishing heads 202 and 206 move toward carrier 216 and wafer W, and polishing pads 210 and 214 press against the front and rear surfaces of wafer W. Polishing slurry is delivered to polishing heads 202 and 206 via channels and applied to polishing pads 210 and 214. The front and rear surfaces of wafer W are polished by rotating polishing heads 202 and 206. Specifically, the rotating polishing pads 210 and 214 cause the polishing slurry to act against the front and rear surfaces of wafer W to remove material from the surface of wafer W, thereby producing a flatter and / or smoother surface. The carrier plate 216 can also be moved during polishing to facilitate the removal of material from the surface of the wafer W. The desired surface configuration (e.g., desired flatness or smoothness) of the wafer W can be achieved by adjusting the polishing process conditions via the controller 218. These conditions include, for example, the rotational speed of one or both of the polishing heads 202 and 206, the polishing pressure between the polishing pads 210 and 214 and the corresponding surface of the wafer W, the flow rate of the polishing slurry, the composition of the polishing slurry, the polishing process time, the polishing process temperature, and the rotational speed of the carrier plate 216 during polishing. Furthermore, the desired surface configuration of the wafer W can be achieved by adjusting the thickness of the carrier plate 216 to increase or decrease the gap G, thereby adjusting the polishing pressure applied by the polishing pads 210 and 214 to the corresponding surface of the wafer W.

[0023] Referring back to Figure 1, the polishing step of the 102 substrate wafer may additionally or alternatively include subjecting the wafer to one or more single-sided polishing operations, wherein the front surface of the wafer is polished but the back surface is not polished, to improve flatness parameters or to smooth the front surface and remove processing scratches. To perform this operation, a single-sided polishing (SSP) assembly, such as SSP assembly 300 (shown in Figure 3), can be used. Typically, a wafer that has been previously coarsely polished (e.g., using DSP assembly 200) and thus has coarsely polished front and back surfaces first undergoes an intermediate SSP operation using a conventional polishing slurry containing abrasive particles and chemical etchant with an SSP assembly. The wafer may then undergo a finishing SSP operation, in which the front surface of the wafer is finished polished to remove fine or “micro” scratches caused by larger colloidal silica (e.g., Syton® from DuPont Air Products Nanomaterials, LLC) in the intermediate SSP step, and to produce a highly reflective, non-destructive front surface of the wafer. Intermediate SSP operations typically remove more material from the wafer's front surface than finishing SSP operations. The wafer can be finished polished using the same SSP assembly used for intermediate polishing (e.g., SSP assembly 300 shown in Figure 3 and described herein). However, a separate SSP assembly can also be used for finishing polishing operations. Finishing polishing slurries typically contain amine groups and a reduced concentration of colloidal silicon dioxide. The finishing polishing slurry acts against the wafer's front surface to remove any residual scratches and turbidity, making the wafer's front surface generally highly reflective and undamaged. Between any polishing operations included in polishing step 102, the wafer may be washed and dried, and may undergo cleaning operations such as wet cleaning or rotary cleaning operations.

[0024] Referring to Figure 3, a portion of the example SSP assembly is schematically and generally indicated at 300. The SSP assembly 300 is used to polish the front surfaces of one or more wafers W. Other types of polishing equipment may be used upon careful consideration.

[0025] The SSP assembly 300 includes a wafer holding mechanism, such as a template comprising a backing film 302 and a retaining ring 304, a polishing head 306, and a turntable 308 having a polishing pad 310. The backing film 302 is located between the polishing head 306 and the retaining ring 304, and receives the wafer W. The backing film is filled with water or other suitable liquid to use the surface tension of the liquid to mount the wafer W to the polishing head 306, as described below. The retaining ring 304 has at least one circular opening therein to receive the wafer W to be polished. The wafer W may have been previously double-sided polished using, for example, the DSP assembly 200 (shown in Figure 2). Although a single wafer W is shown in Figure 3, the SSP assembly 300 can be used to polish multiple wafers.

[0026] The wafer W is attached to the polishing head 306 and held against the polishing head by means of surface tension. To create surface tension, a wet-saturated backing film 302 is attached to the polishing head 306 using a pressure-sensitive adhesive. The backing film 302 and the retaining ring 304 form a template or "wafer holding template". The backing film 302 is typically a soft polymer pad or other suitable material.

[0027] The wafer W is then pressed into the wet-saturated backing film 302 to remove or squeeze out most of the water or other suitable liquid. The squeezing out of water causes the wafer W to remain on the backing film 302 by means of surface tension and atmospheric pressure on the exposed surface of the wafer W. This squeezing out of water then mounts the wafer W to the polishing head 306.

[0028] A portion of the polishing head 306 may be sufficiently flexible to deform in response to changes in pressure applied to the polishing head 306, and sufficiently rigid to avoid deformation when the wafer W is pressed into a wet saturated template. Surface tension provides a constant holding force on the surface of the wafer W. This constant holding force causes any deformation of the polishing head 306 adjacent to the wafer W to be directly translated into a proportional deformation of the wafer W.

[0029] The SSP assembly 300 applies force to the polishing head 306 to move the polishing head 306 vertically, thereby raising and lowering the polishing head 306 relative to the wafer W and the turntable 308. An upward force raises the polishing head 306, and a downward force lowers it. The vertical downward movement of the polishing head 306 against the wafer W provides polishing pressure to push the wafer W into the polishing pad 310 of the turntable 308. As the SSP assembly 300 increases the downward force, the polishing head 306 moves vertically downward to increase the polishing pressure.

[0030] A portion of the polishing head 306, polishing pad 310, and turntable 308 are rotated at a selected rotational speed by a suitable drive mechanism (not shown) known in the art. The rotational speeds of the polishing pad 310 and turntable 308 may be the same or different. The SSP assembly 300 includes a controller 312 that allows the operator to select the rotational speed of one or both of the polishing head 306 and turntable 308, as well as the downward force applied to the polishing head 306. The operator can also control process conditions via the controller 312, including, for example, the flow rate of the slurry supplied during polishing, the composition of the polishing slurry, the polishing process time, and the polishing process temperature.

[0031] During operation, wafer W is positioned between backing film 302 and polishing pad 310 within SSP assembly 300 and mounted on polishing head 306. Polishing head 306 moves vertically downward to increase the polishing pressure applied to wafer W by polishing head 306. Polishing slurry, such as intermediate polishing slurry or finishing polishing slurry, is applied to polishing pad 310 for polishing interaction between polishing pad 310 and the front surface of wafer W. The front surface of wafer W is polished by rotating polishing head 306 and turntable 308. Specifically, the rotating polishing head 306 and turntable 308 cause polishing slurry to act between polishing pad 310 and the front surface of wafer W to remove material from the front surface of wafer W, thereby producing a flatter and / or smoother surface. The target surface configuration (e.g., desired flatness or smoothness) of the wafer W can be achieved by adjusting the polishing process conditions via the controller 312. These polishing process conditions include, for example, the rotational speed of one or both of the polishing head 306 and the turntable 308, the polishing pressure applied by the polishing head 306, the flow rate of the polishing slurry, the composition of the polishing slurry, the polishing process time, and the polishing process temperature.

[0032] Referring back to Figure 1, after polishing the substrate wafer 102 to obtain a polished wafer, process 100 continues at step 104, where the surface configuration of the polished wafer is measured. The polished wafer may be cleaned prior to measurement, if necessary. Example cleaning operations include wet scrubbing or rotary cleaning. Wet scrubbing may involve contacting the polished wafer with an SC-1 cleaning solution (i.e., ammonium hydroxide and hydrogen peroxide) at a high temperature (e.g., from about 50°C to about 80°C), if necessary. Rotary cleaning involves contact with an HF solution and ozone water and can be performed at room temperature.

[0033] Generally, the surface configuration of a polished wafer is measured to determine whether the polished wafer has acceptable wafer parameters. "Wafer parameters" are generally understood to refer to the parameters or quantities used to evaluate the quality of a polished wafer and, more specifically, whether the wafer is suitable for use in device manufacturing. For example, polished wafers are commonly used in the production of integrated circuit (IC) chips on which printed circuit systems are printed. The circuit systems are miniaturized and printed onto the wafer surface as identical integrated circuits ("dies") in a multi-stage manufacturing process. Specifically, the process includes various stages of electron beam lithography or photolithography steps ("lithography") and chemical or physical processing steps (e.g., CMP, etching, and passivation). At each stage, new patterned layers are added to the wafer surface, or existing layers are modified. Precise alignment of layers ("overlap") is crucial to the final performance of the chip. Evaluating one or more wafer parameters can help determine whether there is a risk of manufacturing overlap errors during the manufacturing process of the polished wafer. Identifying wafer parameters indicating potential overlay errors before irreversible lithography occurs helps reduce manufacturing costs and salvage wafers that can be repolished to meet target specifications. In this regard, if the polished wafer measured at step 104 is determined to have one or more unacceptable wafer parameters, step 102 can be repeated before proceeding to step 106. For example, the process conditions during polishing using the DSP assembly 200 and / or SSP assembly 300 can be adjusted as described above to obtain acceptable wafer parameters.

[0034] Conventional metrology tools capable of determining wafer geometry (e.g., KLA-Tencor WaferSight or WaferSight2; Milpitas, California) can be used to measure surface configuration and determine one or more wafer parameters (e.g., shape and / or flatness) of a polished wafer. Shape is the long-wavelength component of the wafer geometry in the chucked state, defined as the deviation of the wafer's intermediate surface from the best-fit intermediate surface reference plane. It can be characterized as a global parameter, such as twist, the sum of the maximum positive and negative deviations relative to the best-fit plane, and the bow – the distance between the surface at the center of the wafer and the best-fit plane. Flatness is the variation of the wafer thickness relative to the reference plane. It can be characterized as a global parameter, such as the Global Backside Ideal Plane / Range (GBIR), or a local parameter, such as the Site Backside Ideal Plane / Range (SBIR) or the Site Frontside Minimum Squared Focal Plane Range (SFQR). The surface configuration near the outer edges of the wafer may also deteriorate during polishing. As used herein, "near the edge" refers to the portion of a wafer near its outer edge. For example, for a 300 mm diameter wafer, the near-edge portion can be defined as the portion of the wafer beginning at a radial distance of approximately 120 mm from the wafer's central axis. Parameters characterizing the surface configuration of the polished wafer at the near-edge portion (also referred to as "near-edge surface configuration") can be used to assess whether the near-edge portion of the wafer is suitable for device fabrication. For example, "edge roll-off" can be observed to determine if there is an unacceptable reduction in the thickness configuration at the near-edge portion of the wafer. Edge roll-off can be calculated using the conventional metrology tools described herein and can also be referred to as "roll-off amount". Other parameters can also be used to assess the near-edge quality of the wafer, such as the edge-to-front minimum square focal plane range (ESFQR), and can be determined using conventional metrology tools as described herein.

[0035] After measuring the polished wafer at step 104 and determining that the polished wafer has acceptable wafer parameters, process 100 continues at step 106, where a material layer is deposited and / or grown on the surface of the polished wafer. For example, the material layer can be deposited on the polished wafer using chemical vapor deposition (CVD) processes such as epitaxial CVD or polycrystalline CVD. However, various processes can be performed to deposit and / or grow a material layer on the polished wafer, and the invention is not limited to any of the specific processes described herein.

[0036] Referring to Figure 4, a partial cross-section of an example system for depositing a material layer on a polished wafer is schematically shown, and generally indicated at 400. In this example, system 400 is a vapor-phase epitaxial reactor 400. Reactor 400 is shown as a single-wafer reactor; however, alternative reactors 400 that can operate with multiple wafers are carefully considered and are within the scope of this invention. Examples of systems suitable for use as reactor 400 for epitaxial deposition include the EPI Centura reactor supplied by Applied Materials.

[0037] Reactor 400 includes chamber 402. Gas manifold 403 supplies an inlet stream 404 of process gas (e.g., silane or silane chloride) into chamber 402. The process gas passes through chamber 402 and exits as outlet gas 406. Polished wafer W is positioned within chamber 402. Support 408 is disposed within chamber 402 and supports wafer W during deposition. Support 408 is suitably constructed of opaque graphite coated with silicon carbide, but other materials are carefully considered.

[0038] Reactor 400 also includes a heating element 410 that supplies heat to chamber 402 to increase the temperature of elements within chamber 402, such as process gases, support 408, and / or wafer W. Non-limiting examples of the heating element 410 include high-intensity lamps, resistance heaters, and / or inductive heaters. The heating element 410 is suitably located in the portion of reactor 400 outside chamber 402. The interior of chamber 402 may be isolated from other parts of reactor 400 by first walls 412 and second walls 414. First and second walls 412 and 414 are typically made of a transparent material to allow radiated heating light to enter chamber 402 and onto the wafer (and / or the support 408 supporting the wafer). For example, first and second walls 412 and 414 may be made of transparent quartz. Quartz is generally transparent to infrared and visible light and is chemically stable under the reaction conditions of the deposition reaction.

[0039] The reactor 400 also includes a controller 416, which allows the operator to select and control the process conditions of the reactor 400 during the deposition process. For example, the operator can control process conditions via the controller 416, such as the flow rate of the inlet stream 404 supplied to the chamber 402, the formulation of the gas supplied to the inlet stream 404, the deposition process time, the deposition process temperature, and the rotational speed of the support 408 during deposition.

[0040] During operation, a cleaning gas, such as hydrogen or a mixture of hydrogen and hydrogen chloride, may be introduced into chamber 402 as inlet stream 404 prior to the deposition process. The cleaning gas contacts the front surface of wafer W (i.e., the surface facing away from the support 408) to preheat and clean the front surface of wafer W. In some instances, the cleaning gas removes native oxide from the front surface, thereby allowing the deposited layer to grow continuously and uniformly on the surface during subsequent deposition steps. The process continues by introducing a deposition gas, such as a vaporized silicon source gas (e.g., silane or silane chloride), as inlet stream 404 into chamber 402 after cleaning the front surface of wafer W. The deposition gas contacts the front surface of wafer W to deposit and / or grow a material (e.g., silicon) layer on the front surface. The support 408 rotates wafer W during the process to allow the epitaxial layer to grow uniformly on the front surface. The target thickness configuration of the material layer deposited and / or grown on the surface of the wafer W can be achieved by adjusting the deposition process conditions via the controller 416. These deposition process conditions include, for example, the flow rate of the inlet flow 404 of the gas supplied to the chamber 402 during cleaning and / or deposition, the formulation of the gas supplied in the inlet flow 404 during cleaning and / or deposition, the cleaning and / or deposition process time, the cleaning and / or deposition process temperature, and the rotational speed of the support 408 during cleaning and / or deposition.

[0041] Referring back to Figure 1, after step 106, where a material layer is deposited on the polished wafer, process 100 continues at step 108, where the surface configuration of the epitaxial wafer is measured. As used herein, "epitaxy wafer" refers to a polished wafer that has undergone subsequent deposition steps of depositing and / or growing a material layer on its surface. As described above, various deposition processes are carefully considered for depositing and / or growing material layers, and epitaxial wafers within the scope of this invention encompass wafers having a material layer formed by any deposition process known in the art. Furthermore, the measurement of the surface configuration of the epitaxial wafer at step 108 can be performed using conventional metrology tools and may involve determining one or more wafer parameters (e.g., flatness) of the epitaxial wafer used for the measurements of the polished wafer at step 104 as described above. For example, the wafer flatness parameters of epitaxial wafers such as GBIR, SFQR, SBIR and ESFQR can be determined when measuring the surface configuration of the epitaxial wafer in step 108.

[0042] If the epitaxial wafer does not possess the acceptable parameters for device manufacturing determined at step 108, the wafer must be discarded because it has undergone irreversible processing and cannot be salvaged. Since the parameters of the polished wafer, determined to be acceptable before deposition step 106, are measured at step 104, the unacceptable parameters of the epitaxial wafer measured at step 108 are attributed to the process conditions during deposition step 106. The conventional method therefore attempts to minimize or prevent unacceptable parameters in the epitaxial wafer by controlling the process conditions during deposition step 106 (e.g., the process conditions described above). A disadvantage associated with this technique is that necessary adjustments are not confirmed until at least one (and usually several) epitaxial wafers have been observed to have unacceptable parameters. This leads to unacceptable yield losses. Yield losses continue to increase because confirmed adjustments are not made until more wafers have undergone deposition step 106. Furthermore, it has been observed that necessary adjustments to improve the yield of acceptable epitaxial wafers may be difficult to identify. This is because there may be very little, or even no, direct correlation between the thickness configuration of the deposited material layer and the wafer parameters obtained from epitaxial wafers. In fact, the acceptability of the wafer parameters of epitaxial wafers often depends on whether the surface configuration of the polished wafer matches the thickness configuration of the material layer deposited and / or grown on the epitaxial wafer.

[0043] Referring to Figure 5, an example process 500 for producing epitaxial wafers with controlled flatness is shown. At step 502, one or more epitaxial semiconductor wafers are measured to determine the epitaxial deposition layer configuration. Epitaxial wafers can be produced using the large-scale process 100 shown in Figure 1. For example, an epitaxial wafer is produced from a polished substrate wafer (e.g., using the DSP assembly 200 shown in Figure 2 and / or the SSP assembly 300 shown in Figure 3), and the epitaxial wafer then undergoes a deposition process (e.g., using the reactor 400 shown in Figure 4). The epitaxial deposition layer configuration determined by measuring the epitaxial wafer at step 502 can be the thickness configuration of the deposited material layer. The thickness configuration of a material layer can be determined by measuring the thickness configuration of a polished wafer before material deposition (e.g., before the deposition of an epitaxial layer) and the thickness configuration of an epitaxial wafer after material deposition, and by subtracting the thickness of the polished wafer from the thickness of the epitaxial wafer. Any suitable method available to those skilled in this art can be used to measure the thickness configuration of the polished and / or epitaxial wafers, including, for example, conventional optical interferometry or metrology tools as described above. Based on the measured thickness configuration of the respective wafer, wafer parameters such as flatness parameters (e.g., GBIR, SBIR, SFQR, and ESFQR) of the polished and / or epitaxial wafers can be determined.

[0044] Measuring the epitaxial wafer at step 502 includes measuring a single epitaxial wafer and determining the thickness configuration of the material deposited on the single epitaxial wafer. Alternatively, measuring the epitaxial wafer at step 502 may include measuring multiple (i.e., two or more) epitaxial wafers and determining the thickness configuration of the material deposited on the multiple epitaxial wafers. In the example where multiple epitaxial wafers are measured at step 502, the average thickness configuration may be determined based on the thickness configuration determined for each of the epitaxial wafers being measured.

[0045] Furthermore, in the example where multiple epitaxial wafers are measured at step 502, each of the multiple epitaxial wafers has been appropriately produced using the same epitaxial equipment (e.g., reactor 400). In this regard, the average thickness configuration determined from the multiple epitaxial wafers can indicate the average thickness configuration produced by the epitaxial equipment. Additionally, the multiple epitaxial wafers measured at step 502 may each have been processed in the epitaxial equipment within a specific process time window. This process time window can be a time window during which the conditions in the epitaxial equipment are substantially constant. For example, the process time window can be one day, several days, or one week. When the conditions of the epitaxial equipment change, a new process time window can begin, and a new set of epitaxial wafers can be measured at step 502 to determine the thickness configuration produced under the changed process conditions. For example, the new process time window can begin when a new support (e.g., support 408 of reactor 400 shown in Figure 4) is installed.

[0046] Process 500 continues at step 504, where the substrate wafer is polished. Step 504 may include the same polishing operation described above for step 102 of process 100. For example, step 504 may include polishing the substrate wafer using the DSP assembly 200 (shown in FIG. 2) and / or SSP assembly 300 (shown in FIG. 3) as described above. The substrate wafer polished at step 504 is a different wafer from the epitaxial wafer measured at step 502. The polished wafer obtained after step 504 is measured at step 506. Step 506 may include the same measurement operation described above for step 104 of process 100. For example, step 506 may include measuring the surface configuration of the polished wafer using conventional metrology tools and determining one or more parameters of the polished wafer as described above.

[0047] At step 508, the predicted epitaxial surface configuration of the polished wafer obtained in step 504 is generated by comparing the surface configuration of the polished wafer measured in step 506 with the thickness configuration of the epitaxial deposited layer determined by measuring the one or more epitaxial wafers in step 502. The comparison at step 508 may include stacking or superimposing the epitaxial deposited layer configuration determined in step 502 onto the surface configuration of the polished wafer measured in step 506. For illustration, FIG6 shows a schematic cross-section of a polished wafer 600, which includes a front surface 602 and an epitaxial deposited layer 604 with a determined thickness configuration superimposed on the front surface 602. The top surface 606 of the wafer 600 has a predicted surface configuration, which is the result of the surface configuration of the front surface 602 and the determined thickness configuration of the epitaxial deposited layer 604 superimposed on the front surface.

[0048] Referring back to Figure 1, at step 510, the predicted post-epitaphing parameters of the polished wafer obtained in step 504 are determined based on the comparison at step 508. The predicted post-epitaphing parameters can be determined based on the predicted surface configuration of the epitaxially deposited polished wafer, which is generated by stacking an epitaxial deposition layer on the surface of the polished wafer. For example, the predicted post-epitaphing parameters can be determined based on the predicted surface configuration of the top surface 606 of the wafer 600 shown in Figure 6. The predicted post-epitaphing parameters may include the parameters described above, such as flatness parameters including one or more of SBIR, GBIR, and SFQR. However, any other predicted post-epitaphing parameters can be determined at step 510 based on the comparison at step 508.

[0049] The predicted epitaxial parameters can also be predicted edge-near parameters. Predicted edge-near parameters can be, for example, the predicted ESFQR after epitaxial growth or the predicted thickness variation along the edge-near configuration of the epitaxial wafer. The predicted edge-near parameters can be determined at step 510 based on the predicted edge-near surface configuration generated at step 508. The predicted edge-near surface configuration can be generated at step 508 by comparing the edge-near surface configuration of the polished wafer measured at step 506 with the edge-near configuration of the epitaxial deposited layer determined at step 502. The comparison of edge-near configurations can include comparing the edge-near thickness configuration of the epitaxial deposited layer with parameters of the edge-near surface configuration of the polished wafer (e.g., maximum edge-near thickness, minimum edge-near thickness, or edge roll-off).

[0050] Once the predicted post-epidural parameters are determined at step 510, the polished wafers can be classified for further processing. Specifically, the polished wafers are classified based on whether the predicted post-epidural parameters indicate that subsequent epitaxial processes using the epitaxial equipment producing the epitaxial deposit configuration will produce high-quality wafers for further equipment manufacturing. For example, step 510 may include determining whether the predicted post-epidural parameters are within predetermined thresholds that set limits for acceptable post-epidural parameters or meet predetermined specifications for acceptable post-epidural parameters. For example, post-epidural parameters may be flatness parameters (e.g., SBIR, GBIR, SFQR, ESFQR, and / or thickness variation near the edge), and step 510 may include determining whether the predicted post-epidural flatness parameters meet predetermined flatness specifications (e.g., meet predetermined specifications for acceptable SBIR, GBIR, SFQR, ESFQR, and / or thickness variation near the edge). If the predicted post-epidural parameters indicate that the polished wafer will have acceptable parameters and quality after the epitaxial process in the epitaxial equipment (e.g., the predicted post-epidural parameters are within predetermined thresholds or meet predetermined parameter specifications), then the polished wafer can undergo the epitaxial process using the epitaxial equipment at step 512. For example, reactor 400 (shown in Figure 4) can be used to deposit and / or grow a material layer on the polished wafer, wherein at step 502 the epitaxial deposition layer configuration is determined based on the epitaxial wafer produced by reactor 400.

[0051] In some cases, the predicted post-epitaxy parameters indicate that the polished wafer will have unacceptable flatness after the epitaxial process in the epitaxial equipment. For example, it can be determined at step 510 that the predicted post-epitaxy parameters are not within a predetermined threshold or do not meet a predetermined parameter specification (e.g., the predicted post-epitaxy flatness parameter does not meet a predetermined flatness specification). Then, at step 514, the predicted post-epitaxy parameters are used to adjust the polishing process conditions for obtaining the polished wafer in step 504. The polishing process conditions can be adjusted as described above for the DSP assembly 200 and the SSP assembly 300. In the DSP assembly 200 (Figure 2), for example, polishing process conditions can be adjusted at step 514, such as the rotational speed of one or both of polishing heads 202 and 206, the polishing pressure between polishing pads 210 and 214 and the corresponding surfaces of the wafer W, the flow rate of the polishing slurry, the composition of the polishing slurry, the polishing process time, the polishing process temperature, the rotational speed of the carrier 216 during polishing, and / or the thickness of the carrier 216 used to increase or decrease the thickness of the gap G. In the SSP assembly 300 (Figure 3), for example, polishing process conditions can be adjusted at step 514, such as the rotational speed of one or both of polishing heads 306 and turntable 308, the polishing pressure applied by polishing head 306, the flow rate of the polishing slurry, the composition of the polishing slurry, the polishing process time, and / or the polishing process temperature.

[0052] The polishing process conditions can be adjusted at step 514 to account for specific unacceptable predicted post-epitaxy parameters determined at step 510. For example, the predicted post-epitaxy edge-near parameters determined at step 510 (e.g., predicted post-epitaxy ESFQR or predicted thickness variation along the edge-near configuration of the post-epitaxy wafer) may indicate that the polished wafer will have unacceptable edge-near flatness after epitaxy. In this example, it can be determined that one or more parameters of the edge-near surface configuration of the polished wafer (e.g., maximum edge-near thickness, minimum edge-near thickness, and / or edge roll-off) do not match the edge-near thickness configuration of the epitaxially deposited layer. In this regard, the polishing process conditions of the polishing operation used at step 504 can be adjusted to control the parameters of the edge-near surface configuration of the polished wafer so that the edge-near surface configuration better matches the edge-near thickness configuration of the epitaxially deposited layer. For example, the polishing process conditions can be adjusted to control the edge roll-off of the polished wafer. Alternatively, polishing process conditions can be adjusted to control other parameters of the surface configuration near the edge. For example, polishing process conditions can be adjusted to control the maximum and / or minimum thickness of the surface configuration near the edge of the polished wafer. The parameters of the surface configuration near the edge (e.g., edge roll-off, maximum or minimum thickness near the edge) can each be controlled to target parameters that better match the thickness configuration of the epitaxial deposited layer near the edge.

[0053] After adjusting the polishing process conditions based on the predicted post-epidural parameters at step 512, step 504 is repeated. In some instances, step 504 can be repeated under the adjusted polishing process conditions to repolish the polished wafer obtained at step 504 and measured at step 506. Alternatively, step 504 can be repeated under the adjusted polishing process conditions to polish one or more substrate wafers other than the previously polished and measured wafers. After repeating step 504, steps 506 through 510 may be repeated as needed.

[0054] Referring to Figure 7, a block diagram of an example system 700 for controlling the flatness of an epitaxial wafer according to process 500 is shown. System 700 includes a control unit 702 connected to one or more polishing assemblies 704 and one or more measurement devices 706. The polishing assembly 704 may be a double-sided polishing assembly, such as a DSP assembly 300 (shown in Figure 2), or a single-sided polishing assembly, such as an SSP assembly 300 (shown in Figure 3). The one or more measurement devices 706 may be, for example, conventional metrology tools described above.

[0055] The control unit 702 may be any known computing device or computer system and includes one or more processors 708 and memory regions 710. The processor 708 executes instructions stored in the memory regions 710. As used herein, the term "processor" means a central processing unit, microprocessor, microcontroller, reduced instruction set computing (RISC) circuit, application-specific integrated circuit (ASIC), logic circuit, and any other circuit or processor capable of performing the functions described herein. These are merely examples and are therefore not intended to limit the definition and / or meaning of the term "processor" in any way. Furthermore, one or more processors 708 may be in a single computing device or a plurality of computing devices operating in parallel.

[0056] The memory region 710 stores, for example, processor-executable instructions used to receive and process input from the measurement device 706, and to control the process conditions of the polishing assembly 704 based on the processed input received from the measurement device 706. The memory region 710 may include (but is not limited to) hardware suitable for storing and / or retrieving processor-executable instructions and / or data for any computer operation. The memory region 710 may include, for example, random access memory (RAM) such as dynamic RAM (DRAM) or static RAM (SRAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and non-volatile RAM (NVRAM). Furthermore, the memory region 710 may include multiple storage units such as hard disks or solid-state drives in a redundant array of low-cost disks (RAID) configuration. The memory region 710 may include a storage area network (SAN) and / or network attached storage (NAS) system. In some embodiments, memory region 710 includes memory integrated into control unit 702. For example, control unit 702 may include one or more hard drives as memory region 710. Memory region 710 may also include memory external to control unit 702 and accessible by a plurality of computing devices. The above memory types are merely examples and therefore do not limit the types of memory that can be used to store processor-executable instructions and / or data.

[0057] The control unit 702 also includes at least one media output component 712 for presenting information to a user. The media output component 712 is any component capable of conveying information to a user. In some embodiments, the media output component 712 includes an output adapter, such as a video adapter and / or an audio adapter. The output adapter is operatively connected to the processor 708 and operatively connected to an output device, such as a display device (e.g., a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), or an "e-ink" display) or an audio output device (e.g., a speaker or a headset). In some embodiments, at least one of these display devices and / or audio devices is included in the media output component 712.

[0058] The control unit 702 may also include an input device 714 for receiving input from a user. The input device 714 may include, for example, a keyboard, pointing device, mouse, stylus, touch-sensitive panel (e.g., touchpad or touchscreen), gyroscope, accelerometer, position detector, or audio input device. For example, a single component such as a touchscreen may serve as both an output device and an input device 714 for the media output component 712.

[0059] The control unit 702 may also include a communication interface 716, which can be communicatively connected to one or more remote devices. The communication interface 716 may include, for example, a wired or wireless network adapter or wireless data transceiver for use with mobile phone networks (e.g., GSM, 3G, 4G, or Bluetooth) or other mobile data networks (e.g., WiMAX).

[0060] Control unit 702 receives measurement data from the polished wafer and the epitaxial wafer from the self-measuring device 706. Based on this measurement data, control unit 702 (e.g., via processor 708) generates a predicted epitaxial surface configuration of the polished wafer and determines the predicted epitaxial parameters, as described above. Control unit 702 can also determine, based on the predicted epitaxial parameters, adjustments to the process conditions of one or more of the polishing assemblies 704 that should be made. Control unit 702 can then transmit a signal corresponding to the determined adjustment to the polishing assembly 704. Polishing assembly 704 then performs the adjustment before polishing subsequent wafers.

[0061] Compared to conventional methods for producing epitaxial wafers, the method of the present invention has several advantages. By comparing the determined epitaxial deposition layer configuration with the surface configuration of the polished wafer before epitaxy, the wafer parameters of the post-epitaxy polished wafer can be predicted, and these wafer parameters can be used to determine whether a high-quality epitaxial wafer will be produced. Unacceptable parameters of the post-epitaxy polished wafer can be identified before irreversible processing occurs, allowing for wafer salvage and reprocessing. Therefore, manufacturing costs and yield losses associated with low-quality epitaxial wafers can be significantly reduced. Furthermore, polishing process conditions can be adjusted to consistently produce polished wafers with a surface configuration that better matches the subsequent deposition material configuration, thereby further increasing yield and reducing manufacturing costs associated with low-quality epitaxial wafers. [Example] []

[0062] Referring to Figure 8, a scatter plot shows the yield of predicted post-epitaxy parameters compared to high-quality epitaxial wafers. In this example, the predicted post-epitaxy parameters are the predicted thickness variation along the configuration near the edge of the epitaxial wafer. The predicted thickness variation is determined by matching the surface configuration near the edge of the polished wafer with the thickness configuration near the edge of the epitaxial deposit. Yield is determined based on acceptable ESFQR parameters of the epitaxial wafer. As shown in Figure 8, the predicted thickness variation parameters determined before epitaxy demonstrate a good correlation with acceptable ESFQR parameters of the epitaxial wafer. These results indicate that predicted post-epitaxy parameters can be used to produce high-quality epitaxial wafers and improve yield.

[0063] Referring to Figure 9, a scatter plot shows the yield of epitaxial wafers compared to the edge roll-off of polished wafers used to produce epitaxial wafers, with and without predicted post-epitaxy parameters. In this example, the predicted post-epitaxy parameters are the predicted thickness variation along the edge-near configuration of the epitaxial wafer. The predicted thickness variation is determined by matching the surface configuration near the edge of the polished wafer to the thickness configuration near the edge of the epitaxially deposited layer. Yield is determined based on acceptable ESFQR parameters for the epitaxial wafer and increases when using predicted post-epitaxy parameters. Specifically, yield increases for all epitaxial wafers and is independent of edge roll-off. Prior art processes control substrate edge roll-off to compensate for epitaxial processes with higher deposition rates near the wafer edges. These processes assume that edge roll-off needs to be within a narrow range to produce high-quality epitaxial wafers. Figure 9 shows that the improved yield using predicted epitaxial parameters applies even to epitaxial wafers produced from polished wafers with previously considered unacceptable edge roll-off. Therefore, by matching the surface configuration of the polished wafer to the configuration of the epitaxial deposited layer, a wider process window for edge roll-off control is achieved.

[0064] When describing elements of the present invention or embodiments thereof, the articles "a / an" and "the / said" are intended to indicate the presence of one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that additional elements may be present in addition to the listed elements. Terms indicating a particular orientation (e.g., "top," "bottom," "side," "downward," "upward," etc.) are used for convenience of description and do not require any particular orientation of the described items.

[0065] Since various changes can be made to the above construction and methods without departing from the scope of the invention, it is intended that all contents included in the above description and shown in the drawings should be interpreted as illustrative rather than restrictive.

[0066] 100: Manufacturing Process 102: Polishing 104: Steps 106: Steps 108: Steps 200: Dual-sided polished assembly 202: First polishing head 204: First shaft 206: Second polishing head 207: Second shaft 208: First board 210: First polishing pad 212: Second board 214: Second polishing pad 216: Generally circular carrier plate 218: Controller 300: Single-sided polishing assembly 302: Backing film 304: Retaining ring 306: Polishing head 308: Turntable 310: Polishing Pad 312: Controller 400: Vapor phase epitaxial reactor 402: Chamber 403: Gas Manifold 404: Inbound Flow 406: Outlet Gas 408: Support 410: Heating element 412: First Wall 414: The Second Wall 416: Controller 500:Process 502: Steps 504: Steps 506: Steps 508: Steps 510: Steps 512: Steps 514: Steps 600: Polished wafer 602: Front surface 604: Epitaxial Deposition Layer 606: Top surface 700: System 702: Control Unit 704: Polishing Assembly 706: Measuring device 708: Processor 710: Memory area 712: Media Output Component 714: Input device 716: Communication Interface G: Gap W: Wafer

Claims

1. A method for producing an epitaxial semiconductor wafer, the method comprising: a) measuring one or more first semiconductor wafers having an epitaxial layer deposited thereon via at least one measuring device in communication with a controller to determine an epitaxial deposition layer configuration produced by an epitaxial device; b) polishing the second semiconductor wafer using a polishing assembly before depositing the epitaxial layer onto a second semiconductor wafer, the polishing assembly being in communication with the controller, wherein the controller controls the polishing of the second semiconductor wafer according to one or more process conditions; c) measuring the polished second semiconductor wafer via the at least one measuring device to determine a surface configuration of the polished second semiconductor wafer; d) generating a predicted epitaxial surface configuration of the polished second semiconductor wafer by comparing the determined surface configuration of the polished second semiconductor wafer with the determined epitaxial deposition layer configuration produced by the epitaxial device; e) determining a predicted epitaxial parameter based on the predicted epitaxial surface configuration. f) Determine one or more adjustments to the process conditions of the polishing assembly via the controller and based on the predicted epitaxial parameters; and g) Adjust one or more process conditions of the polishing assembly via the controller and based on the determined adjustments to the process conditions.

2. The method of claim 1, wherein the one or more process conditions include a polishing pressure, a composition of a polishing slurry, a polishing slurry flow rate, a polishing process time, a polishing process temperature, a rotational speed of a polishing head of the polishing assembly, a rotational speed of a carrier of the polishing assembly, or a rotational speed of a turntable of the polishing assembly.

3. The method of claim 1 further includes, after adjusting the process conditions of the polishing assembly, using the polishing assembly to polish the second semiconductor wafer.

4. The method of claim 3 further includes using the epitaxial device to deposit an epitaxial deposition layer on the polished second semiconductor wafer.

5. The method of claim 1, wherein the polishing assembly includes a double-sided polishing assembly, and wherein the one or more process conditions include a thickness of a gap between a first polishing head and a second polishing head of the double-sided polishing assembly, wherein the thickness of the gap is defined by a thickness of a carrier plate of the double-sided polishing assembly.

6. The method of claim 1, wherein the one or more process conditions comprise a composition of a polishing slurry and a combination of at least one other process condition.

7. The method of claim 6, wherein the at least one other process condition includes a polishing pressure, a polishing slurry flow rate, a polishing process time, a polishing process temperature, a rotational speed of a polishing head of the polishing assembly, or a rotational speed of a turntable of the polishing assembly.

8. The method of claim 1, wherein measuring the one or more first semiconductor wafers having an epitaxial layer deposited thereon to determine the configuration of the epitaxial deposition layer includes measuring a thickness distribution of an epitaxial layer deposited on a single first semiconductor wafer.

9. The method of claim 1, wherein measuring the one or more first semiconductor wafers having an epitaxial layer deposited thereon to determine the configuration of the epitaxial deposition layer includes measuring the thickness distribution of one of the epitaxial layers deposited on the multiple first semiconductor wafers.

10. The method of claim 1, wherein measuring the polished second semiconductor wafer to determine the surface configuration of the polished wafer includes determining the surface configuration near an edge of the polished second semiconductor wafer, and wherein the predicted epitaxial parameter is a predicted epitaxial edge near parameter.

11. The method of claim 1, wherein measuring one or more first semiconductor wafers having an epitaxial layer deposited thereon to determine the configuration of the epitaxial deposited layer includes determining a thickness configuration of an epitaxial deposited layer produced by the epitaxial equipment, and wherein the predicted epitaxial parameters include a flatness parameter of at least one of SBIR, GBIR, SFQR and ESFQR.

12. The method of claim 1 further includes polishing a third semiconductor wafer after adjusting the one or more process conditions of the polishing assembly.

13. A method for producing an epitaxial semiconductor wafer, the method comprising: a) measuring one or more first semiconductor wafers having an epitaxial layer deposited thereon via at least one measuring device in communication with a controller to determine a thickness configuration of an epitaxial deposited layer produced by an epitaxial device; b) polishing the second semiconductor wafer using a polishing assembly in communication with the controller before depositing the epitaxial layer onto a second semiconductor wafer, the polishing assembly being controlled by the controller according to one or more process conditions; c) measuring the polished second semiconductor wafer via the at least one measuring device to determine a surface configuration near an edge of the polished second semiconductor wafer; d) determining a predicted epitaxial near-edge parameter of the polished second semiconductor wafer by comparing the determined surface configuration near the edge of the polished second semiconductor wafer with the determined thickness configuration produced by the epitaxial device. e) The controller determines whether the predicted epitaxial edge near parameters meet a predetermined parameter specification; and f) When the predicted epitaxial edge near parameters do not meet the predetermined parameter specification, the controller and based on the predicted epitaxial parameters determine one or more adjustments to the process conditions of the polishing assembly, and the controller and based on the determined one or more adjustments to the process conditions adjust one or more process conditions of the polishing assembly to control a parameter of the surface configuration near the edge of the polished second semiconductor wafer.

14. The method of claim 13, wherein the parameter of the surface configuration near the edge of the polished second semiconductor wafer includes an edge roll-off, a maximum thickness near the edge, or a minimum thickness near the edge.

15. The method of claim 13, wherein the one or more process conditions include a polishing pressure, a composition of a polishing slurry, a polishing slurry flow rate, a polishing process time, a polishing process temperature, a rotational speed of a polishing head of the polishing assembly, a rotational speed of a carrier of the polishing assembly, or a rotational speed of a turntable of the polishing assembly.

16. The method of claim 13 further includes, after adjusting the one or more process conditions of the polishing assembly, using the polishing assembly to polish the second semiconductor wafer or a third semiconductor wafer.

17. A method for producing an epitaxial semiconductor wafer, the method comprising: a) measuring one or more first semiconductor wafers having an epitaxial layer deposited thereon via at least one measuring device in communication with a controller to determine a thickness configuration of an epitaxial deposited layer produced by an epitaxial device; b) polishing the second semiconductor wafer using a polishing assembly before depositing the epitaxial layer onto a second semiconductor wafer, the polishing assembly being in communication with the controller, wherein the controller controls the polishing of the second semiconductor wafer according to one or more process conditions; c) measuring the polished second semiconductor wafer via the at least one measuring device to determine a surface configuration of the polished second semiconductor wafer; d) By means of the controller, the thickness configuration of the determined epitaxial deposit layer is superimposed on the determined surface configuration of the polished second semiconductor wafer to determine one of the predicted epitaxial parameters of the polished second semiconductor wafer, wherein the predicted epitaxial parameter includes a flatness parameter of at least one of SBIR, GBIR, SFQR and ESFQR; e) By means of the controller, it is determined whether the predicted epitaxial parameter meets a predetermined parameter specification; and f) When the predicted epitaxial parameter does not meet the predetermined parameter specification, by means of the controller and based on the predicted epitaxial parameter, one or more adjustments to the process conditions of the polishing assembly are determined, and by means of the controller and based on the determined adjustments to the process conditions, one or more process conditions of the polishing assembly are adjusted.

18. The method of claim 17, wherein the polishing assembly includes a dual-sided polishing assembly, the method further comprising using the dual-sided polishing assembly to polish the semiconductor wafer after adjusting the one or more process conditions of the dual-sided polishing assembly.

19. The method of claim 17 further comprises: when the predicted epitaxial parameters meet the predetermined parameter specifications, depositing an epitaxial deposition layer on the polished second semiconductor wafer using the epitaxial apparatus.

20. The method of claim 17, wherein the one or more process conditions include a polishing pressure, a composition of a polishing slurry, a polishing slurry flow rate, a polishing process time, a polishing process temperature, a rotational speed of a polishing head of the polishing assembly, a rotational speed of a carrier of the polishing assembly, or a rotational speed of a turntable of the polishing assembly.

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