Method and system of performing erasure code recovery

Abstract

A system and method for client- and network-based erasure code recovery are provided. In some embodiments, the method includes: receiving a retrieval command by a storage node; storing data specified by the retrieval command in the host's memory at the memory address specified by the retrieval command using remote direct memory access by the storage node; sending a response indicating that the retrieval command has been successfully executed by the storage node; and performing erasure code recovery by the host based on the data.

Description

Technical Field

[0001] One or more aspects in accordance with embodiments of the present disclosure relate to storage, and more particularly, to a system and method for erasure code recovery based on a client and a network. Prior Art

[0002] For bandwidth-intensive storage workloads, recovering lost data based on erasure codes may result in high overhead in a storage cluster (e.g., in a cluster of storage nodes). For distributed systems or scale-out systems where data may be sent over a network, such erasure code recovery overhead may increase. Erasure recovery based on a storage cluster may also result in high latency.

[0003] Aspects of the present disclosure relate to such an overall technical environment. Summary of the Invention

[0004] In some embodiments, erasure code recovery may be performed in a host or a client, rather than by storage nodes of a storage system (e.g., a storage cluster). The host may include a graphics processing unit (GPU), which may be used to perform erasure code recovery based on data blocks and parity blocks received from self-sustaining nodes when a storage node fails. In some embodiments, a capable network interface card (NIC) may perform erasure code recovery and store data (including the recovered data in the memory of the GPU), such that the failure of a node and the recovery of data are transparent to the GPU.

[0005] According to an embodiment of the present disclosure, a method is provided, the method including: receiving, by a storage node, a fetch command; storing, by the storage node, data specified by the fetch command in a memory address specified by the fetch command in the memory of a host using remote direct memory access; sending, by the storage node, a response indicating that the fetch command has been successfully executed; and performing, by the host, erasure code recovery based on the data.

[0006] In some embodiments, sending the fetch command includes sending the fetch command via a Transmission Control Protocol (TCP) socket.

[0007] In some embodiments, storing the data includes storing the data via remote direct memory access over Ethernet.

[0008] In some embodiments, storing data by a storage node includes using Remote Direct Memory Access over Converged Ethernet (RoCE) to store the data.

[0009] In some embodiments, an acquire command includes a first scatter-gather list of a first data block.

[0010] In some embodiments, an acquire command includes a first scatter-gather list of a parity block.

[0011] In some embodiments, a host includes a Graphics Processing Unit (GPU), and performing erasure code recovery includes performing erasure code recovery by the GPU.

[0012] In some embodiments, performing erasure code recovery includes: temporarily storing parity data in an area of a shared parity memory pool; and releasing the area of the shared parity memory pool when erasure code recovery is completed.

[0013] In some embodiments, a host includes a Network Interface Card (NIC), and performing erasure code recovery includes performing erasure code recovery by the NIC.

[0014] According to an embodiment of the present disclosure, a system is provided, the system including: a host including processing circuitry; and a storage node including processing circuitry, the processing circuitry of the storage node being configured to: receive an acquire command; store data specified by the acquire command in a memory address specified by the acquire command in the memory of the host using Remote Direct Memory Access; and send a response indicating that the acquire command has been successfully executed, wherein the processing circuitry of the host is configured to perform erasure code recovery based on the data.

[0015] In some embodiments, sending an acquire command includes sending the acquire command via a Transmission Control Protocol (TCP) socket.

[0016] In some embodiments, storing data includes storing data using Remote Direct Memory Access over Ethernet.

[0017] In some embodiments, storing data includes using Remote Direct Memory Access over Converged Ethernet (RoCE) to store the data.

[0018] In some embodiments, an acquire command includes a first scatter-gather list of a first data block.

[0019] In some embodiments, the fetch command includes a first scatter-gather list of parity blocks.

[0020] In some embodiments, the processing circuitry of the host includes a graphics processing unit (GPU), and performing erasure code recovery includes performing erasure code recovery by the GPU.

[0021] In some embodiments, performing erasure code recovery includes: temporarily storing parity data in an area of a shared parity memory pool; and releasing the area of the shared parity memory pool upon completion of erasure code recovery.

[0022] In some embodiments, the host includes a network interface card (NIC), and performing erasure code recovery includes performing erasure code recovery by the NIC.

[0023] According to an embodiment of the present disclosure, a system is provided, the system including: a host including a processing component; and a storage node including a processing component, the processing component of the storage node being configured to: receive a fetch command; store data specified by the fetch command in a memory address specified by the fetch command in the memory of the host using remote direct memory access; and send a response indicating that the fetch command has been successfully executed, wherein the processing component of the host is configured to perform erasure code recovery based on the data.

[0024] In some embodiments, the host includes a network interface card (NIC), and performing erasure code recovery includes performing erasure code recovery by the NIC. Brief Description of the Drawings

[0025] Referring to the specification, claims and drawings, these and other features and advantages of the present disclosure will be appreciated and understood, in the drawings: FIG. 1A shows a block diagram of a system according to an embodiment of the present disclosure, the system including a host connected to a storage system. FIG. 1B is an illustration of a fetch command and a corresponding destination memory area according to an embodiment of the present disclosure. FIG. 1C is an illustration of a response according to an embodiment of the present disclosure. FIG. 2A is a data layout diagram according to an embodiment of the present disclosure. FIG. 2B is an illustration of a remote direct memory access unit according to an embodiment of the present disclosure. FIG. 2C is an illustration of the header and tail of a remote direct memory access unit according to an embodiment of the present disclosure. FIG. 3A is a block diagram of a system including storage nodes according to an embodiment of the present disclosure. FIG. 3B is a diagram of the system shown in FIG. 3A in operation according to an embodiment of the present disclosure. FIG. 4 is a flowchart of a method according to an embodiment of the present disclosure. Embodiments

[0026] The following detailed description presented in conjunction with the accompanying drawings is intended as an illustration of exemplary embodiments of a client- and network-based erasure code recovery system and method provided in accordance with the present disclosure, and is not intended to represent the only form in which the present disclosure may be constructed or utilized. This description sets forth the features of the present disclosure in connection with the illustrated embodiments. However, it is to be understood that the same or equivalent functions and structures may be achieved by different embodiments that are also intended to be encompassed within the scope of the present disclosure. As indicated elsewhere herein, like element numbers are intended to indicate like elements or features.

[0027] Some file and object storage protocols may not support erasure code recovery on the application host or client (e.g., a data recovery operation for recovering data after a storage node failure). Such storage solutions may perform erasure code recovery on the local hardware system of the storage node before returning the data to the host, since all storage devices reside locally. However, such systems may not be able to handle node failures and may require each node to be fault-tolerant as an independent system, a requirement that may significantly increase complexity. For certain types of node-level erasure coding, performing erasure code recovery at the storage node may require high overhead, since (i) reconstruction causes network overhead; and (ii) the number of times of interacting with the data through the system network and hardware. Recovering data at the storage node may also significantly increase the latency caused by such recovery operations.

[0028] In some embodiments, the storage node overhead and the latency incurred during erasure code recovery can be reduced by shifting the data recovery burden to the application host (or the "client" of the data storage system). Such embodiments may further involve using a remote direct memory access (RDMA) protocol to place data directly into the application host memory, such as GPU memory. In some embodiments, data exchange protocols, such as the Amazon S3 protocol, can be extended to support reconstructing erasure-encoded data on the application host without explicit knowledge of the object data format. Such embodiments may provide (i) effective failure recovery of erasure-encoded data on the initiator or receiving host; (ii) effective failure recovery of erasure-encoded data using network components such as network interface cards (NICs) or switches; and (iii) methods for reducing the application overhead for handling erasure-encoded data. Some embodiments include methods for performing real-time erasure code recovery using network components.

[0029] For example, in some embodiments, erasure code recovery can be performed in the host or client rather than by the storage nodes of the storage system. The host may include a Graphics Processing Unit (GPU), which can be used to perform erasure code recovery based on data blocks and parity blocks received from the self-operating nodes when a storage node fails. In some embodiments, a capable network interface card (NIC) can alternatively perform erasure code recovery and store the data (including the recovered data in the memory of the GPU), such that the failure of the node and the recovery of the data are transparent to the GPU. The "data blocks" and "parity blocks" described herein are large amounts of data and large amounts of parity data, which may or may not be consistent with the "blocks" that can be defined for a storage device (e.g., physical blocks in a solid-state drive).

[0030] FIG. 1A shows a block diagram of a system including a host 100 connected to a storage system 102. FIG. 1B shows the data format of a request 105 (including a command, such as an S3 command) in some embodiments. In the illustrated example, the request 105 is a get command (a command used by the host to request data from the storage system). The request can be sent by the host to one of the storage nodes, and the one of the storage nodes can be designated as the "contact node" responsible for relaying certain communications (such as the request 105 and the response 130 (FIG. 1C; further detailed below)) between the host and other storage nodes. In the example of FIG. 1B, the host knows that a storage node (node 5, as shown in a further example below) has failed, and the get command includes a scatter-gather list 110 and a scatter-gather list 115 of parity data blocks (identified as "SGL-P1", "SGL-P2", and "SGL-PN" in FIG. 1B), and the scatter-gather list 110 includes list elements of data blocks (identified as "SGL-1", "SGL-2", and "SGL-N" in FIG. 1B). The parity data blocks are extracted so that the data that would normally be sent by the failed node can be recovered by the host, as further detailed below. A scatter-gather list is a list of the following elements: each of the elements includes a destination memory address, which can be an address in the host memory (e.g., the host graphics processing unit (GPU) memory 120) where the corresponding data will be stored using remote direct memory access. The data blocks can be stored in the GPU memory as shown, and the parity data blocks can be stored at the addresses identified by the scatter-gather list of parity data blocks in a shared parity memory pool 125 (which can also be located in the GPU memory), as further detailed below.

[0031] FIG. 1C shows the data format of the response 130 (e.g., an S3 response). After the data blocks and parity data blocks have been replicated to the host, the response can be sent to the host by the contact node (which can collect some of the data included in the response from other nodes) to indicate that the request has been successfully completed (e.g., returning the requested data to the host, or returning sufficient data and parity data for reconstructing the requested data). The response can include parity data (identified as "SGL-P1", "SGL-P2", and "SGL-PN" in FIG. 1C).

[0032] As described above, data transfer between the storage node and the host can be implemented using remote direct memory access (e.g., remote direct memory access over converged ethernet (RoCE)), or via another type of connection suitable for remote direct memory access (e.g., Infiniband TM). Request 105 and response 130 can be sent via a separate channel (e.g., via a Transmission Control Protocol (TCP) socket). FIG. 2A shows a way to layout data in the storage node (e.g., striped across nodes); FIG. 2A also shows that data blocks and parity data blocks retrieved from the storage node can be stored in the object memory of the host, and the parity data blocks can be stored in the parity memory of the host. The layout of the data in the host memory can be based on a scatter-gather list, as discussed in further detail below. As described above, the host can include a graphics processing unit (GPU) with dedicated memory (or "GPU memory"), which can be used by the host for data processing (e.g., implemented using data retrieved from the storage node). The GPU can also perform erasure code recovery, or as discussed in further detail below, erasure code recovery can be performed by other hardware (e.g., by an intelligent NIC). Data from five nodes (nodes 0 to 4) can be stored in stripes (the first stripe starts at address 0x10000000, the second stripe starts at address 0x10200000, and so on), and a portion of each stripe is initially missing because in the example of FIG. 2A, the sixth node (node 5) has failed. For this reason, parity data blocks can be stored in the shared parity memory pool 125, and the GPU reconstructs the data that would have been sent by the sixth node if the sixth node had not failed based on the data including the parity data blocks, and stores the data in the memory location where the sixth node would have stored the data if the sixth node had not failed. Once the erasure code recovery is complete, the GPU can release the portion of the shared parity memory pool 125 used to perform the erasure code recovery; then, this memory is available for other erasure code recovery operations.

[0033] Data transferred to the host via Remote Direct Memory Access (RDMA) can be encapsulated into blocks (e.g., including or consisting of such blocks) that can be referred to as "RDMA units". As shown in FIG. 2B, each RDMA unit may include a header 215, a data payload 220, padding 225, and a trailer 230. Each payload may include a portion of the amount of data specified by an element of one of the scatter-gather lists of request 105. The header 215 may include: an error code identifier (EC ID) or "reference ID" indicating which stripe the data payload 220 is a part of; a data offset and block size indicating where the data payload 220 will be stored in memory; an erasure code reconstruction identifier (ID) indicating which data will be recovered; and an operation identifier (OP ID) identifying the algorithm to be used for erasure code recovery. The trailer may also (optionally) include an erasure code identifier and, optionally, a cyclic redundancy check (CRC) character for verifying that the RDMA unit has been transmitted without error. In some embodiments, there is no trailer.

[0034] If the total amount of data requested by the host is not a multiple of the total payload size of an RDMA unit, padding 225 may be included in, for example, the last RDMA unit sent in response to request 105.

[0035] FIG. 3A is a block diagram of a host 100 connected to a plurality of storage nodes 310 via a network switch 315. The host includes a central processing unit (CPU) 312, a main memory 315 (connected to the CPU 312), a NIC 320 (which may be an intelligent NIC as shown), a GPU 325, and a GPU memory 330 (connected to the GPU 325). The NIC 320 may be connected to the main memory 315 and to the GPU memory 330, and the NIC 320 may be used to perform RDMA operations to write data to the main memory 315 and to the GPU memory 330. Each of the plurality of storage nodes 310 may be connected to the host 100 via one or more networks (e.g., Ethernet) (e.g., via one or more network switches 217). Each network node may include processing circuitry 335 (explicitly shown only in one of the storage nodes 310 for ease of illustration) and persistent storage (e.g., flash memory).

[0036] In operation, the GPU memory 330 can be partitioned to include an object memory 340 and a shared parity memory pool 125. When all storage nodes 310 are operational, a fetch request sent by the CPU 312 to a storage node 310 can cause each storage node to send data to the corresponding region of the object memory 340, where the data can be further processed by the GPU 325. If one of the storage nodes 310 has failed, each of the remaining operational storage nodes 310 can send data to (i) the corresponding region of the object memory 340, or (ii) (for storage nodes 310 storing parity data) to the shared parity memory pool 125. In such a case, the data placed in the object memory 340 by the storage nodes 310 can have one or more gaps (in the one or more memory regions specified by the scatter-gather list of data blocks) where the failed node would have originally placed data. The GPU 325 can then perform erasure code recovery based on the data in the object memory 340 and the shared parity memory pool 125. The shared parity memory pool 125 can be used as a temporary shared parity buffer because, as described above, once the erasure code recovery is complete, the buffer can be released for use in another erasure code recovery operation while the GPU 325 processes the data in the object memory 340. When each remote direct memory access unit is received, the NIC 320 can store the header 215 and the tail 230 in the main memory 315. When all headers 215 and tails 230 have been stored in the main memory 315, the host 100 can then infer that the transmission is complete (the absence of a header or tail can indicate that the node that was supposed to send the header or tail may have failed). A storage node 310 storing parity data can store parity data in the shared parity memory pool 125 in response to receiving a fetch command that includes a scatter-gather list of parity data blocks.

[0037] In some embodiments, erasure code recovery may be performed by dedicated hardware in, for example, the NIC 320 (in such embodiments, the NIC 320 may be referred to as a “smart NIC”), rather than by the GPU 325 that executes software for this purpose. In such embodiments, the host 100 (e.g., the CPU 312) may notify the NIC 320 that the storage node 310 has failed, and configure the NIC 320 to perform erasure code recovery to recover data that would normally have been generated by the failed storage node 310. Each inbound remote direct memory access unit may be received by the NIC 320, and the NIC 320 may perform erasure code recovery based on the data (including parity data) received by the NIC 320, and store in the object memory 340 (i) the (non-parity) data blocks received by the NIC 320 from the self-running storage node 310, and (ii) the data blocks recovered by the NIC 320 based on the data blocks and parity data blocks received by the NIC 320 from the self-running storage node 310. In such embodiments, there may be no shared parity memory pool 125 and the GPU 325 may not participate in erasure code recovery; furthermore, erasure code recovery may be transparent to the GPU 325, which may receive in the object memory 340 the same data that it would have received had no storage node 310 failed.

[0038] When sending the padding data 225, the padding data 225 may be addressed by the storage node 310 to a region of the host memory (e.g., a region of the main memory 315 or the GPU memory 330 allocated for this purpose), which may be referred to as the “padding data space” 345 (the “padding data space” 345 is shown outside the main memory 315 and outside the GPU memory 330 because the “padding data space” 345 may not necessarily be located within either of them). The CPU 312 and the GPU 325 may ignore (e.g., not read) the data in the padding data space 345.

[0039] FIG. 3B shows further details of the erasure code recovery process. When the host 100 knows that the storage node 310 (e.g., the fourth storage node, i.e., storage node 3) has failed, the host 100 programs the NIC 320 to perform erasure code recovery, e.g., by configuring the NIC 320 using the erasure code recovery table 350 as shown. The erasure code recovery table 350 may include: an error code identifier (EC ID) that identifies the input-output operation related to the data; an operation identifier (OP ID) that specifies the algorithm for performing data recovery (e.g., exclusive or (XOR) or Galois field); a stripe unit (or "block") identifier and the size of the stripe unit; a reconstruction identifier; and a buffer identifier that identifies the address in the object memory 340 where the reconstructed data will be stored. The NIC 320 (or the processing circuit 335 of the NIC) can then recover the data that the fourth storage node would have originally stored in the object memory 340 (e.g., using XOR or Galois field at 355), determine where the data will be stored in the object memory 340 according to the erasure code recovery table 350, and store the recovered data accordingly. When using XOR, the XOR of the available data (data from the nodes that have not failed and parity data) can be calculated to generate the data that would have been provided by the failed node.

[0040] FIG. 4 shows a flowchart of a method. In some embodiments, the method includes: at 405, receiving an acquisition command by a storage node; at 410, storing, by the storage node, the data specified by the acquisition command in a memory address specified by the acquisition command in the memory of a host using remote direct memory access; at 415, sending, by the storage node, a response indicating that the acquisition command has been successfully executed; and at 420, performing erasure code recovery by the host based on the data.

[0041] As used herein, "a part of" something means "at least some of" the thing, and thus may mean less than all of the thing or all of the thing. As such, "a part of" a thing includes the entire thing as a special case, i.e., the entire thing is an instance of a part of the thing. As used herein, when a second quantity is "within Y" of a first quantity X, it means that the second quantity is at least X - Y and the second quantity is at most X + Y. As used herein, when a second number is "within Y%" of a first number, it means that the second number is at least (1 - Y / 100) times the first number and the second number is at most (1 + Y / 100) times the first number. As used herein, the term "or" should be interpreted as "and / or", such that, for example, "A or B" means either "A" or "B" or "A and B".

[0042] The background provided in the Background section of this disclosure portion is included only to set the context and does not admit that the content of this portion is prior art. Any one of the components described or any combination of components (e.g., in any system diagram included herein) can be used to perform one or more of the operations of any flowchart included herein. Additionally, (i) the operations are exemplary operations and can involve various additional steps not explicitly covered, and (ii) the chronological order of the operations can vary.

[0043] As used herein, each of the terms "processing circuit" and "processing component" is meant to refer to any combination of hardware, firmware, and software for processing data or digital signals. Processing circuit hardware can include, for example, application specific integrated circuits (ASICs), general or special purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field programmable gate arrays (FPGAs). In a processing circuit as used herein, each function is performed by hardware configured (i.e., hardwired) to perform the function, or by more general hardware (e.g., a CPU) for executing instructions stored in a non-transitory storage medium. The processing circuit can be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. The processing circuit can include other processing circuits; for example, the processing circuit can include two processing circuits, an FPGA, and a CPU interconnected on a PCB.

[0044] As used herein, when a method (e.g., adjusting) or a first quantity (e.g., a first variable) is said to be "based on" a second quantity (e.g., a second variable), it means that the second quantity is an input to the method or affects the first quantity. For example, the second quantity can be an input to a function that calculates the first quantity (e.g., the only input or one of several inputs), or the first quantity can be equal to the second quantity, or the first quantity can be the same as the second quantity (e.g., stored at the same one or more locations in memory).

[0045] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish between individual elements, components, regions, layers or sections. Thus, without departing from the spirit and scope of the concept of the present invention, the first element, component, region, layer or section discussed herein may be referred to as the second element, component, region, layer or section.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the concept of the present invention. As used herein, the terms "substantially", "about" and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be known to those of ordinary skill in the art.

[0047] Unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" used herein are also intended to include the plural forms. It should be further understood that when the term "comprises and / or comprising" is used in this specification, it specifies the presence of the stated features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "at least one of..." when appearing after a series of elements modify the entire series of elements and not the individual elements of the series. In addition, when the embodiment of the concept of the present invention is described using "may", it refers to "one or more embodiments of the present disclosure". Additionally, the term "exemplary" is intended to mean an example or illustration. The terms "use", "using" and "used" as used herein may be considered synonymous with the terms "utilize", "utilizing" and "utilized", respectively.

[0048] It should be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, the element or layer can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or there can be one or more intervening elements or layers. In contrast, when an element or layer is referred to as being "directly" on, "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers.

[0049] Although exemplary embodiments of systems and methods for client- and network-based erasure code recovery have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it should be understood that the systems and methods for client- and network-based erasure code recovery constructed in accordance with the principles of this disclosure can be implemented differently than specifically described herein. The invention is also defined in the following claims and their equivalents.

[0050] 0, 1, 2, 3, 4, 5: Nodes 100: Host 102: Storage system 105: Request 110, 115: Scatter-gather list 120: Host graphics processing unit (GPU) memory 125: Shared parity memory pool 130: Response 215: Header 217: Network switch 220: Data payload 225: Padding / padded data 230: Tail 310: Storage node 312: Central processing unit (CPU) 315: Main memory / network switch 320: Network interface card (NIC) 325: Graphics processing unit (GPU) 330: GPU memory 335: Processing circuit 340: Object memory 345: Padded data space 350: Erasure code recovery table 355, 405, 410, 415, 420: Operations

Claims

1. A method for performing erase code recovery, comprising: The storage node receives a fetch command from the host, wherein the fetch command indicates a memory address in the host's memory; The storage node uses remote direct memory access to store the data specified by the acquisition command in the host's memory at the memory address specified by the acquisition command, wherein the data includes co-location data; based on the data including the co-location data stored by the storage node in the host's memory, the storage node sends a response to the host, wherein the response includes the memory address where the co-location data is stored; and the host performs the erase code recovery based on the data.

2. The method as described in claim 1, wherein receiving the acquisition command includes receiving the acquisition command via a Transmission Control Protocol (TCP) socket.

3. The method of claim 1, wherein storing the data includes storing the data via Ethernet using remote direct memory access.

4. The method of claim 1, wherein storing the data by the storage node includes storing the data using Remote Direct Memory Access over Converged Ethernet (RoCE).

5. The method as described in request 1, wherein the acquisition command includes a first distributed collection list of the first data block.

6. The method as described in request item 1, wherein the acquisition command includes a first scatter collection list of co-occurring bit blocks.

7. The method as described in request item 1, wherein: The host includes a graphics processing unit (GPU), and performing the erase code recovery includes the GPU performing the erase code recovery.

8. The method as described in claim 1, wherein performing the erase code recovery includes: The co-located data is temporarily stored in a region of the shared co-located memory pool, and the region of the shared co-located memory pool is released when the erase code recovery is completed.

9. A system for performing erase code recovery, comprising: A host computer includes processing circuitry; and a storage node includes processing circuitry, the processing circuitry of the storage node being configured to: receive a fetch command from the host computer, wherein the fetch command indicates a memory address in the host computer's memory; store data specified by the fetch command in the host computer's memory at the memory address specified by the fetch command using remote direct memory access, wherein the data includes co-location data; and send a response to the host computer based on the data including the co-location data stored by the storage node in the host computer's memory, wherein the response includes the memory address where the co-location data is stored, wherein the processing circuitry of the host computer is configured to perform the erase code recovery based on the data.

10. The system as described in claim 9, wherein receiving the acquisition command includes receiving the acquisition command via a Transmission Control Protocol (TCP) socket.

11. The system of claim 9, wherein the processing circuitry of the storage node for storing the data includes the processing circuitry of the storage node for storing the data via Ethernet using remote direct memory access.

12. The system of claim 9, wherein the processing circuitry of the storage node for storing the data includes the storage node's processing circuitry using Remote Direct Memory Access over Converged Ethernet (RoCE) to store the data.

13. The system as claimed in claim 9, wherein the acquisition command includes a first distributed collection list of the first data block.

14. The system as described in claim 9, wherein the acquisition command includes a first distributed collection list of co-occurring bit blocks.

15. The system as described in claim 9, wherein: The host's processing circuitry includes a graphics processing unit (GPU), and the execution of the erase code recovery includes the GPU performing the erase code recovery.

16. The system as described in claim 9, wherein performing the erase code recovery includes: The data is temporarily stored in a region of the shared co-location memory pool, and the region of the shared co-location memory pool is released when the erase code recovery is completed.

17. The system as described in claim 9, wherein: The host includes a network interface card (NIC); and the execution of the erase code recovery includes the network interface card performing the erase code recovery.

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