Electronic device

Abstract

An electronic device includes a heater and a sampling and holding circuit coupled to the heater. The sampling and holding circuit includes a sampling unit, a temporary storage unit, and a feedback unit. The sampling unit is used to receive data signals. The temporary storage unit has an input terminal and an output terminal, the input terminal being coupled to the sampling unit, and the output terminal being used to output a first signal. The feedback unit is coupled to the input and output terminals of the temporary storage unit. When the feedback unit is in an on state, the feedback unit feeds the first signal back to the input terminal.

Description

electronic devices The present disclosure relates to an electronic device, and more particularly to an inkjet head driving circuit manufactured using thin film transistor elements. Inkjet printers spray tiny dots of ink onto paper to create text or images. The smaller the dots, the more detailed the image. The inkjet system is the core of an inkjet printer, consisting primarily of an ink cartridge that stores ink and an inkjet head that releases the ink. Bubble-jet technology uses heat to boil the ink in the print head, generating bubbles. The pressure from the bubbles forces the ink from the print head onto the paper, where it cools to form a fixed image. Inkjet head driver circuits have traditionally been fabricated using a complementary metal-oxide-semiconductor (CMOS) process. However, using thin-film transistors (TFTs) offers cost advantages. While TFTs are suitable for large-area inkjet head driver circuits due to cost considerations, TFTs exhibit higher leakage current and longer signal rise and fall times than CMOS components, a problem that the industry urgently needs to address. An embodiment provides an electronic device comprising a heater and a sampling and holding circuit. The sampling and holding circuit is coupled to the heater and includes a sampling unit, a temporary storage unit, and a feedback unit. The sampling unit is configured to receive a data signal. The temporary storage unit has an input and an output, the input being coupled to the sampling unit, and the output being configured to output a first signal. The feedback unit is coupled to the input and output of the temporary storage unit. When the feedback unit is in an on state, the feedback unit is configured to feed the first signal back to the input. An embodiment provides another electronic device comprising a sample-and-hold circuit, an output buffer, and a heater. The sample-and-hold circuit receives a data signal and outputs a first signal. The output buffer is coupled to the sample-and-hold circuit and receives the first signal and outputs a drive signal. The heater is coupled to the output buffer and receives the drive signal. The rise time of the drive signal has a first duration, and the fall time of the drive signal has a second duration, wherein the first duration is greater than the second duration. The illustrated architecture, number of components, number of layers, positional distribution, and proportions are merely examples to aid in explaining and understanding the embodiments and are not intended to limit the scope and nature of the embodiments. References to numbers such as first and second herein are merely to distinguish between components and do not limit the order or importance of manufacturing processes. Throughout this disclosure and the claims that follow, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but are named differently. In the following description and claims, words such as "having" and "including" are open-ended and should be interpreted as meaning "including, but not limited to..." It should be understood that when an element or film layer is defined as being "on" or "connected to" another element or film layer, it can be directly on or directly connected to the other element or layer, or there can be other intervening elements or layers between the two elements or layers (indirect contact). Conversely, when an element is defined as being "directly on" or "directly connected to" another element or film layer, there can be no intervening elements or layers between the two elements or layers. The terms "about," "equal," "equal," or "substantially the same" typically mean within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. In addition, the term "in the range from a first value to a second value" means that the range includes the first value, the second value, and other values ​​therebetween. Although terms such as first, second, third, etc. can be used to describe different constituent elements, these constituent elements are not limited by these terms. These terms are only used to distinguish constituent elements from other constituent elements in the specification. The claims may not use the same terms, but may use terms such as first, second, third, etc. to indicate the order in which the elements are defined. Therefore, in the following description, the first constituent element may be the second constituent element in the claim. It should be noted that the following embodiments may replace, reorganize, or mix the technical features of several different embodiments to implement other embodiments without departing from the spirit of the present disclosure or causing any conflict. Figure 1 is a schematic diagram of an electronic device 10 according to an embodiment. The electronic device 10 may include a shift register 12 for receiving control signals, a sample-and-hold circuit 13 coupled to the shift register 12, a selection circuit 14 coupled to the sample-and-hold circuit 13, an output buffer 15 coupled to the selection circuit 14, a heater switch 16 coupled to the output buffer 15, and a heater 17 coupled to the heater switch 16. For example, the electronic device 10 may be an inkjet head driver circuit, but is not limited to this. The electronic device 10 may include a thin-film transistor (TFT). The heater 17 may be a thermal inkjet printer. An inkjet printer includes a thermal inkjet printer. A thermal inkjet printer distributes ink supplied from an ink reservoir to multiple chambers, selectively generates pressure in each chamber, and ejects ink droplets from an inkjet head connected to each chamber. The inkjet head driver circuit drives the thermal inkjet printer based on the control signal, causing the inkjet printer to eject ink droplets, thereby recording an image on a recording medium. Please refer to Figures 2 and 3. Figure 2 is a circuit diagram of a sampling and holding circuit 100 according to an embodiment. The sampling and holding circuit 100 may correspond to the sampling and holding circuit 13 of Figure 1. The sampling and holding circuit 100 includes a sampling unit 110, a temporary storage unit 120, and a feedback unit 130. The sampling unit 110 is used to receive a data signal SH. The temporary storage unit 120 has an input terminal and an output terminal, the input terminal being coupled to the sampling unit 110, and the output terminal being used to output a signal DATA. Because the input terminal signal A is prone to leakage, resulting in signal instability and data loss of the input terminal signal A, the embodiment utilizes the feedback unit 130 to couple the input terminal and the output terminal of the temporary storage unit 120, thereby stabilizing the signal of the input terminal signal A through circuit feedback. In more detail, the sampling unit 110 includes a control terminal, a first terminal, and a second terminal. The second terminal of the sampling unit is coupled to the input terminal. The feedback unit 130 includes a control terminal, a first terminal, and a second terminal. The control terminal of the feedback unit 130 is coupled to the control terminal of the sampling unit 110, the first terminal of the feedback unit 130 is coupled to the input terminal of the temporary storage unit 120, and the second terminal of the feedback unit 130 is coupled to the output terminal of the temporary storage unit 120. The sampling unit 110 may include an N-type thin film transistor, and the feedback unit 130 may include a P-type thin film transistor. In another embodiment, the sampling unit 110 may include a P-type thin film transistor, and the feedback unit 130 may include an N-type thin film transistor. The temporary storage unit 120 includes two inverters 122 and 124 coupled to each other. The inverters 122 and 124 are respectively composed of a P-type thin film transistor and an N-type thin film transistor connected in series, and are driven by voltages VH and VL. In the present disclosure, the semiconductor material included in the transistor can be amorphous silicon, low-temperature polysilicon, or metal oxide. The transistor included in the electronic device 10 can also partially include low-temperature polysilicon and another portion include metal oxide. Figure 3 is a schematic diagram of the operating signals of the sample-and-hold circuit 100 according to an embodiment. For example, at time t0, the data signal SH may be at a low level, the sampling unit 110 may be off, and the feedback unit 130 may be on. The first-end signal Q of the sampling unit 110 may be at a high level, and the input signal A of the temporary register unit 120 may be at a high level. Signal A, after passing through inverter 122, generates a signal B at a low level. Signal B, after passing through inverter 124, generates an output signal DATA at a high level. The feedback mechanism of the sample-and-hold circuit 100 can lock the input signal A, ensuring that the input signal A and the output signal DATA are substantially equal. From time t1 to t2, data signal SH is a pulse wave with rapidly varying signal amplitude. At time t1, data signal SH rises to a high level, turning on sampling unit 110 and turning off feedback unit 130. Simultaneously, signal Q at the first terminal of sampling unit 110 drops to a low level, causing signal A at the input terminal of register unit 120 to drop to a low level. Signal A, after passing through inverter 122, generates signal B at a high level. Signal B, after passing through inverter 124, generates signal DATA at the output terminal, which is at a low level. At time t2, data signal SH drops to a low level, turning off sampling unit 110 and turning on feedback unit 130. At time t3, data signal SH is at a low level, sampling unit 110 is turned off, and feedback unit 130 is turned on. Signal Q at the first terminal of sampling unit 110 rises back to a high level. At this point, because sampling unit 110 is turned off, signal Q does not affect signals in other parts of sample-and-hold circuit 100. FIG4 is a circuit diagram of another sample-and-hold circuit 200 according to an embodiment. The sampling unit 110 similarly includes a control terminal, a first terminal, and a second terminal. The temporary register unit 120 similarly includes two inverters 122 and 124 coupled to each other. Inverters 122 and 124 are composed of a P-type thin-film transistor and an N-type thin-film transistor connected in series, respectively, and are driven by voltages VH and VL. However, the sample-and-hold circuit 200 differs from the sample-and-hold circuit 100 in that it lacks the feedback unit 130. Instead, the sample-and-hold circuit 200 further includes a capacitor 140 coupled between the input terminal of the temporary register unit 120 and the voltage terminal of the voltage VL. Capacitor 140 can be used to reduce leakage at the input terminal of the temporary register unit 120, thereby stabilizing the input signal A of the temporary register unit 120. In some embodiments, the sample-and-hold circuit 200 may further include a capacitor coupled between the input terminal of the temporary register unit 120 and the voltage terminal of the voltage VH. Those skilled in the art can design according to needs. FIG5 is a circuit diagram of another embodiment of a sample-and-hold circuit 300. The sampling unit 110 similarly includes a control terminal, a first terminal, and a second terminal. The temporary register unit 120 similarly includes two inverters 122 and 124 coupled to each other. Inverters 122 and 124 are composed of a P-type thin-film transistor and an N-type thin-film transistor connected in series, respectively, and are driven by voltages VH and VL. However, the sample-and-hold circuit 300 differs from the sample-and-hold circuit 100 in that it does not include the feedback unit 130. Instead, the sample-and-hold circuit 300 further includes a capacitor 150 coupled between the output terminal of the temporary register unit 120 and a voltage terminal of the voltage VL. Capacitor 150 can be used to reduce leakage at the output terminal of the temporary register unit 120, thereby stabilizing the output signal DATA of the temporary register unit 120. In some embodiments, the sample-and-hold circuit 300 may further include a capacitor coupled between the output terminal of the temporary register unit 120 and a voltage terminal of the voltage VH. In other embodiments, the sampling and holding circuit 300 may further include a capacitor coupled between the input terminal of the temporary storage unit 120 and the voltage terminal of the voltage VH, and a capacitor coupled between the input terminal of the temporary storage unit 120 and the voltage terminal of the voltage VL. Those skilled in the art may design the circuit according to their needs. Figure 6 is a circuit diagram of another sample-and-hold circuit 400 according to an embodiment. Sample-and-hold circuit 400 differs from sample-and-hold circuit 100 in that the temporary storage unit 420 of sample-and-hold circuit 400 is an operational amplifier. Sampling unit 410 is used to receive data signal SH. Temporary storage unit 420 has an inverting input, a non-inverting input, and an output. The non-inverting input is coupled to sampling unit 410, and the output is used to output signal DATA. Temporary storage unit 420 is driven by voltages VH and VL. The inverting input of temporary storage unit 420 is coupled to the output, while the non-inverting input is coupled to the output via feedback unit 430, stabilizing the signal through circuit feedback. In other words, signal A at the non-inverting input and signal DATA at the output are substantially equal, thereby stabilizing the signals in sample-and-hold circuit 400. The operation of the sample and hold circuit 400 is similar to that of the sample and hold circuit 100 and is not described in detail herein. FIG7 is a circuit diagram of another sample-and-hold circuit 500 according to an embodiment. Sample-and-hold circuit 500 differs from sample-and-hold circuit 100 in that its temporary storage unit 520 is a buffer amplifier. Sampling unit 510 is configured to receive data signal SH. Temporary storage unit 520 has an input and an output. The input is coupled to sampling unit 510, and the output is configured to output signal DATA. Temporary storage unit 520 is driven by voltages VH and VL. The input and output of temporary storage unit 520 are coupled via feedback unit 530, which stabilizes the signal through circuit feedback. Specifically, when data signal SH is at a low level, input signal A and output signal DATA are substantially equal, thereby stabilizing the various signals in sample-and-hold circuit 500. The operation of sample-and-hold circuit 500 is similar to that of sample-and-hold circuit 100 and will not be further described here. FIG8 is a circuit diagram of an output buffer 600 according to an embodiment. Output buffer 600 may correspond to output buffer 15 in FIG1 . Output buffer 600 includes inverters 610, 620, 630, and 640. Inverter 610 includes a P-type transistor MP1 coupled in series with an N-type transistor MN1. Inverter 620 includes a P-type transistor MP2 coupled in series with an N-type transistor MN2. Inverter 630 includes a P-type transistor MP3 coupled in series with an N-type transistor MN3. Inverter 640 includes a P-type transistor MP4 coupled in series with an N-type transistor MN4. P-type transistor MP1 has a control terminal, a first terminal, and a second terminal. The control terminal of P-type transistor MP1 is coupled to input terminal IN. P-type transistor MP2 has a control terminal, a first terminal, and a second terminal. The control terminal of P-type transistor MP2 is coupled to the second terminal of P-type transistor MP1, and the first terminal of P-type transistor MP2 is coupled to the first terminal of P-type transistor MP1. A first terminal of the N-type transistor MN1 is coupled to a second terminal of the P-type transistor MP1, and a first terminal of the N-type transistor MN2 is coupled to a second terminal of the P-type transistor MP2. An inverter 630 is coupled to the second terminal of the P-type transistor MP2, an inverter 640 is coupled to the inverter 630, and the inverter 640 is coupled to the output terminal OUT. Inverters 610 to 640 can be driven by voltages VH and VL. The sources of the N-type transistors MN1 to MN4 can receive voltage VL, and the drains of the P-type transistors MP1 to MP4 can receive voltage VH. The P-type transistors MP1 to MP4 can be P-type thin-film transistors, and the N-type transistors MN1 to MN4 can be N-type thin-film transistors. Inverters 610 and 620 can be used to adjust the time difference between the rise and fall of the signal, and inverters 630 and 640 can be used to produce a current multiplication effect. Therefore, in terms of design, the channel width-to-length ratio of the P-type transistor MP1 is greater than the channel width-to-length ratio of the P-type transistor MP2. The channel width-to-length ratio of the N-type transistor MN1 is smaller than the channel width-to-length ratio of the N-type transistor MN2. Specifically, the channel width-to-length ratio of the P-type transistor MP1 is approximately between 5 and 10, and the channel width-to-length ratio of the P-type transistor MP2 is approximately between 0.5 and 1. In other words, the ratio of the channel width-to-length ratio of the P-type transistor MP1 to the channel width-to-length ratio of the P-type transistor MP2 is between 5 and 20. The channel width-to-length ratio of the N-type transistor MN1 is between 0.5 and 1, and the channel width-to-length ratio of the N-type transistor MN2 is between 5 and 10. That is to say, the ratio of the channel width-to-length ratio of the N-type transistor MN2 to the channel width-to-length ratio of the N-type transistor MN1 is between 5 and 20. In terms of design, the channel width-to-length ratio of the N-type transistors MN3 and MN4, as well as the P-type transistors MP3 and MP4, needs to be maximized to produce a current multiplication effect. In particular, the channel refers to the semiconductor layer between the source and drain of the transistor, which is a conductive layer along the length direction caused by an external electric field. The channel width-to-length ratio is the ratio of the channel width to the channel length. The larger the channel width-to-length ratio, the larger the saturation current of the transistor and the shorter the signal change time. The embodiment adjusts the channel width-to-length ratio so that the rise time of the drive signal at the output terminal OUT is greater than the fall time of the drive signal, thereby improving the isolation between two consecutive drive signals and avoiding errors caused by overlapping drive signals. See below for details. Figure 9 is a diagram of the driving signal at the output terminal OUT of the output buffer 600 of the embodiment shown in Figure 8 . Figure 9 depicts the nth driving signal and the n+1th driving signal (n is a positive integer) of the buffer 600 . The signal waveforms at the input terminal IN and the output terminal OUT of the output buffer 600 are essentially similar; the output buffer 600 merely modifies the signal waveform amplitude and the rising and falling slopes. The nth driving signal at the output terminal OUT is used as an example. When the driving signal is at a low level, the P-type transistors MP2 and MP4 and the N-type transistors MN1 and MN3 are turned off, while the P-type transistors MP1 and MP3 and the N-type transistors MN2 and MN4 are turned on. When the driving signal is at a high level, the P-type transistors MP1 and MP3 and the N-type transistors MN2 and MN4 are turned off, while the P-type transistors MP2, MP4 and the N-type transistors MN1 and MN3 are turned on. As shown in Figure 9, the first time duration T1 represents the time it takes for the drive signal to rise from voltage VL to voltage VH, while the second time duration T2 represents the time it takes for the drive signal to fall from voltage VH to voltage VL. When the nth drive signal rises, the P-type transistor MP2 and the N-type transistor MN1 primarily pull the signal up to a high level (voltage VH). Because the P-type transistor MP2 and the N-type transistor MN1 have smaller channel widths, the saturation current is lower, the signal rise time is longer, and the slope is also smaller. When the nth drive signal falls, the P-type transistor MP1 and the N-type transistor MN2 primarily pull the signal down to a low level (voltage VL). Because the P-type transistor MP1 and the N-type transistor MN2 have larger channel widths, the saturation current is higher, the signal rise time is shorter, and the slope is also larger. As a result, the first time duration T1 is greater than the second time duration T2. This operation reduces the overlap between the nth drive signal and the (n+1)th drive signal, effectively preventing thermal inkjet operation errors. Furthermore, since the operating modes of transistors MN3, MN4, MP3, and MP4 are essentially the same as those of transistors MN1, MN2, MP1, and MP2, those skilled in the art can infer the same, and thus will not be discussed further here. Figure 10 is a circuit diagram of another output buffer 700 according to an embodiment. Output buffer 700 differs from output buffer 600 in that N-type transistors MN1 and MN2 are replaced by resistors R1 and R2, respectively. Resistor R1 is coupled between the second terminal of P-type transistor MP1 and a voltage terminal of voltage VL. Resistor R2 is coupled between the second terminal of P-type transistor MP2 and a voltage terminal of voltage VL. The operation of output buffer 700 is similar to that of output buffer 600, and those skilled in the art can follow similar inferences, so this will not be discussed further here. Because inverters 610 and 620 in Figure 8 require precise control of the rising and falling slopes of the signals, the channel width-to-length ratios of transistors MP1, MP2, MN1, and MN2 must be more precisely controlled, placing higher demands on the transistor manufacturing process. Replacing N-type transistors MN1 and MN2 with resistors R1 and R2, respectively, reduces the number of transistors and lowers manufacturing process requirements. Figure 11 is a circuit diagram of another output buffer 800 according to an embodiment. Output buffer 800 differs from output buffer 600 in that P-type transistors MP1 and MP2 are replaced by resistors R3 and R4, respectively. Resistor R3 is coupled between the first terminal of N-type transistor MN1 and a voltage terminal of voltage VH. Resistor R4 is coupled between the first terminal of N-type transistor MN2 and a voltage terminal of voltage VH. The operation of output buffer 800 is similar to that of output buffer 600, and those skilled in the art can follow similar inferences, so this will not be discussed further here. Because inverters 610 and 620 in Figure 8 require precise control of the rising and falling slopes of the signals, the channel width-to-length ratios of transistors MP1, MP2, MN1, and MN2 must be more precisely controlled, placing higher demands on the transistor manufacturing process. Replacing P-type transistors MP1 and MP2 with resistors R3 and R4, respectively, reduces the number of transistors and lowers manufacturing process requirements. In summary, the electronic devices described in the various embodiments of this disclosure can effectively mitigate high leakage current caused by thin-film transistor devices and improve the rise and fall times of driving signals, thereby preventing operational errors in the electronic devices caused by leakage or driving signal overlap. The above descriptions are merely examples of the present disclosure; all equivalent variations and modifications made within the scope of the present disclosure are intended to be covered by the present disclosure. 10: Electronic device 12: Shift register 13, 100, 200, 300, 400, 500: Sample and hold circuit 14: Selection circuit 15, 600, 700, 800: Output buffer 16: Heater switch 17: Heater 110, 410, 510: Sampling unit 120, 420, 520: Temporary storage unit 130: Feedback unit 140, 150: Capacitor SH: Data signal DATA: Output signals VH, VL: Voltages Q, A, B: Signals t0, t1, t2, t3: Time 122, 124, 610, 620, 630, 640: Inverters MN1, MN2, MN3, MN4: N-type transistors MP1, MP2, MP3, MP4: P-type transistors R1, R2, R3, R4: resistor IN: input terminal OUT: output terminal FIG1 is a schematic diagram of an electronic device according to an embodiment. FIG2 is a schematic diagram of a sampling and holding circuit according to an embodiment. FIG3 is a schematic diagram of operating signals for the sampling and holding circuit according to FIG2 . FIG4 is a schematic diagram of another sampling and holding circuit according to an embodiment. FIG5 is a schematic diagram of another sampling and holding circuit according to an embodiment. FIG6 is a schematic diagram of another sampling and holding circuit according to an embodiment. FIG7 is a schematic diagram of another sampling and holding circuit according to an embodiment. FIG8 is a schematic diagram of an output buffer according to an embodiment. FIG9 is a diagram of driving signals for the output buffer according to FIG8 . FIG10 is a schematic diagram of another output buffer according to an embodiment. FIG11 is a schematic diagram of another output buffer according to an embodiment. 100: Sampling and holding circuit 110: Sampling unit 120: Temporary storage unit 130: Feedback unit 122,124: Inverter VH, VL: voltage Q,A,B:Signal SH: Data signal DATA: output signal

Claims

1. An electronic device, characterized in that it comprises: a thermal inkjet printer; and a sampling and holding circuit coupled to the thermal inkjet printer, comprising: a sampling unit for receiving a data signal; a temporary storage unit, which is a buffer amplifier having an input terminal and an output terminal, the input terminal being coupled to the sampling unit, and the output terminal being used to output a first signal; and a feedback unit coupled to the input terminal and the output terminal of the temporary storage unit; wherein when the feedback unit is in an on state, the feedback unit is used to feed the first signal back to the input terminal.

2. The electronic device as claimed in claim 1, wherein: The sampling unit includes a control terminal, a first terminal and a second terminal, the second terminal of the sampling unit being coupled to the input terminal; and the feedback unit includes a control terminal, a first terminal and a second terminal, the control terminal of the feedback unit being coupled to the control terminal of the sampling unit, the first terminal of the feedback unit being coupled to the input terminal, and the second terminal of the feedback unit being coupled to the output terminal.

3. The electronic device of claim 1, wherein the sampling unit includes a first type of thin-film transistor, the feedback unit includes a second type of thin-film transistor, the first type being either N-type or P-type, and the second type being either N-type or P-type.

4. An electronic device, characterized in that it comprises: a sampling and holding circuit for receiving a data signal and outputting a first signal; an output buffer coupled to the sampling and holding circuit for receiving the first signal and outputting a drive signal; and a heater coupled to the output buffer for receiving the drive signal; wherein the rise time of the drive signal has a first time length, the fall time of the drive signal has a second time length, and the first time length is greater than the second time length.

5. The electronic device of claim 4, wherein the output buffer comprises: a first P-type transistor having a control terminal, a first terminal, and a second terminal; a second P-type transistor having a control terminal, a first terminal, and a second terminal, the control terminal of the second P-type transistor being coupled to the second terminal of the first P-type transistor, and the first terminal of the second P-type transistor being coupled to the first terminal of the first P-type transistor; a first inverter coupled to the second terminal of the second P-type transistor; and a second inverter coupled to the first inverter; wherein the channel aspect ratio of the first P-type transistor is greater than the channel aspect ratio of the second P-type transistor.

6. The electronic device of claim 5, wherein the ratio of the channel width-to-length ratio of the first P-type transistor to the channel width-to-length ratio of the second P-type transistor is between 5 and 20.

7. The electronic device of claim 5, wherein the output buffer further comprises: a first N-type transistor coupled to the second terminal of the first P-type transistor; and a second N-type transistor coupled to the second terminal of the second P-type transistor; wherein the channel width-to-length ratio of the first N-type transistor is smaller than the channel width-to-length ratio of the second N-type transistor.

8. The electronic device of claim 7, wherein the ratio of the channel width-to-length ratio of the second N-type transistor to the channel width-to-length ratio of the first N-type transistor is between 5 and 20.

9. The electronic device of claim 5, wherein the output buffer further includes a first resistor coupled to the second terminal of the first P-type transistor and a second resistor coupled to the second terminal of the second P-type transistor.

10. The electronic device as claimed in claim 4, wherein the heater is a thermal inkjet printer.

11. The electronic device of claim 4, wherein the output buffer comprises: a first N-type transistor having a control terminal, a first terminal, and a second terminal; a second N-type transistor having a control terminal, a first terminal, and a second terminal, the control terminal of the second N-type transistor being coupled to the first terminal of the first N-type transistor, and the second terminal of the second N-type transistor being coupled to the second terminal of the first N-type transistor; a first inverter coupled to the first terminal of the second N-type transistor; and a second inverter coupled to the first inverter; wherein the channel aspect ratio of the first N-type transistor is smaller than the channel aspect ratio of the second N-type transistor.

12. The electronic device of claim 11, wherein the ratio of the channel width-to-length ratio of the second N-type transistor to the channel width-to-length ratio of the first N-type transistor is between 5 and 20.

13. The electronic device of claim 11, wherein the output buffer further includes a third resistor coupled to the first terminal of the first N-type transistor and a fourth resistor coupled to the first terminal of the second N-type transistor.

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