Semiconductor devices and manufacturing methods thereof
By integrating a high-strength component around the adhesive layer, the semiconductor device mitigates crack formation and electrical defects caused by stress concentration, enhancing structural integrity.
TWI934124BActive Publication Date: 2026-08-01KIOXIA CORP
4 Cites 0 Cited by
Patent Information
- Application Number
- TW112117445
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2022-06-09
- Filing Date
- 2023-05-11
- Publication Date
- 2026-08-01
- Estimated Expiration
- 2043-05-10
AI Technical Summary
Technical Problem
Existing semiconductor devices face issues with crack formation due to stress concentration at the interface between the adhesive layer and the sealing resin, which can lead to electrical defects.
Method used
Incorporating a component made of a material with higher strength than the sealing resin around the adhesive layer to suppress crack formation by distributing stress and preventing the adhesive layer from direct contact with the sealing resin.
Benefits of technology
The solution effectively reduces crack formation and subsequent electrical defects by distributing stress and enhancing the structural integrity of the semiconductor device.
✦ Generated by Eureka AI based on patent content.
Abstract
An embodiment of the present invention provides a semiconductor device capable of suppressing the effects of cracks and a method for manufacturing the same. The semiconductor device of this embodiment includes: a substrate, a first semiconductor wafer, a second semiconductor wafer, an adhesive layer, and a component. The substrate has a first surface. The first semiconductor wafer is disposed on the first surface. The second semiconductor wafer is disposed above the first semiconductor wafer, having a first surface and a second surface opposite to the first semiconductor wafer, and covers the first semiconductor wafer when viewed from a direction substantially perpendicular to the first surface. The adhesive layer is disposed between the second surface, the first surface, and the first semiconductor wafer. The component, viewed from a direction substantially perpendicular to the first surface, is disposed on at least a portion of the outer periphery of the adhesive layer.
Need to check novelty before this filing date? Find Prior Art