Semiconductor devices and manufacturing methods thereof

Abstract

An embodiment of the present invention provides a semiconductor device capable of suppressing the effects of cracks and a method for manufacturing the same. The semiconductor device of this embodiment includes: a substrate, a first semiconductor wafer, a second semiconductor wafer, an adhesive layer, and a component. The substrate has a first surface. The first semiconductor wafer is disposed on the first surface. The second semiconductor wafer is disposed above the first semiconductor wafer, having a first surface and a second surface opposite to the first semiconductor wafer, and covers the first semiconductor wafer when viewed from a direction substantially perpendicular to the first surface. The adhesive layer is disposed between the second surface, the first surface, and the first semiconductor wafer. The component, viewed from a direction substantially perpendicular to the first surface, is disposed on at least a portion of the outer periphery of the adhesive layer.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a method for manufacturing the same. Prior Art

[0002] In the packaging structure of semiconductor devices, memory chips are sometimes arranged by covering the controller chip on the substrate with a thicker DAF (Die Attach Film). Summary of the Invention

[0003] The problem to be solved by the present invention is to provide a semiconductor device and a manufacturing method thereof that can suppress the influence of cracks.

[0004] The semiconductor device of this embodiment includes a substrate, a first semiconductor wafer, a second semiconductor wafer, an adhesive layer, and a component. The substrate has a first surface. The first semiconductor wafer is disposed on the first surface. The second semiconductor wafer is disposed above the first semiconductor wafer and has a first surface and a second surface opposite the first semiconductor wafer, covering the first semiconductor wafer when viewed in a direction substantially perpendicular to the first surface. The adhesive layer is disposed between the second surface, the first surface, and the first semiconductor wafer. The component is disposed on at least a portion of the outer periphery of the adhesive layer when viewed in a direction substantially perpendicular to the first surface. Simple diagram description

[0005] FIG1 is a cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. FIG2 is a top view showing an example of the positional relationship among the wiring substrate, semiconductor wafer, adhesive layer, and components of FIG1. ​​FIG3A is a diagram showing an example of a method for manufacturing a semiconductor device according to the first embodiment. FIG3B is a diagram showing an example of a method for manufacturing a semiconductor device that is continuous with FIG3A. FIG3C is a diagram showing an example of a method for manufacturing a semiconductor device that is continuous with FIG3B. FIG3D is a diagram showing an example of a method for manufacturing a semiconductor device that is continuous with FIG3C. FIG3E is a diagram showing an example of a method for manufacturing a semiconductor device that is continuous with FIG3D. FIG4A is a diagram showing an example of a method for manufacturing a semiconductor device according to the first embodiment. FIG4B is a diagram showing an example of a method for manufacturing a semiconductor device that is continuous with FIG4A. FIG4C is a diagram showing an example of a method for manufacturing a semiconductor device that is continuous with FIG4B. FIG4D is a diagram showing an example of a method for manufacturing a semiconductor device that is continuous with FIG4C. FIG4E is a diagram showing an example of a method for manufacturing a semiconductor device subsequent to FIG4D . FIG4F is a diagram showing an example of a method for manufacturing a semiconductor device subsequent to FIG4E . FIG5 is a cross-sectional view showing an example of the structure of a semiconductor device according to a comparative example. FIG6 is a top view showing an example of the positional relationship among a wiring board, a semiconductor chip, and components according to a modified example. FIG7 is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. FIG8 is a cross-sectional view showing an example of the structure of a semiconductor device according to the third embodiment. Implementation Method

[0006] The following describes embodiments of the present invention with reference to the drawings. These embodiments do not limit the present invention. In the following embodiments, the "up-down" direction of a wiring board refers to the relative orientation when the surface on which the semiconductor chip is mounted is facing upward, and may differ from the "up-down" direction based on gravitational acceleration. The drawings are schematic or conceptual, and the proportions of various components are not necessarily the same as in actual objects. In the specification and drawings, elements identical to those described in previously mentioned drawings are given the same reference numerals, and detailed descriptions are omitted where appropriate.

[0007] (First Embodiment) FIG1 is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to a first embodiment. Semiconductor device 1 includes a wiring substrate 10, semiconductor chips 20, 30-33, adhesive layers 40-43, a member 50, an adhesive layer 60, bonding wires 90, and a sealing resin 91. Semiconductor device 1 is, for example, a NAND flash memory package.

[0008] Wiring substrate 10 can be a printed circuit board or interposer comprising a wiring layer (not shown) and an insulating layer (not shown). For example, a low-resistance metal such as copper, nickel, or their alloys can be used for the wiring layer. For example, an insulating material such as glass epoxy can be used for the insulating layer. Wiring substrate 10 can have a multilayer wiring structure composed of a plurality of wiring layers and a plurality of insulating layers stacked together. For example, like an interposer, wiring substrate 10 can have through-electrodes (not shown) extending through its front and back surfaces.

[0009] Pads 10p1 and 10p2 connected to the wiring layer are provided on the front surface (upper surface) F10a of the wiring substrate 10. The surface F10a is an example of the first surface.

[0010] Metal bumps 13 are provided on the back surface (lower surface) of the wiring substrate 10. The metal bumps 13 are provided to electrically connect the wiring substrate 10 with other components (not shown).

[0011] Semiconductor chip 20 is disposed on the front surface (surface F10a) of wiring substrate 10. Semiconductor chip 20 is bonded to wiring substrate 10 via adhesive layer 21. Semiconductor chip 20 is, for example, a controller chip that controls a memory chip. Semiconductor elements (not shown) are disposed on the surface (front surface) of semiconductor chip 20 opposite to the surface facing wiring substrate 10. These elements may be, for example, CMOS (Complementary Metal Oxide Semiconductor) circuits that constitute a controller. Bonding wires 22 electrically connect bonding pads 10p2 disposed on the front surface of wiring substrate 10 to bonding pads (not shown) disposed on the front surface of semiconductor chip 20.

[0012] A semiconductor chip 30 is bonded to the semiconductor chip 20 via an adhesive layer 40. Semiconductor chip 30 is, for example, a memory chip including NAND flash memory. Semiconductor chip 30 has a semiconductor element (not shown) on its front surface. The semiconductor element may be, for example, a memory cell array and its peripheral circuits (CMOS circuits). The memory cell array may be a three-dimensional memory cell array comprising a plurality of memory cells arranged three-dimensionally. Furthermore, semiconductor chip 31 is bonded to semiconductor chip 30 via an adhesive layer 41. Semiconductor chip 32 is bonded to semiconductor chip 31 via an adhesive layer 42. Semiconductor chip 33 is bonded to semiconductor chip 32 via an adhesive layer 43. Semiconductor chips 31-33, like semiconductor chip 30, are memory chips including NAND flash memory. Semiconductor chips 30-33 may be the same memory chip. In the figure, in addition to semiconductor chip 20 serving as a controller chip, four semiconductor chips 30-33 serving as memory chips are also stacked. However, the number of semiconductor chips stacked may be three or fewer, or five or more.

[0013] More specifically, semiconductor wafer 30 has surface F30a and surface F30b opposite surface F30a, and has adhesive layer 40 on surface F30a. Surface F30a is surface F10a of wiring board 10 and faces semiconductor wafer 20. Surface F30a is an example of a second surface. Surface F30b is an example of a third surface.

[0014] Furthermore, adhesive layer 40 is thicker than adhesive layers 41-43 and is provided to bury (cover) semiconductor wafer 20 and bonding wires 22. Specifically, adhesive layer 40 is provided between surface F30a of semiconductor wafer 30 and surface F10a of wiring substrate 10 and semiconductor wafer 20. Furthermore, the side surfaces of adhesive layer 40 are substantially parallel to the side surfaces of semiconductor wafer 30 located between surfaces F30a and F30b. In other words, the width of adhesive layer 40 is substantially the same as the width of semiconductor wafer 30. Furthermore, this width is the width in a direction substantially parallel to surface F10a. This is to facilitate singulation of the wafer to which the adhesive layer is attached by dicing, as will be described later with reference to Figures 3A-3E.

[0015] Component 50 is disposed on the outer periphery of adhesive layer 40. Component 50 is bonded to wiring substrate 10 via adhesive layer 60. Details of the arrangement of component 50 will be described later with reference to FIG2 . In the example shown in FIG1 , the height of the upper surface of component 50 is substantially the same as the height of surface F30a of semiconductor wafer 30.

[0016] The bonding wire 90 is connected to any pad of the wiring substrate 10 and the semiconductor chips 30 to 33. In order to connect with the bonding wire 90, the semiconductor chips 30 to 33 are stacked by shifting the portion of the pad.

[0017] More specifically, the bonding wire 90 electrically connects the bonding pad 10 p 1 provided on the front surface of the wiring substrate 10 and the bonding pad (not shown) provided on the front surface of the semiconductor chips 30 to 33 .

[0018] Furthermore, the sealing resin (resin layer) 91 seals the semiconductor chips 20, 30-33, the adhesive layers 40-43, 60, the member 50, the bonding wires 90, etc. Thus, the semiconductor device 1 forms a semiconductor package by combining the plurality of semiconductor chips 20, 30-33 on the wiring substrate 10.

[0019] Fig. 2 is a top view showing an example of the positional relationship among wiring board 10, semiconductor chip 20, adhesive layer 40, and member 50 of Fig. 1. Fig. 2 is a view taken from above the paper of Fig. 1, looking at a plane parallel to plane F30a shown in Fig. 1 (see line AA of Fig. 1).

[0020] The outer edge of the adhesive layer 40 (the outer edge of the semiconductor wafer 30) viewed from a direction substantially perpendicular to the plane F10a is located outside the outer edge of the semiconductor wafer 20. That is, the semiconductor wafer 30 is disposed to cover the semiconductor wafer 20 as viewed from a direction substantially perpendicular to the plane F10a.

[0021] The member 50 is provided on the outer periphery of the adhesive layer 40 when viewed from a direction substantially perpendicular to the plane F10a. More specifically, the member 50 is provided along the outer periphery of the adhesive layer 40 so as to cover the outer periphery of the adhesive layer 40. That is, the member 50 is provided between the adhesive layer 40 and the sealing resin 91.

[0022] Furthermore, member 50 is made of a material with higher strength than sealing resin 91. Examples of strength include tensile strength, bending strength, and hardness. The tensile strength of member 50 is, for example, greater than 10 kgf / mm². This helps prevent cracks from occurring.

[0023] Adhesive layer 40 is, for example, a thermosetting adhesive. Its main component is, for example, an acrylic resin. The thermal expansion coefficient of adhesive layer 40 is, for example, approximately 70 ppm / °C at room temperature and approximately 120 ppm / °C at 260°C. The materials constituting adhesive layer 40 are not limited to those described above.

[0024] Sealing resin 91 is, for example, a thermosetting resin. Its main component is, for example, epoxy resin. The thermal expansion coefficient of sealing resin 91 is, for example, approximately 9 ppm / °C at room temperature and approximately 36 ppm / °C at 260°C. The flexural strength of sealing resin 91 is, for example, approximately 170 MPa at 30°C and approximately 19 MPa at 260°C. The materials constituting sealing resin 91 are not limited to those described above.

[0025] Component 50 is made of, for example, silicon (Si). Furthermore, the material of component 50 is not limited to silicon; for example, any material having a strength higher than that of sealing resin 91 may be used. Furthermore, component 50 is preferably made of a material that can be processed into any shape. Component 50 can be made of, for example, resin.

[0026] Next, a method for manufacturing a semiconductor device is described.

[0027] 3A to 3E show the steps of singulating the wafer W with the adhesive layer 40 attached thereto into semiconductor chips 30. FIG4A to 4F show the steps of placing the semiconductor chips 20, 30 and the component 50 on the wiring substrate 10. FIG4B shows the steps of singulating the semiconductor chips 20, 30 and the component 50 on the wiring substrate 10. FIG4C shows the steps of singulating the semiconductor chips 20, 30 and the component 50

[0028] 3A to 3E are diagrams showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment.

[0029] As shown in Figure 3A, a silicon wafer W (hereinafter referred to as a wafer) is prepared, having a plurality of semiconductor device portions formed thereon. Wafer W includes a third surface having the semiconductor device portions and a fourth surface separated from the third surface in the Z-axis direction. Next, a surface protection tape 110 is attached to the third surface of wafer W.

[0030] 3B , the wafer W is turned over and the fourth surface of the wafer W is ground using the grinding stone 120 , thereby retracting the wafer W. This step is known as the BSG (Back Side Grinding) step.

[0031] 3C, the wafer W is turned over and the fourth surface of the wafer W is bonded to the bonding resin attached to the dicing ring 130. An example of the bonding resin is DAF (Die Attach Film) 140a.

[0032] Next, as shown in FIG. 3D , the surface protection tape 110 is peeled off from the third surface of the wafer W.

[0033] Next, as shown in FIG3E , the wafer W is cut using a blade 150 . Cut lines 160 are formed on the wafer W. The cut lines 160 are formed along both the X-axis and the Y-axis directions. The wafer W is separated into a plurality of semiconductor chips 30 .

[0034] Furthermore, the DAF 140 a as the second bonding layer is singulated together with the wafer W to form the bonding layer 40 as the first bonding layer.

[0035] 4A to 4F are diagrams showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment. The left side of FIG4A to FIG4F shows a top view, and the right side of FIG4A to FIG4F shows a side view.

[0036] As shown in FIG4A , semiconductor chip 20 is placed (mounted) on surface F10a of wiring board 10 via adhesive layer 21. Adhesive layer 21 is previously attached to semiconductor chip 20. Bonding wires 22 are then formed. Adhesive layer 21, bonding wires 22, and pads 10p2 are omitted.

[0037] Next, as shown in FIG4B , the semiconductor wafer 30 singulated by the steps of FIG3A to FIG3E is placed on surface F10a of the wiring substrate 10 via adhesive layer 40. More specifically, the semiconductor wafer 30 is placed so that the adhesive layer 40 provided on surface F30a buries (covers) the semiconductor wafer 20 and the bonding wires 22.

[0038] Furthermore, as described above, the side surface of the adhesive layer 40 is substantially parallel to the side surface of the semiconductor chip 30 located between the surface F30a and the surface F30b. In other words, the width of the adhesive layer 40 is substantially the same as the width of the semiconductor chip 30.

[0039] Next, as shown in FIG4C , component 5 is placed on surface F10a of wiring board 10 via adhesive layer 60 . Adhesive layer 60 is previously attached to component 51 . Component 51 is placed, for example, along one side (short side) of semiconductor wafer 30 . Component 51 is part of component 50 .

[0040] Next, as shown in FIG4D , component 52 is placed on surface F10a of wiring board 10 via adhesive layer 60 . Adhesive layer 60 is previously attached to component 52 . Component 52 is placed, for example, along one side (long side) of semiconductor wafer 30 . Component 52 is part of component 50 .

[0041] Next, as shown in FIG4E , component 53 is placed on surface F10a of wiring board 10 via adhesive layer 60 . Adhesive layer 60 is previously attached to component 53 . Component 53 is placed, for example, along one side (short side) of semiconductor wafer 30 . Component 53 is part of component 50 .

[0042] Next, as shown in FIG4F , component 54 is placed on surface F10a of wiring board 10 via adhesive layer 60 . Adhesive layer 60 is previously attached to component 54 . Component 54 is placed, for example, along one side (long side) of semiconductor wafer 30 . Component 54 is part of component 50 .

[0043] As shown in FIG4F , components 51 to 54 are provided along all sides of semiconductor wafer 30 (outside the periphery of adhesive layer 40). Components 51 to 54 correspond to component 50 shown in FIG2 . Furthermore, the order in which components 51 to 54 are provided is not limited to the example shown in FIG4C to FIG4F .

[0044] As described above, according to the first embodiment, member 50 is provided on the outer periphery of adhesive layer 40 when viewed from a direction substantially perpendicular to plane F10a. Since member 50 is made of a material having a higher strength than sealing resin 91, cracking due to stress concentration can be suppressed, thereby minimizing the effects of cracking.

[0045] (Comparative Example) Fig. 5 is a cross-sectional view showing an example of the structure of a semiconductor device 1a according to a comparative example. The comparative example differs from the first embodiment in that the member 50 and the adhesive layer 60 are not provided.

[0046] In the example shown in FIG5 , cracks C may occur. The region between the adhesive layer 40 and the sealing resin 91 may become the starting point of cracks C due to stress concentration caused by temperature changes. In the example shown in FIG5 , cracks C may occur at the boundary between the semiconductor wafer 30, the adhesive layer 40, and the sealing resin 91.

[0047] If the crack C extends to the wiring substrate 10, it will affect the wiring in the wiring substrate 10, and there is a possibility of causing electrical failures such as disconnection.

[0048] In contrast, in the first embodiment, the member 50 is provided to prevent contact between the adhesive layer 40 and the sealing resin 91. By providing the member 50, which is stronger than the sealing resin 91, around the adhesive layer 40, that is, between the adhesive layer 40 and the sealing resin 91, cracking can be prevented.

[0049] Furthermore, in the example shown in FIG4F , components 51-54 are disposed substantially without gaps. However, component 50 may not be disposed within a portion of the outer periphery of adhesive layer 40. Thus, component 50 may be disposed within at least a portion of the outer periphery of adhesive layer 40 when viewed from a direction substantially perpendicular to plane F10a.

[0050] For example, the influence of stress caused by temperature changes (expansion) may vary depending on the material, structure, or shape of the adhesive layer 40. Consequently, the susceptibility of cracks to formation may vary depending on the contact location between the adhesive layer 40 and the sealing resin 91. In such cases, components 50 may be placed in locations prone to cracks, while components 50 may not be placed in other locations. For example, in Figures 4B to 4F , if it is known that cracks or other defects are likely to occur along the short sides of the semiconductor wafer 30, components 51 and 53 may be placed along the short sides, while components 52 and 54 may not be placed.

[0051] (Variation) FIG. 6 is a plan view showing an example of the positional relationship among the wiring board 10, the semiconductor chip 30, and the member 50 according to a variation.

[0052] Wiring substrate 10 may have an area A1 where wiring is provided, and an area A2 where no wiring is provided. In Figure 6, area A2 is the area on wiring substrate 10 outside area A1. Even if a crack extends to area A2, no wire breakage will occur. Therefore, component 50 need not be provided on the periphery of adhesive layer 40 on the area A2 side (the side of semiconductor wafer 30 on the area A2 side), as viewed in a direction substantially perpendicular to plane F10a. This reduces the material cost of component 50. In the example shown in Figure 6, the left short side of semiconductor wafer 20 is area A2. Therefore, component 50 is not provided on the left short side of semiconductor wafer 20.

[0053] (Second Embodiment) Fig. 7 is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to a second embodiment. In the second embodiment, the height of the upper surface of the member 50 is different from that in the first embodiment.

[0054] The height of the upper surface of the member 50 is higher than the height of the surface F30a of the semiconductor wafer 30. More specifically, the height of the upper surface of the member 50 is the height of the surface F30b of the semiconductor wafer 30. The member 50 functions as a spacer to support the semiconductor wafer 31 disposed on the semiconductor wafer 30. This supports the semiconductor wafer 31 during the formation of the bonding wire 90 to the semiconductor wafer 31. As a result, the effects of the weight and stress applied during wire bonding are suppressed, thereby preventing the occurrence of cracks.

[0055] Since the other structures of the semiconductor device 1 of the second embodiment are the same as the corresponding structures of the semiconductor device of the first embodiment, their detailed description is omitted. The semiconductor device 1 of the second embodiment can obtain the same effects as the first embodiment.

[0056] (Third Embodiment) Fig. 8 is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to a third embodiment. In the third embodiment, the height of the upper surface of the member 50 is different from that in the first embodiment.

[0057] The height of the upper surface of the component 50 is lower than the surface F30a of the semiconductor chip 30. In this case, the volume of the component 50 can be reduced and the material cost can be suppressed.

[0058] Even if crack C, as shown in FIG5 , occurs, member 50 covers surface F10a of wiring substrate 10, preventing crack C from reaching wiring substrate 10. In other words, member 50 of the third embodiment functions as a wiring protection member in wiring substrate 10, thereby suppressing the effects of crack C.

[0059] For example, the member 50 is provided from the outer periphery of the adhesive layer 40 to the bonding pad 10p1. To protect the wiring, the member 50 is preferably provided over a wider area parallel to the plane F10a. However, in the direction of the bonding pad 10p1 (the horizontal direction of the paper in FIG. 8 ), the member 50 is preferably provided close to the bonding pad 10p1 so as not to contact the bonding wire 90.

[0060] Since the other structures of the semiconductor device 1 of the third embodiment are the same as the corresponding structures of the semiconductor device 1 of the first embodiment, their detailed description is omitted. The semiconductor device 1 of the third embodiment can obtain the same effects as the first embodiment.

[0061] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be encompassed by the inventions described in the claims and their equivalents, as long as they fall within the scope and spirit of the invention. [Reference to Related Applications]

[0062] This application claims priority from Japanese Patent Application No. 2022-093908 (filing date: June 9, 2022), the entire contents of which are incorporated herein by reference.

[0063] 1,1a:Semiconductor devices 10: Wiring board 10p1, 10p2: solder pad 13:Metal bumps 20, 30, 31, 32, 33: semiconductor wafers 21,40,41,42,43,60: Adhesion layer 22,90:Joint line 50,51,52,53,54: components 91: Sealing resin 110: Surface protection tape 120:Grinding stone 130: Cutting ring 140a:DAF 150: Blade 160: cutting line AA:Line A1: Area C: Crack F10a, F30a, F30b: Face W: Wafer

Claims

1. A semiconductor device comprising: a substrate having a first surface; a first semiconductor wafer disposed on the first surface; a second semiconductor wafer disposed above the first semiconductor wafer, having a second surface opposite to the first surface and the first semiconductor wafer, and covering the first semiconductor wafer when viewed from a direction substantially perpendicular to the first surface; a first adhesive layer disposed between the second surface and the first surface and the first semiconductor wafer; a member disposed on at least a portion of the outer periphery of the first adhesive layer when viewed from a direction substantially perpendicular to the first surface; and a resin layer disposed on the first surface, covering the second semiconductor wafer, the first adhesive layer, and the member; wherein the first adhesive layer and the resin layer are made of different materials, and the tensile strength of the member is higher than the tensile strength of the resin layer.

2. The semiconductor device of claim 1, wherein the aforementioned first bonding layer comprises acrylic.

3. The semiconductor device of claim 1, wherein the aforementioned resin layer comprises epoxy resin.

4. The semiconductor device of claim 1, wherein the height of the upper surface of the aforementioned component is greater than or equal to the height of the aforementioned second surface.

5. The semiconductor device of claim 4, wherein the height of the upper surface of the aforementioned member is the height of the third surface of the aforementioned second semiconductor wafer, which is opposite to the aforementioned second surface.

6. The semiconductor device of claim 5, further comprising a third semiconductor wafer disposed on the aforementioned second semiconductor wafer; and the aforementioned component supporting the aforementioned third semiconductor wafer.

7. The semiconductor device of claim 1, wherein the height of the upper surface of the aforementioned component is lower than that of the aforementioned second surface.

8. The semiconductor device of claim 7, further comprising: a bonding pad disposed on the first surface of the aforementioned substrate; and a lead electrically connecting the bonding pad and the aforementioned second semiconductor wafer; and the aforementioned component being disposed from the periphery of the aforementioned first bonding layer to the bonding pad.

9. The semiconductor device of claim 1, wherein the substrate has: a first region in which wiring is disposed internally, and a second region in which wiring is not disposed internally; and the aforementioned member, when viewed from a direction substantially perpendicular to the first surface, is not disposed on the outer periphery of the second region side of the first bonding layer.

10. The semiconductor device of claim 1, wherein the coefficient of thermal expansion of the first adhesive layer is different from the coefficient of thermal expansion of the resin layer.

11. A method for manufacturing a semiconductor device, comprising: disposing a first semiconductor wafer on a first surface of a substrate; disposing a second semiconductor wafer on the first surface such that the first semiconductor wafer is covered by a first adhesive layer disposed on a second surface of a second semiconductor wafer; disposing a member on at least a portion of the outer periphery of the first adhesive layer when viewed from a direction substantially perpendicular to the first surface; and disposing a resin layer on the first surface that covers the second semiconductor wafer, the first adhesive layer, and the member; wherein the first adhesive layer and the resin layer are made of different materials, and the tensile strength of the member is higher than the tensile strength of the resin layer.

12. The method of manufacturing a semiconductor device as claimed in claim 11, further comprising: providing a second bonding layer on the fourth surface of a wafer having a third surface on which semiconductor elements are formed and a fourth surface opposite to the third surface; and forming a second semiconductor wafer on which the first bonding layer is provided on the second surface by monolithically combining the wafer and the second bonding layer.

Images