Manufacturing method of electronic device, and electronic device

Abstract

This disclosure provides a method for manufacturing an electronic device, comprising the following steps: First, a first conductive layer is formed on a substrate. Next, a first insulating layer and a second conductive layer are formed on the first conductive layer, wherein the first insulating layer is disposed between the second conductive layer and the first conductive layer, and the first insulating layer has a through-hole that exposes a portion of the first conductive layer. The aspect ratio of the through-hole in the first insulating layer is greater than 1, and at least a portion of the sidewalls of the first insulating layer is covered by the second conductive layer.

Description

Technical Field

[0001] The present disclosure relates to a manufacturing method of an electronic device and the electronic device. Prior Art

[0002] Electronic devices typically include at least one electrical connection structure. Conventional methods for manufacturing such structures utilize a through-hole formed in an insulating layer to electrically connect two conductive layers disposed on opposing surfaces of the insulating layer. However, as the aspect ratio of the through-hole increases, the likelihood of the two conductive layers being electrically disconnected increases due to the hole being too small and / or too deep, potentially reducing the yield of the electronic device. Summary of the Invention

[0003] The present disclosure is directed to a method for manufacturing an electronic device, which can reduce the possibility of problems such as reduced yield of the manufactured electronic device.

[0004] According to some embodiments of the present disclosure, a method for manufacturing an electronic device includes the following steps: First, forming a first conductive layer on a substrate. Next, forming a first insulating layer and a second conductive layer on the first conductive layer, wherein the first insulating layer is disposed between the second conductive layer and the first conductive layer, and the first insulating layer has a through hole that exposes a portion of the first conductive layer. The through hole in the first insulating layer has an aspect ratio greater than 1, and at least a portion of the sidewalls of the first insulating layer are covered by the second conductive layer.

[0005] The present disclosure is directed to an electronic device that can reduce problems such as yield reduction.

[0006] According to some embodiments of the present disclosure, an electronic device is provided, comprising a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and an electrical connection layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer, wherein the first insulating layer has a through-hole exposing a portion of the first conductive layer. The second conductive layer is disposed on the first insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer via the through-hole in the first insulating layer. The through-hole in the first insulating layer has an aspect ratio greater than 1, and at least a portion of the sidewalls of the first insulating layer are covered by the second conductive layer. Simple diagram description

[0007] FIG. 1 is a cross-sectional schematic diagram of a manufacturing method of an electronic device according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a second embodiment of the present disclosure. FIG. 3 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a third embodiment of the present disclosure. FIG. 4 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a fourth embodiment of the present disclosure. FIG. 5 is a cross-sectional schematic diagram of a manufacturing method of an electronic device according to a fifth embodiment of the present disclosure. FIG. 6 is a cross-sectional schematic diagram of a manufacturing method of an electronic device according to a sixth embodiment of the present disclosure. FIG. 7 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a seventh embodiment of the present disclosure. FIG. 8 is a cross-sectional schematic diagram of a manufacturing method of an electronic device according to an eighth embodiment of the present disclosure. FIG. 9A is a schematic top view of an electronic device according to an embodiment of the present disclosure. FIG. 9B is a schematic cross-sectional view of an embodiment taken along the line AA′ of FIG. 9A . Implementation Method

[0008] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, like reference numerals are used in the drawings and the description to refer to the same or like parts.

[0009] Throughout this disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, words such as "including," "comprising," and "having" are open-ended and should be interpreted as meaning "including, but not limited to..." Therefore, when the terms "including," "comprising," and / or "having" are used in the description of this disclosure, they specify the presence of corresponding features, regions, steps, operations, and / or components, but do not preclude the presence of one or more corresponding features, regions, steps, operations, and / or components.

[0010] Directional terms used herein, such as "up," "down," "front," "back," "left," and "right," refer only to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present disclosure. In the accompanying drawings, each diagram depicts the general characteristics of methods, structures, and / or materials used in specific embodiments. However, these diagrams should not be construed as defining or limiting the scope or nature of the embodiments. For example, the relative sizes, thicknesses, and positions of various layers, regions, and / or structures may be exaggerated or reduced for clarity.

[0011] When a component (such as a layer or region) is referred to as being "on" another component, it can be directly on the other component or with other components interposed between the two. On the other hand, when a component is referred to as being "directly on" another component, no components are interposed between the two components. Furthermore, when a component is referred to as being "on" another component, the two components have a top-to-bottom relationship in a top-down view, and the component can be above or below the other component, depending on the orientation of the device.

[0012] The terms "about," "equal to," "equal" or "same," "substantially" or "approximately" are generally interpreted as meaning within a range of 20% of a given value, or within a range of 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0013] The use of ordinal numbers such as "first" and "second" in the specification and claims to modify an element does not, by itself, imply or indicate any prior ordinal number of the element(s), nor does it indicate the order of one element relative to another, or the order of manufacturing methods. Such ordinal numbers are used solely to clearly distinguish a named element from another element with the same name. The claims and the specification may not use the same terminology; thus, the first element in the specification may be the second element in the claims.

[0014] It should be noted that the following embodiments may be implemented by replacing, recombining, or combining features from various embodiments to create other embodiments without departing from the spirit of the present disclosure. Features from various embodiments may be mixed and matched as needed, as long as they do not violate the spirit of the invention or conflict with it.

[0015] The electrical connection or coupling described in this disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of two circuit components are directly connected or connected to each other via a conductor segment. In the case of indirect connection, the endpoints of the two circuit components are connected by a switch, diode, capacitor, inductor, other suitable element, or a combination of the above elements, but is not limited to these.

[0016] In the present disclosure, thickness, length, and width can be measured using an optical microscope, and thickness can be measured using cross-sectional images obtained through an electron microscope, but this is not limited to these measurements. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If a first value is equal to a second value, this implies that there may be an error of approximately 10% between the first and second values. If a first direction is perpendicular to a second direction, the angle between the first and second directions may be between 80 and 100 degrees. If a first direction is parallel to a second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0017] The electronic devices disclosed herein may include, but are not limited to, antennas (e.g., liquid crystal antennas), displays, light-emitting diodes, sensors, touch controls, splicing, other suitable functions, or combinations of the above functions. The electronic devices include, but are not limited to, rollable or flexible electronic devices. The display device may, for example, include liquid crystal, light-emitting diodes (LEDs), quantum dots (QDs), fluorescence, phosphors, other suitable materials, or combinations of the above. The light-emitting diodes may, for example, include, but are not limited to, organic light-emitting diodes (OLEDs), micro-LEDs (micro-LEDs, mini-LEDs), or quantum dot light-emitting diodes (QLEDs, QDLEDs). The antenna device may, for example, include a frequency selective surface (FSS), a radio frequency filter (RF-Filter), a polarizer, a resonator, or an antenna. The electronic components may include, but are not limited to, capacitors, resistors, inductors, transistors, circuit boards, chips, dies, integrated circuits (ICs), or combinations thereof or other suitable electronic components.

[0018] The following examples illustrate exemplary embodiments of the present disclosure, and the same reference numerals are used in the drawings and description to represent the same or similar parts.

[0019] FIG. 1 is a cross-sectional schematic diagram of a manufacturing method of an electronic device according to a first embodiment of the present disclosure.

[0020] 1 , a first conductive layer M1 is formed on a substrate SB.

[0021] The substrate SB, for example, has good support and / or stability, such as for supporting film layers subsequently formed thereon and being able to withstand the temperatures of subsequent heating processes. In some embodiments, the material of the substrate SB may include glass, plastic, other suitable materials, or combinations thereof. In other embodiments, the substrate SB may be a circuit board, but the present disclosure is not limited thereto. In the case where the electronic device 10a is an antenna device, the material of the substrate SB may be selected to have a low dielectric constant (Dk) and / or a low dissipation factor (Df) to reduce signal loss during transmission therethrough, but the present disclosure is not limited thereto.

[0022] The first conductive layer M1 can be formed on the substrate SB by, for example, sputtering, electroless plating, bonding, or other suitable processes, but the present disclosure is not limited thereto. In some embodiments, the material of the first conductive layer M1 can include a metal. For example, the material of the first conductive layer M1 can include copper, aluminum, or other suitable metals, but the present disclosure is not limited thereto. In other embodiments, the material of the first conductive layer M1 can include electroless nickel immersion gold (ENIG), which can reduce the possibility of metal oxidation and facilitate electrical connection between the subsequently formed electrical connection layer EL and the first conductive layer M1.

[0023] 1 , an insulating layer IL1 and a second conductive layer M2 are formed on the first conductive layer M1 , wherein the insulating layer IL1 is disposed between the second conductive layer M2 and the first conductive layer M1 , and the insulating layer IL1 has a through hole IL1_V exposing a portion of the first conductive layer M1 .

[0024] In this embodiment, the following steps may be performed to form the insulating layer IL1 and the second conductive layer M2 on the first conductive layer M1, but the present disclosure is not limited thereto.

[0025] (1) First, an insulating material layer IL1′ is formed on the first conductive layer M1.

[0026] The insulating material layer IL1′ can be formed on the first conductive layer M1 by, for example, chemical vapor deposition (CVD) or other suitable processes, but the present disclosure is not limited thereto. In some embodiments, the insulating material layer IL1′ can be made of an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of these materials), an organic material (e.g., polyimide resin, epoxy resin, or acrylic resin), or a combination thereof, but the present disclosure is not limited thereto.

[0027] (2) Forming a second conductive material layer M2' on the insulating material layer IL1'. The second conductive material layer M2' can be formed on the insulating material layer IL1', for example, by performing a sputtering process, a chemical plating process, a patch process, or other suitable processes, but the present disclosure is not limited thereto. In some embodiments, the material of the second conductive material layer M2' can include metal. For example, the material of the second conductive material layer M2' can include copper, aluminum, or other suitable metals, but the present disclosure is not limited thereto. In other embodiments, the material of the second conductive material layer M2' can include electroless nickel immersion gold (ENIG), which can reduce the possibility of metal oxidation and facilitate the electrical connection between the subsequently formed electrical connection layer EL and the second conductive layer M2.

[0028] (3) Removing a portion of the second conductive material layer M2′ to form a second conductive layer M2. Removing a portion of the second conductive material layer M2′ can be accomplished, for example, by performing a patterning process, but the present disclosure is not limited thereto. The material of the second conductive layer M2 can be the same as or different from the material of the first conductive layer M1, but the present disclosure is not limited thereto.

[0029] (4) Forming an insulating layer IL2 on the insulating material layer IL1'. The insulating layer IL2 may be formed by, for example, first forming an insulating material layer (not shown) on the insulating material layer IL1' by chemical vapor deposition or other suitable processes, and then patterning the insulating material layer, but the present disclosure is not limited thereto. In this embodiment, the insulating layer IL2 has an opening IL2_OP that exposes a portion of the insulating material layer IL1'. The opening IL2_OP, together with the second conductive layer M2, can expose a portion of the insulating material layer IL1'.

[0030] (5) A portion of the insulating material layer IL1′ is removed to form an insulating layer IL1 having a through hole IL1_V, wherein the through hole IL1_V of the insulating layer IL1 exposes a portion of the first conductive layer M1. The through hole IL1_V of the insulating layer IL1 can be formed, for example, by performing an etching process (e.g., a wet etching process), a drilling process (e.g., a mechanical drilling process or a laser drilling process), or other suitable processes, but the present disclosure is not limited thereto. From another perspective, the insulating layer IL1 has a top surface IL1_T, a bottom surface IL1_B, and sidewalls IL1_S, wherein the top surface IL1_T of the insulating layer IL1 faces the second conductive layer M2, the bottom surface IL1_B of the insulating layer IL1 faces the first conductive layer M1, and the sidewalls IL1_S of the insulating layer IL1 define the outline of the through hole IL1_V.

[0031] In this embodiment, the insulating layer IL1 is formed to have an aspect ratio greater than 1. The aspect ratio of the insulating layer IL1 is, for example, the ratio between the height IL1_H of the insulating layer IL1 and the aperture IL1_D of the insulating layer IL1. The aperture IL1_D of the insulating layer IL1 may be, for example, the diameter or width of the through-hole IL1_V in the insulating layer IL1. In some embodiments, the aspect ratio of the insulating layer IL1 may be less than 6, but the present disclosure is not limited thereto. The height IL1_H of the insulating layer IL1 may be, for example, between 15 microns and 200 microns (15 μm ≦ IL1_H ≦ 200 μm), and the aperture IL1_D of the insulating layer IL1 may be, for example, less than 150 microns (IL1_D < 150 μm), but the present disclosure is not limited thereto.

[0032] 1 , an electrical connection layer EL is formed in the through hole IL1_V of the insulating layer IL1 .

[0033] In this embodiment, the following steps may be performed to form the electrical connection layer EL in the through hole IL1_V of the insulating layer IL1 , but the present disclosure is not limited thereto.

[0034] (1) First, a conductive ball CB is formed in the through hole IL1_V of the insulating layer IL1. The conductive ball CB can be implanted in the through hole IL1_V of the insulating layer IL1 using an existing ball implantation machine, but the present disclosure is not limited thereto. In some embodiments, the number of conductive balls CB can be single or multiple depending on the needs. In this embodiment, the conductive ball CB is shown as a single conductive ball, but the present disclosure is not limited thereto. In some embodiments, the material of the conductive ball CB can include metal. For example, the material of the conductive ball CB can include tin, tin alloy, or other suitable metal / alloy, but the present disclosure is not limited thereto.

[0035] (2) Then, the conductive balls CB are subjected to a reflow process to form the electrical connection layer EL. In this embodiment, the temperature, time, or other process conditions of the reflow process for the conductive balls CB can be set based on the material of the conductive balls CB, and this disclosure does not impose any restrictions.

[0036] In this embodiment, the electrical connection layer EL is formed by performing a reflow process on the conductive balls CB, so that the electrical connection layer EL can be formed in the through hole IL1_V of the insulating layer IL1 having a relatively large aspect ratio. The electrical connection layer EL can be electrically connected to the first conductive layer M1 and the second conductive layer M2. This can reduce the possibility of the first conductive layer M1 and the second conductive layer M2 being electrically disconnected, thereby improving the yield of the electronic device 10a.

[0037] Furthermore, in this embodiment, the distance EL_D between the electrical connection layer EL and the substrate SB is smaller than the distance IL2_D between the insulating layer IL2 and the substrate SB. The aforementioned distance EL_D can, for example, be measured between the portion of the electrical connection layer EL furthest from the substrate SB and the substrate SB in the normal direction n to the substrate SB, and the aforementioned distance IL2_D can, for example, be measured between the portion of the insulating layer IL2 furthest from the substrate SB and the substrate SB in the normal direction n to the substrate SB. Because the distance EL_D between the electrical connection layer EL and the substrate SB in this embodiment is smaller than the distance IL2_D between the insulating layer IL2 and the substrate SB, the height of the electrical connection layer EL can be smaller than the height of the insulating layer IL2, thereby reducing the possibility of unnecessary electrical connection between subsequently formed layers and the electrical connection layer EL. However, in other embodiments, the distance EL_D between the electrical connection layer EL and the substrate SB can be greater than the distance IL2_D between the insulating layer IL2 and the substrate SB.

[0038] At this point, the manufacturing of the electronic device 10a of this embodiment is completed, but the present disclosure is not limited thereto.

[0039] FIG2 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a second embodiment of the present disclosure. It should be noted that the embodiment of FIG2 may retain the component numbers and some of the details of the embodiment of FIG1 , wherein identical or similar components are represented by identical or similar numbers, and descriptions of identical technical details are omitted.

[0040] 2 , the main difference between the manufacturing method of the electronic device 10b in FIG. 2 and the manufacturing method of the aforementioned electronic device 10a is that it further includes forming a second conductive layer M2a on the sidewall IL1_S of the insulating layer IL1.

[0041] Specifically, in this embodiment, after forming the insulating layer IL1 having the through hole IL1_V and before forming the electrical connection layer EL in the through hole IL1_V of the insulating layer IL1, a second conductive layer M2a may be further formed on the sidewalls IL1_S of the insulating layer IL1. In some embodiments, at least a portion of the sidewalls IL1_S of the first insulating layer IL1 is covered by the second conductive layer M2a.

[0042] The second conductive layer M2a can be formed on the sidewalls IL1_S of the insulating layer IL1 by, for example, sputtering, chemical plating, or other suitable processes, but the present disclosure is not limited thereto. In some embodiments, the material of the second conductive layer M2a can include metal. For example, the material of the second conductive layer M2a can include copper, aluminum, or other suitable metals, but the present disclosure is not limited thereto.

[0043] In this embodiment, the second conductive layer M2a is in the form of a continuous film layer and may be electrically connected to the first conductive layer M1 and / or the second conductive layer M2, but the present disclosure is not limited thereto. Furthermore, the material of the second conductive layer M2a may be the same as or different from the material of the first conductive layer M1 and / or the second conductive layer M2, but the present disclosure is not limited thereto.

[0044] In this embodiment, the electrical connection layer EL may cover the second conductive layer M2a on the sidewall IL1_S of the first insulating layer IL1, but the present disclosure is not limited thereto.

[0045] In this embodiment, by forming the second conductive layer M2a on the sidewall IL1_S of the insulating layer IL1, the wettability between the sidewall IL1_S of the insulating layer IL1 and the conductive ball CB after the reflow process can be improved, so that the formed electrical connection layer EL can almost completely fill the through hole IL1_V of the insulating layer IL1. This further reduces the possibility of the first conductive layer M1 and the second conductive layer M2 being electrically disconnected due to defects in the electrical connection layer EL, thereby improving the yield of the electronic device 10b.

[0046] FIG3 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a third embodiment of the present disclosure. It should be noted that the embodiment of FIG3 may retain the component numbers and some details of the embodiment of FIG1 , wherein identical or similar reference numbers are used to represent identical or similar components, and descriptions of identical technical details are omitted.

[0047] 3 , the main difference between the manufacturing method of the electronic device 10 c in FIG. 3 and the manufacturing method of the aforementioned electronic device 10 a is that the method further includes forming a second conductive layer M2 b on the sidewall IL1_S of the insulating layer IL1 .

[0048] Specifically, in this embodiment, after forming the insulating layer IL1 having the through-hole IL1_V and before forming the electrical connection layer EL in the through-hole IL1_V of the insulating layer IL1, a second conductive layer M2b may be formed on the sidewall IL1_S of the insulating layer IL1. In some embodiments, at least a portion of the sidewall IL1_S of the first insulating layer IL1 is covered by the second conductive layer M2b. In some embodiments, the second conductive layer M2b covers the portion of the sidewall IL1_S adjacent to the second conductive layer M2, but does not cover the portion of the sidewall IL1_S adjacent to the first conductive layer M1, but is not limited thereto.

[0049] The second conductive layer M2b can be formed on the sidewalls IL1_S of the insulating layer IL1 by, for example, sputtering, chemical plating, or other suitable processes, but the present disclosure is not limited thereto. In some embodiments, the material of the second conductive layer M2b can include metal. For example, the material of the second conductive layer M2b can include copper, aluminum, or other suitable metals, but the present disclosure is not limited thereto.

[0050] In this embodiment, the second conductive layer M2b is in the form of a discontinuous film layer. For example, the second conductive layer M2b may include multiple separate conductive patterns. In some embodiments, most or all of the conductive patterns are not electrically connected to the first conductive layer M1 and the second conductive layer M2, but this is not limited to this. In some embodiments, the conductive patterns may be electrically connected to the second conductive layer M2 but not to the first conductive layer M1.

[0051] In this embodiment, the electrical connection layer EL may cover the second conductive layer M2b on the sidewall IL1_S of the first insulating layer IL1, but the present disclosure is not limited thereto.

[0052] In this embodiment, by forming the second conductive layer M2b on the sidewall IL1_S of the insulating layer IL1, the wettability between the sidewall IL1_S of the insulating layer IL1 and the conductive balls CB obtained after the reflow process can be improved, so that the formed electrical connection layer EL can almost completely fill the through hole IL1_V of the insulating layer IL1. This further reduces the possibility of electrical disconnection between the first conductive layer M1 and the second conductive layer M2 due to defects in the electrical connection layer EL, thereby improving the yield of the electronic device 10c.

[0053] FIG4 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a fourth embodiment of the present disclosure. It should be noted that the embodiment of FIG4 may utilize the same component numbers and some details as the embodiment of FIG1 , with identical or similar components being designated by the same or similar numbers and descriptions of identical technical details being omitted.

[0054] 4 , the main difference between the manufacturing method of the electronic device 10d in FIG. 4 and the manufacturing method of the aforementioned electronic device 10a is that in the step of forming the electrical connection layer EL in the through hole IL1_V of the insulating layer IL1, the first metal layer M1 and the conductive ball CB have opposite electrical properties to each other.

[0055] In detail, in this embodiment, the following steps may be performed to form the electrical connection layer EL in the through hole IL1_V of the insulating layer IL1, but the present disclosure is not limited thereto.

[0056] (1) First, a conductive ball CB is formed in the through hole IL1_V of the insulating layer IL1. The conductive ball CB can be implanted in the through hole IL1_V of the insulating layer IL1 using, for example, a conventional ball implantation machine, but the present disclosure is not limited thereto. In this embodiment, the conductive ball CB is shown as a plurality of conductive balls, but the present disclosure is not limited thereto. Furthermore, the material of the conductive ball CB can refer to the above embodiment and will not be further described here.

[0057] (2) Next, the first metal layer M1 is charged with a first charge, and the conductive ball CB is charged with a second charge. The method of charging the first metal layer M1 with the first charge and the conductive ball CB with the second charge may be, for example, by applying an electric field, a magnetic field, or other suitable methods, but the present disclosure is not limited thereto. In this embodiment, the electrical properties of the first charge and the second charge are opposite to each other. For example, the first charge may be a positive charge, and the second charge may be a negative charge; or the first charge may be a negative charge, and the second charge may be a positive charge. It is worth noting that in some embodiments, the second metal layer M2 may also be charged with a second charge.

[0058] (3) Next, the conductive balls CB are subjected to a reflow process to form the electrical connection layer EL. In this embodiment, the temperature, time, or other process conditions of the reflow process for the conductive balls CB can be set based on the material of the conductive balls CB, and this disclosure does not impose any restrictions.

[0059] In this embodiment, by ensuring that the first metal layer M1 and the conductive balls CB have opposite electrical properties, the conductive balls CB can be attracted to the first conductive layer M1 through the through holes IL1_V of the insulating layer IL1. This allows the formed electrical connection layer EL to almost completely fill the through holes IL1_V of the insulating layer IL1. This reduces the possibility of electrical disconnection between the first conductive layer M1 and the second conductive layer M2 due to defects in the electrical connection layer EL, thereby improving the yield of the electronic device 10d.

[0060] FIG5 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a fifth embodiment of the present disclosure. It should be noted that the embodiment of FIG5 may utilize the same component numbers and some details as the embodiments of FIG3 and FIG4 , wherein identical or similar components are represented by the same or similar numbers, and descriptions of identical technical details are omitted.

[0061] 5 , the manufacturing method of the electronic device 10e in FIG5 combines part of the manufacturing method of the electronic device 10c and part of the manufacturing method of the electronic device 10d.

[0062] Specifically, in this embodiment, after forming the insulating layer IL1 having the through hole IL1_V, the second conductive layer M2b is formed on the sidewall IL1_S of the insulating layer IL1. Next, after forming the second conductive layer M2b on the sidewall IL1_S of the insulating layer IL1, the electrical connection layer EL is formed in the through hole IL1_V of the insulating layer IL1.

[0063] Based on this, in the present embodiment, by forming the second conductive layer M2b on the sidewall IL1_S of the insulating layer IL1, the wettability between the sidewall IL1_S of the insulating layer IL1 and the conductive ball CB after the reflow process can be improved, so that the formed electrical connection layer EL can almost completely fill the through hole IL1_V of the insulating layer IL1, thereby reducing the possibility of the first conductive layer M1 and the second conductive layer M2 being electrically disconnected due to defects in the electrical connection layer EL, thereby improving the yield of the electronic device 10e.

[0064] Furthermore, in this embodiment, by ensuring that the first metal layer M1 and the conductive balls CB have opposite electrical properties, the conductive balls CB can be attracted to the first conductive layer M1 via the through holes IL1_V of the insulating layer IL1, so that the formed electrical connection layer EL can be almost completely filled into the through holes IL1_V of the insulating layer IL1. This reduces the possibility of electrical disconnection between the first conductive layer M1 and the second conductive layer M2 due to defects in the electrical connection layer EL, thereby improving the yield of the electronic device 10e.

[0065] FIG6 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a sixth embodiment of the present disclosure. It should be noted that the embodiment of FIG6 may utilize the same component numbers and some details as the embodiment of FIG3 , wherein identical or similar components are represented by the same or similar numbers, and descriptions of identical technical details are omitted.

[0066] 6 , the main difference between the manufacturing method of the electronic device 10 f in FIG. 6 and the manufacturing method of the aforementioned electronic device 10 c is that after forming the second conductive layer M2 b on the sidewall IL1_S of the insulating layer IL1, an electrical connection layer EL including a plurality of conductive particles CP and a resin layer RL is formed in the through hole IL1_V of the insulating layer IL1.

[0067] In this embodiment, forming the electrical connection layer EL including the plurality of conductive particles CP and the resin layer RL may include performing the following steps, but the present disclosure is not limited thereto.

[0068] (1) First, an electrical connection material layer EL' is formed on the insulating layer IL1, wherein the electrical connection material layer EL' overlaps with the through hole IL1_V of the insulating layer IL1 in the normal direction n of the substrate SB. The electrical connection material layer EL' can be formed on the insulating layer IL1, for example, by a coating process or other suitable process, but the present disclosure is not limited thereto. In this embodiment, the material of the electrical connection material layer EL' includes a plurality of conductive particles CP and a resin RS, wherein the plurality of conductive particles CP are dispersed in the resin RS. The material properties of the plurality of conductive particles CP can be, for example, the same or similar to the material of the first conductive layer M1, the second conductive layer M2 and / or the second conductive layer M2b, so that the plurality of conductive particles CP tend to approach the first conductive layer M1, the second conductive layer M2 and / or the second conductive layer M2b and connect thereto during the subsequent heating process. In some embodiments, the material of the plurality of conductive particles CP can include copper, aluminum or other suitable metals, and the resin RS can include epoxy, acrylic or other suitable resins, but the present disclosure is not limited thereto.

[0069] (2) Next, a heating process is performed on the electrical connection material layer EL' to form the electrical connection layer EL. In this embodiment, the temperature, time, or other process conditions of the heating process for the electrical connection material layer EL' can be set based on the material of the electrical connection material layer EL', and this disclosure does not limit this.

[0070] In the present embodiment, by performing a heating process on the electrical connection material layer EL′, the plurality of conductive particles CP therein can move toward the first conductive layer M1, the second conductive layer M2, and / or the second conductive layer M2b. For example, the conductive particles CP can be gathered on the sidewall IL1_S of the insulating layer IL1 and connected to the second conductive layer M2b. Thus, the first conductive layer M1 and the second conductive layer M2 can be electrically connected to each other via the plurality of conductive particles CP and the second conductive layer M2b. This reduces the possibility of the first conductive layer M1 and the second conductive layer M2 being not electrically connected due to defects in the electrical connection layer EL, thereby improving the yield of the electronic device 10f.

[0071] In addition, in the present embodiment, the resin RS forms a resin layer RL due to the aforementioned heating process, wherein the resin layer RL can fill the through hole IL1_V of the insulating layer IL1 , but the present disclosure is not limited thereto.

[0072] In this embodiment, the distance between adjacent conductive patterns in the second conductive layer M2b can be less than 20 microns. This facilitates electrical connection between adjacent conductive patterns in the second conductive layer M2b when the plurality of conductive particles CP are aggregated on the sidewalls IL1_S of the insulating layer IL1. However, the present disclosure is not limited to this. It is worth noting that in this embodiment, the second conductive layer M2a can also be formed as a continuous film on the sidewalls IL1_S of the insulating layer IL1. However, the present disclosure is not limited to this.

[0073] FIG7 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to a seventh embodiment of the present disclosure. It should be noted that the embodiment of FIG7 may retain the component numbers and some details of the embodiment of FIG1 , wherein identical or similar components are represented by identical or similar numbers, and descriptions of identical technical details are omitted.

[0074] 7 , the main difference between the manufacturing method of the electronic device 10g in FIG. 7 and the manufacturing method of the aforementioned electronic device 10a is that a buffer layer BF is further formed between the insulating layer IL1 and the second conductive layer M2.

[0075] Specifically, after the insulating layer IL1 is formed and / or before the second conductive layer M2 is formed, a buffer layer BF may be formed on the top surface IL1_T of the insulating layer IL1. The buffer layer BF may be formed, for example, by sputtering, chemical plating, or other suitable processes, but the present disclosure is not limited thereto. In some embodiments, the material of the buffer layer BF may include a conductive material. For example, the material of the buffer layer BF may include silver, aluminum, gold, tungsten, copper, other metals, or other suitable materials, but the present disclosure is not limited thereto. In some embodiments, the thickness of the buffer layer BF is less than or equal to 1 micron, which can reduce the possibility of warping of the electronic device 10g during subsequent manufacturing processes.

[0076] After forming the buffer layer BF, a roughening process may be optionally performed to roughen the sidewalls IL1_S of the insulating layer IL1. After the roughening process, because the insulating layer IL1 and the buffer layer BF comprise different materials, the sidewalls IL1_S of the insulating layer IL1 may have a relatively rough surface relative to the surface of the buffer layer BF. In some embodiments, the roughening process may include a mechanical roughening process or a chemical roughening process, but the present disclosure is not limited thereto. Furthermore, in this embodiment, the top surface IL1_T of the insulating layer IL1 is covered by the buffer layer BF and is not affected by the roughening process. Therefore, the roughening process may result in the top surface IL1_T of the insulating layer IL1 having a roughness less than that of the sidewalls IL1_S of the insulating layer IL1, but the present disclosure is not limited thereto.

[0077] Furthermore, in this embodiment, the second conductive layer M2 can be formed by a sputtering process or a chemical plating process, and the second conductive layer M2a can be further disposed on the sidewalls IL1_S of the insulating layer IL1. In some embodiments, the sidewalls IL1_S of the insulating layer IL1 have a relatively large roughness due to the aforementioned roughening process, thereby improving the adhesion between subsequently formed layers and the sidewalls IL1_S of the insulating layer IL1. Therefore, the second conductive layer M2a disposed on the sidewalls IL1_S of the insulating layer IL1 can be in the form of a continuous layer, but the present disclosure is not limited thereto.

[0078] Furthermore, in this embodiment, the electrical connection layer EL can be formed on the second conductive layer M2 by electroplating or other suitable processes, but the present disclosure is not limited thereto. In some embodiments, the material of the electrical connection layer EL may include a metal. For example, the material of the electrical connection layer EL may include copper, aluminum, or other suitable metals, but the present disclosure is not limited thereto. In other embodiments, the electronic device 10g may further include an electroless nickel immersion gold (ENIG) layer (not shown) formed on the electrical connection layer EL to facilitate electrical connection between the electronic device 10g and electronic components, but the present disclosure is not limited thereto.

[0079] Based on this, in this embodiment, a roughening process is performed to give the top surface BF_T of the buffer layer BF and the sidewalls IL1_S of the insulating layer IL1 a relatively rough surface. This facilitates adhesion of the subsequently formed second conductive layer M2 to the top surface BF_T of the buffer layer BF and the sidewalls IL1_S of the insulating layer IL1. This reduces the likelihood of delamination of the second conductive layer M2 during subsequent manufacturing processes, thereby improving the yield of the electronic device 10g. Furthermore, the provision of the buffer layer BF ensures that the top surface IL1_T of the insulating layer IL1 remains relatively flat during the roughening process, thereby improving the signal transmission quality of the electronic device 10g.

[0080] FIG8 is a cross-sectional flow diagram of a method for manufacturing an electronic device according to an eighth embodiment of the present disclosure. It should be noted that the embodiment of FIG8 may utilize the same component numbers and some details as the embodiment of FIG7 , with identical or similar components being designated by the same or similar numbers and descriptions of identical technical details being omitted.

[0081] 8 , the main difference between the manufacturing method of the electronic device 10h in FIG. 8 and the manufacturing method of the aforementioned electronic device 10g is that the buffer layer BF is used as a mask to form the through hole IL1_V in the insulating layer IL1 .

[0082] Specifically, after forming the insulating material layer IL1', a buffer layer BF is formed on the insulating material layer IL1', wherein the buffer layer BF exposes a portion of the insulating material layer IL1'. That is, in this embodiment, the buffer layer BF is formed before forming the insulating layer IL1.

[0083] Then, using the buffer layer BF as a mask, a laser drilling process is performed on the insulating material layer IL1' to form a through hole IL1_V in the insulating layer IL1. In this embodiment, the buffer layer BF may have the characteristics of (1) high reflectivity to laser light (e.g., greater than 90%) and / or (2) low absorptivity (A) to laser light (e.g., less than 0.05), thereby reducing the possibility of laser light passing through the buffer layer BF and / or reducing the possibility of defects caused by excessive absorption of laser light by the buffer layer BF, thereby improving the process stability of forming the through hole IL1_V in the insulating layer IL1, wherein the absorptivity (A) satisfies the following relationship: , I 0 is the laser intensity incident on the buffer layer BF, and I 1 is the laser intensity transmitted through the buffer layer BF.

[0084] Based on this, in this embodiment, the buffer layer BF can be provided to serve as a mask during the laser drilling process of the insulating material layer IL1′. The buffer layer BF can adjust the angle between the sidewall IL1_S of the insulating layer IL1 and the top surface IL1_T and / or bottom surface IL1_B of the insulating layer IL1, so that the angle between the sidewall IL1_S of the insulating layer IL1 and the top surface IL1_T and / or bottom surface IL1_B of the insulating layer IL1 can approach 90 degrees. In some embodiments, the angle between the sidewall IL1_S of the insulating layer IL1 and the top surface IL1_T and / or bottom surface IL1_B of the insulating layer IL1 can be greater than or equal to 80 degrees and less than or equal to 100 degrees.

[0085] Table 1 below shows the relationship between the wavelength of the laser used in the laser drilling process in this embodiment and the material included in the buffer layer BF, but the present disclosure is not limited thereto.

[0086] [Table 1] Lasers used in the laser drilling process Buffer layer BF includes materials laser source Laser wavelength Materials with laser reflectivity >90% Materials with laser absorption brightness <0.05 CO2 laser 10640nm Aluminum, copper, gold, silver Molybdenum, aluminum, copper, gold, silver Fiber laser 1070-1080nm Aluminum, copper, gold, silver Aluminum, copper, gold, silver Green laser 532nm silver silver

[0087] Figure 9A is a schematic top view of an electronic device according to an embodiment of the present disclosure, and Figure 9B is a schematic cross-sectional view of an embodiment taken along line AA' in Figure 9A. It should be noted that the electronic device 10 depicted in Figures 9A and 9B may be any of the electronic devices 10a-10h described above, and the present disclosure is not limited thereto. The following briefly describes the structure of the electronic device 10 according to this embodiment with reference to Figures 9A and 9B. Identical or similar reference numbers are used to represent identical or similar components, and descriptions of identical technical details are omitted.

[0088] In this embodiment, the electronic device 10 is an antenna device that can receive high-frequency signals (such as electromagnetic waves) from the outside world or can transmit high-frequency signals to the outside world, but the present disclosure is not limited thereto.

[0089] Referring to Figures 9A and 9B , the electronic device 10 of this embodiment may include a substrate SB, a first conductive layer M1, an insulating layer IL1, a second conductive layer M2, and an electrical connection layer EL. In this embodiment, the electrical connection layer EL may include multiple patterned structures. For example, the electrical connection layer EL includes a patterned electrical connection layer EL1 and a patterned electrical connection layer EL2, wherein a portion of the top surface IL1_T of the insulating layer IL1 may be exposed between adjacent patterned electrical connection layers EL1 and EL2, but the present disclosure is not limited to this. In some embodiments, the electrical connection layer EL includes a patterned structure that may be filled into one or more through-holes IL1_V of the insulating layer IL1 to electrically connect to the first conductive layer M1. For example, the patterned electrical connection layer EL1 may be filled into two through-holes IL1_V of the insulating layer IL1, and the patterned electrical connection layer EL2 may be filled into one through-hole IL1_V of the insulating layer IL1, but the present disclosure is not limited to this.

[0090] The first conductive layer M1 is, for example, disposed on the substrate SB. The materials of the substrate SB and the first conductive layer M1 can refer to the above embodiments and will not be described in detail herein.

[0091] The insulating layer IL1 is, for example, disposed on the first conductive layer M1, wherein the insulating layer IL1 has a through hole IL1_V that exposes a portion of the first conductive layer M1. In this embodiment, the through hole IL1_V of the insulating layer IL1 has an aspect ratio greater than 1. In some embodiments, the roughness of the top surface IL1_T of the insulating layer IL1 may be less than the roughness of the sidewalls IL1_S of the insulating layer IL1. The materials comprising the insulating layer IL1 can refer to the above embodiments and are not further described here.

[0092] The second conductive layer M2 is, for example, disposed on the insulating layer IL1, wherein at least a portion of the sidewalls IL1_S of the first insulating layer IL1 may be covered by the second conductive layer. The materials comprising the second conductive layer M2 can be referred to in the above embodiment and will not be further described here. The second conductive layer M2 may be electrically connected to the first conductive layer M1 via the through-holes IL1_V of the insulating layer IL1. Specifically, the second conductive layer M2a is disposed within the through-holes IL1_V of the insulating layer IL1 and is in the form of a continuous layer, but the present disclosure is not limited thereto. In other embodiments, although not shown in FIG. 9B , at least a portion of the sidewalls IL1_S of the first insulating layer IL1 may be covered by the second conductive layer M2b, wherein the second conductive layer M2b disposed within the through-holes IL1_V of the insulating layer IL1 is in the form of a discontinuous layer. For example, the second conductive layer M2b disposed within the through-holes IL1_V of the insulating layer IL1 may include a plurality of separate conductive patterns.

[0093] The electrical connection layer EL, for example, is disposed in the through hole IL1_V of the insulating layer IL1, where the electrical connection layer EL is electrically connected to the first conductive layer M1 and the second conductive layer M2. In some embodiments, the roughness of the top surface EL_T of the electrical connection layer EL may be less than the roughness of the sidewalls IL1_S of the insulating layer IL1. The materials comprising the electrical connection layer EL can be referenced to the above embodiments and are not further described here.

[0094] In some embodiments, the electronic device 10 of this embodiment may further include a buffer layer BF. The buffer layer BF is, for example, disposed between the insulating layer IL1 and the second conductive layer M2, and is located, for example, on the top surface IL1_T of the insulating layer IL1. In some embodiments, the top surface BF_T of the buffer layer BF may have a roughness less than the roughness of the sidewalls IL1_S of the insulating layer IL1. The materials comprising the buffer layer BF can be referenced to the above embodiments and are not further described here.

[0095] In summary, in the electronic devices provided in some embodiments of the present disclosure, the process for forming the electrical connection layer proposed in each embodiment of the present disclosure can form the electrical connection layer in a through hole of the insulating layer having a relatively large aspect ratio, and this electrical connection layer can be utilized to electrically connect the first conductive layer and the second conductive layer to each other, thereby reducing the possibility of the first conductive layer and the second conductive layer not being electrically connected, thereby improving the yield of the electronic devices provided in some embodiments of the present disclosure.

[0096] 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h: Electronic devices A-A': section line BF: buffer layer BF_T, IL1_T: top surface CB: Conductive ball CP: Conductive particles EL: Electrical connection layer EL': electrical connection material layer EL1, EL2: patterned electrical connection layer EL_D, IL2_D: distance IL1, IL2: insulation layer IL1': insulation material layer IL1_B: bottom surface IL1_D: aperture IL1_H: Height IL1_S: Sidewall IL1_V: Through hole IL2_OP: Opening M1: first conductive layer M2, M2a, M2b: second conductive layer M2': second conductive material layer n: normal direction RL: resin layer RS: Resin SB:Substrate

Claims

1. A method for manufacturing an electronic device, comprising: A first conductive layer is formed on the substrate; A first insulating layer and a second conductive layer are formed on the first conductive layer, wherein the first insulating layer is disposed between the second conductive layer and the first conductive layer, and the first insulating layer has a through-hole that exposes a portion of the first conductive layer; and forming an electrical connection layer in the through-hole of the first insulating layer, wherein the electrical connection layer covers the second conductive layer on the sidewall of the first insulating layer, wherein the aspect ratio of the through-hole of the first insulating layer is greater than 1, and wherein at least a portion of the sidewall of the first insulating layer is covered by the second conductive layer.

2. A method of manufacturing an electronic device as claimed in claim 1, wherein the step of forming the electrical connection layer in the through-hole of the first insulating layer comprises: Conductive spheres are formed in the through-holes of the insulating layer; And the conductive balls undergo a reflow soldering process.

3. The method of manufacturing an electronic device as claimed in claim 2, wherein the step of forming the electrical connection layer in the through-hole of the first insulating layer further comprises: Before the reflow process is performed on the conductive ball, the first conductive layer is given a first charge and the conductive ball is given a second charge, wherein the first charge and the second charge are opposite in polarity.

4. A method of manufacturing an electronic device as claimed in claim 1, wherein the step of forming the electrical connection layer in the through-hole of the first insulating layer comprises: An electrical connection material layer is formed on an insulating layer, wherein the electrical connection material layer overlaps with the through-hole of the insulating layer in the normal direction of the substrate, the material of the electrical connection material layer includes a plurality of conductive particles and resin, and the plurality of conductive particles are dispersed in the resin; and a heating process is performed on the electrical connection material layer to dispose the plurality of conductive particles on the sidewall of the first insulating layer and electrically connect them to the first conductive layer and the second conductive layer.

5. A method of manufacturing an electronic device as claimed in claim 1, wherein the step of forming the first insulating layer and the second conductive layer on the first conductive layer comprises: A first insulating material layer is formed on the first conductive layer; A second insulating layer is formed on the first insulating material layer, wherein the second insulating layer has an opening that exposes a portion of the first insulating material layer; A second conductive layer is formed on the first insulating material layer, wherein the second conductive layer exposes a portion of the first insulating material layer; And remove a portion of the first insulating material layer to form the first insulating layer having the through-hole.

6. The method of manufacturing an electronic device as claimed in claim 1, wherein the step of forming the first insulating layer and the second conductive layer on the first conductive layer further comprises: A buffer layer is formed between the first insulating layer and the second conductive layer, wherein the buffer layer is disposed on the top surface of the first insulating layer; And a roughening process is performed to roughen the sidewalls of the first insulating layer.

7. A method of manufacturing an electronic device as claimed in claim 6, wherein the buffer layer is used as a mask to form the through-hole of the first insulating layer.

8. An electronic device comprising: substrate; A first conductive layer is disposed on the substrate; A first insulating layer is disposed on the first conductive layer, wherein the first insulating layer has a through-hole exposing a portion of the first conductive layer; a second conductive layer is disposed on the first insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer through the through-hole of the first insulating layer; and an electrical connection layer is disposed in the through-hole of the first insulating layer, wherein the electrical connection layer is electrically connected to both the first conductive layer and the second conductive layer, and the electrical connection layer covers the second conductive layer on the sidewall of the first insulating layer, wherein the aspect ratio of the through-hole of the first insulating layer is greater than 1, and wherein at least a portion of the sidewall of the first insulating layer is covered by the second conductive layer.

9. The electronic device of claim 8, wherein the second conductive layer covering at least a portion of the sidewall of the first insulating layer is a continuous film layer.

10. The electronic device of claim 8, wherein the second conductive layer covering at least a portion of the sidewall of the first insulating layer is a discontinuous film layer.

11. The electronic device of claim 8, wherein the electrical connection layer comprises conductive particles and a resin layer, wherein the conductive particles are electrically connected to the first conductive layer and the second conductive layer, and the resin layer fills the through-hole of the first insulating layer.

12. The electronic device of claim 8, further comprising a buffer layer disposed between the first insulating layer and the second conductive layer, and located on the top surface of the first insulating layer.

13. The electronic device of claim 12, wherein the roughness of the top surface of the buffer layer is less than the roughness of the sidewall of the first insulating layer.

14. The electronic device of claim 12, wherein the roughness of the top surface of the first insulating layer is less than the roughness of the sidewall of the first insulating layer.

15. The electronic device of claim 8, wherein the roughness of the top surface of the electrical connection layer is less than the roughness of the sidewall of the first insulating layer.

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