Method for forming semiconductor device structure and interconnect structure

Abstract

A method for forming a semiconductor device structure is provided. The method includes forming one or more first conductive structures in a first dielectric layer; forming a metal layer on each of the first conductive structures; forming a first etch stop layer on the metal layer; and forming a second etch stop layer on the first etch stop layer, wherein the second etch stop layer is a nitrogen-free layer. The method also includes forming a second dielectric layer on the second etch stop layer; and forming a second conductive structure in the second dielectric layer, wherein the second conductive structure passes through the second etch stop layer, the first etch stop layer, and the metal layer.

Description

Method for Forming a Semiconductor Device Structure and Interconnection Structure Embodiments of the present invention relate to semiconductor device structures, and more particularly to interconnection structures. As the semiconductor industry introduces a new generation of integrated circuits with higher performance and more functions, the component density of the formed integrated circuits increases, and the size of components or elements or the space between them decreases. In the past, size reduction was only limited by the photolithography ability to define structures, but smaller-sized devices introduce new limiting factors. For example, the aspect ratio of the conductive structure in the dielectric material of the interconnection structure in the back-end process increases, and the resistance随之 increases. Therefore, the interconnection structure needs to be improved. One embodiment is a method for forming a semiconductor device structure. The method includes forming one or more first conductive structures in a first dielectric layer; forming a metal layer on each of the first conductive structures; forming a first etch stop layer on the metal layer; forming a second etch stop layer on the first etch stop layer, where the second etch stop layer is a nitrogen-free layer. The method also includes forming a second dielectric layer on the second etch stop layer; and forming a second conductive structure in the second dielectric layer, and the second conductive structure passes through the second etch stop layer, the first etch stop layer, and the metal layer. Another embodiment is a method for forming a semiconductor device structure. The method includes forming one or more first conductive structures in a dielectric layer; forming a metal layer on each of the first conductive structures; selectively forming a barrier layer on the exposed surface of the dielectric layer; selectively forming a pre-layer on the metal layer; removing the barrier layer; covering the exposed surface of the pre-layer with a first etch stop layer such that a part of the first etch stop layer contacts the dielectric layer; and forming a second etch stop layer on the first etch stop layer. Other embodiments are interconnection structures, which include a first dielectric layer; a second dielectric layer located on the first dielectric layer; a metal layer located between the first dielectric layer and the second dielectric layer; a pre-layer located above the metal layer and between the first dielectric layer and the second dielectric layer, where the pre-layer contacts the upper surface and sidewalls of the metal layer. The interconnection structure also includes a first etch stop layer located above the pre-layer and between the first dielectric layer and the second dielectric layer; a second etch stop layer located above the first etch stop layer and between the first dielectric layer and the second dielectric layer, where the second etch stop layer is a metal-free layer; and a conductive structure extending from the first dielectric layer to the second dielectric layer. The following detailed description can be combined with the drawings for illustration to facilitate understanding of various aspects of the present invention. It should be noted that the various structures are only for illustrative purposes and are not drawn to scale, as is common in the industry. In fact, for clarity of illustration, the sizes of various structures can be arbitrarily increased or decreased. The following content provides different embodiments or examples that can implement different structures of the present invention. The embodiments of the following specific components and arrangements are used to simplify the content of the present invention rather than limit the present invention. For example, the description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where there are other additional components between the two rather than in direct contact. In addition, multiple examples of the present invention may reuse the same reference numerals for brevity, but the components with the same reference numerals in multiple embodiments and / or arrangements do not necessarily have the same corresponding relationships. In addition, spatial relative terms such as "below", "beneath", "lower", "above", "upper", or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. The spatial relative terms can extend to elements used in other directions, rather than being limited to the illustrated directions. The element can also be rotated 90 degrees or other angles, so the directional terms are only used to illustrate the directions in the illustration. FIG. 1A shows a stage of manufacturing a semiconductor device structure 100 including a device layer 200 and an interconnect structure 250. FIG. 1B shows a cross-sectional view of the device layer 200 in some embodiments. The device layer 200 includes a substrate 102 and one or more devices formed in or on the substrate 102. The substrate 102 can be a semiconductor substrate. In some embodiments, the substrate 102 includes a single-crystalline semiconductor layer on at least one surface of the substrate 102. The substrate 102 can include single-crystalline semiconductor materials such as, but not limited to, silicon, germanium, silicon-germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, gallium indium arsenide, gallium phosphide antimonide, gallium antimonide arsenide, or indium phosphide. For example, the composition of the substrate 102 is silicon. In some embodiments, the substrate 102 is a silicon-on-insulator substrate, which includes an insulating layer (not shown) between two silicon layers. In one embodiment, the insulating layer is an oxygen-containing material such as an oxide. The substrate 102 can include various regions, which can be doped with appropriate impurities (such as p-type or n-type impurities). For example, the dopant can be phosphorus for an n-type fin field-effect transistor, or boron for a p-type fin field-effect transistor. As described above, device layer 200 may include any suitable devices such as transistors, diodes, image sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. In some embodiments, device layer 200 includes transistors such as planar field-effect transistors, fin field-effect transistors, nanostructure transistors, or other suitable transistors. Nanostructure transistors may include nanosheet transistors, nanowire transistors, all-around-gate transistors, multi-bridge-channel transistors, or any transistor having a gate surrounding a channel. Examples of devices formed on substrate 102 may be the fin field-effect transistors shown in FIGS. 1A and 1B. Device layer 200 includes source / drain regions 124 and gate stacks 140 (only one is shown in FIG. 1A). Gate stacks 140 may each be located between source / drain region 124 as a source region and source / drain region 124 as a drain region. For example, gate stacks 140 may each extend along the Y axis between one or more source / drain regions 124 as a source region and one or more source / drain regions 124 as a drain region. As shown in FIG. 1B, two gate stacks 140 are formed on substrate 102. In some embodiments, more than two gate stacks 140 are formed on substrate 102. Although not shown, a channel region is formed between source / drain regions 124, and gate stacks 140 cover at least three surfaces of the channel region. Source / drain region 124 may include semiconductor materials such as silicon or germanium, III-V semiconductor compounds, II-VI semiconductor compounds, or other suitable semiconductor materials. Exemplary source / drain regions 124 may include, but are not limited to, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, gallium phosphoarsenide, silicon phosphide, indium arsenide, aluminum arsenide, indium phosphide, gallium nitride, indium gallium arsenide, aluminum indium arsenide, gallium antimonide, aluminum antimonide, gallium phosphide, or the like. Source / drain region 124 may include p-type dopants such as boron, n-type dopants such as phosphorus or arsenic, and / or other suitable dopants containing combinations thereof. The method of forming source / drain region 124 may be epitaxial growth, which may employ chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The channel region may include one or more semiconductor materials such as silicon, germanium, germanium tin, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium phosphide antimonide, gallium arsenide antimonide, gallium nitride, gallium phosphide, or indium phosphide; the channel region may include the same semiconductor material as substrate 102. In some embodiments, device layer 200 may include fin field-effect transistors, and the channel region is a plurality of fins located under gate stacks 140. In some embodiments, device layer 200 may include nanostructure transistors, and gate stacks 140 surround the channel region. As shown in FIGS. 1A and 1B, each of the gate stacks 140 includes a gate layer 138 located over the channel region (or surrounding the channel region used for the nanoscale transistor). The gate layer 138 can be a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, multi-layers of the foregoing, or the like, and can be deposited by atomic layer deposition, plasma-assisted chemical vapor deposition, molecular beam deposition, physical vapor deposition, or any suitable deposition technique. The gate stack 140 can further include a gate dielectric layer 136 located over the channel region. The gate layer 138 can be located over the gate dielectric layer 136. In some embodiments, an interface layer (not shown) can be located between the channel region 108 and the gate dielectric layer 136, and one or more work function layers (not shown) can be located between the gate dielectric layer 136 and the gate layer 138. The interface layer can include a dielectric material such as an oxygen-containing material, a nitrogen-containing material, or multi-layers of the foregoing, and can be formed by any suitable deposition method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition. The gate dielectric layer 136 can include a dielectric material such as an oxygen-containing material, a nitrogen-containing material, a high-k dielectric material having a dielectric constant greater than that of silicon oxide, or multi-layers of the foregoing. The gate dielectric layer 136 can be formed by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition. In some embodiments, the gate dielectric layer 136 can be a conformal layer. As used herein, the term "conformal layer" refers to a layer having substantially the same thickness over various regions. One or more work function layers can include titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, or the like. Gate spacers 122 can be formed along the sidewalls of the gate stack 140 (such as the sidewalls of the gate dielectric layer 136). The gate spacers 122 can include silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, the like, multi-layers of the foregoing, or combinations of the foregoing, and can be deposited by chemical vapor deposition, atomic layer deposition, or other suitable deposition techniques. In some embodiments, fin sidewall spacers 123 can be located on both sides of each source / drain region 124, and the fin sidewall spacers 123 and the gate spacers 122 can include the same material. Portions of the gate stack 140, the gate spacers 122, and the fin sidewall spacers 123 can be located over the isolation region 114. The isolation region 114 is located on the substrate 102. The isolation region 114 can include an insulating material such as an oxygen-containing material, a nitrogen-containing material, or a combination of the foregoing. In some embodiments, the isolation region 114 is a shallow trench isolation. The insulating material can be formed by high density plasma chemical vapor deposition, flowable chemical vapor deposition, or other suitable deposition processes. In one embodiment, the isolation region 114 includes silicon oxide formed by a flowable chemical vapor deposition process. A contact etch stop layer 126 is formed on the source / drain regions 124 and the isolation regions 114, and an interlayer dielectric layer 128 is formed on the contact etch stop layer 126. The contact etch stop layer 126 can provide a mechanism for stopping the etching process when forming an opening in the interlayer dielectric layer 128. The contact etch stop layer 126 can be conformally deposited on the surfaces of the source / drain regions 124 and the isolation regions 114. The contact etch stop layer 126 can include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, the like, or a combination thereof, and the deposition method thereof can be chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. The interlayer dielectric layer 128 can include an oxide formed from tetraethyl orthosilicate, undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass, fluorosilicate glass, phosphosilicate glass, borosilicate glass, organosilicate glass, silicon carbon oxide), and / or any suitable low dielectric constant dielectric material (such as a material with a dielectric constant lower than that of silicon dioxide), and the deposition method thereof can be spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, or any suitable deposition technique. The source / drain contact 142 can be located in the interlayer dielectric layer 128 and above the source / drain regions 124. The source / drain contact 142 can be conductive and include one or more of ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, and tantalum nitride, and the conductive contact can be formed by any suitable method such as electroless plating or physical vapor deposition. A silicide layer 144 can be located between the source / drain contact 142 and the source / drain regions 124. The composition of the silicide layer 144 can be a silicide of a metal or a metal alloy, and the metal can include noble metals, refractory metals, rare earth metals, alloys thereof, or a combination thereof. In an integrated circuit, an interconnection structure is used to provide signal wiring and power to semiconductor devices. An integrated circuit chip typically includes device layers fabricated by a front-end process, a middle-end process, and a back-end process. The device layers can be formed in and / or on a substrate, and the back-end process layers can be formed on the front side and / or the back side of the device layers. The device layers can include various semiconductor devices such as transistors, diodes, capacitors, resistors, or the like, and are formed in and / or on the substrate. In some embodiments, the device layers can also include middle-end process structures, such as one or more dielectric layers and conductive structures to connect to the gate and source / drain structures in the device layers. The interconnection structure generally includes conductive lines and vias formed in the device layers and the back-end process layers. FIG. 2 is a side cross-sectional view of stages of manufacturing a semiconductor device structure 100 in some embodiments. The interconnect structure 250 is located on the device layer 200 and the substrate 102. The interconnect structure 250 includes various conductive structures such as a plurality of conductive structures 204 and a plurality of conductive structures 206, and an intermetal dielectric layer 202 for separating and isolating the various conductive structures 204 and 206. In some embodiments, the conductive structure 204 is a conductive line, and the conductive structure 206 is a conductive via. The interconnect structure 250 includes multiple layers of the conductive structure 204, and the conductive structure 204 is disposed in each layer to provide a conductive path to the underlying device layer 200. The conductive structure 206 provides vertical electrical wiring from the device layer 200 to the conductive structure 204 and between the conductive structures 204. For example, the bottommost conductive structure 206 of the interconnect structure 250 can be electrically connected to the source / drain region 124 (FIGS. 1A and 1B) and the conductive contact on the gate layer 138 (FIGS. 1A and 1B). The composition of the conductive structure 204 and the conductive structure 206 can be one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, the composition of the conductive structure 204 and the conductive structure 206 is copper, aluminum, copper-aluminum alloy, titanium, titanium nitride, tantalum, tantalum nitride, titanium silicon nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten silicon nitride, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or a combination of the above. In some embodiments, a backside interconnect structure (not shown) similar to the interconnect structure 250 can be formed on the backside of the device layer 200 to provide power and / or additional signal connections to the device layer 200. The intermetal dielectric layer 202 includes one or more dielectric materials to provide an isolation function for the various conductive structures 204 and 206. The intermetal dielectric layer 202 can include multiple dielectric layers to bury the multiple layers of the conductive structures 204 and 206. The composition of the intermetal dielectric layer 202 can be a dielectric material such as silicon oxide, silicon oxycarbide, or silicon carbide. In some embodiments, the intermetal dielectric layer 202 includes a dielectric material having a dielectric constant of about 1 to about 5. FIGS. 3A to 3H are side cross-sectional views of various stages in manufacturing an interconnect structure 300 in some embodiments. The interconnect structure 300 can be used to form one or more layers of the interconnect structure 250 shown in FIGS. 1A and 1B and FIG. 2. As shown in FIG. 3A, the interconnect structure 300 includes a dielectric layer 310 and a dielectric layer 314 on the dielectric layer 310. The dielectric layer 310 can be an interlayer dielectric layer or an intermetallic dielectric layer. For example, the dielectric layer 310 can be the interlayer dielectric layer 128 (FIGS. 1A and 1B) or the intermetallic dielectric layer 202 (FIG. 2). The dielectric layer 310 can include the same material as the interlayer dielectric layer 128 or the intermetallic dielectric layer 202. In some embodiments, the dielectric layer 310 includes a low dielectric constant dielectric material with a dielectric constant of about 1.5 to about 3.9. In an exemplary embodiment, the dielectric layer 310 is silicon oxycarbide. The method of forming the dielectric layer 310 can be chemical vapor deposition, flowable chemical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. The dielectric layer 314 can include the same material as the dielectric layer 310, and the method of forming it can be the same as the process for forming the dielectric layer 310. The dielectric layer 310 includes one or more conductive structures 312 (only one is shown) located in the dielectric layer 310. The conductive structures 312 include conductive materials such as copper, cobalt, ruthenium, molybdenum, chromium, tungsten, molybdenum, rhodium, iridium, nickel, palladium, platinum, silver, gold, aluminum, alloys of the above, or other suitable materials. In some embodiments, the conductive structures 312 include metals. The method of forming the conductive structures 312 can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable processes. One or more conductive structures 312 can be electrically connected to the source / drain regions 124 (FIGS. 1A and 1B) and the gate layer 138 (FIGS. 1A and 1B). In some embodiments, the conductive structures 312 can be conductive contacts located in the interlayer dielectric layer 128, or conductive structures 204 and 206 located in the intermetallic dielectric layer 202. For example, the conductive structures 312 can be the conductive lines or conductive vias shown in FIG. 2. In some embodiments, the conductive structures 312 can include a barrier layer (not shown) between the dielectric layer 310 and the conductive material of the conductive structures 312. The liner layer can include a conductive material such as a metal or a metal nitride. In FIG. 3B, openings 311 and 313 are formed in the dielectric layer 314. The openings 311 and 313 will be filled with a conductive material to form conductive structures (such as conductive structures 204 or 206) therein. The openings 311 and 313 can be via openings or line openings, and can be formed by one or more etching processes. For example, the opening 311 can be a via opening, and the opening 313 can be a line opening, and the method of forming them can be a dual damascene process or any suitable etching and patterning process. In FIG. 3C, the method of forming one or more conductive structures 316 and 317 in the dielectric layer 314 can be to fill the openings 311 and 313 with a conductive material. The conductive structures 316 and 317 include conductive materials such as copper, cobalt, aluminum, ruthenium, molybdenum, tungsten, nickel, titanium, zirconium, tantalum, zinc, alloys of the above, or other suitable materials. The method of forming the conductive structures 316 and 317 can be any suitable process, such as electrochemical plating, electroless deposition, physical vapor deposition, or chemical vapor deposition. The conductive structure 316 can be the conductive structure 206, and the conductive structure 317 can be the conductive structure 204. A barrier layer 318 can be formed between the dielectric layer 314 and the conductive structures 316 and 317. In some embodiments, a liner (not shown) can be formed between the barrier layer 318 and the conductive structures 316 and 317. The method of forming the barrier layer 318 and the liner can be any suitable process, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition. In some embodiments, the barrier layer 318 and the liner (if employed) are compliant layers formed by atomic layer deposition. The barrier layer 318 can include tantalum, titanium, manganese, zirconium, indium, tantalum nitride, titanium nitride, or other suitable materials. In some embodiments, the conductive structures 316 and 317 include metals such as copper that are prone to diffusion, and the barrier layer 318 can prevent the metal from diffusing from the conductive structures 316 and 317 into the dielectric layer 314. If a liner is employed, it can act as an adhesion layer to adhere the conductive structures 316 and 317 and the barrier layer 318 to the liner. In these examples, the liner can include a metal such as cobalt. In these examples, the liner can alternatively include the same material as the conductive structures 316 and 317. In some embodiments, the conductive structures 316 and 317 include metals such as cobalt that are not prone to diffusion, so the barrier layer 318 and the liner can be omitted. In some embodiments, the conductive structures 316 and 317 near the top of the interconnect structure 300 do not include a liner, while the conductive structures 316 and 317 near the bottom of the interconnect structure 300 include a liner. After forming the conductive structures 316 and 317 in the openings 311 and 313, a planarization process such as a chemical mechanical polishing process can be performed until the dielectric layer 314 is exposed. After the planarization process, the upper surfaces of the conductive structures 316 and 317, the barrier layer 318, the liner (if present), and the dielectric layer 314 are substantially coplanar. Next, a metal layer 322 is selectively formed on each of the conductive structures 316 and 317. In the example where the barrier layer 318 and the pad (if used) include metal, the metal layer 322 is also formed on the barrier layer 318 and the pad. The metal layer 322 includes a metal having a higher carbon solubility than the materials of the conductive structures 316 and 317. In some embodiments, the metal layer 322 includes cobalt, nickel, tungsten, molybdenum, or ruthenium, while the conductive structures 316 and 317 include copper. The metal layer 322 is selectively formed on the metal surfaces of the conductive structures 316 and the barrier layer 318, and not on the dielectric surfaces of the dielectric layer 314. For example, the exposed surface of the dielectric layer 314 can be treated first with a gas containing a hydrophobic functional group, and the hydrophobic functional group is formed on the exposed surface of the dielectric layer 314. The gas containing the hydrophobic functional group does not react with the metal surfaces of the barrier layer 318, the pad, and the conductive structure 316. The hydrophobic functional group formed on the exposed surface of the dielectric layer 314 can prevent the metal layer 322 from being formed on the dielectric layer 314. In FIG. 3D, a first etch stop layer 330 is formed on the dielectric layer 314, the metal layer 322, and the side surfaces of the metal layer 322. The material included in the first etch stop layer 330 can have a low capacitance or a low dielectric constant (such as less than or equal to 7, for example less than or equal to 4). Using a material with a low capacitance or a low dielectric constant as the first etch stop layer 330 helps to reduce the capacitance of the damascene-based interconnect structure used in the back-end process technology without degrading the resistance-capacitance delay. Using the first etch stop layer 330 with a low capacitance can reduce the capacitance of the interconnect structure in the back-end damascene process by about 3% to about 5%. In various embodiments, the first etch stop layer 330 is a metal-free layer. Different from the conventional etch stop layer using metal oxide and increasing resistance due to carbon content, the first etch stop layer 330 does not contain metal and has a lower resistance than the etch stop layer using metal oxide. In some examples, the dielectric constant of the first etch stop layer 330 is less than 4. Exemplary materials used for the first etch stop layer 330 can include but are not limited to silicon carbonitride, boron nitride, silicon carbonitride oxide, oxygen-doped silicon carbide, silicon carbide oxide, or the like. In some embodiments, the first etch stop layer 330 can be a material containing methyl. The method for forming the first etch stop layer 330 can be plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, spin coating, or any suitable deposition process. In an exemplary embodiment, the first etch stop layer 330 is silicon carbonitride. In these examples, the deposition method of the first etch stop layer 330 can be exposing the interconnect structure 300 to a single precursor containing silicon, carbon, and nitrogen, such as hexamethyldisilane. The deposition method of the first etch stop layer 330 can be changed to exposing the interconnect structure 300 to multiple precursors, such as a silicon precursor (such as silane), a nitrogen precursor (such as ammonia), and a carbon precursor (such as methane, acetylene, benzene, or the like). Next, a second etch stop layer 331 is formed on the first etch stop layer 330. The etch selectivity of the second etch stop layer 331 is different from that of the first etch stop layer 330. The second etch stop layer 331 serves as a moisture barrier layer, which can prevent the conductive structures 316 and 317 from oxidizing in subsequent processes. Similar to the first etch stop layer 330, the second etch stop layer 331 can also be a metal-free layer. In some examples, the dielectric constant of the second etch stop layer 331 is less than 4. In some embodiments, the second etch stop layer 331 does not contain nitrogen (i.e., a nitrogen-free layer). In some embodiments, the second etch stop layer 331 includes carbon. In some embodiments, the second etch stop layer 331 includes silicon and carbon. In some embodiments, the second etch stop layer 331 includes silicon and oxygen. In some embodiments, the second etch stop layer 331 includes silicon, oxygen, and carbon. An exemplary material used for the second etch stop layer 331 can be SiO x C y , where x is from about 0.5 to about 2.4, and y is from about 0.6 to about 3. The method of forming the second etch stop layer 331 can be plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, thermal atomic layer deposition, or any suitable deposition process. In some embodiments, the first etch stop layer 330 and the second etch stop layer 331 are compliant layers formed by an atomic layer deposition-based deposition process. In these examples, the profiles of the first etch stop layer 330 and the second etch stop layer 331 can follow the profile of the metal layer 322. FIG. 3D-1 is a cross-sectional view of a part of the interconnect structure 300, and the method of forming the first etch stop layer 330 and the second etch stop layer 331 can be an atomic layer deposition-based deposition process. In any case, the ratio of the thickness of the first etch stop layer 330 to the thickness of the dielectric layer 314 can be from about 1:3 to about 1:15. The ratio of the thickness of the second etch stop layer 331 to the thickness of the dielectric layer 314 can be from about 1:3 to about 1:15. In some embodiments, the thickness of each of the first etch stop layer 330 and the second etch stop layer 331 can be from about 50 Å to about 200 Å, such as about 100 Å. In an exemplary embodiment, the thickness of the first etch stop layer 330 can be about 90 Å, and the thickness of the dielectric layer 314 can be about 330 Å. Some embodiments can be combined with any other embodiments of the present invention, and a third etch stop layer 337 can be deposited on the second etch stop layer 331, as shown in FIG. 3D-2. The third etch stop layer 337 can include an oxide or nitride of a semiconductor such as silicon. The method of forming the third etch stop layer 337 can be any suitable process, such as chemical vapor deposition or atomic layer deposition. In some embodiments, the third etch stop layer 337 can be located between the first etch stop layer 330 and the second etch stop layer 331. In FIG. 3E, a dielectric layer 332 is formed on the second etch stop layer 331. In some embodiments, the dielectric layer 332 may include the same material as the dielectric layer 314, and the method of forming it may be the same as the process of forming the dielectric layer 314. In FIG. 3F, openings 333 and 335 are formed in and through the dielectric layer 332. The opening 335 may be a trench opening formed in the upper portion of the dielectric layer 332. The opening 333 may be located on at least one conductive structure 316. The opening 333 may be a via opening that passes through the dielectric layer 332, the second etch stop layer 331, the first etch stop layer 330, and the metal layer 322 to expose a portion of the conductive structure 316. The openings 333 and 335 will be filled with a conductive material to form conductive structures therein. The method of forming the openings 333 and 335 may be any suitable process, such as one or more etching processes. In some embodiments, the openings 333 and 335 may be formed by a dual damascene process. The etching process may remove a portion of the second etch stop layer 331, the first etch stop layer 330, and the metal layer 322, causing the opening 333 to expose a portion of the upper surface of the corresponding conductive structure 316. Next, a barrier layer 336 is selectively formed on the exposed upper surface of the conductive structure 316. In some embodiments, the method of forming the barrier layer 336 may be to expose the upper surface of the conductive structure 316 to a barrier agent, which may employ chemical vapor deposition, atomic layer deposition, wet coating, infiltration process, or other suitable processes. The barrier agent may include one or more inhibitors that are configured to selectively adhere to the metal surface of the conductive structure 316. Suitable inhibitors may include, but are not limited to, benzotriazole, benzimidazole, tolyltriazole, oxalic acid, malonic acid, citric acid, lactic acid, ethylenediaminetetraacetic acid, tetraacetic acid, diethylenetriaminepentaacetic acid, nitrilotriacetic acid, or the like. In other embodiments, the barrier agent may include inorganic inhibitors such as chromates, nitrites, molybdates, and phosphates, and cathodic type inhibitors such as zinc and polyphosphate inhibitors. In some embodiments, the blocking layer 336 can be an organic material containing small molecules or polymers. The blocking layer 336 can include one or more self-assembled monolayers having a head group and a tail group. The choice of the head group of the self-assembled monolayer can depend on the material of the conductive structure 316. For example, the head group of the self-assembled monolayer can include an azole-containing compound (when the conductive structure 316 uses copper or cobalt), or an alkyne-capped compound (when the conductive structure 316 uses ruthenium). In some embodiments, the head group of the self-assembled monolayer includes a phosphorus, sulfur, silicon, or nitrogen-capped compound that only adheres to the metal surface of the conductive structure 316. The head group of the self-assembled monolayer may not be formed on the dielectric surfaces of the dielectric layer 332, the first etch stop layer 330, and the second etch stop layer 331. The tail group of the self-assembled monolayer can include highly hydrophobic long alkane chains to block the absorption of precursors (such as precursors used to form the barrier layer 338 subsequently) to form the barrier layer 338 on the blocking layer 336. In some embodiments, the tail group includes a polymer such as polyimide. The method for forming the blocking layer 336 can be applying a blocking agent to the exposed surface, such as chemical vapor deposition, atomic layer deposition, molecular layer deposition, wet coating, infiltration process, or other suitable methods. In some embodiments, the method for forming the blocking layer 336 is a wet coating process, and the solution used in the wet coating process can be a protic organic solvent such as alcohols, carboxylic acids, or a combination thereof. Exemplary protic organic solvents can include but are not limited to methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, 1-pentanol, 1-hexanol, 1-heptanol, 2-ethoxyethanol, or a mixture thereof. The solution used for wet coating can also be a polar or non-polar protic solvent. Exemplary polar aprotic solvents can include but are not limited to N,N-dimethylformamide, N-methyl-2-pyrrolidone, acetonitrile, acetone, ethyl acetate, benzyl ether, trioctylphosphine, trioctyloxide phosphine, or a mixture thereof. Exemplary non-polar protic solvents can include but are not limited to alkanes, alkenes, aromatics, esters, ester or ether solvents, hexane, octane, benzene, toluene, xylene, or a mixture thereof. In FIG. 3G, a barrier layer 338 is deposited on the exposed dielectric surfaces, such as on the dielectric layer 332, the second etch stop layer 331, and the first etch stop layer 330. The barrier layer 338 is used to prevent metal from diffusing from subsequent formed conductive structures such as conductive vias 340 and conductive structures such as conductive lines 342 into the dielectric layer 332. A blocking layer 336 (FIG. 3F) is formed on the metal surface of the conductive structure 316, and the barrier layer 338 is selectively formed on the dielectric layer 332, the first etch stop layer 330, and the second etch stop layer 331, but not on the blocking layer 336. A method of selectively depositing the barrier layer 338 can employ the blocking layer 336. For example, the blocking layer 336 can block the formation of the barrier layer 338 on the metal surface of the conductive structure 316. Specifically, the blocking layer 326 blocks the precursors of the barrier layer 328 from forming thereon, causing the precursors of the barrier layer 338 to grow on the dielectric surfaces (such as on the surfaces of the dielectric layer 332, the first etch stop layer 330, and the second etch stop layer 331). An atomic layer deposition process and / or a molecular layer deposition process can be employed to achieve and / or enhance the selective deposition of the barrier layer 338, such that the barrier layer 338 has specific bonding with the dielectric layer 332, the first etch stop layer 330, and the second etch stop layer 331 through self-limiting surface reactions. The barrier layer 338 can include the same material as the barrier layer 318, and its formation method can be a conformal process such as atomic layer deposition. In some embodiments, a pad (not shown) can be formed on the barrier layer 338 to assist in adhering subsequent conductive structures such as conductive vias 340 and conductive structures such as conductive lines 342 to the barrier layer 338. Since the barrier layer 338 includes a metal material, the pad can be selectively formed on the metal surface of the barrier layer 338, but not on the organic material or polymer used for the blocking layer 336. If a pad is employed, it can use the same material as the pad between the conductive structure 317 and the barrier layer 318, and its formation method can be a conformal process such as atomic layer deposition. After depositing the barrier layer 338, the blocking layer 336 can be removed to expose the upper surface of the conductive structure 316. The blocking layer 336 can be removed by thermal degradation, plasma bombardment, or other suitable processes. The removal process does not substantially affect the barrier layer 338 or the conductive structure 316. In FIG. 3H, the conductive vias 340 and the conductive lines 342 are formed in the openings 333 and 335 (FIG. 3G), respectively. The conductive vias 340 and the conductive lines 342 can be formed by filling the openings 333 and 335 with a conductive material. The conductive vias 340 and the conductive lines 342 can include any suitable conductive material such as copper, ruthenium, tungsten, nickel, aluminum, cobalt, iridium, osmium, gold, palladium, platinum, silver, tantalum, titanium, or an alloy thereof. The deposition methods of the conductive vias 340 and the conductive lines 342 can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, electroless plating, other suitable deposition processes, or a combination thereof, followed by a planarization process such as a chemical mechanical polishing process. The interconnect structure 300 includes the conductive vias 340 and the conductive lines 342 formed in the dielectric layer 332. The conductive vias 340 can have a first size, the conductive lines 342 can have a second size, and the second size is greater than the first size. The conductive vias 340 directly contact the underlying conductive structure 316 in the dielectric layer 314. The conductive vias 340 directly contacting the conductive structure 316 can have the lowest resistance because of the direct metal-to-metal contact. In addition, since there is no barrier layer or liner layer between the conductive vias 340 and the conductive structure 316, the contact resistance between the conductive vias 340 and the conductive structure 316 can be reduced. In addition, by using a low-capacitance material for the first etch stop layer 330, the capacitance of the damascene backend process structure can be further reduced to avoid high-resistance capacitance delay. FIGS. 3I-1 to 3I-4 are enlarged views of a part of the interconnect structure 300 in some embodiments. In FIG. 3I-1, the sidewalls of the conductive vias 340 and the conductive structure 316 can be perpendicular or inclined. In one embodiment, in the sidewall profiles of the conductive vias 340 and the conductive structure 316, the dimensions gradually decrease along the Z direction. For example, the top dimensions of the conductive vias 340 and the conductive structure 316 are greater than the bottom dimensions of the conductive vias 340 and the conductive structure 316. The conductive vias 340 can be regarded as having a part A and a part B. The dimension of part A gradually changes from a first width to a second width. The dimension of part B gradually changes from a third width to a fourth width. The first width is greater than the second width, and the third width is greater than the fourth width. The third width is greater than the second width, and the first width is greater than the fourth width. The conductive structure 316 can be regarded as a part C with a dimension gradually changing from a fifth width to a sixth width. The fifth width is greater than the sixth width, and the fifth width is greater than the fourth width. The fifth width can be greater than or less than the first width. As shown in FIG. 3I-1, the metal layer 322 is embedded in the first etch stop layer 330 and contacts the conductive via 340 and the conductive structure 316. The metal layer 322 surrounds portion B of the conductive via 340 and contacts a portion of the upper surface of the conductive structure 316. The metal layer 322 does not contact the barrier layer 318 and the barrier layer 338. The barrier layer 318 contacts the conductive structure 316, the dielectric layer 314, and the first etch stop layer 330. The barrier layer 338 contacts the dielectric layer 332, the conductive via 340, the first etch stop layer 330, and the second etch stop layer 331. Depending on the thickness of the blocking layer 336 (FIG. 3F), the barrier layer 338 may further contact the metal layer 322. In some embodiments, the conductive via 340 and the conductive line 342 may include a first conductive material, the conductive structure 316 may include a second conductive material, and the second conductive material is different from the first conductive material. FIG. 3I-2 is substantially the same as FIG. 3I-1, except that the metal layer 322 extends further over the barrier layer 318 and contacts the barrier layer 318. FIGS. 3I-3 and 3I-4 are substantially the same as the embodiments of FIGS. 3I-1 and 3I-2, except that portions of the first etch stop layer 330 and the second etch stop layer 331 follow the contour of the metal layer 322. FIGS. 4A to 4H are cross-sectional views of various stages of manufacturing an interconnect structure 400 in some embodiments. Various embodiments of the interconnect structure 400 can be used to form one or more layers of the interconnect structure shown in FIGS. 1A, 1B, and 2. As detailed below, the embodiments shown in FIGS. 4A to 4H are similar to the embodiments shown in FIGS. 3A to 3H, except that a pre-layer 450 is formed between the dielectric layer 314 and the first etch stop layer 330 to improve the adhesion between the first etch stop layer 330 and the metal layer 322. The interconnect structure 400 in FIGS. 4A to 4C may be substantially the same as the interconnect structure 300 shown in FIGS. 3A to 3C, and thus is not repeated here for simplicity of description. In FIG. 4D, a pre-layer 450 is deposited on the dielectric layer 314, the metal layer 322, and the side surface of the metal layer 322. The pre-layer 450 can serve as an adhesion layer, which can improve the adhesion between the first etch stop layer 330 and the metal layer 322, thereby minimizing or avoiding void formation at the interface between the first etch stop layer 330 and the metal layer 322. The pre-layer 450 helps to remove voids, so that subsequent conductive structures (such as conductive vias 340) do not land on the voids, thereby improving the device yield. The above voids may occur at and / or near the metal layer 322 due to poor adhesion. In some embodiments, the pre-layer 450 is a nitrogen-rich layer. For example, the nitrogen content in the pre-layer 450 can be about 40 atomic % to about 80 atomic %. The nitrogen-rich pre-layer 450 can further reduce the capacitance of the interconnect structure in the back-end-of-line (BEOL) process and improve reliability such as time-dependent dielectric breakdown and voltage breakdown of semiconductor devices. In some embodiments, the pre-layer 450 can be a nitride of a metal such as aluminum, titanium, zirconium, hafnium, yttrium, or other suitable metals. In some embodiments, the pre-layer 450 includes a nitride of a semiconductor such as silicon. The method of forming the pre-layer 450 can be any suitable process, such as physical vapor deposition, atomic layer deposition, or chemical vapor deposition. In an exemplary embodiment, the pre-layer is aluminum nitride or aluminum oxynitride formed by a chemical agent mainly composed of aluminum (such as trimethylaluminum, triethylaluminum, trimethylamine alane borohydride, other suitable aluminum-containing chemical agents, or a combination thereof), a chemical agent mainly composed of nitrogen (such as ammonia, nitrogen gas, other suitable nitrogen-containing chemical agents, or a combination thereof), and a chemical agent mainly composed of oxygen (such as oxygen, ozone, water, or other suitable oxygen-containing chemical agents) at a process temperature less than about 400˚C. In some embodiments, the pre-layer 450 is a conforming layer formed by a deposition process mainly based on atomic layer deposition. In these examples, the profile of the pre-layer 450 follows the profile of the metal layer 322. FIG. 4D-1 is a cross-sectional view of a part of the interconnect structure 400, which shows the pre-layer 450 formed by a deposition process mainly based on atomic layer deposition. In FIG. 4E, the first etch stop layer 330, the second etch stop layer 331, and the dielectric layer 332 are sequentially formed on the pre-layer 450. The first etch stop layer 330, the second etch stop layer 331, and the dielectric layer 332 can be formed in a similar manner as described above with reference to FIG. 3D. In FIG. 4F, openings 433 and 435 are formed in and penetrate through dielectric layer 332. Opening 435 can be a trench opening formed in the upper portion of dielectric layer 332. Opening 433 can be a via opening that penetrates through dielectric layer 332, second etch stop layer 331, first etch stop layer 330, pre-layer 450, and metal layer 322 to expose a portion of conductive structure 316. Similar to openings 333 and 335, openings 433 and 435 will be filled with a conductive material to form conductive structures therein. Openings 433 and 435 can be structures of a dual damascene process, and the method of forming them can be the same as the forming process used for openings 333 and 335 described above with reference to FIG. 3F. Thereafter, a barrier layer 336 can be selectively formed on the exposed surface of conductive structure 316, and the forming method can be similar to the manner described above with reference to FIG. 3F. In FIG. 4G, a barrier layer 338 is deposited on the exposed dielectric surfaces, such as on dielectric layer 332, second etch stop layer 331, first etch stop layer 330, and pre-layer 450. Barrier layer 338 and dielectric layer 310 can include the same material, and the method of forming barrier layer 338 can be similar to the manner described above with reference to FIG. 3G. After depositing barrier layer 338, barrier layer 336 (FIG. 4F) is removed to expose the upper surface of conductive structure 316. The removal process does not substantially affect barrier layer 338 or conductive structure 316. In FIG. 4H, conductive via 440 and conductive line 442 are respectively formed in openings 433 and 435 (FIG. 4G). The method of forming conductive via 440 and conductive line 442 can be similar to the manner described above with reference to FIG. 3H. Similarly, conductive via 440 can have a first size, conductive line 442 can have a second size, and the second size is greater than the first size. Conductive via 440 directly contacts the underlying conductive structure 316 without considering the unwanted voids caused by forming pre-layer 450. The direct contact of conductive via 440 with conductive structure 316 can have the lowest resistance due to the direct metal-to-metal contact. In addition, since there is no barrier layer or liner layer between conductive via 440 and conductive structure 316, the contact resistance between conductive via 440 and conductive structure 316 can be reduced. Further, by using a low-capacitance material for first etch stop layer 330, the capacitance of the back-end-of-line structure of the damascene can be further reduced to avoid high-resistance capacitance delay. Figures 4I-1 and 4I-2 are enlarged views of a part of the interconnect structure 400 in some embodiments. In Figure 4I-1, the conductive vias 440 may be perpendicular or inclined to the sidewalls of the conductive structure 316. In one embodiment, in the sidewall profiles of the conductive vias 440 and the conductive structure 316 respectively, the dimensions gradually decrease along the Z direction. For example, the top dimensions of the conductive vias 440 and the conductive structure 316 are greater than the bottom dimensions of the conductive vias 440 and the conductive structure 316. The conductive via 440 can be regarded as having a part D and a part E. The dimension of part D gradually changes from a first width to a second width. The dimension of part E gradually changes from a third width to a fourth width. The first width is greater than the second width, and the third width is greater than the fourth width. The third width is greater than the second width, and the first width is greater than the fourth width. The conductive structure 316 can be regarded as a part C whose dimension gradually changes from a fifth width to a sixth width. The fifth width is greater than the sixth width, and the fifth width is greater than the fourth width. The fifth width may be greater than or less than the first width. As shown in Figure 4I-1, the metal layer 322 is buried in the pre-layer 450 and contacts the conductive vias 440 and the conductive structure 316. The metal layer 322 surrounds part E of the conductive via 440 and contacts a part of the upper surface of the conductive structure 316. The metal layer 322 does not contact the barrier layer 318 and the barrier layer 338. The barrier layer 318 contacts the conductive structure 316, the dielectric layer 314, and the pre-layer 450. The barrier layer 338 contacts the dielectric layer 332, the conductive vias 440, the pre-layer 450, the first etch stop layer 330, and the second etch stop layer 331. Depending on the thickness of the barrier layer 336 (Figure 4F), the barrier layer 338 may further contact the metal layer 322. In some embodiments, the conductive vias 440 and the conductive lines 442 may include a first conductive material, the conductive structure 316 may include a second conductive material, and the second conductive material is different from the first conductive material. The embodiment of Figure 4I-2 is substantially the same as that of Figure 4I-1, except that the metal layer 322 extends further over the barrier layer 318 and contacts the barrier layer 318. Figures 5A to 5L are side cross-sectional views of various stages of manufacturing the interconnect structure 500 in some embodiments. Various embodiments of the interconnect structure 500 are used to form one or more layers of the interconnect structure 250 shown in Figures 1A, 1B, and 2. As detailed below, the embodiments shown in Figures 5A to 5L are similar to the embodiments shown in Figures 4A to 4H, except that the pre-layer is selectively formed between the metal layer 322 and the first etch stop layer 330. The interconnect structure 500 in Figures 5A to 5C is substantially the same as the interconnect structure 400 shown in Figures 4A to 4C, and thus is not repeated here for simplicity of description. In FIG. 5D, a blocking layer 560 is selectively formed on the exposed surface of the dielectric layer 314. In some embodiments, the blocking layer 560 can be formed by molecules having silicon-based functional groups, so that the blocking layer 560 is formed on the dielectric layer 314 (and low dielectric constant materials) and not on the metal layer 322 (such as cobalt). For example, the blocking layer 560 can include a head group connected to the functional group via a molecular chain. The head group is configured to adhere to a preferred surface such as the surface of the dielectric layer 314 and not to other surfaces such as the surface of the metal layer 322. In some embodiments, the head group can include butyltriethoxysilane, cyclohexyltrimethoxysilane, cyclopentyltrimethoxysilane, dodecyltriethoxysilane, dodecyltrimethoxysilane, decyltriethoxysilane, dimethoxy(methyl)-n-octylsilane, triethoxyethylsilane, ethyltrimethoxysilane, hexyltrimethoxysilane, hexyltriethoxysilane, hexadecyltrimethoxysilane, hexadecyltriethoxysilane, triethoxymethylsilane, trimethoxy(methyl)silane, methoxy(dimethyl)octadecylsilane, methoxy(dimethyl)-n-octylsilane, octadecyltriethoxysilane, triethoxy-n-octylsilane, octadecyltrimethoxysilane, trimethoxy(propyl)silane, trimethoxy-n-octylsilane, triethoxy(propyl)silane, methane, ethane, propane, butane, pentane, hexane, heptane, octane, nonane, decane, undecane, dodecane, pentadecane, hexadecane, any combination of the above, or the like. In some embodiments, the functional group can include hydrophobic interfacial properties that repel dielectric materials, thereby preventing the dielectric material from adhering to the blocking layer 560 during subsequent metal-on-dielectric processes. In some embodiments, the functional group can include a methyl group, which can provide hydrophobic interfacial properties. In some embodiments, the method of forming the blocking layer 560 can be a wet process such as dip coating, spin coating, spray coating, or other suitable processes. Prior to the blocking layer 560, a treatment process can be performed to reduce the native oxide on the metal surface of the metal layer 322. The treatment process can be a plasma treatment process that uses process gases such as hydrogen, ammonia, and / or oxygen-containing gases. In FIG. 5E, the pre-layer 550 is selectively deposited on the metal layer 322. Due to the presence of the barrier layer 560, the pre-layer 550 is deposited on the exposed surface of the metal layer 322 rather than on the barrier layer 560, thereby selectively depositing the pre-layer 550 on the metal layer 322. Similarly, the pre-layer 550 acts as an adhesion layer to improve the adhesion between the first etch stop layer 330 and the metal layer 322. The pre-layer 550 helps to remove voids, preventing subsequent conductive structures (such as the conductive via 340) from landing on the voids, thereby improving the device yield. The above-mentioned voids may occur at and / or near the metal layer 322 due to poor adhesion. Compared with the embodiments shown in FIGS. 4A to 4H, the capacitance of the interconnect structure 500 can be further reduced because the pre-layer 550 is selectively deposited on the metal layer 322 and does not extend into the region between the first etch stop layer 330 and the dielectric layer 314. Similar to the pre-layer 450, the pre-layer 550 is a nitrogen-rich layer. In some embodiments, the pre-layer 550 can be a nitride of a metal such as aluminum, titanium, zirconium, hafnium, yttrium, or other suitable metals. In some embodiments, the pre-layer 550 includes a nitride of a semiconductor such as silicon. The pre-layer 550 can be formed by any suitable process such as atomic layer deposition or chemical vapor deposition process. In one embodiment, the pre-layer 550 can be deposited by a thermal atomic layer deposition process. In another embodiment, the pre-layer 550 can be deposited by a thermal chemical vapor deposition process. The thermal atomic layer deposition process or the thermal chemical vapor deposition process has the advantage that it does not damage the surface of the barrier layer 560 or the dielectric layer 314. In some embodiments, the pre-layer 550 is a conforming layer deposited by an atomic layer deposition-based deposition process. In these examples, the profile of the pre-layer 550 follows the profile of the metal layer 322. FIG. 5E-1 is a cross-sectional view of a part of the interconnect structure 500, and the pre-layer 550 is formed by an atomic layer deposition-based deposition process. The pre-layer 550 is deposited on the upper surface and the side surface of the metal layer 322. In some examples, a part of the pre-layer 550 contacts the dielectric layer 314 but does not contact the barrier layer 318, as shown in FIG. 5E-1. In some examples, a part of the pre-layer 550 contacts the dielectric layer 314 and the barrier layer 318, as shown in FIG. 5E-2. In any example, the ratio of the thickness of the pre-layer 550 to the thickness of the dielectric layer 314 can be about 1:3 to about 1:15. In FIG. 5F, after depositing the pre-layer 550, the barrier layer 560 can be removed to expose the upper surface of the dielectric layer 314. The barrier layer 560 can be removed by thermal degradation, plasma bombardment, or other suitable processes. The removal process does not substantially affect the pre-layer 550. In some other embodiments, the method of selectively depositing the pre-layer 550 on the metal layer 322 can be a processing procedure for the interconnect structure 500. FIG. 5D-1 shows the interconnect structure 500 undergoing the processing procedure 580 in one embodiment. In one embodiment, the processing procedure is a curing procedure, so that at least the dielectric layer 314 is exposed to ultraviolet energy in an environment containing hydrogen (such as hydrogen gas) and / or nitrogen (such as ammonia). In some embodiments, the energy density of the ultraviolet energy is about 10 mJ / cm 2 to about 100 J / cm 2 . During the curing procedure, the partial pressure of the hydrogen-containing gas or nitrogen-containing gas can be greater than or equal to about 30 atmospheres (such as greater than or equal to about 50 atmospheres), and the temperature can be about 200˚C to about 350˚C. The processing procedure using ultraviolet energy can achieve the selective deposition of the subsequent pre-layer 550 because the general plasma pretreatment of the metal layer 322 can reduce the native oxide on the metal layer 322. Plasma pretreatment may damage the dielectric layer 314 (such as silicon oxycarbide) to retain a small amount of methyl groups (such as silicon-methyl bonds) and a high concentration of oxygen on the surface of the dielectric layer 314. When the surface of the dielectric layer 314 has a low content of methyl groups, the subsequent pre-layer 550 (which is a nitride of metal or silicon) tends to absorb onto the dielectric layer 314. Using ultraviolet energy not only reduces the native oxide of the metal but also helps to maintain methyl groups (such as silicon-methyl bonds) on the surface of the dielectric layer 314. The high concentration of methyl groups on the surface of the dielectric layer 314 can prevent the precursors (used to form the subsequent pre-layer 550) from absorbing onto the dielectric layer 314, resulting in the selective deposition of the pre-layer 550 on the metal layer 322. FIG. 5D-2 shows the stage after forming the pre-layer 550 on the metal layer 322, where the ultraviolet-treated dielectric layer 314 includes a first region (upper region) 314-1 and a second region (lower region) 314-2. The first region 314-1 has a first concentration of methyl groups, the second region 314-2 has a second concentration of methyl groups, and the second concentration is less than the first concentration. In FIG. 5G, the interconnect structure 500 can be pretreated as appropriate. In some embodiments using the barrier layer 560, the pretreatment procedure can be the same as the procedure used to remove the barrier layer 560. In some embodiments, the pretreatment procedure is a plasma treatment using a hydrogen-containing gas and an inert gas such as argon or nitrogen. Optionally or alternatively, a plasma treatment can be performed using a carbon-containing gas such as CH x (x can be an integer such as 1, 2, or 4), carbon dioxide, or the like. During the pretreatment procedure, the interconnect structure 500 can be heated to about 200˚C to about 450˚C. The pretreatment can be changed to a heat-dominated procedure and without using plasma. In FIGS. 5G, 5H, and 5I, a first etch stop layer 330, a second etch stop layer 331, and a dielectric layer 332 may be sequentially formed on a pre-layer 450 after a pre-treatment process. The method of forming the first etch stop layer 330, the second etch stop layer 331, and the dielectric layer 332 may be similar to the manner described above in conjunction with FIG. 1D. In FIG. 5J, openings 533 and 535 are formed in and through the dielectric layer 332. The opening 535 may be a trench opening formed in the upper portion of the dielectric layer 332. The opening 533 may be a via opening that passes through the dielectric layer 332, the second etch stop layer 331, the first etch stop layer 330, the pre-layer 550, and the metal layer 322 to expose a portion of the conductive structure 316. Similar to the openings 333 and 335, the openings 533 and 535 may also be filled with a conductive material to form a conductive structure therein. The method of forming the openings 533 and 535 may be a dual-damascene process and may employ the same process used to form the openings 333 and 335 described above in conjunction with FIG. 3F. Thereafter, a barrier layer 336 may be selectively formed on the exposed upper surface of the conductive structure 316, and the method of forming it may be similar to the manner described above in conjunction with FIG. 3F. In FIG. 5K, a barrier layer 338 is deposited on the exposed dielectric surfaces, such as on the dielectric layer 332, the second etch stop layer 331, the first etch stop layer 330, and the pre-layer 550. Depending on the thickness of the barrier layer 336, the barrier layer 338 may further contact the metal layer 322. The barrier layer 338 and the dielectric layer 310 may include the same material, and the method of forming the barrier layer 338 may be similar to the above-described manner in conjunction with FIG. 3G. After depositing the barrier layer 338, the barrier layer 336 (FIG. 5J) is removed to expose the upper surface of the conductive structure 316. The removal process substantially does not affect the barrier layer 338 or the conductive structure 316. In FIG. 5L, the conductive vias 540 and the conductive lines 542 are respectively formed in the openings 533 and 535 (FIG. 5K). The method of forming the conductive vias 540 and the conductive lines 542 can be similar to the manner described above in conjunction with FIG. 3H. The conductive vias 540 directly contact the underlying conductive structure 316 without worrying about the unwanted voids caused by forming the pre-layer 550. Specifically, the pre-layer 550 is selectively deposited on the metal layer 322 without extending into the region between the first etch stop layer 330 and the dielectric layer 314 to greatly reduce the capacitance of the interconnect structure 500. The conductive vias 540 directly contacting the conductive structure 316 have the lowest resistance due to the direct metal-to-metal contact. In addition, since there is no barrier layer or pad layer between the conductive vias 540 and the conductive structure 316, the contact resistance between the conductive vias 540 and the conductive structure 316 can be reduced. In addition, using a low-capacitance material for the first etch stop layer 330 can further reduce the capacitance of the damascene backend process structure to avoid high-resistance capacitance delay. FIGS. 5M-1 to 5M-4 are enlarged views of a part of the interconnect structure 500 in some embodiments. In FIG. 5M-1, the sidewalls of the conductive vias 540 and the conductive structure 316 can be perpendicular or inclined. In one embodiment, in the sidewall profiles of the conductive vias 540 and the conductive structure 316 respectively, the dimensions gradually decrease along the Z direction. For example, the top dimensions of the conductive vias 540 and the conductive structure 316 are greater than the bottom dimensions of the conductive vias 540 and the conductive structure 316. The conductive vias 540 can be regarded as having a part F and a part G. The dimension of the part F gradually changes from a first width to a second width. The dimension of the part G gradually changes from a third width to a fourth width. The first width is greater than the second width, and the third width is greater than the fourth width. The third width is greater than the second width, and the first width is greater than the fourth width. The conductive structure 316 can be regarded as a part C whose dimension gradually changes from a fifth width to a sixth width. The fifth width is greater than the sixth width, and the fifth width is greater than the fourth width. The fifth width can be greater than or less than the first width. As shown in FIG. 5M-1, the metal layer 322 is embedded in the pre-layered material 550 and contacts the conductive via 540 and the conductive structure 316. The metal layer 322 surrounds the portion G of the conductive via 540 and contacts a part of the upper surface of the conductive structure 316. The metal layer 322 does not contact the barrier layer 318 and the barrier layer 338. The barrier layer 318 contacts the conductive structure 316, the dielectric layer 314, and the pre-layered material 550. The barrier layer 338 contacts the dielectric layer 332, the conductive via 340, the first etch stop layer 330, and the second etch stop layer 331. Depending on the thickness of the blocking layer 336 (see FIG. 5J), the barrier layer 338 may further contact the metal layer 322. The first etch stop layer 330 is located between the dielectric layer 314 and the second etch stop layer 331 and contacts the dielectric layer 314 and the second etch stop layer 331. In some embodiments, the conductive via 340 and the conductive line 342 may include a first conductive material, the conductive structure 316 may include a second conductive material, and the second conductive material is different from the first conductive material. The embodiment of FIG. 5M-2 is substantially the same as that of FIG. 5M-1, except that the metal layer 322 further extends over the barrier layer 318 and contacts the barrier layer 318. The embodiments of FIGS. 5M-3 and 5M-4 are substantially the same as those of FIGS. 5M-1 and 5M-2, except that portions of the first etch stop layer 330 and the second etch stop layer 331 follow the contour of the pre-layered material 550. Some embodiments relate to an interconnect structure for reducing contact resistance and reducing resistance-capacitance delay. Embodiments of the present invention provide a barrier-free conductive via structure to directly contact a conductive line. The conductive via structure extends through a first interlayer dielectric layer (which is metal-free and has a low capacitance value), a second etch stop layer (which is metal-free and has a low dielectric constant value), and a metal layer. Specifically, a pre-layered material (a nitrogen-rich metal nitride or silicon nitride) is located between the metal layer and the first etch stop layer to improve adhesion and avoid void formation between the first etch stop layer and the metal layer. The use of the pre-layered material allows the conductive via not to land on voids. Voids may occur in and / or near the metal layer due to poor adhesion. In this way, the yield of the interconnect structure can be improved. A method of forming a semiconductor device structure is disclosed. The method includes forming one or more first conductive structures in a first dielectric layer; forming a metal layer on each of the first conductive structures; forming a first etch stop layer on the metal layer; forming a second etch stop layer on the first etch stop layer, wherein the second etch stop layer is a nitrogen-free layer. The method also includes forming a second dielectric layer on the second etch stop layer; and forming a second conductive structure in the second dielectric layer, and the second conductive structure passes through the second etch stop layer, the first etch stop layer, and the metal layer. In one embodiment, the above method further includes forming a pre-layered material between the metal layer and the second conductive structure before forming the first etch stop layer. In one embodiment, a pre-layered material is deposited on the exposed surfaces of the metal layer and the first dielectric layer. In one embodiment, the step of forming the pre-layered material further includes selectively depositing a barrier layer on the first dielectric layer; forming the pre-layered material on the exposed surface of the metal layer; and removing the barrier layer after forming the pre-layered material. In one embodiment, the step of forming the pre-layered material further includes applying ultraviolet energy to at least the first dielectric layer. In one embodiment, the environment for applying ultraviolet energy contains hydrogen and / or nitrogen. In one embodiment, the partial pressure of hydrogen and / or nitrogen is greater than or equal to about 30 atmospheres. In one embodiment, the second conductive structure passes through the second etch stop layer, the first etch stop layer, the pre-layered material, and the metal layer. In one embodiment, the method further includes forming a barrier layer, wherein the barrier layer extends between and contacts the second conductive structure, the second dielectric layer, the second etch stop layer, the first etch stop layer, and the pre-layered material. In one embodiment, the first etch stop layer is a metal-free layer. Another embodiment is a method of forming a semiconductor device structure. The method includes forming one or more first conductive structures in a dielectric layer; forming a metal layer on each of the first conductive structures; selectively forming a barrier layer on the exposed surface of the dielectric layer; selectively forming a pre-layered material on the metal layer; removing the barrier layer; covering the exposed surface of the pre-layered material with a first etch stop layer such that a portion of the first etch stop layer contacts the dielectric layer; and forming a second etch stop layer on the first etch stop layer. In one embodiment, the above method further includes, before selectively forming the barrier layer on the exposed surface of the dielectric layer, performing a pretreatment process on the semiconductor device structure such that an upper region of the first dielectric layer has a first concentration of methyl groups, a second region of the first dielectric layer has a second concentration of methyl groups, and the second concentration is less than the first concentration. In one embodiment, the pretreatment process exposes the semiconductor device structure to an ultraviolet curing process in an environment containing hydrogen and / or nitrogen. In one embodiment, the above method further includes forming a first barrier layer to contact side surfaces of each of the first conductive structures. In one embodiment, the metal layer covers the top of the first barrier layer. In one embodiment, a portion of the pre-layered material contacts the top of the first barrier layer. In one embodiment, the nitrogen content of the pre-layered material is about 40 atomic % to about 80 atomic %. In one embodiment, the above method further includes forming a second dielectric layer on the second etch stop layer; forming a second conductive structure in the second dielectric layer, and the second conductive structure passes through the second etch stop layer, the first etch stop layer, the pre-layer, and the metal layer; and forming a second barrier layer between the second dielectric layer and the second conductive structure, wherein the second barrier layer contacts the first conductive structure. Other embodiments are interconnect structures, which include a first dielectric layer; a second dielectric layer located on the first dielectric layer; a metal layer located between the first dielectric layer and the second dielectric layer; a pre-layer located above the metal layer and between the first dielectric layer and the second dielectric layer, wherein the pre-layer contacts the upper surface and sidewalls of the metal layer. The interconnect structure also includes a first etch stop layer located above the pre-layer and between the first dielectric layer and the second dielectric layer; a second etch stop layer located above the first etch stop layer and between the first dielectric layer and the second dielectric layer, wherein the second etch stop layer is a metal-free layer; and a conductive structure extending from the first dielectric layer to the second dielectric layer. In one embodiment, the above interconnect structure further includes a first barrier layer located between the first dielectric layer and the third part of the conductive structure; and a second barrier layer located between the second dielectric layer and the first part of the conductive structure. The features of the above embodiments are advantageous for those of ordinary skill in the art to understand the present invention. Those of ordinary skill in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those of ordinary skill in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention. A, B, C, D, E, F, G: Portion B - B: Section line 100: Semiconductor device structure 102: Substrate 108: Channel region 114: Isolation region 122: Gate spacer 123: Fin sidewall spacer 124: Source / drain region 126: Contact etch stop layer 128: Interlayer dielectric layer 136: Gate dielectric layer 138: Gate layer 140: Gate stack 142: Source / drain contact 144: Silicide layer 200: Device layer 202: Intermetal dielectric layer 204, 206, 312, 316, 317: Conductive structure 250, 300, 400, 500: Interconnection structure 310, 314, 332: Dielectric layer 311, 313, 333, 335, 433, 435, 533, 535: Opening 314 - 1: First region 314 - 2: Second region 318, 328, 338: Barrier layer 322: Metal layer 326, 336, 560: Blocking layer 330: First etch stop layer 331: Second etch stop layer 337: Third etch stop layer 340, 440, 540: Conductive via 342, 442, 542: Conductive line 450, 550: Prelayer FIG. 1A is a perspective view of one of various stages of manufacturing a semiconductor device structure in some embodiments. FIG. 1B is a side cross-sectional view along section line B - B of the stage of manufacturing a semiconductor device structure in some embodiments. FIG. 2 is a side cross-sectional view of a stage of manufacturing a semiconductor device structure in some embodiments. FIGS. 3A to 3H are side cross-sectional views of various stages of manufacturing an interconnection structure in some embodiments. FIG. 3D - 1 is a cross-sectional view of a portion of the interconnection structure shown in FIG. 3D in some embodiments. FIG. 3D - 2 is a cross-sectional view of a portion of the interconnection structure shown in FIG. 3D in some embodiments. FIGS. 3I - 1 to 3I - 4 are enlarged views of a portion of the interconnection structure shown in FIG. 3H in some embodiments. FIGS. 4A to 4H are side cross-sectional views of various stages of manufacturing an interconnection structure in some embodiments. FIG. 4D - 1 is a cross-sectional view of a portion of the interconnection structure shown in FIG. 4D in some embodiments. FIGS. 4I - 1 to 4I - 2 are enlarged views of a portion of the interconnection structure shown in FIG. 4H in some embodiments. FIGS. 5A to 5L are side cross-sectional views of various stages of manufacturing an interconnection structure in some embodiments. FIG. 5D - 1 is a cross-sectional view of the interconnection structure on which a processing process is performed in some embodiments. FIG. 5D - 2 is a cross-sectional view of forming a prelayer on a metal layer in some embodiments. FIGS. 5E - 1 to 5E - 2 are cross-sectional views of a portion of the interconnection structure shown in FIG. 5E in some embodiments. FIGS. 5M - 1 to 5M - 4 are enlarged views of a portion of the interconnection structure shown in FIG. 5L in some embodiments. 300: Interconnection structure 310, 314, 332: Dielectric layer 312, 316, 317: Conductive structure 318, 338: Barrier layer 322: Metal layer 330: First etching stop layer 331: Second etching stop layer 340: Conductive via 342: Conductive line

Claims

1. A method for forming a semiconductor device structure, comprising: One or more first conductive structures are formed in a first dielectric layer; A metal layer is formed on each of the first conductive structures; A pre-layer is formed on the metal layer; a first etch stop layer is formed on the metal layer and the first dielectric layer, wherein a portion of the first etch stop layer contacts the first dielectric layer; a second etch stop layer is formed on the first etch stop layer, wherein the second etch stop layer is a nitrogen-free layer; a second dielectric layer is formed on the second etch stop layer; and a second conductive structure is formed in the second dielectric layer, wherein the second conductive structure passes through the second etch stop layer, the first etch stop layer, and the metal layer.

2. The method for forming a semiconductor device structure as claimed in claim 1, wherein the pre-layer is deposited on the exposed surfaces of the metal layer and the first dielectric layer.

3. The method for forming a semiconductor device structure as claimed in claim 1, wherein the step of forming the pre-layer further includes: A barrier layer is selectively deposited on the first dielectric layer; The pre-layered material is formed on the exposed surface of the metal layer; And after the pre-layered structure is formed, the barrier layer is removed.

4. The method for forming a semiconductor device structure as claimed in claim 3, wherein the step of forming the pre-layer further includes: At least ultraviolet energy is applied to the first dielectric layer.

5. A method for forming a semiconductor device structure, comprising: One or more first conductive structures are formed in a dielectric layer; A metal layer is formed on each of the first conductive structures; Selectively form a barrier layer on the exposed surface of the dielectric layer; selectively form a pre-layer on the metal layer; remove the barrier layer; cover the exposed surface of the pre-layer with a first etch stop layer, such that a portion of the first etch stop layer contacts the dielectric layer; and form a second etch stop layer on the first etch stop layer.

6. The method for forming the semiconductor device structure as described in claim 5 further includes: Before selectively forming the barrier layer on the exposed surface of the dielectric layer, a pretreatment process is performed on the semiconductor device structure to give the upper region of the dielectric layer a first concentration of methyl groups, the second region of the dielectric layer a second concentration of methyl groups, and the second concentration being less than the first concentration.

7. The method for forming a semiconductor device structure as claimed in claim 6, wherein the pretreatment process exposes the semiconductor device structure to an ultraviolet curing process in an environment containing hydrogen and / or nitrogen.

8. An interconnect structure, comprising: First dielectric layer; A second dielectric layer is located on the first dielectric layer; A metal layer is located between the first dielectric layer and the second dielectric layer; A pre-layered structure is located above the metal layer and between the first dielectric layer and the second dielectric layer, wherein the pre-layered structure contacts the upper surface and sidewalls of the metal layer; a first etch stop layer is located above the pre-layered structure and between the first dielectric layer and the second dielectric layer, wherein a portion of the first etch stop layer contacts the first dielectric layer; a second etch stop layer is located above the first etch stop layer and between the first dielectric layer and the second dielectric layer, wherein the second etch stop layer is a metal-free layer; and a conductive structure extends from the first dielectric layer to the second dielectric layer.

9. As in the connection structure within request item 8, it further includes: A first barrier layer is located between the first dielectric layer and the third part of the conductive structure; And a second barrier layer, located between the second dielectric layer and the first part of the conductive structure.

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