Semiconductor device and method of forming the same

Abstract

The device includes a stack of multiple nanostructures; a gate structure covering the nanostructures; an isolation region located between the stack of nanostructures and another stack of multiple nanostructures adjacent to the stack of nanostructures along a first direction; a source / drain region adjacent to at least one of the nanostructures; and a spacer layer located on the sidewalls of the gate structure and the sidewalls of the source / drain region, and the spacer layer covering the region between the source / drain region and an adjacent source / drain region of another transistor along the first direction.

Description

Semiconductor device and method for forming the same Embodiments of the present invention generally relate to electronic devices, and more particularly to electronic devices containing field effect transistors. The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have enabled each generation of integrated circuits to feature smaller and more complex circuits than the previous one. In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit chip area) has generally increased as chip size (i.e., the smallest component or circuit that can be produced by the fabrication process) has decreased. Process size reduction generally increases production capacity and reduces associated costs. However, this reduction in size also increases the complexity of processing and manufacturing the integrated circuits. In at least one embodiment, a semiconductor device includes a first circuit region comprising: a first stack of a plurality of first nanostructures; an isolation region adjacent to the first stack and located between the first stack and another stack of a plurality of nanostructures adjacent to the first stack; a spacer layer located on the isolation region, the spacer layer covering a peripheral portion and a central portion of an upper surface of the isolation region; a first gate structure encapsulating the first nanostructures; a second epitaxial layer adjacent to one of the first nanostructures; and a first source / drain region, wherein the second epitaxial layer physically and electrically isolates the first source / drain region from one of the first nanostructures and the first source / drain region contacts the other of the first nanostructures; and a second circuit region offset from the first circuit region and including: a second stack of a plurality of second nanostructures, the number of second nanostructures in the second stack being the same as the number of first nanostructures in the first stack; a second gate structure encapsulating the second nanostructures; and a second source / drain region, wherein the number of second nanostructures contacting the second source / drain region is greater than the number of first nanostructures contacting the first source / drain region. In at least one embodiment, a semiconductor device includes a stack of multiple nanostructures; a gate structure encapsulating the nanostructures; an isolation region located between the stack of nanostructures and another stack of multiple nanostructures adjacent to the stack of nanostructures along a first direction; a source / drain region adjacent to at least one of the nanostructures; and a spacer layer located on sidewalls of the gate structure and sidewalls of the source / drain region, with the spacer layer covering the source / drain region and an area between the source / drain region and an adjacent source / drain region of another transistor along the first direction. In at least one embodiment, a method for forming a semiconductor device includes: forming a multilayer structure of multiple first semiconductor layers and multiple second semiconductor layers alternating on a substrate; patterning the multilayer structure to form a stack of fins and multiple nanostructures on the fins; forming an isolation region adjacent to the fins; forming a sacrificial gate structure on the stack; forming a spacer layer on the sidewalls of the stack and on the upper surface of the isolation region; forming a mask layer on the spacer layer; recessing the mask layer to expose the upper portion of the stack; forming a source / drain opening with the mask layer covering the isolation region; forming at least one epitaxial layer in the source / drain opening; forming a bottom dielectric layer on at least one epitaxial layer in the source / drain opening; forming a source / drain region on the bottom dielectric layer; and replacing the dummy gate structure with a gate structure, and the gate structure encapsulating the stacked nanostructures. The following detailed description may be accompanied by accompanying drawings to facilitate an understanding of various aspects of the present invention. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is common practice in the industry. In practice, the dimensions of the various structures may be arbitrarily increased or decreased for clarity. The following provides different embodiments or examples that can implement different structures of the present invention. The following examples of specific components and arrangements are intended to simplify the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by additional components but not in direct contact. In addition, multiple embodiments of the present invention may repeatedly use the same reference numerals for simplicity, but elements with the same reference numerals in multiple embodiments and / or arrangements do not necessarily have the same corresponding relationship. Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or similar terms are used to describe the relationship of one element or structure to another element or structure in the drawings. These spatially relative terms encompass different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90 degrees or otherwise, the spatially relative terms used will be interpreted based on the orientation. Embodiments of the present invention generally relate to electronic devices, and more particularly to electronic devices containing field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs, or nanostructured FETs (e.g., fully wound gate FETs, nanosheet FETs, nanowire FETs, or the like). In advanced technology nodes, fully wound gate hybrid circuit cells may include different active region widths to provide different effective widths (Weff). For example, different effective widths are beneficial for both speed performance and power efficiency, with logic cells with smaller effective widths having improved power efficiency, while logic cells with larger effective widths have improved speed performance. Forming different active region widths is a straightforward method for providing different effective widths. However, larger active region widths increase the cell area, while smaller active region widths make it difficult to form inner spacers, limiting the process tolerances for source / drain epitaxial growth. A multi-chip assembly (or hybrid chip) structure can provide different effective widths for logic circuit cells, improving cell size and process tolerances. However, different channel epitaxy and active area etching may increase the difficulty of patterning the active area and etching the nanosheet. In an embodiment of the present invention, multiple slices are provided for use in a hybrid logic circuit unit. These slices can be formed by growing an epitaxial layer upward from the bottom of the source / drain opening to isolate the slices from the subsequently formed source / drain regions. Devices with fewer slices contacting the source / drain regions due to a taller epitaxial layer (e.g., a fully wound gate field-effect transistor) are more energy-efficient, while devices with more slices contacting the source / drain regions due to a shorter epitaxial layer are more advantageous for high-speed operation. A bottom insulator layer, or "elastic bottom insulator," at varying heights of the epitaxial layer from bottom to top helps reduce mesa leakage. During the process of forming the source / drain openings, depositing multiple channel-fail epitaxial layers causes one or more nanosheets to fail (e.g., isolating the nanosheet from the source / drain regions). Multiple etching steps increase the risk of breaking through the shallow trench isolation (STI) and exposing the semiconductor fin sidewalls. Consequently, epitaxial growth of the source / drain regions results in unwanted growth from the exposed sidewalls of the semiconductor fins. In severe cases, this unwanted growth can create current paths, or "bridging," between adjacent semiconductor fins. In an embodiment of the present invention, a spacer layer protects the shallow trench isolation (STI). The spacer layer is not removed from the STI prior to subsequent etching operations to form the source / drain openings and the channel fail layer. This results in virtually no additional STI loss, reducing the risk of polysilicon collapse during step-undoped silicon epitaxy. The STI can be protected by a mask, such as a bottom anti-reflective coating (BARC). The nanostructure device may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double or multiple patterning processes. Generally, double or multiple patterning processes combine photolithography with self-aligned processes to produce patterns with a pitch smaller than that obtained using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. A self-aligned process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure device. 1A through 1C are side cross-sectional views of a portion of an integrated circuit wafer 10 according to various embodiments. FIG. 1A shows a portion of the integrated circuit wafer 10 cut along a semiconductor fin 32 (along a first direction, such as the X direction). FIG. 1B and 1C show portions of the integrated circuit wafer 10 cut along a source / drain region 82 (along a second direction, such as the Y direction, which is perpendicular to the X direction). FIG1A shows a portion of an integrated circuit chip 10. Integrated circuit chip 10 includes a first device region 20A and a second device region 20B. In first device region 20A, all channels of each device, such as nanostructures 22A, 22B, and 22C, contact source / drain regions 82 on either side thereof. In second device region 20B, the bottommost channel of each device, such as nanostructure 22A, is isolated from source / drain regions 82, while the other channels, such as nanostructures 22B and 22C, contact source / drain regions 82. The bottommost channel in second device region 20B, such as nanostructure 22A, contacts epitaxial layer 110B and, optionally, second bottom dielectric layer 800B. Other structures of integrated circuit chip 10 will be described in detail below in conjunction with method 1000 shown in FIGS. 2A through 14. Figures 2A through 13F illustrate various stages of fabrication of an integrated circuit device, such as an integrated circuit chip 10, according to various embodiments of the present invention. Figure 14 is a flow chart of a method 1000 for fabricating a semiconductor device according to various embodiments of the present invention. The various stages of fabricating the integrated circuit device shown in Figures 2A through 13F can be performed according to the method of Figure 14. Figure 14 is a flow chart of method 1000 for forming an integrated circuit device, or a portion thereof, from a workpiece according to one or more embodiments of the present invention. Method 1000 is provided for illustrative purposes only and is not intended to limit the specific description of method 1000 according to the embodiments of the present invention. Additional steps may be provided before, during, or after method 1000, and additional embodiments of the present invention may replace, omit, or interchange some of the steps described. Not all steps are described in detail here to simplify the description. One embodiment of method 1000 will be described below with partial perspective and / or cross-sectional views of the workpiece (e.g., Figures 2A through 13F) illustrating various stages of fabrication. For the avoidance of doubt, the X direction in all figures is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions. It is worth noting that since the workpiece can be manufactured into a semiconductor device, the workpiece can be regarded as a semiconductor device depending on the context. Figures 2A through 13F are perspective and cross-sectional views of intermediate stages in the fabrication of field-effect transistors, such as nanosheet field-effect transistors, in some embodiments. Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A illustrate perspective views. Figures 2B, 3B, 4B, 4D, 4F, 4H, 5B, 5D, 6B, 7B, 7E, 7G, 7I, 7K, 7L, 7N, 7O, 8B, 8E, 8F, 8G, 9B, 10B, 11D, 12, 13B, 13D, and 13F illustrate side views along reference cross-section BB' (gate cross section or source / drain cross section, YZ plane) shown in Figures 2A, 3A, and 4A. Figures 4C, 4E, 4G, 5C, 6C, 7C, 7D, 7F, 7H, 7J, 7M, 8C, 8D, 9C, 10C, 11A, 11B, 11C, 13A, 13C, and 13E show side views along the reference section CC' (fin section, XZ plane) shown in Figure 4A. In Figures 2A and 2B, a substrate 110 is provided. Substrate 110 can be a semiconductor substrate such as a bulk semiconductor or the like, which can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of substrate 110 can include silicon; germanium; semiconductor compounds such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; semiconductor alloys such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates such as single-layer substrates, multi-layer substrates, or substrates with graded composition can also be used. In Figures 2A and 2B, a multilayer stack 25 or "lattice" of first semiconductor layers 21A, 21B, and 21C (collectively referred to as first semiconductor layer 21) alternating with second semiconductor layer 23 is formed on substrate 110, corresponding to step 1100 of Figure 14. In some embodiments, first semiconductor layer 21 may be composed of a first semiconductor material suitable for n-type nanofield-effect transistors, such as silicon, silicon carbide, or the like, while second semiconductor layer 23 may be composed of a second semiconductor material suitable for p-type nanofield-effect transistors, such as silicon germanium or the like. The epitaxial growth method for each layer of multilayer stack 25 may be chemical vapor deposition, atomic layer deposition, vapor phase epitaxy, molecular beam epitaxy, or the like. The figure shows three first semiconductor layers 21 and three second semiconductor layers 23. In some embodiments, the multilayer stack 25 may include one, two, four, or more first semiconductor layers 21 and one, two, four, or more second semiconductor layers 23. Although the multilayer stack 25 shown in the figure includes the second semiconductor layer 23 as the bottom layer, in some embodiments, the bottom layer of the multilayer stack 25 may be the first semiconductor layer 21. Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, allowing the first semiconductor layer 21 to be patterned into the channel region of the nanostructured field-effect transistor. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region. The high etch selectivity can be used to remove the first semiconductor layer 21 of the first semiconductor material without significantly removing the second semiconductor layer 23 of the second semiconductor material, allowing the second semiconductor layer 23 to be patterned into the channel region of the nanostructured field-effect transistor. In Figures 3A and 3B , a fin 32 and a vertical stack 26 of nanostructures 22A, 22B, 22C, and 24 are formed in substrate 110 and multilayer stack 25, corresponding to step 1200 of Figure 14 . Nanostructures 22A through 22C may be collectively referred to as nanostructure 22 . In some embodiments, nanostructures 22 and 24 and fin 32 may be formed by etching trenches in multilayer stack 25 and substrate 110 . The etching process may be any acceptable etching process, such as reactive ion etching, neutral beam etching, similar etching, or a combination thereof. The etching process may be anisotropic. Nanostructures 22A, 22B, and 22C (which may be considered channels) may be formed from first semiconductor layer 21 , and nanostructure 24 may be formed from second semiconductor layer 23 . The distance CD1 between adjacent fins 32 and nanostructures 22 and 24 can be between about 18 nm and about 100 nm, less than 18 nm, or greater than 100 nm. The portion of integrated circuit chip 10 shown in Figures 3A and 3B includes two fins 32 to simplify the diagram. The method 1000 shown in Figures 2A through 13F can be extended to any number of fins and is not limited to the two fins 32 shown in Figures 3A through 13F. In some figures, three fins are shown instead of two. The fins 32 and the nanostructures 22 and 24 may be patterned by any suitable method. For example, one or more photolithography processes may be used to form the fins 32 and the nanostructures 22 and 24, such as a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines photolithography with a self-alignment process to produce a pattern pitch that is smaller than the pattern pitch obtained using a single direct photolithography process. In the case of a multiple patterning process, for example, a sacrificial layer may be formed on a substrate and the sacrificial layer may be patterned using a photolithography process. Self-alignment is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 32. 3A and 3B illustrate fin 32 having tapered sidewalls such that the width of fin 32 and / or nanostructures 22 and 24 increases continuously in a direction toward substrate 110. In these embodiments, nanostructures 22 and 24 may each have different widths and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-trapezoidal), such that the widths of fin 32 and nanostructures 22 and 24 are substantially similar, and nanostructures 22 and 24 are each rectangular. In Figures 3A and 3B, isolation regions 36, such as shallow trench isolation regions, may be formed adjacent to fins 32, corresponding to step 1300 of Figure 14. Isolation regions 36 may be formed by depositing an insulating material over substrate 110, fins 32, and nanostructures 22 and 24, as well as between adjacent fins 32 and nanostructures 22 and 24. The insulating material may be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition, flowable chemical vapor deposition, the like, or a combination thereof. In some embodiments, a liner (not shown) may be formed along the surfaces of substrate 110, fins 32, and nanostructures 22 and 24. The insulating material described above may then be formed over the liner. The insulating material may be subjected to a removal process such as chemical mechanical polishing, an etch back process, a combination thereof, or the like to remove excess insulating material from the nanostructures 22 and 24. After the removal process is completed, the top surfaces of the nanostructures 22 and 24 may be exposed and flush with the insulating material. The insulating material is then recessed to form isolation regions 36. After the recessing step, upper portions of nanostructures 22 and 24 and fin 32 may protrude from between adjacent isolation regions 36. The upper surface of isolation regions 36 may be flat, as shown, a raised surface, a recessed surface, or a combination thereof. In some embodiments, isolation regions 36 are recessed using an acceptable etching process, such as an oxide removal process using dilute hydrofluoric acid, that is selective to insulating materials and leaves fin 32 and nanostructures 22 and 24 substantially intact. Figures 2A-3B illustrate a method for forming fin 32 and nanostructures 22 and 24 in one embodiment (e.g., etch-last). In some embodiments, fin 32 and / or nanostructures 22 and 24 may be epitaxially grown in trenches in a dielectric layer (e.g., etch-first). The epitaxial structure may include alternating semiconductor materials, such as alternating first and second semiconductor materials. In some embodiments, the spacing between channels, such as nanostructures 22A-22C (e.g., between channels, such as nanostructure 22B and channels, such as nanostructures 22A or 22C), can be between about 8 nm and about 12 nm. In some embodiments, the spacing is less than 8 nm. In some embodiments, the thickness (measured in the Z direction) of each channel, such as nanostructures 22A-22C, is between about 5 nm and about 8 nm. In some embodiments, the width (measured in the Y direction) of each channel, such as nanostructures 22A-22C, is at least about 8 nm. In some embodiments, the width is less than 8 nm. As shown in Figures 3A and 3B, appropriate well regions (not shown) can be formed in the fin 32, nanostructures 22 and 24, and / or isolation region 36. Using a mask, n-type impurities can be implanted in the p-type region of the substrate 110, and p-type impurities can be implanted in the n-type region of the substrate 110. Examples of n-type impurities may include phosphorus, arsenic, antimony, or the like. Examples of p-type impurities may include boron, boron fluoride, indium, or the like. Annealing may be performed after implantation to repair implantation damage and activate the p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fin 32 and nanostructures 22 and 24 may omit a separate implantation step, but in-situ doping and implantation doping may be used in combination. In Figures 4A to 4D, a sacrificial gate structure 40 is formed on the fin 32 and / or the nanostructures 22 and 24, corresponding to step 1400 of Figure 14. A sacrificial gate layer 45 is formed on the fin 32 and / or the nanostructures 22 and 24. The material of the sacrificial gate layer 45 has a high etch selectivity relative to the isolation region 36. The sacrificial gate layer 45 can be a conductive material, a semiconductor material, or a non-conductive material, and can be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, and metal. The sacrificial gate layer 45 can be deposited by physical vapor deposition, chemical vapor deposition, sputtering deposition, or other techniques used to deposit the selected material. For example, a mask layer 47 is formed on the sacrificial gate layer 45 and can include silicon nitride, silicon oxynitride, or the like. Mask layer 47 may include one or more layers, such as a first mask layer and a second mask layer. The first mask layer may be formed in a first deposition process, while the second mask layer may be formed in a second deposition process after the first deposition process. In some embodiments, before forming sacrificial gate layer 45, a sacrificial gate dielectric layer 43 is formed between the subsequently formed sacrificial gate layer 45 and the fins 32 and / or nanostructures 22 and 24, as shown in FIG4C. A spacer layer 41 or sidewall spacers is formed on and covers the sidewalls of the mask layer 47, the sacrificial gate layer 45, and the isolation region 36, corresponding to step 1500 of FIG. 14 . In some embodiments, the spacer layer 41 may be composed of an insulating material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, or the like, and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The spacer layer 41 may be formed by depositing a spacer material layer (not shown) on the mask layer 47 and the sacrificial gate layer 45. In some embodiments, the spacer layer 41 includes one or more material layers. For example, the spacer layer 41 may include a spacer layer 41A contacting the sacrificial gate structure 40 and a spacer layer 41B contacting the spacer layer 41A, as shown in FIG. 4C and 4D . The spacer layer 41A may be formed in a first deposition process, and the spacer layer 41B may be formed in a second deposition process after the first deposition process. As shown in Figures 4A, 4C, and 4D, the spacer material layer between the sacrificial gate structures 40 is not removed. For example, in Figure 4D, a horizontal portion of spacer layer 41 is present over isolation regions 36. Spacer layer 41 may have a thickness of approximately 5 nm to approximately 20 nm, as described above. Although not shown in the top view, spacer layer 41 may cover isolation regions 36. Spacer layer 41 may completely cover isolation regions 36. In some embodiments, spacer layer 41 may actually completely cover isolation regions 36. For example, spacer layer 41 may completely cover each isolation region 36, which helps protect isolation regions 36 during etching steps to form source / drain openings and epitaxial layers (which isolate channels such as nanostructures 22 from source / drain regions 82). In some embodiments, spacer layers 41A and 41B cover isolation regions 36, as described above. In some embodiments, spacer layer 41B may be removed from isolation regions 36, so that only spacer layer 41A covers isolation regions 36. It should be understood that the spacer layers 41A and 41B may cover the respective central portions of the isolation regions 36 regardless of whether the spacer layer 41B is removed from the respective central portions of the isolation regions 36 , as shown in FIG. 4D . Figures 4A to 4C illustrate a process for forming a gate spacer layer 41. In some embodiments, an additional spacer layer may be formed after removing the sacrificial gate layer 45. In these embodiments, the sacrificial gate layer 45 is removed to leave an opening, and a spacer material may be conformally coated along the sidewalls of the opening to form the spacer layer. Prior to forming an active gate such as gate structure 200, the conformally coated material may be removed from the bottom of the opening corresponding to the upper surface of the uppermost channel (e.g., channel such as nanostructure 22A). Figures 4E to 4H illustrate a method for forming a mask layer on the isolation region 36, corresponding to step 1600 in Figure 14. The mask layer may be or include a photoresist, a bottom anti-reflective coating, other mask materials, combinations thereof, or the like. The mask layer is then referred to as the bottom anti-reflective coating 400. The bottom anti-reflective coating 400 may be deposited using a spin coater. Initially, a thin layer of the bottom anti-reflective coating material may be deposited on the substrate surface using a spin coater, followed by high-speed rotation of the substrate to evenly spread the material over the surface. After applying the bottom anti-reflective coating material, the bottom anti-reflective coating material may be cured by heating to a selected temperature and maintaining the temperature for a selected time, which facilitates adhesion of the bottom anti-reflective coating material to the substrate and achieving selected optical properties. The cured bottom anti-reflective coating material may be the bottom anti-reflective coating 400, as shown in Figures 4E and 4F. After curing, a layer of photoresist material may optionally be formed on top of the bottom anti-reflective coating 400 (not shown). The photoresist material may then be patterned using lithography, which exposes selected areas of the photoresist to a light source. A developer solution may then be used to remove the exposed or unexposed portions of the photoresist, leaving the patterned photoresist layer on top of the bottom anti-reflective coating. The bottom anti-reflective coating 400 may comprise one or more materials, such as one or more organic bottom anti-reflective coatings, one or more inorganic bottom anti-reflective coatings, a hybrid bottom anti-reflective coating, combinations thereof, or the like. An organic bottom anti-reflective coating may comprise a polymeric material such as polyimide, poly(methyl methacrylate), or a phenolic resin. An inorganic bottom anti-reflective coating may comprise a metal oxide such as silicon oxide or titanium oxide. A hybrid bottom anti-reflective coating may comprise one or more combinations of organic and inorganic materials, such as silsesquioxanes or organometallic polymers. In Figures 4G and 4H , the bottom anti-reflective coating 400 is recessed. The bottom anti-reflective coating 400 can be recessed by a wet or dry etching step. Wet etching can utilize a chemical solution to remove the bottom anti-reflective coating material from selected areas of the substrate. Dry etching can utilize an electrochemical-based technique, such as reactive ion etching or plasma etching, to remove the bottom anti-reflective coating material. In Figures 4G and 4H , the bottom anti-reflective coating 400 can be recessed uniformly. In some embodiments, the bottom anti-reflective coating 400 can be recessed according to a pattern. After the bottom anti-reflective coating recessing process is completed, a cleaning step can be performed to remove any residual bottom anti-reflective coating material or etchant. The bottom anti-reflective coating 400 can be recessed below the uppermost surface of the channel, such as the nanostructure 22, to expose the sacrificial gate structure 40 and the spacer layer 41 above at least the uppermost channel, such as the nanostructure 22C, corresponding to step 1700 in Figure 14 . In some embodiments, the bottom anti-reflective coating 400 is recessed to a height below that shown in Figure 4H . For example, the bottom anti-reflective coating 400 can be recessed to below the bottom surface of the uppermost channel, such as the nanostructure 22C, or below the upper or lower surface of an intermediate channel, such as the nanostructure 22B. After recessing the bottom anti-reflective coating 400, the top of the vertical stack 26 can be exposed from the bottom anti-reflective coating 400, but the spacer layer 41 still covers the top of the vertical stack 26. In Figures 5A through 5D , an etching process comprising one or more etching steps is performed to etch the raised fins 32 and / or nanostructures 22 and 24 uncovered by the sacrificial gate structure 40 to form the illustrated structure. For example, a first etching step may recess the upper portion of the vertical stack 26 uncovered by the bottom anti-reflective coating 400 and the exposed portion of the spacer layer 41 above the sacrificial gate structure 40, and / or remove the exposed portion of the spacer layer 41. Following the first etching step, a second etching step may be performed to remove the exposed portion of the vertical stack 26 to form the structure shown in Figures 5A , 5C , and 5D . The recessing process may form source / drain openings 49 between adjacent channels, such as stacks of nanostructures 22, on the same fin 32, corresponding to step 1800 of Figure 14 . The recessing process may be anisotropic to protect and not etch the portion of the fin 32 directly beneath the sacrificial gate structure 40 and the spacer layer 41. In some embodiments, the upper surface of the recessed fin 32 can be substantially coplanar with the upper surface of the isolation region 36. As shown in FIG5D , the upper surface of the recessed fin 32 can be recessed and slightly lower than the upper surface of the isolation region 36. FIG5C shows two vertical stacks 26 of nanostructures 22 and 24 after the etching process to simplify the diagram. In general, the etching process can be used to form any selected number of vertical stacks 26 of nanostructures 22 and 24 on the fin 32. As shown in FIG5D , because the spacer layer 41 covers the isolation region 36, the etching process that forms the source / drain openings does not substantially etch the isolation region 36, and thus the isolation region 36 protects the sidewalls of the fin 32. The dashed lines in FIG5D conceptually represent the portions of the isolation region 36 that the etching process would remove if the spacer layer 41 were not located on the isolation region 36 as described herein. After forming the source / drain openings 49 , the mask, such as the bottom anti-reflective coating 400 , is removed, which corresponds to step 1900 of FIG. 14 . As shown in Figures 6A to 6C and 7A to 7G, inner spacers 74 are formed, corresponding to step 2000 in Figure 14. A selective etching process is performed to recess the end portions of nanostructure 24 exposed by the openings in spacer layer 41 without significantly etching nanostructure 22, as shown in Figures 6A to 6C. After the selective etching process, recesses 64 are formed in nanostructure 24 at the locations where the removed end portions were originally located. The final structure is shown in Figures 6A to 6C. Next, an inner spacer layer 74L is formed to fill (e.g., partially or completely fill) the recess 64 in the nanostructure 22 formed by the previous selective etching process, as shown in Figures 7D and 7E. Inner spacer layer 74L can be a suitable dielectric material such as silicon carbonitride, silicon oxycarbonitride, or the like, and can be formed by a suitable deposition method such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. An etching process such as an anisotropic etching process can be performed to remove the portion of the inner spacer layer outside the recess in the nanostructure 24. The remaining portion of the inner spacer layer (e.g., the portion located within the recess 64 in the nanostructure 24) forms the inner spacer 74. The final structure is shown in Figures 7A to 7C, 7F, and 7G. 7H-7O are side cross-sectional views of forming epitaxial layers 110A and 110B and a second bottom dielectric layer 800B in various embodiments. The epitaxial layers 110A and 110B isolate one or more channels such as nanostructures 22A-22C, corresponding to step 2100 of FIG. In Figures 7H and 7I, after the source / drain openings 49 and the inner spacers 74 are formed, the source / drain openings 49 extend below the upper surface of the fin 32. In some embodiments, an epitaxial layer 110A is formed in a portion of the source / drain opening 49 at a height below the upper surface of the fin 32, as shown in Figure 7H. The epitaxial layer 110A can be an undoped semiconductor layer such as an undoped silicon layer. The undoped silicon layer such as the epitaxial layer 110A can be grown in an epitaxial chamber, and the process used can be chemical vapor deposition. In chemical vapor deposition, a silicon source gas (such as silane) and a carrier gas (such as hydrogen) can be introduced into a heated chamber. The gas reacts on the surface of the fin 32, and the gas can be heated to between about 900°C and 1100°C. During the reaction, the silicon source gas can be decomposed to release silicon atoms, which can diffuse onto the surface of the fin 32 to form a single crystal silicon layer. The low pressure environment is conducive to reducing the presence of impurities and improving the consistency of the deposition rate. In order to grow undoped silicon, no additional dopant gas is introduced into the chamber. The final layer has a low level of impurities and is electrically neutral, so the epitaxial layer 110A can be an insulating layer. The method for forming the epitaxial layer 110A can be global, that is, there is no mask on the integrated circuit chip 10 during chemical vapor deposition. FIG7J is a cross-sectional view of the first device region 20A and the second device region 20B of the integrated circuit chip 10 according to various embodiments. FIG7K and FIG7L are cross-sectional views along lines KK and LL, respectively. In FIG7J , 7K , and 7L , after forming the epitaxial layer 110A, an epitaxial layer 110B may be formed within a portion of the source / drain opening 49 in the second device region 20B. Epitaxial layer 110B may be an undoped semiconductor layer, such as an undoped silicon layer, and may be formed using a method similar to that used to form epitaxial layer 110A. Epitaxial layer 110B may extend from the top of the fin 32 to a height above one or more channels, such as nanostructures 22, to electrically and / or physically isolate the one or more channels from the source / drain regions 82 formed in subsequent processing. In the example shown in FIG7J , epitaxial layer 110B extends to a height above the bottommost channel, such as nanostructure 22C. In some embodiments, epitaxial layer 110B may extend to any height above the bottommost channel, such as nanostructure 22C, and below the topmost channel, such as nanostructure 22A. When forming the epitaxial layer 110B, the first device region 20A may be masked. For example, a hard mask may cover the first device region 20A. The hard mask may include aluminum oxide or another suitable material. After forming the epitaxial layer 110B, the hard mask may be removed. In Figures 7M, 7N, and 7O, a bottom dielectric layer may be formed after forming the epitaxial layers 110A and 110B. The bottom dielectric layer, or flexible bottom insulator (FBI), helps prevent mesa leakage in the integrated circuit chip 10. The bottom dielectric layer includes a first bottom dielectric layer 800A formed on the epitaxial layer 110A in the first device region 20A, and a second bottom dielectric layer 800B formed on the epitaxial layer 110B in the second device region 20B. The first bottom dielectric layer 800A may directly contact the epitaxial layer 110A, while the second bottom dielectric layer 800B may directly contact the epitaxial layer 110B. The bottom dielectric layer comprising the first bottom dielectric layer 800A and the second bottom dielectric layer 800B may be formed in the same deposition step, so that the first bottom dielectric layer 800A and the second bottom dielectric layer 800B have the same material and thickness. The bottom dielectric layer may include silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, combinations thereof, or the like. In some embodiments, the bottom dielectric layer may have a thickness of about 1 nm to about 5 nm. In some embodiments, the bottom dielectric layer has a thickness greater than 5 nm. If the spacer layer 41 does not cover the isolation region 36 when forming the source / drain openings 49 and the epitaxial layers 110A and 110B, the etching process described herein will remove the dashed area 710A of the isolation region 36 shown in Figures 7N and 7O. Figures 8A to 8G illustrate a method for forming source / drain regions 82, corresponding to step 2200 of Figure 14. The source / drain regions may represent a source or a drain, either individually or collectively, depending on the context. In the described embodiment, the source / drain regions 82 may be epitaxially grown epitaxial material. In some embodiments, the source / drain regions 82 apply stress to individual channels, such as nanostructures 22A to 22C, to improve performance. The source / drain regions 82 are formed such that the sacrificial gate structures 40 are located between individual pairs of source / drain regions 82. In some embodiments, the spacer layer 41 separates the source / drain regions 82 from the sacrificial gate layer 45 by an appropriate lateral distance to prevent the source / drain regions 82 from electrically bridging to the subsequently formed gate of the final device. The source / drain region 82 may include any acceptable material, such as a material suitable for an n-type or p-type device. For n-type devices in some embodiments, the source / drain region 82 includes a material that can apply tensile stress in the channel region, and the material may be silicon, silicon carbon phosphide, silicon phosphide, or the like. In some embodiments, when forming a p-type device, the source / drain region 82 includes a material that can apply compressive stress in the channel region, and the material may be silicon germanium, silicon germanium boride, germanium, germanium tin, or the like. The source / drain region 82 may have a surface that rises from the individual surfaces of the fins and may have crystal planes. In some embodiments, adjacent source / drain regions 82 may merge to form a single source / drain region 82 adjacent to two nearby fins 32. In some embodiments, a first epitaxial growth process may be performed to form n-type source / drain regions 82, and a second epitaxial growth process may be performed to form p-type source / drain regions 82. It should be understood that the terms "first" and "second" are interchangeable. For example, n-type epitaxial growth may be performed before or after p-type epitaxial growth. Dopants may be implanted into the source / drain region 82 and then annealed. The impurity concentration of the source / drain region may be between about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used in the source / drain regions 82 may be any of the aforementioned impurities. In some embodiments, the source / drain regions 82 may be in-situ doped during growth. An etch stop layer and an interlayer dielectric layer (not shown in Figures 8A to 8C to simplify the diagram) may then be formed to cover the sacrificial gate structure 40 and the source / drain regions 82. As shown in FIG8D , the source / drain region 82 in the first device region 20A contacts all three channels, such as nanostructures 22A, 22B, and 22C, while the source / drain region 82 in the second device region 20B does not contact all three channels, such as nanostructures 22A, 22B, and 22C (e.g., it contacts channels such as nanostructures 22B and 22C but does not contact channel such as nanostructure 22A). As a result, the effective width (Weff) in the first device region 20A exceeds the effective width (Weff) in the second device region 20B. Figures 8E and 8F are side cross-sectional views of the source / drain region 82 on the fin 32 in the YZ plane, in various embodiments. The source / drain region 82 in the first device area 20A may have a greater height in the Z-axis direction than the source / drain region 82 in the second device area 20B. Although not shown in Figures 8E and 8F, the source / drain region 82 in the first device area 20A and the source / drain region 82 in the second device area 20B may have different profiles (except for the height in the Z-axis direction described above). For example, the bottom shape of the source / drain region 82 in the first device area 20A may be different from the bottom shape of the source / drain region 82 in the second device area 20B, such as being longer or shorter in the Y-axis and / or X-axis directions. In another example, the bottom profile of the source / drain region 82 in the first device area 20A and the bottom profile of the source / drain region 82 in the second device area 20B may be different. Spacer layers 41A and 41B limit the lateral growth of source / drain regions 82, and lateral portions of source / drain regions 82 may be higher than spacer layers 41A and 41B, as shown. As shown in Figures 1B, 1C, 11D, and 11E, spacer layers 41A and 41B may remain in integrated circuit chip 10 without being removed. That is, spacer layers 41A and 41B may be present in a final product or structure containing integrated circuit chip 10. In some embodiments, spacer layers 41A and 41B may be removed before depositing etch stop layer 131 and interlayer dielectric layer 130 (see Figures 1A to 1C and Figure 11A). FIG8G is a side cross-sectional view of epitaxial mushrooms and / or bridges when the spacer layer is absent from respective central portions of isolation regions 36 and the sidewalls of fins 32 are exposed by etching isolation regions 36. For example, when growing source / drain regions 82, mushroom portions 82X may be grown laterally from one or both of the fins 32 shown in FIG8G . In Figures 9A to 9C , after forming source / drain regions 82, nanostructures 24, mask layer 47, and sacrificial gate layer 45 can be removed to expose the fin channel, such as nanostructures 22A to 22C. A planarization process, such as chemical mechanical polishing, can be performed to level the sacrificial gate layer 45 with the top surface of the spacer layer 41. The planarization process also removes mask layer 47 on the sacrificial gate layer 45 and removes portions of the spacer layer 41 along the sidewalls of mask layer 47. As a result, the top surface of the sacrificial gate layer 45 is exposed. The sacrificial gate layer 45 is then removed in an etching process to form the recess 92. In some embodiments, the sacrificial gate layer 45 can be removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 45 without etching the spacer layer 41. If the sacrificial gate dielectric layer 43 is present, it can serve as an etch stop layer when etching the sacrificial gate layer 45. After removing the sacrificial gate layer 45, the sacrificial gate dielectric layer 43 can be removed. Nanostructure 24 is removed to release nanostructure 22. After nanostructure 24 is removed, nanostructure 22 forms a plurality of nanosheets extending horizontally (e.g., parallel to the major upper surface of substrate 110) and stacked vertically. The nanosheets can be collectively considered as channels, such as nanostructure 22, of a nanostructure device, such as a nanosheet field-effect transistor (which can be a fully wound gate field-effect transistor). In some embodiments, a selective etching process that is selective to the material of nanostructure 24 may be used to remove nanostructure 24 without substantially etching nanostructure 22. In some embodiments, the etching process may be an isotropic etching process using an etching gas and, optionally, a carrier gas, wherein the etching gas includes fluorine gas and hydrofluoric acid, and the carrier gas may be an inert gas such as argon, helium, nitrogen, combinations thereof, or the like. In some embodiments, nanostructure 24 is removed and nanostructure 22 is patterned to form the channel regions of the p-type field-effect transistor and the n-type field-effect transistor. However, in some embodiments, nanostructure 24 may be removed and nanostructure 22 may be patterned to form the channel region of the first nanostructure device, and nanostructure 22 may be removed and patterned to form the channel region of the second nanostructure device. In some embodiments, nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of the first nanostructure device, and nanostructure 24 may be removed and patterned to form the channel region of the second nanostructure device. In some embodiments, nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of the p-type field-effect transistor and the n-type field-effect transistor. In some embodiments, an additional etching process can be performed to reshape (e.g., thin) a nanosheet, such as nanostructure 22, of a nanostructure device to improve the tolerance of a gate fill process. An isotropic etching process selective to a nanosheet, such as nanostructure 22, can be performed to reshape the nanosheet, such as nanostructure 22. After reshaping the nanosheet, such as nanostructure 22, the nanosheet can have a dog-bone shape, with a middle portion along the X-direction being thinner than the end portions. In Figures 10A to 10C , a replacement gate, such as gate structure 200, is then formed. Gate structure 200 typically includes an interface layer 210, a gate dielectric layer 600, and a metal fill layer 290 (see Figure 12 ). In some embodiments, gate structure 200 further includes a work function metal layer. The method for forming gate structure 200 is described in detail with reference to Figure 12 . FIG11A shows a semiconductor device including an interlayer dielectric layer 130 and an etch stop layer 131. The interlayer dielectric layer 130 can provide electrical isolation between various components of the semiconductor device, such as the gate structure 200 and subsequently formed source / drain contacts. The etch stop layer 131 can be formed before forming the interlayer dielectric layer 130. The etch stop layer 131 can be laterally positioned between the interlayer dielectric layer 130 and a gate spacer, such as the spacer layer 41, and vertically positioned between the interlayer dielectric layer 130 and the source / drain regions 82. In some embodiments, the insulating material forming the interlayer dielectric layer 130 can include silicon oxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, a low-k dielectric material such as fluorosilicate glass, silicon hydroxide, a carbon-doped oxide, a flowable oxide, a porous oxide (such as a xerogel or aerogel), or the like, or a combination thereof. The dielectric material for the interlayer dielectric layer 130 may be deposited by any suitable method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, plasma-assisted chemical vapor deposition, sub-pressure chemical vapor deposition, flowable chemical vapor deposition, spin coating, and / or the like, or combinations thereof. In some embodiments, the etch stop layer 131 may be or include a dielectric material such as silicon nitride, silicon carbonitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, hafnium oxide, zirconium oxide, zirconium aluminum oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, or other suitable materials. The dielectric material for the etch stop layer 131 may be deposited by any suitable method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, plasma-assisted chemical vapor deposition, sub-pressure chemical vapor deposition, flowable chemical vapor deposition, spin coating, and / or the like, or combinations thereof. In some embodiments, the etch stop layer 131 may have a thickness of about 1 nm to about 5 nm. FIG11B shows a semiconductor device including a backside interconnect structure 800 in various embodiments. FIG11B omits the frontside interconnect structure for clarity. In some embodiments, after forming the frontside interconnect structure, the substrate 110 may be thinned or removed, and the fin 32 may be thinned or removed. After thinning the substrate 110 and, if necessary, the fin 32, the backside interconnect structure 800 may be formed. A first backside interlayer dielectric layer 810 may be formed on the back side of the semiconductor device, and its materials and formation process may be similar to those of the interlayer dielectric layer 130 described above. A first removal step, such as an etching step, may then be performed to pattern the first backside interlayer dielectric layer 810 and, if necessary, pattern the fin 32 to form a first opening, which exposes one or more source / drain regions 82. A first backside contact 830 is formed in one of the openings to contact the back side of the source / drain region 82. In some embodiments, silicide may be formed between the first backside contact 830 and the source / drain region 82. A second backside interlayer dielectric layer 820 is formed on the first backside interlayer dielectric layer 810. Its materials and formation process may be similar to those of the aforementioned interlayer dielectric layer 130. A second removal process, such as a second etching step, is used to form a second opening in the second backside interlayer dielectric layer 820 to pattern the second backside interlayer dielectric layer 820. A first backside trace 840 is formed in the second opening. The method for forming the first backside contact 830 may be similar in many respects to the method for forming the source / drain contact 120. Figures 11C, 11D, and 11E illustrate steps for forming source / drain contacts 120 in various embodiments. Source / drain contacts 120 can include a conductive material such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or combinations thereof. A barrier layer (not shown), such as silicon nitride or titanium nitride, can surround source / drain contacts 120 to help prevent or reduce material from outdiffusion from and / or into source / drain contacts 120. A silicide layer 118 can also be formed between source / drain structure 82 and source / drain contacts 120 to reduce source / drain contact resistance. Silicide layer 118 can include nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. In some embodiments, the thickness of the silicide layer (in the Z-axis direction) may be from about 0.5 nm to about 5 nm. In some embodiments, the height of the source / drain contacts 120 may be from about 1 nm to about 50 nm. As shown in Figures 11D and 11E, the etching process for forming the source / drain openings 49, the epitaxial layers 110A and 110B, the first and second bottom dielectric layers 800A and 800B, and the source / drain regions 82 may thin or remove the spacer layer 41B on the isolation region 36. For example, the thickness of the spacer layer 41 when formed may be approximately 5 nm to approximately 20 nm. In some embodiments, one or more materials of the spacer layer 41, the interlayer dielectric layer 130, and the etch stop layer 131 may be different from or the same as each other. Generally, the interlayer dielectric layer 130 and the etch stop layer 131 are different in material. In some embodiments, the material of the spacer layer 41 may be the same as the material of the interlayer dielectric layer 130 or the etch stop layer 131. In some embodiments, the materials of the spacer layer 41, the interlayer dielectric layer 130, and the etch stop layer 131 are different from each other. When forming the etch stop layer 131, the thickness of the horizontal portion of the spacer layer 41 over the isolation region 36 may be approximately 2 nm to approximately 8 nm. When the spacer layer 41B over the isolation region 36 is removed, one or more openings may exist in the spacer layer 41B. The one or more openings may overlap with the upper surface of the isolation region 36. In some embodiments, the spacer layer 41B below the one or more openings may be recessed. In some embodiments, the spacer layer 41B is removed, leaving the one or more openings exposed to the upper surface of the isolation region 36. In some embodiments, the spacer layer 41B is removed, leaving the one or more openings exposed to the upper surface of the isolation region 36. In some embodiments, the spacer layer 41B is not substantially thinned or removed over the isolation region 36 when forming the source / drain openings 49, the epitaxial layers 110A and 110B, the first and second bottom dielectric layers 800A and 800B, and the source / drain regions 82. Figure 12 is a side cross-sectional view of region 170 of Figure 10B in various embodiments. A gate structure 200 is positioned above and between channels, such as nanostructures 22A-22C. Gate structure 200 may cover each channel, such as nanostructures 22A-22C. In some embodiments, gate structure 200 is positioned above and between channels, such as nanostructures 22A-22C, and the channels may be silicon channels for n-type devices, silicon germanium channels for p-type devices, or silicon channels for both n-type and p-type devices. In some embodiments, gate structure 200 includes an interfacial layer 210, one or more gate dielectric layers 600, one or more work function metal layers 900, and a metal fill layer 290. Interface layer 210 may be an oxide of the material of the channels, such as nanostructures 22A-22C, and may be formed on the exposed areas of the channels, such as nanostructures 22A-22C, and on the upper surface of fin 32. Interface layer 210 facilitates adhesion of gate dielectric layer 600 to the channels, such as nanostructures 22A-22C. In some embodiments, interface layer 210 has a thickness of approximately 5 Å to approximately 50 Å. In some embodiments, interface layer 210 has a thickness of approximately 10 Å. Too thin an interface layer 210 may result in voids or insufficient adhesion. Too thick an interface layer 210 depletes the process tolerance for gate fill, which is related to threshold voltage adjustment and resistance as described above. In some embodiments, interface layer 210 is doped (e.g., with lanthanum) to impart a dipole property to adjust the threshold voltage. A gate dielectric layer 600 may be formed on the interfacial layer 210. In some embodiments, the gate dielectric layer 600 includes at least one high-k gate material, which can be considered a dielectric material having a high k dielectric constant (greater than the k dielectric constant of silicon oxide, such as approximately 3.9). Exemplary high-k dielectric materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium zirconium oxide, zirconium oxide, tantalum oxide, or combinations thereof. In some embodiments, the gate dielectric layer 600 has a thickness of approximately 5 Å to approximately 100 Å. In some embodiments, the gate dielectric layer 600 may include dopants (e.g., metal ions driven into the high-k gate dielectric layer from lanthanum oxide, magnesium oxide, yttrium oxide, titanium oxide, aluminum oxide, niobium oxide, or the like, or boron ions driven into the high-k gate dielectric layer from boron oxide), and the dopant concentration can be used to adjust the threshold voltage. In one example, for n-type transistors, a higher concentration of lanthanum ions can lower the threshold voltage compared to a layer with a lower concentration of lanthanum ions or no lanthanum ions. The opposite is true for p-type devices. In some embodiments, the gate dielectric layer 600 of these transistor devices (e.g., input / output transistors) is free of dopants present in other transistor devices (e.g., n-type core logic transistors or p-type input / output transistors). For example, a higher threshold voltage is desired in n-type input / output transistors, so the high-k dielectric layer of the input / output transistor is preferably free of lanthanum ions, which would otherwise lower the threshold voltage. In some embodiments, the gate structure 200 further includes one or more work function metal layers, which may be collectively referred to as work function metal layer 900. When configured as an n-type field effect transistor, the work function metal layer 900 of the fully wrapped gate device may include at least one n-type work function metal layer, an in-situ capping layer, and an oxygen barrier layer. In some embodiments, the n-type work function metal layer may be or include an n-type metal material such as titanium aluminum carbide, titanium aluminum, tantalum aluminum carbide, tantalum aluminum, or the like. The in-situ capping layer is formed on the n-type work function metal layer and may include titanium nitride, titanium silicon nitride, tantalum nitride, or another suitable material. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen diffusion into the n-type work function metal layer, which may cause an undesirable threshold voltage shift. The oxygen barrier layer may be composed of a dielectric material that prevents oxygen from penetrating into the n-type work function layer and protects the n-type work function layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, silicon germanium, or another suitable material. In some embodiments, the work function metal layer 900 includes more layers or fewer layers than described above. The work function metal layer 900 may further include one or more barrier layers comprising a metal nitride such as titanium nitride, tungsten nitride, molybdenum nitride, tantalum nitride, or the like. Each of the one or more barrier layers may have a thickness of approximately 5 Å to approximately 20 Å. The inclusion of one or more barrier layers provides additional threshold voltage adjustment flexibility. Generally, each additional barrier layer increases the threshold voltage. Thus, for n-type field-effect transistors, higher threshold voltage devices (such as input / output transistors) may have at least one or more additional barrier layers, while lower threshold voltage devices (such as core logic transistors) may have few or even no additional barrier layers. For p-type field-effect transistors, higher threshold voltage devices (such as input / output transistors) may have few or even no additional barrier layers, while lower threshold voltage devices (such as core logic transistors) may have at least one or more additional barrier layers. In the foregoing description, threshold voltage is described in terms of magnitude. For example, the input / output transistors of an n-type field-effect transistor and the input / output transistors of a p-type field-effect transistor may have similar threshold voltage amplitudes but opposite polarities, such as +1 V for the input / output transistors of the n-type field-effect transistor and -1 V for the input / output transistors of the p-type field-effect transistor. In this way, since the additional barrier layers each increase the absolute value of the threshold voltage (e.g., +0.1 V / layer), adding barrier layers will increase the threshold voltage amplitude of the n-type field-effect transistor and reduce the threshold voltage amplitude of the p-type field-effect transistor. The gate structure 200 also includes a metal fill layer 290. The metal fill layer 290 may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In channels such as nanostructures 22A to 22C, one or more work function metal layers 900 may circumferentially surround the metal fill layer 290 in a cross-sectional view, the gate dielectric layer 600 may circumferentially surround the work function metal layer 900 in a cross-sectional view, and the interface layer 210 may circumferentially surround the gate dielectric layer 600 in a cross-sectional view. The gate structure 200 may also include an adhesion layer formed between the one or more work function metal layers 900 and the metal fill layer 290 to enhance adhesion. The adhesion layer is not shown in FIG12 to simplify the diagram. In some embodiments, a conductive layer is formed on the gate structure 200 to contact the metal fill layer 290, the one or more work function metal layers 900, and the gate dielectric layer 600. The conductive layer may include fluorine-free tungsten or another suitable material. In some embodiments, a dielectric cap layer is present on the conductive layer. Additional processes may be performed after fabricating the semiconductor device. For example, a gate contact may be formed to electrically couple to the gate structure 200, and a source / drain via may be formed to electrically couple to the source / drain contact 120. An interconnect structure (e.g., a front-side interconnect structure) may then be formed over the source / drain contact 120 and the gate contact. The interconnect structure may include multiple interconnect layers, each of which may include one or more dielectric layers and metal structures (e.g., conductive lines and conductive vias) embedded therein to form electrical connections between devices on the integrated circuit chip 10. In some embodiments, a conductive layer or conductive cap is present over the gate structure 200. In some embodiments, a dielectric cap layer is present over the gate structure 200 and / or the source / drain contact 120. The configuration where the dielectric cap layer exists only on the gate structure 200 (without a second cap layer on the source / drain contacts 120) can be considered a single SAC structure, while the configuration where the cap layer exists on both the gate structure 200 and the source / drain contacts 120 can be considered a dual SAC structure. 13A to 13F are side cross-sectional views of forming source / drain regions 82 in various embodiments, omitting epitaxial layers 110A and 110B and / or first and second bottom dielectric layers 800A and 800B. Figures 13A and 13B are substantially the same or similar to Figures 7F and 7G. In Figures 13C and 13D , after forming the source / drain openings 49 and inner spacers 74, source / drain regions 82 can be formed, as shown. The method for growing the source / drain regions 82 can be the same or similar to the process described with reference to Figures 8A through 8F . In the embodiment shown in Figures 13A through 13F , the source / drain regions 82 can be grown from both the fin 32 and the channel, such as the nanostructure 22 . In the embodiment shown in Figures 8A through 8F , the source / drain regions 82 can be grown only from the channel, such as the nanostructure 22 , because the epitaxial layer 110A (and optionally the epitaxial layer 110B) and the first and second bottom dielectric layers 800A and 800B cover the fin 32 . In Figures 13E and 13F, the gate structure 200 and the source / drain contacts 120 are formed, which may be the same or similar to those described in Figures 9A to 12. Embodiments may provide several advantages. Protecting the portion of spacer layer 41 above isolation region 36, thereby retaining spacer layer 41 above isolation region 36, can protect isolation region 36 during the formation of source / drain openings 49, epitaxial layers 110A and 110B, first and second bottom dielectric layers 800A and 800B, and source / drain regions 82. The inclusion of epitaxial layers 110A and 110B allows for mixed effective widths based on the number of channels isolated by epitaxial layer 110B. The first and second bottom dielectric layers 800A and 800B can prevent mesa leakage. In at least one embodiment, a semiconductor device includes a first circuit region comprising: a first stack of a plurality of first nanostructures; an isolation region adjacent to the first stack and located between the first stack and another stack of a plurality of nanostructures adjacent to the first stack; a spacer layer located on the isolation region, the spacer layer covering a peripheral portion and a central portion of an upper surface of the isolation region; a first gate structure encapsulating the first nanostructures; a second epitaxial layer adjacent to one of the first nanostructures; and a first source / drain region, wherein the second epitaxial layer physically and electrically isolates the first source / drain region from one of the first nanostructures and the first source / drain region contacts the other of the first nanostructures; and a second circuit region offset from the first circuit region and including: a second stack of a plurality of second nanostructures, the number of second nanostructures in the second stack being the same as the number of first nanostructures in the first stack; a second gate structure encapsulating the second nanostructures; and a second source / drain region, wherein the number of second nanostructures contacting the second source / drain region is greater than the number of first nanostructures contacting the first source / drain region. In some embodiments, the semiconductor device further includes a first bottom dielectric layer located between the first source / drain region and the second epitaxial layer; and a second bottom dielectric layer located between the second source / drain region and the first epitaxial layer, and the height of the second bottom dielectric layer is lower than the height of the first bottom dielectric layer. In some embodiments, the spacer layer includes: a first spacer layer contacting the isolation region; and a second spacer layer on the first spacer layer. In some embodiments, the second spacer layer has an opening to overlap the isolation region. In some embodiments, the semiconductor device further includes an interlayer dielectric layer on the isolation region, and a spacer layer is separated from the isolation region. In some embodiments, a thickness of the spacer layer on the first source / drain region is smaller than a thickness of the spacer layer on a central portion of the upper surface of the isolation region. In at least one embodiment, a semiconductor device includes a stack of multiple nanostructures; a gate structure encapsulating the nanostructures; an isolation region located between the stack of nanostructures and another stack of multiple nanostructures adjacent to the stack of nanostructures along a first direction; a source / drain region adjacent to at least one of the nanostructures; and a spacer layer located on sidewalls of the gate structure and sidewalls of the source / drain region, with the spacer layer covering the source / drain region and an area between the source / drain region and an adjacent source / drain region of another transistor along the first direction. In some embodiments, the spacer layer completely covers the upper surface of the isolation region. In some embodiments, the semiconductor device further includes a fin; and a bottom dielectric layer located between the fin and the source / drain regions. In some embodiments, the semiconductor device further includes source / drain contacts extending through the bottom dielectric layer and contacting the source / drain regions. In some embodiments, the semiconductor device further includes an etch stop layer, and the spacer layer is located between the etch stop layer and the isolation region. In some embodiments, the thickness of the spacer layer on the sidewalls of the source / drain regions is about 5 nm to about 20 nm, and the thickness of the spacer layer on the upper surface of the isolation region is about 2 nm to about 8 nm. In some embodiments, the semiconductor device further includes an undoped silicon layer adjacent to at least one of the other nanostructures, and the undoped silicon layer isolates at least one of the other nanostructures from the source / drain region. In at least one embodiment, a method for forming a semiconductor device includes: forming a multilayer structure of multiple first semiconductor layers and multiple second semiconductor layers alternating on a substrate; patterning the multilayer structure to form a stack of fins and multiple nanostructures on the fins; forming an isolation region adjacent to the fins; forming a sacrificial gate structure on the stack; forming a spacer layer on the sidewalls of the stack and on the upper surface of the isolation region; forming a mask layer on the spacer layer; recessing the mask layer to expose the upper portion of the stack; forming a source / drain opening with the mask layer covering the isolation region; forming at least one epitaxial layer in the source / drain opening; forming a bottom dielectric layer on at least one epitaxial layer in the source / drain opening; forming a source / drain region on the bottom dielectric layer; and replacing the dummy gate structure with a gate structure, and the gate structure encapsulating the stacked nanostructures. In some embodiments, the method further includes removing the mask layer after forming the source / drain openings and before forming the at least one epitaxial layer. In some embodiments, the step of forming at least one epitaxial layer includes: forming a first epitaxial layer extending to the upper surface of the fin; and forming a second epitaxial layer on the first epitaxial layer, wherein the second epitaxial layer extends to a height higher than the at least one stacked nanostructure. In some embodiments, the second epitaxial layer is formed in the second device region containing the stack and masks the first device region containing another stack of the plurality of nanostructures. In some embodiments, the step of forming the bottom dielectric layer includes: forming a first bottom dielectric layer on the first epitaxial layer in the second device area; and forming a second bottom dielectric layer on the second epitaxial layer in the first device area, and the height of the second bottom dielectric layer is higher than the height of the first bottom dielectric layer. In some embodiments, the step of forming the spacer layer includes forming a spacer layer having a first thickness, and wherein a second thickness of the spacer layer before forming the source / drain regions is less than the first thickness. In some embodiments, the step of forming a spacer layer includes: forming a first spacer layer to cover the upper surface of the isolation region; and forming a second spacer layer on the first spacer layer; and when forming the source / drain region, at least one opening exists in the second spacer layer on the isolation region. The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention. BB', CC': Reference cross section CD1: Distance KK, LL: Cross section line 10: Integrated circuit chip 20A: First device area 20B: Second device area 21, 21A, 21B, 21C: First semiconductor layer 22, 22A, 22B, 22C, 24: Nanostructure 23: Second semiconductor layer 25: Multilayer stack 26: Vertical stack 32: Fin 36: Isolation region 40: Sacrificial gate structure 41, 41A, 41B: Spacer layer 43: Sacrificial gate dielectric layer 45: Sacrificial gate layer 47: Mask layer 49: Source / drain opening 64: Recess 74: Inner spacer 74L: Inner spacer layer 82: Source / drain region 82X: Mushroom portion 92: Recess 110: Substrate 110A, 110B: Epitaxial wafer Layer 118: Silicide Layer 120: Source / Drain Contacts 130: Interlayer Dielectric Layer 131: Etch Stop Layer 170: Region 200: Gate Structure 210: Interface Layer 290: Metal Fill Layer 400: Bottom Anti-Reflective Coating 600: Gate Dielectric Layer 710A: Dashed Area 800: Backside Interconnect Structure 800A: First Bottom Dielectric Layer 800B: Second Bottom Dielectric Layer 810: First Backside Interlayer Dielectric Layer 820: Second Backside Interlayer Dielectric Layer 830: First Backside Contact 840: First Backside Line 900: Work Function Metal Layer 1000: Methods 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200: Steps Figures 1A through 1C are side cross-sectional views of a portion of an integrated circuit device according to an embodiment of the present invention. Figures 2A through 13F are diagrams of an integrated circuit device at various stages of fabrication according to various embodiments of the present invention. Figure 14 is a flow chart of a method for fabricating a semiconductor device according to various embodiments of the present invention. B-B', C-C': Reference section 10: Integrated circuit chip 20A: First device area 20B: Second device area 22A, 22B, 22C: Nanostructure 32: Fins 41, 41A, 41B: spacer layer 74: medial spacer 82: Source / Drain Region 110:Substrate 110A, 110B: epitaxial layer 130: interlayer dielectric layer 131: Etching stop layer 800A: First bottom dielectric layer 800B: Second bottom dielectric layer

Claims

1. A semiconductor device, comprising: A first circuit region includes: a first stack of a plurality of first nanostructures; an isolation region adjacent to the first stack and located between the first stack and another stack of a plurality of nanostructures near the first stack; a spacer layer located on the isolation region, and the spacer layer covering a peripheral portion and a central portion of the upper surface of the isolation region, wherein the spacer layer includes: a first spacer layer having a U-shaped profile covering the isolation region; and a second spacer layer located on the first spacer layer, wherein the second spacer layer includes two vertical portions, and the two vertical portions cover the two sidewalls of the U-shaped profile of the first spacer layer and expose a portion of the top surface of the U-shaped profile; a first gate structure encapsulating the first nanostructures; and a second epitaxial layer adjacent to one of the first nanostructures; A first source / drain region, wherein the second epitaxial layer physically and electrically isolates the first source / drain region from one of the first nanostructures, and the first source / drain region contacts the other of the first nanostructures; a first bottom dielectric layer, located between the first source / drain region and the second epitaxial layer, wherein the first bottom dielectric layer has a first width at a first horizontal height and a second width at a second horizontal height higher than the first horizontal height, and the second width is greater than the first width; a first backside contact extending through the first bottom dielectric layer to be electrically connected to the first source / drain region; and a second circuit region, offset from the first circuit region and including: a second stack of a plurality of second nanostructures, wherein the number of the second nanostructures in the second stack is the same as the number of the first nanostructures in the first stack; A second gate structure covering the second nanostructures; and a second source / drain region, wherein the number of the second nanostructures contacting the second source / drain region is greater than the number of the first nanostructures contacting the first source / drain region.

2. The semiconductor device as claimed in claim 1 further includes: A second bottom dielectric layer is located between the second source / drain region and a first epitaxial layer, and the height of the second bottom dielectric layer is lower than the height of the first bottom dielectric layer.

3. The semiconductor device of claim 1 or 2, wherein the first spacer layer contacts the isolation region.

4. The semiconductor device of claim 3, wherein the second spacer layer has an opening to overlap with the isolation region.

5. A semiconductor device, comprising: A stack of multiple nanostructures; a gate structure encapsulating the nanostructures; a first epitaxial layer adjacent to one of the nanostructures; an isolation region located between the stack of the nanostructures and another stack of multiple nanostructures adjacent to the stack of the nanostructures along a first direction; a source / drain region adjacent to at least one of the nanostructures; a spacer layer located on the sidewalls of the gate structure and the sidewalls of the source / drain region, and the spacer layer covering the source / drain region and a region between an adjacent source / drain region of another transistor along the first direction, wherein the spacer layer includes: a first spacer layer having a U-shaped profile covering the isolation region; and a second spacer layer located on the first spacer layer, wherein the second spacer layer includes two vertical portions, and the two vertical portions cover the two sidewalls of the U-shaped profile of the first spacer layer and expose a portion of the top surface of the U-shaped profile; A bottom dielectric layer is located between the source / drain region and the first epitaxial layer, wherein the bottom dielectric layer has a first width at a first horizontal height and a second width at a second horizontal height higher than the first horizontal height, and the second width is greater than the first width; and a back-side contact extends through the bottom dielectric layer to be electrically connected to the source / drain region.

6. The semiconductor device of claim 5, wherein the spacer layer completely covers the upper surface of the isolation region.

7. The semiconductor device as claimed in claim 5 or 6 further includes: A fin-like structure, wherein the bottom dielectric layer is located between the fin and the source / drain region.

8. A method for forming a semiconductor device, comprising: A multilayer structure with multiple first semiconductor layers and multiple second semiconductor layers interleaved is formed on a substrate; The multilayer structure is patterned to form a fin and a stack of multiple nanostructures on the fin; an isolation region is formed adjacent to the fin; a sacrificial gate structure is formed on the stack; a spacer layer is formed on the sidewalls of the stack and the upper surface of the isolation region, wherein the spacer layer includes: a first spacer layer having a U-shaped profile covering the isolation region; and a second spacer layer located on the first spacer layer, wherein the second spacer layer includes two vertical portions, and the two vertical portions cover the two sidewalls of the U-shaped profile of the first spacer layer and expose a portion of the top surface of the U-shaped profile; A masking layer is formed on the spacer layer; the masking layer is recessed to expose the upper portion of the stack; a source / drain opening is formed by the masking layer covering the isolation region; at least one epitaxial layer is formed in the source / drain opening; a bottom dielectric layer is formed on the at least one epitaxial layer in the source / drain opening; a source / drain region is formed on the bottom dielectric layer; and the dummy gate structure is replaced with a gate structure, and the gate structure covers the nanostructures of the stack.

9. The method of forming a semiconductor device as claimed in claim 8 further includes removing the masking layer after forming the source / drain opening and before forming the at least one epitaxial layer.

10. A method for forming a semiconductor device as claimed in claim 8 or 9, wherein the step of forming at least one epitaxial layer includes: A first epitaxial layer is formed, which extends to the upper surface of the fin; And a second epitaxial layer is formed on the first epitaxial layer, and the second epitaxial layer extends to a height above the height of at least one of the stacked nanostructures.

Images